WO2017054258A1 - Tft阵列基板的制备方法、tft阵列基板及显示装置 - Google Patents

Tft阵列基板的制备方法、tft阵列基板及显示装置 Download PDF

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Publication number
WO2017054258A1
WO2017054258A1 PCT/CN2015/092351 CN2015092351W WO2017054258A1 WO 2017054258 A1 WO2017054258 A1 WO 2017054258A1 CN 2015092351 W CN2015092351 W CN 2015092351W WO 2017054258 A1 WO2017054258 A1 WO 2017054258A1
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Prior art keywords
layer
source
drain
gate
patterned polysilicon
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PCT/CN2015/092351
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English (en)
French (fr)
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肖军城
赵莽
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/890,698 priority Critical patent/US9899528B2/en
Publication of WO2017054258A1 publication Critical patent/WO2017054258A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/22—Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of liquid crystal technology, and in particular, to a method for fabricating a TFT array substrate, a TFT array substrate, and a display device.
  • FIG. 1 is a schematic flow chart of a method for fabricating a TFT array substrate of the prior art.
  • 2 is a process flow diagram of a method of fabricating a TFT array substrate of the prior art.
  • a method for preparing an LTPS-TFT having a bottom gate structure includes the following steps:
  • a gate pattern layer 41 is formed on the substrate 40.
  • a gate insulating layer 42 is formed on the gate pattern layer 41.
  • a patterned polysilicon layer 43 is formed on the gate insulating layer 42, and the patterned polysilicon layer 43 is connected to the gate pattern layer 41.
  • a source heavily doped region 431 and a drain heavily doped region 432 are formed on both sides of the patterned polysilicon layer 43, respectively.
  • a source lightly doped region 434 is formed inside the source heavily doped region 431 by using a photomask, and a drain lightly doped region 433 is formed inside the drain heavily doped region 432, and the source is lightly doped. Between the impurity region 434 and the drain lightly doped region 433 is a channel region 430.
  • a source and drain pattern layer 45 is formed on the isolation layer 44, and the source and drain pattern layers 45 are connected to the patterned polysilicon layer 43.
  • step S14 when the lightly doped region is formed in step S14, it is necessary to specifically design a mask to occlude the region outside the region where the lightly doped region needs to be formed, so that the cost of the method is high.
  • the invention provides a method for preparing a TFT array substrate, a TFT array substrate and a display device, which can solve the problem that the prior art needs to specifically design a mask for forming a lightly doped region, resulting in high production cost.
  • a technical solution adopted by the present invention is to provide a method for fabricating a TFT array substrate, the method comprising the steps of: forming a gate pattern layer on a substrate; and on the gate pattern layer Forming a gate insulating layer; forming a patterned polysilicon layer on the gate insulating layer, the patterned polysilicon layer being connected to the gate pattern layer; forming on each side of the patterned polysilicon layer a source heavily doped region and a drain heavily doped region, wherein a central region of the patterned polysilicon layer is a channel region; an isolation layer is formed on the patterned polysilicon layer; and the isolation layer is used a photomask is formed by a photolithography process to form a source and a drain pattern layer, the source and drain pattern layers are connected to the patterned polysilicon layer, and the mask covers one side of the channel region, using the same
  • the reticle forms a lightly doped region on the other side of the unobstructed channel region.
  • the step of forming a source and drain pattern layer by a photolithography process using a photomask includes: depositing a metal on the isolation layer to form a metal layer; coating the metal layer a photoresist; exposing the photoresist by ultraviolet light through a mask; developing the photoresist to form a pattern of the photoresist, the pattern formed by the photoresist obscuring a portion of the metal layer, another portion of the metal layer is exposed; etching a portion of the exposed metal layer to form the source and drain pattern layers; using the same photomask pair
  • the other side of the occluded channel region is ion implanted to form the lightly doped region; the photoresist is stripped.
  • the method further includes: forming a gate through hole on the gate insulating layer, and filling a conductive material in the gate through hole; Forming a patterned polysilicon layer on the gate insulating layer, wherein the patterned polysilicon layer is electrically connected to the gate pattern layer, the patterned polysilicon layer passes through the conductive layer in the gate through hole A material is coupled to the gate pattern layer.
  • the method further includes: forming a source through hole on the isolation layer at a position corresponding to the source heavily doped region, corresponding to a drain through hole is formed at a position of the drain heavily doped region; in a step of depositing a metal on the isolation layer to form a metal layer, a metal fills the source through hole and the drain through hole And connecting the source and drain pattern layers to the polysilicon layer.
  • the step of forming a patterned polysilicon layer on the gate insulating layer comprises: depositing an amorphous silicon layer on the gate insulating layer; converting the amorphous silicon layer into a polysilicon layer; The layer is etched into a patterned polysilicon layer.
  • the amorphous silicon layer is converted into a polysilicon layer by excimer laser annealing or solid phase crystallization.
  • a TFT array substrate which includes: a substrate, a gate pattern layer, a gate insulating layer, a patterned polysilicon layer, an isolation layer, and Source and drain pattern layers.
  • a gate pattern layer is formed on the substrate; a gate insulating layer is formed on the gate pattern layer; a patterned polysilicon layer is formed on the gate insulating layer, the polysilicon layer is The gate pattern layer is connected, the two sides of the patterned polysilicon layer are respectively a source heavily doped region and a drain heavily doped region, and a central region of the patterned polysilicon layer is a channel region; the isolation layer is formed On the patterned polysilicon layer; a source and a drain pattern layer are formed on the isolation layer, and the source and drain pattern layers are connected to the patterned polysilicon layer, the source and the drain The pattern of the pattern layer blocks one side of the channel region, and the other side of the channel region that is not blocked by the source and drain pattern layers is a lightly doped region.
  • the gate insulating layer is provided with a gate through hole, the gate through hole is filled with a conductive material, and the patterned polysilicon layer passes through the conductive material in the gate through hole and the patterned The gate pattern layer is connected.
  • a source through hole is disposed at a position corresponding to the source heavily doped region on the isolation layer, and a drain through hole is disposed at a position corresponding to the heavily doped region of the drain.
  • the source and drain pattern layers are formed of a metal that fills the source via and the drain via to connect the source and drain pattern layers to the patterned polysilicon layer.
  • a display device including a TFT array substrate, the TFT array substrate including: a substrate, a gate pattern layer, a gate insulating layer, and a pattern The polysilicon layer, the isolation layer, and the source and drain pattern layers.
  • a gate pattern layer is formed on the substrate; a gate insulating layer is formed on the gate pattern layer; a patterned polysilicon layer is formed on the gate insulating layer, the polysilicon layer is The gate pattern layer is connected, the two sides of the patterned polysilicon layer are respectively a source heavily doped region and a drain heavily doped region, and a central region of the patterned polysilicon layer is a channel region; the isolation layer is formed On the patterned polysilicon layer; a source and a drain pattern layer are formed on the isolation layer, and the source and drain pattern layers are connected to the patterned polysilicon layer, the source and the drain The pattern of the pattern layer blocks one side of the channel region, and the other side of the channel region that is not blocked by the source and drain pattern layers is a lightly doped region.
  • the gate insulating layer is provided with a gate through hole, the gate through hole is filled with a conductive material, and the patterned polysilicon layer passes through the conductive material in the gate through hole and the patterned The gate pattern layer is connected.
  • a source through hole is disposed at a position corresponding to the source heavily doped region on the isolation layer, and a drain through hole is disposed at a position corresponding to the heavily doped region of the drain.
  • the source and drain pattern layers are formed of a metal that fills the source via and the drain via to connect the source and drain pattern layers to the patterned polysilicon layer.
  • the shape of the reticle used when forming the source and drain pattern layers blocks one side of the channel region,
  • the same reticle can be formed on the other side of the channel region when forming the lightly doped region, thereby eliminating the need to design a reticle for forming the lightly doped region, thereby saving the design of the reticle, thereby saving cost.
  • the preparation method has strong design flexibility, and the area of the lightly doped region can be controlled by shielding the area of the channel region by the reticle, thereby flexibly controlling the effect of reducing the leakage current in the lightly doped region.
  • FIG. 1 is a schematic flow chart of a method for fabricating a TFT array substrate of the prior art
  • FIG. 2 is a process flow diagram of a method for fabricating a TFT array substrate of the prior art
  • FIG. 3 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate of the present invention
  • FIG. 4 is a process flow diagram of a first embodiment of a method for fabricating a TFT array substrate of the present invention
  • FIG. 5 is a schematic flowchart of step S102 in FIG. 3;
  • FIG. 6 is a schematic flow chart of step S105 in Figure 3;
  • FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate of the present invention.
  • FIG. 8 is a schematic view showing a layered structure of a cross section of an embodiment of a TFT array substrate of the present invention.
  • FIG. 9 is a schematic structural view of an embodiment of a display device of the present invention.
  • FIG. 3 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate according to the present invention
  • FIG. 4 is a flow chart of a first embodiment of a method for fabricating a TFT array substrate of the present invention.
  • the method for preparing the TFT array substrate of the present invention comprises the following steps:
  • a gate pattern layer 21 is formed on the substrate 20.
  • the gate pattern layer 21 is formed by depositing a metal on the substrate 20 to form a gate metal layer.
  • the metal of the gate electrode is usually aluminum and an aluminum alloy, or a metal compound conductive layer formed by stacking an aluminum layer, a tungsten layer, and a chromium layer.
  • a photoresist is then applied over the gate metal layer.
  • the photoresist is then photolithographically patterned to form a desired pattern of the photoresist, the pattern formed by the photoresist blocks a portion of the gate metal layer, and the other portion of the gate metal layer that is not blocked is exposed. .
  • the exposed portions of the gate metal layer are etched to form the desired gate pattern.
  • the photoresist is stripped to form the gate pattern layer 21.
  • a gate insulating layer 22 is formed on the gate pattern layer 21.
  • the gate insulating layer 22 is formed by a CVD or PECVD technique, and the gate insulating layer 22 has a one-layer structure, for example, an SiO2 layer.
  • the gate insulating layer 22 may also be a two-layer structure, for example, a SiO 2 layer and a superposed SiN x layer.
  • a patterned polysilicon layer 23 is formed on the gate insulating layer 22, and the patterned polysilicon layer 23 is connected to the gate pattern layer 22.
  • FIG. 5 is a schematic flowchart of step S102 in FIG.
  • the deformation of the patterned polysilicon layer 23 includes the following steps:
  • step S1021 the amorphous silicon layer is converted into a polysilicon layer by excimer laser annealing or solid phase crystallization.
  • Step S1022 specifically includes the following steps:
  • a photoresist 26 is coated on the polysilicon layer, and the photoresist 26 is photolithographically patterned by a photomask to form a desired pattern of the photoresist 26.
  • the pattern formed by the photoresist 26 blocks a portion of the polysilicon layer. Another portion of the polysilicon layer that is blocked is revealed. The exposed portions of the polysilicon layer are etched to form a desired pattern of polysilicon layers. Finally, the photoresist 26 is stripped. Thereby, the patterned polysilicon layer 23 is formed.
  • a source heavily doped region 231 and a drain heavily doped region 232 are formed on both sides of the patterned polysilicon layer 23, and a central region of the patterned polysilicon layer 23 is a channel region 230.
  • step S103 first, a photoresist is coated on the patterned polysilicon layer 230, and then the patterned polysilicon layer 23 is formed by a process such as exposure, development, etc., and the source heavily doped region 231 and the drain are required to be formed.
  • the position of the doped region 232 is revealed, and then ions are implanted at the position by ion implantation to form the source heavily doped region 231 and the drain heavily doped region 232.
  • the isolation layer 24 is an SiO2 layer formed by CVD or PECVD techniques.
  • the isolation layer 24 overlies the patterned polysilicon layer 23 for isolating the patterned polysilicon layer 23 and the source and drain pattern layers 25.
  • a source and a drain pattern layer 25 are formed by a photolithography process using a mask, and the source and drain pattern layers 25 are connected to the patterned polysilicon layer 23, and the mask covers one of the channel regions 230.
  • a lightly doped region 233 is formed on the other side of the unobstructed channel region 230 using the same mask.
  • step S105 the specific formation process of the source and drain pattern layer 25 is as shown in FIG. 6.
  • the process includes the following steps:
  • Step S1050 is formed by a sputtering process, for example, sputtering a metal such as aluminum or chromium to form a metal layer.
  • the step S1051 adopts a spin coating process.
  • the thickness of the photoresist is 15000 ⁇ 500 ⁇ .
  • a positive photoresist is used, and the photoresist is irradiated with ultraviolet rays through the photomask, wherein the photomask blocks a part of the photoresist, and the other part is exposed, and the exposed portion of the photoresist is The ultraviolet ray is softened, and the photoresist blocked by the reticle does not change.
  • step S1053 the softened portion of the photoresist is removed using a developing solution.
  • etching is to remove unnecessary metal to form a metal layer.
  • the etching process includes wet etching and dry etching, and the wet etching is performed with an etching solution to remove unwanted metals.
  • Dry etching is a treatment in which a gas under reduced pressure is discharged to cause a reaction to form a gaseous state.
  • the other side of the unmasked channel region 230 is ion implanted with the same mask to form a lightly doped region 233.
  • Lightly doped drain 233 Lightly doped drain 233 (Lightly The DopedDrain (LDD) structure is a structure adopted to reduce the electric field in the drain region to improve the thermal electron degradation effect, that is, to provide a lightly doped drain region in the channel, so that the lightly doped drain region is also subjected to Partial voltage, this structure prevents the degradation of hot electrons.
  • LDD Lightly doped drain
  • the channel length under the gate structure also decreases, and the reduction in channel length in the transistor increases the likelihood of charge breakdown between the source and drain and causes undesirable channel currents.
  • step S1055 the reticle used in step S1052 is used to keep the position of the reticle, and the reticle blocks one side of the channel.
  • the reticle blocks the near-source of the channel region 230.
  • One side of the doped region 231 is exposed, and the side of the channel region 230 adjacent to the drain heavily doped region 232 is revealed.
  • the lightly doped region 233 is formed on one side of the channel region 230 by ion implantation. Therefore, the mask of step S1052 is used in this step, thereby saving the design of the mask of this step and reducing the cost.
  • the source and drain metal pattern layers 25 are exposed.
  • the peeling process can be performed by wet stripping and dry stripping.
  • Wet stripping is a photoresist used to remove a pattern by using a stripper.
  • the dry stripping is performed by oxidizing the photoresist by oxygen discharge under reduced pressure to form a gaseous state to be removed, or by oxidizing the photoresist to form a volatile gas by ozone and UV irradiation.
  • the TFT prepared by the method of the present invention is a TFT having a single-sided lightly doped region 233.
  • the lightly doped region 233 is required to achieve the same effect of reducing leakage current as the double-sided lightly doped region, the mask can be shielded from the smaller area of the channel region by the reticle design, thereby obtaining a larger light-doped region.
  • the larger lightly doped region 233 can achieve the same effect of reducing leakage current as the bilateral lightly doped region.
  • the TFT on the TFT array substrate of this embodiment is an N-type TFT, and the source heavily doped region 231 and the drain heavily doped region 232 of the patterned polysilicon layer 23 are doped with a pentavalent element (such as phosphorus). Zone 230 is undoped with impurity elements.
  • the substitution of the phosphorus element for the position of the silicon atom in the crystal lattice forms an N-type semiconductor.
  • free electrons are multi-sub-members, and holes are small, mainly by free electron conduction. Free electrons are mainly provided by impurity atoms, and holes are formed by thermal excitation. The more impurities are incorporated, the higher the concentration of multi-child (free electrons) and the stronger the conductivity.
  • the preparation method of the present invention is also applicable to a P-type TFT.
  • a source heavily doped region and a drain heavily doped region of a P-type TFT are doped with a trivalent element (such as boron),
  • the P-type semiconductor is formed by replacing the position of the silicon atom in the crystal lattice.
  • a hole is a multi-substance, a free electron is a minority, and a hole is mainly conducted.
  • the holes are mainly provided by impurity atoms, and the free electrons are formed by thermal excitation. The more impurities are incorporated, the higher the concentration of the multi-holes (holes) and the stronger the conductivity.
  • the method for fabricating the TFT array substrate of the present invention uses the shape of the reticle to form one side of the channel region when forming the source and drain pattern layers, so that when the lightly doped region is formed
  • the same reticle can be formed on the other side of the channel region, thereby eliminating the need to design a reticle for forming a lightly doped region, saving the design of the reticle, thereby saving cost.
  • the preparation method has strong design flexibility, and the area of the lightly doped region can be controlled by shielding the area of the channel region by the reticle, thereby flexibly controlling the effect of reducing the leakage current in the lightly doped region.
  • FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate according to the present invention.
  • a gate through hole is formed on the gate insulating layer, and a conductive material is filled in the gate through hole.
  • a source through hole is formed on the isolation layer at a position corresponding to the source heavily doped region, and a drain through hole is formed at a position corresponding to the drain heavily doped region.
  • a metal layer is formed on the isolation layer, and the metal layer is formed into a source and a drain pattern layer by a photolithography process, wherein the metal layer is filled into the source through hole and the drain through hole to make the source,
  • the drain pattern layer is connected to the patterned polysilicon layer.
  • the reticle blocks one side of the channel region, and the same reticle forms a lightly doped region on the other side of the unobstructed channel region.
  • FIG. 8 is a schematic diagram showing the layered structure of a cross section of an embodiment of a TFT array substrate according to the present invention.
  • the present invention provides a TFT array substrate including a substrate 10, a gate pattern layer 11, a gate insulating layer 12, a patterned polysilicon layer 13, an isolation layer 14, and source and drain pattern layers 15.
  • the substrate 10 may be a glass substrate which is uniform in material, has high transparency and low reflectance, and has good thermal stability so as to maintain stable properties after a plurality of high temperature processes. Since the chemicals used in the TFT manufacturing process are many, the glass substrate needs to have good chemical resistance. The glass substrate also needs to have sufficient mechanical strength, good precision machining characteristics, and excellent electrical insulation properties.
  • the gate pattern layer 11 is formed on the substrate 10.
  • the gate layer pattern layer 11 is usually a metal compound conductive layer formed by laminating aluminum and aluminum alloy, or aluminum layer, tungsten layer or chromium layer, and forming a gate metal layer first. And then etched into the gate pattern layer 11.
  • the gate insulating layer 12 is overlaid on the gate pattern layer 11.
  • the gate insulating layer 12 may be one layer or two layers.
  • the first layer may be SiO, SiN or AlO, and has a thickness of about 175-300 nm.
  • the gate insulating layer 12 of this embodiment includes a layer of SiO2.
  • a gate through hole (not shown) is provided on the gate insulating layer 12, and the gate through hole is filled with a conductive material.
  • the patterned polysilicon layer 13 is formed on the gate insulating layer 12, and the patterned polysilicon layer 13 is connected to the gate pattern layer 11. Specifically, the patterned polysilicon layer 13 passes through the conductive material in the gate through-hole. The gate pattern layer 11 is connected. The two sides of the patterned polysilicon layer 13 are a source heavily doped region 131 and a drain heavily doped region 132, respectively, and a central region of the patterned polysilicon layer 13 is a channel region 130.
  • the isolation layer 14 is overlaid on the patterned polysilicon layer 13 for isolating the patterned polysilicon layer 13 and the source and drain pattern layers 15.
  • the isolation layer 14 of this embodiment is an SiO2 layer.
  • a source through hole 141 is disposed on the isolation layer 14 at a position corresponding to the source heavily doped region 131, and a drain through hole 142 is disposed at a position corresponding to the drain heavily doped region 132. .
  • the source and drain pattern layers 15 are disposed on the isolation layer 14, and the source and drain pattern layers 15 are connected to the patterned polysilicon layer 13. Specifically, the source and drain pattern layers 15 are formed of a metal. When the source and drain pattern layers 15 are formed, the metal fills the source through holes 141 and the drain through holes 142 to form the source and drain pattern layers 15 . Connected to the patterned polysilicon layer 13. The pattern of the source and drain pattern layers 15 blocks one side of the channel region 130, and the other side of the channel region 130 that is not blocked by the source and drain pattern layers 15 is a lightly doped region 133.
  • the source and drain pattern layers 15 are made of aluminum alloy, or metal aluminum, or metal chrome, wherein the source is connected to the pixel electrode and the drain is connected to the data signal line.
  • FIG. 10 is a schematic structural diagram of an embodiment of a display device according to the present invention.
  • the display device provided by the present invention includes a housing 31 and the above TFT array substrate 32.
  • the invention saves the design of the reticle in the step of forming the lightly doped region, thereby saving cost, and has strong design flexibility, and can flexibly control the lightly doped region to reduce leakage current.

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Abstract

一种TFT阵列基板的制备方法、TFT阵列基板及显示装置，该制备方法包括以下步骤：在衬底（10, 20）上依次形成栅极图案层（11, 21）、栅极绝缘层（12, 22）、图案化的多晶硅层（13, 23）、隔离层（14, 24），并在隔离层（14, 24）上采用一光罩通过光刻工艺以形成源、漏极图案层（15, 25），源、漏极图案层（15, 25）与图案化的多晶硅层（13, 23）连接，该光罩遮挡沟道区（130, 230）的一侧，采用同一光罩在未被遮挡的沟道区（130, 230）的另一侧形成轻掺杂区（133, 233）。其能够降低生产成本，且具有很强的设计灵活性。

Description

TFT阵列基板的制备方法、TFT阵列基板及显示装置
【技术领域】
本发明涉及液晶技术领域，特别是涉及一种TFT阵列基板的制备方法、TFT阵列基板及显示装置。
【背景技术】
随着低温多晶硅（LTPS）半导体薄膜晶体管（TFT）的发展，以及由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到System on Panel（SOP）的相关技术研究，并逐步成为现实。与此同时，由于LTPS半导体高迁移率的因素，其漏电特性相对于A-Si而言变得很差，漏电成为在LTPS设计中不可忽略的一部分。
如图1和图2所示，图1是现有技术的TFT阵列基板的制备方法的流程示意图。图2是现有技术的TFT阵列基板的制备方法的工艺流程图。现有技术中，具有底栅结构的LTPS-TFT的制备方法包括以下步骤：
S10，在衬底40上形成栅极图案层41。
S11，在栅极图案层41上形成栅极绝缘层42。
S12，在栅极绝缘层42上形成图案化的多晶硅层43，图案化的多晶硅层43与栅极图案层41连接。
S13，在图案化的多晶硅层43的两侧分别形成源极重掺杂区431和漏极重掺杂区432。
S14，采用一光罩在所述源极重掺杂区431内侧形成源极轻掺杂区434，在所述漏极重掺杂区432内侧形成漏极轻掺杂区433，源极轻掺杂区434和漏极轻掺杂区433之间为沟道区430。
S15，在所述图案化的多晶硅层43上形成隔离层44。
S16，在隔离层44上形成源、漏极图案层45，并将源、漏极图案层45连接到图案化的多晶硅层43上。
该制备方法中，在步骤S14形成轻掺杂区的时候，需要专门设计一光罩对需要形成轻掺杂区的区域之外的区域进行遮挡，而使得该方法的成本较高。
【发明内容】
本发明提供一种TFT阵列基板的制备方法、TFT阵列基板及显示装置，能够解决现有技术存在的需要专门设计一个光罩用于形成轻掺杂区导致制备成本高的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT阵列基板的制备方法，该制备方法包括以下步骤：在衬底上形成栅极图案层；在所述栅极图案层上形成栅极绝缘层；在所述栅极绝缘层上形成图案化的多晶硅层，所述图案化的多晶硅层与所述栅极图案层连接；在所述图案化的多晶硅层的两侧分别形成源极重掺杂区和漏极重掺杂区，所述图案化的多晶硅层的中部区域为沟道区；在所述图案化的多晶硅层上形成隔离层；在所述隔离层上，采用一光罩通过光刻工艺形成源、漏极图案层，所述源、漏极图案层与所述图案化的多晶硅层连接，所述光罩遮挡所述沟道区的一侧，采用同一所述光罩在未被遮挡的所述沟道区的另一侧形成轻掺杂区。
其中，在所述隔离层上，采用一光罩通过光刻工艺以形成源、漏极图案层的步骤包括：在所述隔离层上淀积金属以形成金属层；在所述金属层上涂光刻胶；采用紫外光通过一光罩对所述光刻胶进行曝光；对所述光刻胶进行显影，以使所述光刻胶形成图案，所述光刻胶形成的图案遮挡了所述金属层的一部分，所述金属层的另一部分则显露出来；对显露出来的所述金属层的部位进行蚀刻，以形成所述源、漏极图案层；采用同一所述光罩对未被遮挡的所述沟道区的另一侧进行离子注入以形成所述轻掺杂区；剥离所述光刻胶。
其中，在所述栅极图案层上形成栅极绝缘层的步骤之后，还包括：在所述栅极绝缘层上形成栅极贯通孔，并在所述栅极贯通孔内填充导电材料；在所述栅极绝缘层上形成图案化的多晶硅层，所述图案化的多晶硅层与所述栅极图案层连接的步骤中，所述图案化的多晶硅层通过所述栅极贯通孔内的导电材料与所述栅极图案层进行连接。
其中，在所述图案化的多晶硅层上形成隔离层的步骤之后，还包括：在所述隔离层上、对应于所述源极重掺杂区的位置处形成源极贯通孔，在对应于所述漏极重掺杂区的位置处形成漏极贯通孔；在所述隔离层上淀积金属以形成金属层的步骤中，金属填充到所述源极贯通孔和所述漏极贯通孔而使所述源、漏极图案层与所述多晶硅层进行连接。
其中，在所述栅极绝缘层上形成图案化的多晶硅层的步骤包括：在所述栅极绝缘层上沉积非晶硅层；将所述非晶硅层转化为多晶硅层；将所述多晶硅层蚀刻为图案化的多晶硅层。
其中，将所述非晶硅层转化为多晶硅层的步骤中，采用准分子激光退火或者固相结晶的方法将所述非晶硅层转化为多晶硅层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT阵列基板，该阵列基板包括：衬底、栅极图案层、栅极绝缘层、图案化的多晶硅层、隔离层以及源、漏极图案层。其中，栅极图案层形成于衬底之；栅极绝缘层形成于所述栅极图案层之上；图案化的多晶硅层形成于所述栅极绝缘层之上，所述多晶硅层与所述栅极图案层连接，所述图案化的多晶硅层的两侧分别为源极重掺杂区和漏极重掺杂区，所述图案化的多晶硅层的中部区域为沟道区；隔离层形成于所述图案化的多晶硅层之上；源、漏极图案层形成于所述隔离层之上，所述源、漏极图案层与所述图案化的多晶硅层连接，所述源、漏极图案层的图案遮挡所述沟道区的一侧，未被所述源、漏极图案层遮挡的所述沟道区的另一侧为轻掺杂区。
其中，所述栅极绝缘层上设有栅极贯通孔，所述栅极贯通孔内填充有导电材料，图案化的多晶硅层通过所述栅极贯通孔内的导电材料与所述图案化的栅极图案层进行连接。
其中，所述隔离层上、对应于所述源极重掺杂区的位置处设有源极贯通孔，在对应于所述漏极重掺杂区的位置处设有漏极贯通孔，所述源、漏极图案层由金属形成，该金属填充所述源极贯通孔和所述漏极贯通孔而使所述源、漏极图案层与所述图案化的多晶硅层连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示装置，该显示装置包括TFT阵列基板，该TFT阵列基板包括：衬底、栅极图案层、栅极绝缘层、图案化的多晶硅层、隔离层以及源、漏极图案层。其中，栅极图案层形成于衬底之；栅极绝缘层形成于所述栅极图案层之上；图案化的多晶硅层形成于所述栅极绝缘层之上，所述多晶硅层与所述栅极图案层连接，所述图案化的多晶硅层的两侧分别为源极重掺杂区和漏极重掺杂区，所述图案化的多晶硅层的中部区域为沟道区；隔离层形成于所述图案化的多晶硅层之上；源、漏极图案层形成于所述隔离层之上，所述源、漏极图案层与所述图案化的多晶硅层连接，所述源、漏极图案层的图案遮挡所述沟道区的一侧，未被所述源、漏极图案层遮挡的所述沟道区的另一侧为轻掺杂区。
其中，所述栅极绝缘层上设有栅极贯通孔，所述栅极贯通孔内填充有导电材料，图案化的多晶硅层通过所述栅极贯通孔内的导电材料与所述图案化的栅极图案层进行连接。
其中，所述隔离层上、对应于所述源极重掺杂区的位置处设有源极贯通孔，在对应于所述漏极重掺杂区的位置处设有漏极贯通孔，所述源、漏极图案层由金属形成，该金属填充所述源极贯通孔和所述漏极贯通孔而使所述源、漏极图案层与所述图案化的多晶硅层连接。
本发明的有益效果是：区别于现有技术的情况，本发明的TFT阵列基板的制备方法在形成源、漏极图案层的时候采用的光罩的形状遮挡了沟道区的一侧的，使得在形成轻掺杂区的时候可以采用同一光罩在沟道区的另一侧形成，从而无需再设计一个用于形成轻掺杂区的光罩，节省了光罩的设计，从而节省了成本。此外，该制备方法具有很强的设计灵活性，可以通过光罩遮挡沟道区的面积大小来控制轻掺杂区的面积大小，从而能灵活控制轻掺杂区降低漏电流的效果。
【附图说明】
图1是现有技术的TFT阵列基板的制备方法的流程示意图；
图2是现有技术的TFT阵列基板的制备方法的工艺流程图；
图3是本发明TFT阵列基板的制备方法第一实施例的流程示意图；
图4是本发明TFT阵列基板的制备方法第一实施例的工艺流程图；
图5是图3中步骤S102的流程示意图；
图6是图3中步骤S105的流程示意图；
图7是本发明TFT阵列基板的制备方法第二实施例中的流程示意图；
图8是本发明一种TFT阵列基板实施例的截面的层状结构示意图
图9是本发明一种显示装置实施例的结构示意图。
【具体实施方式】
下面结合附图和具体实施方式对本发明进行详细说明。
请参阅图3和图4，图3是本发明TFT阵列基板的制备方法第一实施例的流程示意图；图4是本发明TFT阵列基板的制备方法第一实施例的工艺流程图
具体地，本发明TFT阵列基板的制备方法包括以下步骤：
S100，在衬底20上形成栅极图案层21。
举例而言，该栅极图案层21的形成如下：在衬底20上淀积金属以形成栅极金属层。栅极的金属通常为铝及铝合金，或者铝层、钨层、铬层叠加后形成的金属化合物导电层。然后在栅极金属层上涂光刻胶。再采用光罩对光刻胶进行光刻，以使光刻胶形成所需的图案，光刻胶形成的图案遮挡栅极金属层的一部分，未被遮挡的另一部分栅极金属层则显露出来。对显露出来的栅极金属层的部位进行蚀刻，以形成所需的栅极图案。最后，剥离光刻胶，从而形成栅极图案层21。
S101，在栅极图案层21上形成栅极绝缘层22。
步骤S101中，通过CVD或者PECVD技术形成栅极绝缘层22，栅极绝缘层22为一层结构，例如，SiO2层。当然，该栅极绝缘层22也可以是双层结构，例如，SiO2层和叠加的SiNx层。
S102，在栅极绝缘层22上形成图案化的多晶硅层23，图案化的多晶硅层23与栅极图案层22连接。
具体而言，如图5所示，图5是图3中步骤S102的流程示意图。图案化的多晶硅层23的形变包括以下步骤：
S1020，在栅极绝缘层22上沉积非晶硅层。
S1021，将非晶硅层转化为多晶硅层。
步骤S1021中，采用准分子激光退火或者固相结晶的方法将非晶硅层转化为多晶硅层。
S1022，将多晶硅层蚀刻为图案化的多晶硅层23。
步骤S1022具体包括以下步骤：
在多晶硅层上涂光刻胶26，再采用光罩对光刻胶26进行光刻，以使光刻胶26形成所需的图案，光刻胶26形成的图案遮挡了多晶硅层的一部分，未被遮挡的另一部分多晶硅层则显露出来。对显露出来的多晶硅层的部位进行蚀刻，以形成所需的多晶硅层的图案。最后，剥离光刻胶26。从而形成图案化多晶硅层23。
S103，在图案化的多晶硅层23的两侧分别形成源极重掺杂区231和漏极重掺杂区232，图案化的多晶硅层23的中部区域为沟道区230。
具体而言，步骤S103中，首先在图案化多晶硅层230上涂光刻胶，再通过曝光、显影等工艺将图案化的多晶硅层23的、需要形成源极重掺杂区231和漏极重掺杂区232的位置显露出来，然后通过离子注入法在该位置注入离子以形成源极重掺杂区231和漏极重掺杂区232。
S104，在图案化的多晶硅层23上形成隔离层24。
步骤S104中，隔离层24为通过CVD或者PECVD技术形成的SiO2层。该隔离层24覆盖在图案化的多晶硅层23之上，用于隔绝图案化的多晶硅层23和源、漏极图案层25。
S105，在隔离层24上，采用一光罩通过光刻工艺形成源、漏极图案层25，源、漏极图案层25与图案化的多晶硅层23连接，光罩遮挡沟道区230的一侧，采用同一光罩在未被遮挡的沟道区230的另一侧形成轻掺杂区233。
步骤S105中，源、漏极图案层25的具体形成过程请参阅图6，该过程包括以下步骤：
S1050，在隔离层24上淀积金属以形金属层。
步骤S1050是通过溅射工艺形成的，例如，溅射铝或铬等金属形成金属层。
S1051，在金属层上涂光刻胶。
本实施例中，步骤S1051采用的是旋转涂胶工艺。其中，光刻胶的厚度为15000±500Å。
S1052，采用紫外光通过一光罩对光刻胶进行曝光。
本实施例中采用的是正性光刻胶，用紫外线通过该光罩照射光刻胶，其中，光罩遮挡了光刻胶的一部分，另一部分则显露出来，显露出来的部分光刻胶由于被紫外线照射而变软，被光罩遮挡住的光刻胶则不发生变化。
S1053，对光刻胶进行显影，以使光刻胶形成图案，光刻胶形成的图案遮挡了金属层的一部分，金属层的另一部分则显露出来。
步骤S1053中，采用显影液除去光刻胶的软化部分。
S1054，对显露出来的金属层的部位进行蚀刻，以形成源、漏极图案层25。
其中，蚀刻是为了去除不需要的金属以使金属层形成图案。蚀刻工艺包括湿刻和干刻，湿刻是用腐蚀液进行处理，以除去不需要的金属。干刻则是用减压下的气体放电，使之反应形成气态的处理。
S1055，采用同一光罩对未被遮挡的沟道区230的另一侧进行离子注入以形成轻掺杂区233。
轻掺杂漏区233（Lightly DopedDrain，LDD）结构，是为了减弱漏区电场、以改进热电子退化效应所采取的一种结构，即是在沟道中设置一个轻掺杂的漏区，让该轻掺杂的漏区也承受部分电压，这种结构可防止热电子退化效应。随着栅宽度的不断减小，栅结构下的沟道长度也不断减小，晶体管中沟道长度的减小增加了源漏间电荷击穿的可能性，并引起不希望的沟道电流。
步骤S1055中，继续使用步骤S1052中使用的光罩，保持其位置不动，该光罩遮挡了沟道的一侧，本实施例中，光罩遮挡的是沟道区230的靠近源极重掺杂区231的一侧，而沟道区230上、靠近漏极重掺杂区232的一侧则显露出来。通过离子注入使沟道区230上显露出来的一侧形成轻掺杂区233。由此本步骤采用的是步骤S1052的光罩，因而节省了该步骤的光罩的设计，降低了成本。
S1056，剥离光刻胶。
剥离光刻胶之后，源、漏极金属图案层25得以显露出来。其中，剥离工艺可以采用湿法剥离和干法剥离。湿法剥离是用剥离液除去形成图形时使用的光刻胶。干法剥离则是在减压条件下用氧气放电的方式使光刻胶氧化，形成气体状态而被除去，或者用臭氧和UV照射使光刻胶氧化形成挥发态气体而被除去。
本发明的方法制备的TFT为具有单边轻掺杂区233的TFT。当要求该轻掺杂区233达到跟双边轻掺杂区一样的降低漏电流的效果时，可以通过光罩的设计使光罩遮挡沟道区的较小的面积，从而获得较大的轻掺杂区233来实现，较大的轻掺杂区233可以达到双边轻掺杂区一样的降低漏电流的效果。
本实施例的TFT阵列基板上TFT的为N型TFT，图案化的多晶硅层23的源极重掺杂区231和漏极重掺杂区232掺杂了五价元素（如磷），沟道区230未掺杂杂质元素。磷元素取代晶格中硅原子的位置，就形成了N型半导体。在N型半导体中，自由电子为多子，空穴为少子，主要靠自由电子导电。自由电子主要由杂质原子提供，空穴由热激发形成。掺入的杂质越多，多子（自由电子）的浓度就越高，导电性能就越强。
值得一提的是，本发明的制备方法也适用于P型TFT，通常，P型TFT的源极重掺杂区和漏极重掺杂区掺杂的是三价元素（如硼），使之取代晶格中硅原子的位子，就形成P型半导体。在P型半导体中，空穴为多子，自由电子为少子，主要靠空穴导电。空穴主要由杂质原子提供，自由电子由热激发形成。掺入的杂质越多，多子（空穴）的浓度就越高，导电性能就越强。
区别于现有技术，本发明的TFT阵列基板的制备方法在形成源、漏极图案层的时候采用的光罩的形状遮挡了沟道区的一侧的，使得在形成轻掺杂区的时候可以采用同一光罩在沟道区的另一侧形成，从而无需再设计一个用于形成轻掺杂区的光罩，节省了光罩的设计，从而节省了成本。此外，该制备方法具有很强的设计灵活性，可以通过光罩遮挡沟道区的面积大小来控制轻掺杂区的面积大小，从而能灵活控制轻掺杂区降低漏电流的效果。
请参阅图7，图7是本发明TFT阵列基板的制备方法第二实施例中的流程示意图。
本实施例的TFT的制备方法包括以下步骤：
S200，在衬底上形成栅极图案层。
S201，在栅极图案层上形成栅极绝缘层。
S202，在栅极绝缘层上形成栅极贯通孔，在栅极贯通孔内填充导电材料。
S203，在栅极绝缘层上形成图案化的多晶硅层，图案化的多晶硅层通过栅极贯通孔内的导电材料与栅极图案层进行连接。
S204，在图案化的多晶硅层的两侧分别形成源极重掺杂区和漏极重掺杂区，图案化的多晶硅层的中部区域为沟道区。
S205，在图案化的多晶硅层上形成隔离层。
S206，在隔离层上、对应于源极重掺杂区的位置处形成源极贯通孔，在对应于漏极重掺杂区的位置处形成漏极贯通孔。
S207，在隔离层上形成金属层，采用一光罩通过光刻工艺将该金属层形成源、漏极图案层，其中，该金属层填充到源极贯通孔和漏极贯通孔而使源、漏极图案层与图案化的多晶硅层连接。该光罩遮挡沟道区的一侧，采用同一光罩在未被遮挡的沟道区的另一侧形成轻掺杂区。
请参阅图8，图8是本发明一种TFT阵列基板实施例的截面的层状结构示意图
本发明提供了一种TFT阵列基板，该阵列基板包括衬底10、栅极图案层11、栅极绝缘层12、图案化的多晶硅层13、隔离层14以及源、漏极图案层15。
具体地，衬底10可以是玻璃基板，该玻璃基板材质均匀，具有高透明度和低反射率，并且有好的热稳定性，从而能在多次高温工艺之后保持性质稳定。由于TFT制造工艺中用到的化学药品很多，因而，该玻璃基板需具有很好的化学耐药性。该玻璃基板还需要具有足够的机械强度，还需要有很好的精密机械加工特性以及要有优良的电学绝缘特性。
栅极图案层11形成在衬底10上，栅极层图案层11通常是采用铝以及铝合金、或者铝层、钨层、铬层叠加后形成的金属化合物导电层，先形成栅极金属层，然后蚀刻成栅极图案层11。
栅极绝缘层12覆盖在栅极图案层11之上，栅极绝缘层12可以为一层，也可以是两层，第一层可以是SiO，SiN或AlO，厚度在175-300nm左右。本实施例的栅极绝缘层12包括一层SiO2层。
本实施例中，在栅极绝缘层12上设有栅极贯通孔（图未示），栅极贯通孔内填充有导电材料。
图案化的多晶硅层13形成在栅极绝缘层12之上，图案化的多晶硅层13与栅极图案层11连接，具体地，该图案化的多晶硅层13通过栅极贯通孔内的导电材料与栅极图案层11连接。图案化的多晶硅层13的两侧分别为源极重掺杂区131和漏极重掺杂区132，图案化的多晶硅层13的中部区域为沟道区130。
隔离层14覆盖在图案化的多晶硅层13上，用于隔离图案化多晶硅层13和源、漏极图案层15。本实施例的隔离层14为SiO2层。
本实施例中，隔离层14上、对应于源极重掺杂区131的位置处设有源极贯通孔141，在对应于漏极重掺杂区132的位置处设有漏极贯通孔142。
源、漏极图案层15设在隔离层14之上，源、漏极图案层15与图案化的多晶硅层13连接。具体而言，源、漏极图案层15由金属形成，在形成源、漏极图案层15的时候，该金属填充源极贯通孔141和漏极贯通孔142而使源、漏极图案层15与图案化的多晶硅层13连接。源、漏极图案层15的图案遮挡沟道区130的一侧，未被源、漏极图案层15遮挡的沟道区130的另一侧为轻掺杂区133。
源、漏极图案层15采用铝合金，或者金属铝，或者金属铬制作而成，其中，源极与像素电极相接，漏极与数据信号线相接。
请参阅图10，图10是本发明一种显示装置实施例的结构示意图。
本发明提供的显示装置包括外壳31和上述TFT阵列基板32。
本发明节省了形成轻掺杂区步骤中的光罩的设计，从而节省了成本，并且具有很强的设计灵活性，能灵活控制轻掺杂区降低漏电流。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种TFT阵列基板的制备方法，其中，包括以下步骤：
    在衬底上形成栅极图案层；
    在所述栅极图案层上形成栅极绝缘层；
    在所述栅极绝缘层上形成图案化的多晶硅层，所述图案化的多晶硅层与所述栅极图案层连接；
    在所述图案化的多晶硅层的两侧分别形成源极重掺杂区和漏极重掺杂区，所述图案化的多晶硅层的中部区域为沟道区；
    在所述图案化的多晶硅层上形成隔离层；
    在所述隔离层上，采用一光罩通过光刻工艺形成源、漏极图案层，所述源、漏极图案层与所述图案化的多晶硅层连接，所述光罩遮挡所述沟道区的一侧，采用同一所述光罩在未被遮挡的所述沟道区的另一侧形成轻掺杂区。
  2. 根据权利要求1所述的方法，其中，在所述隔离层上，采用一光罩通过光刻工艺形成源、漏极图案层的步骤包括：
    在所述隔离层上淀积金属以形成金属层；
    在所述金属层上涂光刻胶；
    采用紫外光通过一光罩对所述光刻胶进行曝光；
    对所述光刻胶进行显影，以使所述光刻胶形成图案，所述光刻胶形成的图案遮挡了所述金属层的一部分，所述金属层的另一部分则显露出来；
    对显露出来的所述金属层的部位进行蚀刻，以形成所述源、漏极图案层；
    采用同一所述光罩对未被遮挡的所述沟道区的另一侧进行离子注入以形成所述轻掺杂区；
    剥离所述光刻胶。
  3. 根据权利要求2所述的方法，其中，在所述栅极图案层上形成栅极绝缘层的步骤之后，还包括：在所述栅极绝缘层上形成栅极贯通孔，并在所述栅极贯通孔内填充导电材料；
    在所述栅极绝缘层上形成图案化的多晶硅层，所述图案化的多晶硅层与所述栅极图案层连接的步骤中，所述图案化的多晶硅层通过所述栅极贯通孔内的导电材料与所述栅极图案层进行连接。
  4. 根据权利要求3所述的方法，其中，在所述图案化的多晶硅层上形成隔离层的步骤之后，还包括：在所述隔离层上、对应于所述源极重掺杂区的位置处形成源极贯通孔，在对应于所述漏极重掺杂区的位置处形成漏极贯通孔；
    在所述隔离层上淀积金属以形成金属层的步骤中，金属填充到所述源极贯通孔和所述漏极贯通孔而使所述源、漏极图案层与所述多晶硅层进行连接。
  5. 根据权利要求4所述的方法，其中，在所述栅极绝缘层上形成图案化的多晶硅层的步骤包括：
    在所述栅极绝缘层上沉积非晶硅层；
    将所述非晶硅层转化为多晶硅层；
    将所述多晶硅层蚀刻为图案化的多晶硅层。
  6. 根据权利要求5所述的方法，其中，将所述非晶硅层转化为多晶硅层的步骤中，采用准分子激光退火或者固相结晶的方法将所述非晶硅层转化为多晶硅层。
  7. 一种TFT阵列基板，其中，包括：
    衬底；
    形成于衬底之上的栅极图案层；
    形成于所述栅极图案层之上的栅极绝缘层；
    形成于所述栅极绝缘层之上的图案化的多晶硅层，所述图案化的多晶硅层与所述栅极图案层连接，所述图案化的多晶硅层的两侧分别为源极重掺杂区和漏极重掺杂区，所述图案化的多晶硅层的中部区域为沟道区；
    形成于所述图案化的多晶硅层之上的隔离层；
    形成于所述隔离层之上的源、漏极图案层，所述源、漏极图案层与所述图案化的多晶硅层连接，所述源、漏极图案层的图案遮挡所述沟道区的一侧，未被所述源、漏极图案层遮挡的所述沟道区的另一侧为轻掺杂区。
  8. 根据权利要求7所述的TFT阵列基板，其中，所述栅极绝缘层上设有栅极贯通孔，所述栅极贯通孔内填充有导电材料，图案化的多晶硅层通过所述栅极贯通孔内的导电材料与所述栅极图案层进行连接。
  9. 根据权利要求8所述的TFT阵列基板，其中，所述隔离层上、对应于所述源极重掺杂区的位置处设有源极贯通孔，在对应于所述漏极重掺杂区的位置处设有漏极贯通孔，所述源、漏极图案层由金属形成，该金属填充所述源极贯通孔和所述漏极贯通孔而使所述源、漏极图案层与所述图案化的多晶硅层连接。
  10. 一种显示装置，其中，包括TFT阵列基板，所述TFT阵列基板包括：
    衬底；
    形成于衬底之上的栅极图案层；
    形成于所述栅极图案层之上的栅极绝缘层；
    形成于所述栅极绝缘层之上的图案化的多晶硅层，所述图案化的多晶硅层与所述栅极图案层连接，所述图案化的多晶硅层的两侧分别为源极重掺杂区和漏极重掺杂区，所述图案化的多晶硅层的中部区域为沟道区；
    形成于所述图案化的多晶硅层之上的隔离层；
    形成于所述隔离层之上的源、漏极图案层，所述源、漏极图案层与所述图案化的多晶硅层连接，所述源、漏极图案层的图案遮挡所述沟道区的一侧，未被所述源、漏极图案层遮挡的所述沟道区的另一侧为轻掺杂区。
  11. 根据权利要求10所述的显示装置，其中，所述栅极绝缘层上设有栅极贯通孔，所述栅极贯通孔内填充有导电材料，图案化的多晶硅层通过所述栅极贯通孔内的导电材料与所述栅极图案层进行连接。
  12. 根据权利要求11所述的显示装置，其中，所述隔离层上、对应于所述源极重掺杂区的位置处设有源极贯通孔，在对应于所述漏极重掺杂区的位置处设有漏极贯通孔，所述源、漏极图案层由金属形成，该金属填充所述源极贯通孔和所述漏极贯通孔而使所述源、漏极图案层与所述图案化的多晶硅层连接。
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