WO2019029008A1 - 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板 - Google Patents

薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板 Download PDF

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Publication number
WO2019029008A1
WO2019029008A1 PCT/CN2017/106973 CN2017106973W WO2019029008A1 WO 2019029008 A1 WO2019029008 A1 WO 2019029008A1 CN 2017106973 W CN2017106973 W CN 2017106973W WO 2019029008 A1 WO2019029008 A1 WO 2019029008A1
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Prior art keywords
layer
insulating
source
conductor
semiconductor layer
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PCT/CN2017/106973
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English (en)
French (fr)
Inventor
李松杉
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武汉华星光电半导体显示技术有限公司
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Priority to US15/737,302 priority Critical patent/US10431691B2/en
Publication of WO2019029008A1 publication Critical patent/WO2019029008A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method of manufacturing a thin film transistor and a thin film transistor, and a liquid crystal display panel.
  • Thin Film Transistor is widely used in liquid crystal display devices (Liquid) Crystal Display (abbreviated as LCD) and active matrix driven organic electroluminescent display device (Active Matrix Organic Light-Emitting) Diode, referred to as AMOLED), therefore, thin film transistors affect the development of the display industry.
  • LCD Liquid
  • AMOLED Active Matrix Organic Light-Emitting
  • thin film transistors affect the development of the display industry.
  • the formed thin film transistor has a problem that the leakage current is excessively large, and the characteristics of the thin film transistor are affected.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor and a thin film transistor, and a liquid crystal display panel to solve the problem of excessive leakage current of the thin film transistor.
  • a technical solution adopted by the embodiment of the present invention is to provide a thin film transistor including a substrate, a gate layer and an insulating layer.
  • the gate layer is formed on the substrate, and the insulating layer covers the gate.
  • a semiconductor layer formed on the insulating layer; a conductor layer formed on the semiconductor layer; an insulating spacer layer formed on the insulating layer; a source/drain layer formed on the conductor layer and the insulating spacer layer; and a passivation layer formed On the source drain layer and the semiconductor layer; wherein the insulating spacer layer is between the source drain layer and the semiconductor layer.
  • another technical solution adopted by the embodiment of the present invention is to provide a method for manufacturing a thin film transistor, which comprises a substrate; a gate layer and an insulating layer are disposed on the substrate, and the insulating layer covers the gate a layer; a semiconductor layer and a conductor layer are sequentially disposed on the insulating layer; an insulating spacer layer is disposed on the insulating layer; a source and drain layer is disposed on the conductor layer and the insulating spacer layer; wherein the insulating spacer layer is located at the source and drain layers and the semiconductor layer Providing a passivation layer on the source and drain layers and the semiconductor layer.
  • liquid crystal display panel includes a thin film transistor
  • the thin film transistor includes:
  • the gate layer is formed on the substrate, and the insulating layer covers the gate layer;
  • the semiconductor layer has a channel region, the channel region is divided into left and right portions, and the conductor layer is formed on the left and right portions of the semiconductor layer to form a two-island structure;
  • a source drain layer formed on the conductor layer and the insulating spacer layer
  • the insulating spacer layer is located between the source and drain layers and the semiconductor layer;
  • the gate layer and the source and drain layers are metal materials
  • the insulating layer, the insulating spacer layer, and the passivation layer are all insulating materials.
  • the invention has the beneficial effects that: by providing a gate layer and an insulating layer on the substrate, the insulating layer covers the gate layer; the semiconductor layer and the conductor layer are sequentially disposed on the insulating layer; the insulating spacer layer is disposed on the insulating layer; a source and a drain layer are disposed on the layer and the insulating spacer layer; wherein the insulating spacer layer is located between the source and drain layers and the semiconductor layer; and an insulating spacer layer is disposed between the source and drain layers and the semiconductor layer to prevent the source and drain layers and the semiconductor
  • the layers are in direct contact, thereby achieving a reduction in leakage current and improving the characteristics of the thin film transistor.
  • FIG. 1 is a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a thin film transistor according to another embodiment of the present invention.
  • FIG. 3 is a flow chart showing a method of manufacturing a thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart showing a method of manufacturing a thin film transistor according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural view of a glass substrate formed in step S22 of the method for manufacturing the thin film transistor shown in FIG. 4;
  • FIG. 6 is a schematic structural view of a glass substrate formed in step S23 of the manufacturing method of the thin film transistor shown in FIG. 4;
  • FIG. 7 is a schematic flow chart showing a first formation manner of an insulating spacer layer in the method of manufacturing the thin film transistor shown in FIG. 4;
  • FIG. 8 is a schematic structural view of a thin film transistor formed after steps S231-S251 in the first formation mode of the insulating spacer layer shown in FIG. 7;
  • FIG. 9 is a schematic flow chart showing a second formation manner of an insulating spacer layer in the method of manufacturing the thin film transistor shown in FIG. 4;
  • FIG. 10 is a schematic structural view of a thin film transistor formed after steps S242-S252 in the second formation manner of the insulating spacer layer shown in FIG. 9;
  • FIG. 11 is a schematic structural view of a liquid crystal display panel according to an embodiment of the invention.
  • FIG. 12 is a schematic structural view of a liquid crystal display panel according to another embodiment of the present invention.
  • a plurality is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “comprises” and “comprising” and “comprising” are intended to cover a non-exclusive inclusion.
  • a process, method, system, product, or device that comprises a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or, optionally, Other steps or units inherent to these processes, methods, products or equipment.
  • references to "an embodiment” herein mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the invention.
  • the appearances of the phrases in various places in the specification are not necessarily referring to the same embodiments, and are not exclusive or alternative embodiments that are mutually exclusive. Those skilled in the art will understand and implicitly understand that the embodiments described herein can be combined with other embodiments.
  • FIG. 1 is a schematic structural view of a thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a thin film transistor according to another embodiment of the present invention.
  • the thin film transistor 100 includes a substrate 110, a gate layer 120, an insulating layer 130, a semiconductor layer 140, a conductor layer 150, an insulating spacer layer 160, a source and drain layer 170, and a passivation layer 180.
  • the thin film transistor 100 has a laminated structure, and each of the above layers is sequentially formed on the substrate 110, and the substrate 110 may be a glass substrate.
  • the gate layer 120 is formed on the substrate 110, and the insulating layer 130 covers the gate layer 120.
  • the thin film transistor 100 is a bottom gate structure.
  • the semiconductor layer 140 is formed as an active layer of the thin film transistor 100 on the insulating layer 130; the conductive layer 150 is formed on the semiconductor layer 140 for connecting the semiconductor layer 140 and the source and drain layers 170, and the source and drain layers 170 pass between After the conductor layer 150 is formed with a current through the semiconductor layer 140, the semiconductor layer 140 is directly connected to the source and drain layer 170. In this embodiment, the conductor layer 150 has a small resistance, and the source and drain layers 170 and the semiconductor layer 140 can be reduced. Leakage current condition.
  • An insulating spacer layer 160 is further formed on the insulating layer 130 in the embodiment, that is, the insulating spacer layer 160 is disposed in the same layer as the semiconductor layer 140; the source and drain layer 170 is formed on the conductor layer 150 and the insulating spacer layer 160, and The insulating spacer layer 160 is located between the semiconductor layer 140 and the source and drain layers 170.
  • the conductive layer 150 and the insulating spacer layer 160 are disposed between the semiconductor layer 140 and the source and drain layers 170, that is, there is no direct contact connection between the semiconductor layer 140 and the source and drain layers 170, thereby effectively reducing the semiconductor layer 140. Leakage current between the source and drain layers 170.
  • the semiconductor layer 140 has a channel region 141 which divides the semiconductor layer 140 into left and right portions, and a conductor layer 150 is formed on the left and right portions of the semiconductor layer 140 to form a two-island structure.
  • the source and drain layers 170 formed on the two island structures of the conductor layer 150 are also distinguished as a source and a drain.
  • the passivation layer 180 is formed on the source and drain layers 170 and the semiconductor layer 140, specifically formed on the channel region 141 of the semiconductor 140, and formed between the two island structures of the conductor layer 150.
  • the insulating layer 130, the insulating spacer layer 160, and the passivation layer 180 are all insulating materials, and may be silicon oxide or silicon nitride.
  • the gate layer 120 and the source/drain layer 170 are made of a metal material, and may be a metal material such as molybdenum or aluminum, or a metal material of a combination of molybdenum-aluminum-molybdenum.
  • the semiconductor layer 140 may be polysilicon, and the conductor layer 150 may be a P+ conductor layer formed of polysilicon doped with B ions.
  • the insulating spacer layer 160 in this embodiment may be formed on the insulating layer 130 in various ways, such as the two modes shown in FIGS. 1 and 2.
  • an insulating spacer layer 160 is formed on the insulating layer 130 and has a first thickness h1 and a second thickness h2, the second thickness h2 is smaller than the first thickness h1, and the second thickness h2 is greater than or equal to the thickness of the semiconductor layer 140.
  • H3, the second thickness h2 of the insulating spacer layer in FIG. 1 is equal to the thickness h3 of the semiconductor layer 140.
  • the structure of the insulating spacer layer 160 in FIG. 1 is such that the source and drain layers 170 are not formed on the insulating layer 130, and then the distance between the source and drain layers 170 and the gate layer 120 is increased, which prevents breakdown and can be reduced.
  • the formed passivation layer 180 is further disposed on the insulating spacer layer 160.
  • the insulating spacer layer 160 is formed on the side of the semiconductor layer 140 and the conductor layer 150 on the insulating layer 130, and the thickness h thereof may be greater than or equal to the thickness h3 of the semiconductor layer 140.
  • the thickness h of the insulating spacer layer 160 in FIG. Layer 140 has a thickness h3 and is equal to the thickness h3+h4 of both semiconductor layer 140 and conductor layer 150.
  • the structure of the insulating spacer layer 160 in FIG. 2 is such that the source and drain layers 170 are further disposed on the insulating layer 130, the insulating spacer layer 160 can be located between the conductive layer 150 and the source and drain layers 170, and the passivation layer 180 is further disposed in the insulating layer. On layer 130.
  • the insulating spacer layer is located between the source and drain layers and the semiconductor layer, which can block the direct contact between the source and drain layers and the semiconductor layer, thereby reducing the problem of leakage current, thereby improving the performance of the thin film transistor.
  • FIG. 3 is a schematic flow chart of a method for fabricating a thin film transistor according to an embodiment of the present invention.
  • the method of manufacturing the thin film transistor may include the following steps:
  • a substrate for manufacturing a thin film transistor which may be a glass substrate, is prepared.
  • S12 A gate layer and an insulating layer are disposed on the substrate.
  • a layer of metal is deposited on the glass substrate prepared in the above step S11 to form a gate layer.
  • the metal material forming the gate layer is molybdenum, and in other embodiments, It may be other metal materials; and an insulating layer is disposed on the gate layer that has been disposed, wherein the insulating layer is overlaid on the gate layer, that is, the gate layer is formed between the substrate and the insulating layer, in this embodiment
  • the material of the insulating layer in the example is silicon oxide, and in other embodiments, it may be silicon nitride or other material capable of achieving the purpose of insulation.
  • the glass substrate formed in this step is used in the following step S13.
  • S13 A semiconductor layer and a conductor layer are sequentially disposed on the insulating layer.
  • the semiconductor layer and the conductor layer are further disposed on the glass substrate obtained in the above step S12. Specifically, a semiconductor layer is disposed on the upper surface of the insulating layer, and a conductor layer is disposed on the upper surface of the semiconductor layer.
  • the semiconductor layer is formed on the upper surface of the insulating layer, that is, the insulating layer is between the semiconductor layer and the gate layer, and the semiconductor layer is intermediate between the insulating layer and the conductor layer.
  • S14 An insulating spacer layer is disposed on the insulating layer.
  • step S14 the processing is continued on the glass substrate obtained in the above step S13.
  • an insulating spacer layer is disposed on the insulating layer, and the insulating spacer layer is formed. At both ends of the semiconductor layer, and a portion of the insulating spacer layer in contact with the semiconductor layer is greater than or equal to a height of the semiconductor layer.
  • S15 providing a source and drain layer on the conductor layer and the insulating spacer layer.
  • step S15 the processing is continued on the glass substrate obtained in the above step S14.
  • a source/drain layer is disposed on the conductor layer and the insulating spacer layer.
  • the insulating spacer layer is located at both ends of the semiconductor layer and is also located between the source and drain layers and the semiconductor layer.
  • step S16 the processing is continued on the glass substrate obtained in the above step S15.
  • the source and drain layers are disposed in the above step, the source and drain layers, the conductor layer and the upper surface of the semiconductor layer are further formed.
  • a channel, a passivation layer is disposed on the source and drain layers and the semiconductor layer to complete the fabrication of the thin film transistor, the passivation layer is disposed over the source and drain layers and the semiconductor layer, and is in contact with the conductor layer, that is, the passivation layer is covered Protects the channel.
  • the manufacturing method of the thin film transistor of this embodiment includes preparing a substrate, disposing a gate layer and an insulating layer on the substrate, sequentially providing a semiconductor layer and a conductor layer on the insulating layer, and providing an insulating spacer layer on the insulating layer, and spacing between the conductor layer and the insulating layer a source-drain layer is disposed on the layer, a passivation layer is disposed on the source-drain layer and the semiconductor layer, and an insulating spacer layer is formed on the insulating layer to form an insulating spacer layer having a height greater than or equal to a height of the semiconductor layer at both ends of the semiconductor layer.
  • the source/drain layer is prevented from coming into contact with the semiconductor layer to cause an increase in the leakage path, and there is an effect of reducing leakage current.
  • FIG. 4 is a schematic flow chart of a method for fabricating a thin film transistor according to another embodiment of the present invention.
  • the method of manufacturing the thin film transistor may include the following steps:
  • a substrate for manufacturing a thin film transistor which may be a glass substrate, is prepared.
  • a gate layer and an insulating layer are provided on the glass substrate, specifically, PVD (Physical) is used on the glass substrate.
  • Vapor Deposition physical vapor deposition technique deposits a layer of metal and is patterned to form a gate layer.
  • the metal material forming the gate layer in this embodiment is molybdenum, although other metal materials may be used in other embodiments;
  • Reuse PECVD Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method deposits an insulating material to form an insulating layer, and the insulating layer covers the gate layer, that is, the gate layer is formed between the glass substrate and the insulating layer, in this embodiment
  • the material of the insulating layer is silicon oxide, and in other embodiments it may be silicon nitride or other material capable of achieving the purpose of insulation.
  • FIG. 5 is a schematic structural view of the glass substrate formed in step S22 of the method for manufacturing the thin film transistor shown in FIG.
  • the glass substrate 110, the gate layer 120, and the insulating layer 130 are shown.
  • the gate layer 120 is formed on the substrate 110, and the insulating layer 130 covers the gate layer 120.
  • S23 A semiconductor layer and a conductor layer are sequentially disposed on the insulating layer.
  • the semiconductor layer and the conductor layer are continuously disposed on the glass substrate obtained in the above step S22.
  • an amorphous silicon material is deposited on the insulating layer by PECVD technology, and is performed in the amorphous silicon material.
  • Doping treatment and crystallization treatment to form a polysilicon material close to the insulating layer and a conductor material away from the insulating layer specifically, implanting a dose of B ions by an ion implantation technique in the amorphous silicon material, in this embodiment
  • the implantation dose of B ion can be set according to actual needs, for example, implanted in 0.1 ml, 0.5 ml, 1 ml, etc., and heated at 650 ° C ( ⁇ 50 ° C) for 15 min ( ⁇ 1 min) by rapid heating technique. It can be crystallized, and the temperature and time of heating can be set according to actual conditions.
  • amorphous silicon is crystallized by heating at 650 ° C for 15 min by rapid heating technique, because the upper surface contains more B ion, the temperature and time of crystallization are reduced, so the crystal direction is from top to bottom, forming a conductor material away from the insulating layer and close to the insulating layer Crystalline silicon, polysilicon material and the conductive material was patterned, the semiconductor layer is obtained and the conductor layer.
  • FIG. 6 shows that the semiconductor layer 140 is formed on the insulating layer 130.
  • Layer 150 is formed on semiconductor layer 140, and other reference numerals are the same as described in FIG.
  • an insulating spacer layer is disposed on the insulating layer, and a source/drain layer is disposed on the conductor layer and the insulating spacer layer.
  • step S24 an insulating spacer layer and a source/drain layer are disposed on the insulating layer formed on the glass substrate obtained in the above step S23.
  • the insulating spacer layer is formed in various manners, and the insulating spacer layer is formed. The formation involves the difference of step S23 and step S25, so the steps S23-S25 are collectively explained below, and two formation modes S231-S251 and S242-S252 are given below.
  • FIG. 7 is a schematic flow chart showing the first formation manner of the insulating spacer layer in the manufacturing method of the thin film transistor shown in FIG.
  • a semiconductor layer and a conductor layer are sequentially disposed on the insulating layer, and a photoresist material is disposed on the conductor layer.
  • S241 oxidizing the semiconductor layer and the conductor layer to form an insulating spacer layer disposed on the insulating layer, removing the photoresist material, and providing a source/drain layer on the conductor layer and the insulating spacer layer.
  • the semiconductor layer and the conductor layer are sequentially disposed in step S231, and a layer of photoresist material is covered on the conductor layer, and the conductor layer region is defined by illumination and dry etching. At this time, the photoresist material is not removed first.
  • the semiconductor layer and the conductor layer are oxidized in step S241 to form an insulating spacer layer disposed on the insulating layer.
  • the oxidation treatment is to treat the sidewall of the semiconductor layer by oxygen plasma to form a
  • the silicon oxide layer of the sidewall of the layer, that is, the insulating spacer layer is also formed on the insulating layer, wherein the height of the insulating spacer layer is greater than or equal to the height of the sidewall of the semiconductor layer.
  • the photoresist material can be removed, and the source and drain layers are further disposed.
  • a metal material superposed by molybdenum-aluminum-molybdenum is deposited by PVD technology.
  • the patterning process is performed to form a source and drain layer.
  • the source and drain layers are only in contact with the upper surface of the conductor layer, the insulating spacer layer is located between the source and drain layers and the semiconductor layer, and the sidewalls of the source and drain layers are insulated.
  • the barrier of the spacer layer is not in contact with the semiconductor layer.
  • a channel is formed on the glass substrate obtained in the above step S241, and a passivation layer is provided on the source/drain layer and the semiconductor layer, and the passivation layer serves to protect the channel of the formed thin film transistor.
  • the source/drain layer formed in the above step S241 is a metal electrode, and is used as a photomask to dry-etch the conductor layer to form a channel, and the conductor layer on the upper surface of the channel is removed. Lower channel semiconductor layer to obtain a thin film transistor.
  • a passivation material is deposited by PECVD, patterned to form a passivation layer, and the passivation material may be silicon oxide or other materials, which is passivated in this embodiment. The material is silicon oxide.
  • FIG. 8 is a schematic structural diagram of a thin film transistor formed after steps S231-S251 in the first formation manner of the insulating spacer layer shown in FIG. 7.
  • the semiconductor layer 140 is formed on the insulating layer 130 away from the gate layer 120.
  • the conductor layer 150 is formed on a side of the semiconductor layer 140 facing away from the insulating layer 130.
  • the insulating spacer layer 160 is formed on the sidewall of the semiconductor layer 140, and is also formed on the insulating layer 130.
  • the source and drain layer 170 is formed on the conductor layer 150.
  • the source and drain layers 170 are further formed over the insulating layer 130, and the passivation layer 180 is formed over the source and drain layers 170, the semiconductor layer 140, and the insulating layer 130, FIG.
  • Other reference numerals are shown in the same description as in FIG. 6.
  • FIG. 9 is a schematic flow chart showing the second formation manner of the insulating spacer layer in the manufacturing method of the thin film transistor shown in FIG.
  • S242 depositing an insulating material on the conductor layer and the insulating layer, patterning the insulating material, removing the insulating material on the conductor layer, and forming an insulating spacer layer on the insulating layer.
  • a conductive material is deposited on the conductive layer formed in the above step S23 and an insulating layer is formed on the insulating layer in the step S22.
  • the insulating material may be silicon oxide or silicon nitride, and the thickness of the insulating material is greater than or Equal to the thickness of the semiconductor layer, the insulating material is patterned by illumination and dry etching to remove the insulating material on the conductor layer to form an insulating silicon oxide or silicon nitride at both ends of the semiconductor layer, that is, insulating A spacer layer, at which time an insulating spacer layer is also formed on the insulating layer.
  • the source and drain layers are further disposed. Specifically, after removing the photoresist material, a metal material superposed by three layers of molybdenum-aluminum-molybdenum is deposited by PVD technology, and the pattern is processed to form a source. a drain layer, wherein the source and drain layers are only in contact with the upper surface of the conductor layer, the insulating spacer layer is located between the source and drain layers and the semiconductor layer, and the sidewall of the source and drain layers is not blocked by the insulating spacer layer contact.
  • a channel is formed on the glass substrate obtained in the above step S242, and a passivation layer is provided on the source/drain layer and the semiconductor layer, and the passivation layer serves to protect the channel of the formed thin film transistor.
  • the source and drain layers formed in the above step S24 are metal electrodes, which are used as a mask to dry-etch the conductor layer to form a channel, and the conductor layer on the upper surface of the channel is removed. Lower channel semiconductor layer to obtain a thin film transistor.
  • a passivation material is deposited by PECVD, patterned to form a passivation layer, and the passivation material may be silicon oxide or other materials, which is passivated in this embodiment.
  • the material is silicon oxide.
  • FIG. 10 is a schematic structural view of a thin film transistor formed after steps S242-S252 in the second formation mode of the insulating spacer layer shown in FIG. 9.
  • the semiconductor layer 140 is formed on a side of the insulating layer 130 facing away from the gate layer 120.
  • the conductor layer 150 is formed on a side of the semiconductor layer 140 facing away from the insulating layer 130.
  • the insulating spacer layer 160 is formed at both ends of the semiconductor layer 140, and the source and drain are formed.
  • the pole layer 170 is formed over the conductor layer 150 and the insulating spacer layer 160, and the passivation layer 180 is formed over the source drain layer 170, the semiconductor layer 140, and the insulating spacer layer 160, and other labeled portions are shown in FIG. The description is the same.
  • the manufacturing method of the thin film transistor of this embodiment includes preparing a substrate, disposing a gate layer and an insulating layer on the substrate, sequentially providing a semiconductor layer and a conductor layer on the insulating layer, and providing an insulating spacer layer on the insulating layer, and spacing between the conductor layer and the insulating layer a source drain layer is disposed on the layer, a passivation layer is disposed on the source drain layer and the semiconductor layer, and an insulating spacer layer is disposed on the insulating layer to form an insulation greater than or equal to a height of the semiconductor layer on sidewalls or both ends of the semiconductor layer
  • the spacer layer has a effect of preventing the source/drain layer from coming into contact with the semiconductor layer to cause an increase in the leakage path, and has an effect of reducing leakage current.
  • FIG. 11 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention
  • FIG. 12 is a schematic structural diagram of a liquid crystal display panel according to another embodiment of the present invention.
  • the liquid crystal display panel comprises the above-mentioned thin film transistor, and the liquid crystal display panel differs only in the shape of the insulating spacer layer on the thin film transistor on the liquid crystal display panel, so the two embodiments of FIG. 11 and FIG. 12
  • the same reference numerals as in Figs. 1 and 2 are used.
  • the thin film transistor 100 on the liquid crystal display panel 200 has a laminated structure, and the above layers are sequentially formed on the substrate 110, and the substrate 110 may be a glass substrate.
  • the gate layer 120 is formed on the substrate 110, and the insulating layer 130 covers the gate layer 120.
  • the thin film transistor 100 is a bottom gate structure.
  • the semiconductor layer 140 is formed as an active layer of the thin film transistor 100 on the insulating layer 130; the conductive layer 150 is formed on the semiconductor layer 140 for connecting the semiconductor layer 140 and the source and drain layers 170, and the source and drain layers 170 pass between After the conductor layer 150 is formed with a current through the semiconductor layer 140, the semiconductor layer 140 is directly connected to the source and drain layer 170. In this embodiment, the conductor layer 150 has a small resistance, and the source and drain layers 170 and the semiconductor layer 140 can be reduced. Leakage current condition.
  • An insulating spacer layer 160 is further formed on the insulating layer 130 in the embodiment, that is, the insulating spacer layer 160 is disposed in the same layer as the semiconductor layer 140; the source and drain layer 170 is formed on the conductor layer 150 and the insulating spacer layer 160, and The insulating spacer layer 160 is located between the semiconductor layer 140 and the source and drain layers 170.
  • the conductive layer 150 and the insulating spacer layer 160 are disposed between the semiconductor layer 140 and the source and drain layers 170, that is, there is no direct contact connection between the semiconductor layer 140 and the source and drain layers 170, thereby effectively reducing the semiconductor layer 140. Leakage current between the source and drain layers 170.
  • the semiconductor layer 140 has a channel region 141 which divides the semiconductor layer 140 into left and right portions, and a conductor layer 150 is formed on the left and right portions of the semiconductor layer 140 to form a two-island structure.
  • the source and drain layers 170 formed on the two island structures of the conductor layer 150 are also distinguished as a source and a drain.
  • the passivation layer 180 is formed on the source and drain layers 170 and the semiconductor layer 140, specifically formed on the channel region 141 of the semiconductor 140, and formed between the two island structures of the conductor layer 150.
  • the insulating layer 130, the insulating spacer layer 160, and the passivation layer 180 are all made of an insulating material, and may be silicon oxide or silicon nitride.
  • the gate layer 120 and the source/drain layer 170 are made of a metal material, and may be a metal material such as molybdenum or aluminum, or a metal material of a combination of molybdenum-aluminum-molybdenum.
  • the semiconductor layer 140 may be polysilicon, and the conductor layer 150 may be a P+ conductor layer formed of polysilicon doped with B ions.
  • the insulating spacer layer 160 in this embodiment may be formed on the insulating layer 130 in various ways, such as the two modes shown in FIGS. 11 and 12.
  • an insulating spacer layer 160 is formed on the insulating layer 130 and has a first thickness h1 and a second thickness h2, the second thickness h2 is smaller than the first thickness h1, and the second thickness h2 is greater than or equal to the thickness of the semiconductor layer 140.
  • H3 the second thickness h2 of the insulating spacer layer in FIG. 11 is equal to the thickness h3 of the semiconductor layer 140.
  • the structure of the insulating spacer layer 160 in FIG. 11 is such that the source and drain layers 170 are not formed on the insulating layer 130, and then the distance between the source and drain layers 170 and the gate layer 120 is increased, which prevents breakdown and can be reduced.
  • the formed passivation layer 180 is further disposed on the insulating spacer layer 160.
  • the insulating spacer layer 160 is formed on the side of the semiconductor layer 140 and the conductor layer 150 on the insulating layer 130, and the thickness h thereof may be greater than or equal to the thickness h3 of the semiconductor layer 140.
  • the thickness h of the insulating spacer layer 160 in FIG. 12 is larger than that of the semiconductor.
  • Layer 140 has a thickness h3 and is equal to the thickness h3+h4 of both semiconductor layer 140 and conductor layer 150.
  • the source and drain layers 170 are further disposed on the insulating layer 130, the insulating spacer layer 160 can be located between the conductor layer 150 and the source and drain layers 170, and the passivation layer 180 is further disposed in the insulating layer.
  • the passivation layer 180 is further disposed in the insulating layer.
  • the insulating spacer layer of the thin film transistor on the liquid crystal display panel is located between the source and drain layers and the semiconductor layer, which can block the direct contact between the source and drain layers and the semiconductor layer, thereby reducing the problem of leakage current, thereby improving the thin film transistor. performance.

Abstract

一种薄膜晶体管（100）及薄膜晶体管（100）的制造方法、液晶显示面板（200），涉及显示技术领域。该薄膜晶体管（100）包括基板（110）、栅极层（120）及绝缘层（130），栅极层（120）形成于基板（110）上，绝缘层（130）覆盖于栅极层（120）；半导体层（140），形成于绝缘层（130）上；导体层（150），形成于半导体层（140）上；绝缘间隔层（160），形成在绝缘层（130）上；源漏极层（170），形成在导体层（150）和绝缘间隔层（160）上；钝化层（180），形成于源漏极层（170）和半导体层（140）上；其中，绝缘间隔层（160）位于源漏极层（170）和半导体层（140）之间，可以解决薄膜晶体管（100）存在漏电流过大的问题。

Description

薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板。
【背景技术】
薄膜晶体管(Thin Film Transistor，简称TFT)广泛应用于液晶显示装置(Liquid Crystal Display，简称LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light-Emitting Diode，简称AMOLED)中，因此，薄膜晶体管影响到显示行业的发展。然而当前薄膜晶体管的制造方法中，形成的薄膜晶体管存在漏电流过大的问题，导致薄膜晶体管的特性受到影响。
【发明内容】
本发明实施例提供一种薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板，以解决薄膜晶体管存在漏电流过大的问题。
为解决上述技术问题，本发明实施例采用的一个技术方案是：提供一种薄膜晶体管，该薄膜晶体管包括基板、栅极层及绝缘层，栅极层形成于基板上，绝缘层覆盖于栅极层；半导体层，形成于绝缘层上；导体层，形成于半导体层上；绝缘间隔层，形成在绝缘层上；源漏极层，形成在导体层和绝缘间隔层上；钝化层，形成于源漏极层和半导体层上；其中，绝缘间隔层位于源漏极层和半导体层之间。
为解决上述技术问题，本发明实施例采用的另一个技术方案是：提供一种薄膜晶体管的制造方法，该制造方法包括基板；在基板上设置栅极层及绝缘层，绝缘层覆盖于栅极层；在绝缘层上依次设置半导体层和导体层；在绝缘层上设置绝缘间隔层；在导体层和绝缘间隔层上设置源漏极层；其中绝缘间隔层位于源漏极层和半导体层之间；在源漏极层和半导体层上设置钝化层。
为解决上述技术问题，本发明实施例采用的又一个技术方案是：提供一种液晶显示面板，该液晶显示面板包括薄膜晶体管，该薄膜晶体管包括：
基板、栅极层及绝缘层，栅极层形成于基板上，绝缘层覆盖于栅极层；
半导体层，形成于绝缘层上；
导体层，形成于半导体层上；
半导体层具有一沟道区，沟道区将半导体层分为左右部分，导体层形成于半导体层的左右部分上，以形成两岛体结构；
绝缘间隔层，形成在绝缘层上；
源漏极层，形成在导体层和绝缘间隔层上；
钝化层，形成于源漏极层和半导体层上；
其中，绝缘间隔层位于源漏极层和半导体层之间；
栅极层和源漏极层为金属材料；
绝缘层、绝缘间隔层以及钝化层均为绝缘材料。
本发明的有益效果是：通过在基板上设置栅极层及绝缘层，绝缘层覆盖于栅极层；在绝缘层上依次设置半导体层和导体层；在绝缘层上设置绝缘间隔层；在导体层和绝缘间隔层上设置源漏极层；其中绝缘间隔层位于源漏极层和半导体层之间；在源漏极层和半导体层之间设置绝缘间隔层，能够阻止源漏极层与半导体层直接接触，从而实现减小漏电流的情况，改善薄膜晶体管的特性。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一实施例薄膜晶体管的结构示意图；
图2是本发明另一实施例薄膜晶体管的结构示意图；
图3是本发明一实施例薄膜晶体管的制造方法的流程示意图；
图4是本发明另一实施例薄膜晶体管的制造方法的流程示意图；
图5是图4所示薄膜晶体管的制造方法步骤S22中形成的玻璃基板的结构示意图；
图6是图4所示薄膜晶体管的制造方法步骤S23中形成的玻璃基板的结构示意图；
图7是图4所示薄膜晶体管的制造方法中绝缘间隔层第一种形成方式的流程示意图；
图8是图7所示绝缘间隔层第一种形成方式中步骤S231-S251后形成的薄膜晶体管的结构示意图；
图9是图4所示薄膜晶体管的制造方法中绝缘间隔层第二种形成方式的流程示意图；
图10是图9所示绝缘间隔层第二种形成方式中步骤S242-S252后形成的薄膜晶体管的结构示意图；
图11是本发明一实施例一种液晶显示面板的结构示意图；
图12是本发明另一实施例一种液晶显示面板的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
请参阅图1和图2，图1是本发明一实施例薄膜晶体管的结构示意图，图2是本发明另一实施例薄膜晶体管的结构示意图。
在图1和图2两实施例中，薄膜晶体管的区别仅仅在于绝缘间隔层形状的不同，因此图1和图2的两实施例均采用相同标号。
薄膜晶体管100包括基板110、栅极层120、绝缘层130、半导体层140、导体层150、绝缘间隔层160、源漏极层170以及钝化层180。
薄膜晶体管100为层叠结构，上述各层依次形成在基板110上，基板110可以为玻璃基板。其中，栅极层120形成于基板110上，绝缘层130覆盖于栅极层120，本实施例中薄膜晶体管100为底栅结构。
半导体层140作为薄膜晶体管100的有源层，形成于绝缘层130上；导体层150形成于半导体层140上，用于连接半导体层140和源漏极层170，源漏极层170之间通过导体层150后经由半导体层140形成电流，相较于源漏极层170直接连接半导体层140，本实施例中导体层150电阻较小，能够减少源漏极层170与半导体层140之间的漏电流情况。
本实施例中的绝缘层130上还形成有绝缘间隔层160，即该绝缘间隔层160与半导体层140同层设置；源漏极层170则形成在导体层150和绝缘间隔层160上，且绝缘间隔层160位于半导体层140和源漏极层170之间。
在实施例中半导体层140和源漏极层170之间设置有导体层150和绝缘间隔层160，即半导体层140与源漏极层170之间没有直接接触连接，因而能够有效减少半导体层140与源漏极层170之间的漏电流。
半导体层140具有一沟道区141，沟道区141将半导体层140分为左右部分，导体层150形成在半导体层140的左右部分上，形成两岛体结构。形成在导体层150两岛体结构上的源漏极层170也被区分为源极和漏极。
钝化层180形成于源漏极层170和半导体层140上，具体形成于半导体140的沟道区141上，且形成于导体层150的两岛体结构之间。
对于上述结构的薄膜晶体管100，其中绝缘层130、绝缘间隔层160以及钝化层180均为绝缘材料，可以为氧化硅或氮化硅。栅极层120和源漏极层170则为金属材料，可以为钼、铝的等金属材料，还可为钼-铝-钼三层组合的金属材料。半导体层140可以为多晶硅，导体层150则可以为掺杂B离子的多晶硅所形成的P+导体层。
此外，本实施例中绝缘间隔层160可以以多种方式形成在绝缘层130上，例如图1和图2所示的两种方式。
图1中，绝缘间隔层160形成在绝缘层130上，且具有第一厚度h1和第二厚度h2，第二厚度h2小于第一厚度h1，并且第二厚度h2大于或等于半导体层140的厚度h3，图1中绝缘间隔层的第二厚度h2等于半导体层140的厚度h3。图1中绝缘间隔层160的结构使得源漏极层170不会形成在绝缘层130上，继而增到了源漏极层170与栅极层120之间的距离，可防止击穿，且能够减少源漏极层170与栅极层120之间的寄生电容。在图1中，所形成的钝化层180进一步设置于绝缘间隔层160上。
图2中，绝缘间隔层160形成于半导体层140和导体层150侧面，位于绝缘层130上，其厚度h可以大于或等于半导体层140的厚度h3，图2中绝缘间隔层160厚度h大于半导体层140厚度h3，且等于半导体层140和导体层150二者的厚度h3+h4。图2中绝缘间隔层160的结构使得源漏极层170进一步设置在绝缘层130上，绝缘间隔层160能够位于导体层150和源漏极层170之间，钝化层180则进一步设置在绝缘层130上。
上述实施例中绝缘间隔层位于源漏极层和半导体层之间，能够阻隔源漏极层和半导体层的直接接触，减少漏电流的问题，从而提高薄膜晶体管的性能。
为制得上述薄膜晶体管，本发明还提出一种薄膜晶体管的制造方法，请参阅图3，图3是本发明一实施例薄膜晶体管的制造方法的流程示意图。在本实施例中，薄膜晶体管的制造方法可以包括以下步骤：
S11：准备基板。
准备制造薄膜晶体管的基板，该基板可以是玻璃基板。
S12：在基板上设置栅极层及绝缘层。
在本步骤S12中，在上述步骤S11中准备的玻璃基板上沉积一层金属使之图形化形成栅极层，在本实施例中形成栅极层的金属材料是钼，在其他实施例中也可以是其他的金属材料；再在已经设置完成的栅极层上设置一层绝缘层，其中绝缘层是覆盖在栅极层上的，即栅极层形成在基板和绝缘层中间，在本实施例中绝缘层的材料是氧化硅，在其他实施例中也可以是氮化硅或其他能够达到绝缘目的的材料，在本步骤中形成的玻璃基板用于下述步骤S13中使用。
S13：在绝缘层上依次设置半导体层和导体层。
在本步骤S13中，在上述步骤S12中得到的玻璃基板上继续设置半导体层和导体层，具体来说，在绝缘层上表面设置一层半导体层，再在半导体层上表面设置一层导体层，半导体层形成于绝缘层的上表面，即绝缘层在半导体层和栅极层之间，半导体层在绝缘层和导体层中间。
S14：在绝缘层上设置绝缘间隔层。
在本步骤S14中，继续在上述步骤S13中的到的玻璃基板上进行处理，在上述步骤S13中形成导体层和半导体层后，在绝缘层之上设置一层绝缘间隔层，绝缘间隔层形成于半导体层的两端，并且绝缘间隔层与半导体层接触的部分高度大于或等于半导体层的高度。
S15：在导体层和绝缘间隔层上设置源漏极层。
在本步骤S15中，继续在上述步骤S14中得到的玻璃基板上进行处理，在上述步骤S14中形成绝缘间隔层之后，在导体层上和绝缘间隔层上设置一层源漏极层，此时绝缘间隔层位于半导体层两端，且还位于源漏极层和半导体层之间。
S16：在源漏极层和半导体层上设置钝化层。
在本步骤S16中，继续在上述步骤S15中得到的玻璃基板上进行处理，在上述步骤中设置源漏极层之后，进一步还形成由源漏极层、导体层与半导体层的上表面共同组成的沟道，在源漏极层和半导体层上设置钝化层以完成薄膜晶体管的制造，钝化层设置于源漏极层和半导体层的上方，并且与导体层接触，即钝化层覆盖在沟道上起保护作用。
本实施例薄膜晶体管的制造方法包括准备基板，在基板上设置栅极层及绝缘层，在绝缘层上依次设置半导体层和导体层，在绝缘层上设置绝缘间隔层，在导体层和绝缘间隔层上设置源漏极层，在源漏极层和半导体层上设置钝化层，通过在绝缘层上设置绝缘间隔层，在半导体层的两端形成大于或等于半导体层高度的绝缘间隔层，有防止源漏极层与半导体层相接触而导致增大漏电路径的情况发生，有减小漏电流的效果。
请参阅图4，图4是本发明另一实施例薄膜晶体管的制造方法的流程示意图。在本实施例中，薄膜晶体管的制造方法可以包括以下步骤：
S21：准备基板。
准备制造薄膜晶体管的基板，该基板可以是玻璃基板。
S22：在基板上设置栅极层及绝缘层。
在本步骤S22中，首先会在玻璃基板上设置栅极层和绝缘层，具体来说，在玻璃基板上利用PVD（Physical Vapor Deposition，物理气相沉积）技术沉积一层金属，并且图形化以形成栅极层，在本实施例中形成栅极层的金属材料是钼，当然在其他实施例中也可以是其他金属材料；接着再利用PECVD（Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积法）技术沉积一层绝缘物质形成绝缘层，绝缘层是覆盖在栅极层上的，即栅极层形成在玻璃基板和绝缘层中间，在本实施例中绝缘层的材料是氧化硅，在其他实施例中也可以是氮化硅或其他能够达到绝缘目的的材料。
本步骤S22完成后，得到形成有栅极层和绝缘层的玻璃基板，可结合图5理解，图5是图4所示薄膜晶体管的制造方法步骤S22中形成的玻璃基板的结构示意图，图5中示出玻璃基板110、栅极层120及绝缘层130，栅极层120形成于基板110上，绝缘层130覆盖于栅极层120。
S23：在绝缘层上依次设置半导体层和导体层。
在本步骤S23中，在上述步骤S22中得到的玻璃基板上继续设置半导体层和导体层，具体来说，在绝缘层上利用PECVD技术沉积一层非晶硅材料，在非晶硅材料中进行掺杂处理以及结晶处理，以形成靠近绝缘层的多晶硅材料以及远离绝缘层的导体材料，具体来说，在非晶硅材料中通过离子注入技术植入一定剂量的B离子，在本实施例中，B离子的植入剂量可以根据实际需求进行设定，例如植入0.1毫升、0.5毫升、1毫升等等，利用快速加热技术在650℃（±50℃）的温度下加热15min（±1min）就可以结晶，加热的温度和时间可以根据实际情况进行设定，在本实施例中，利用快速加热技术在650℃的温度下加热15min使非晶硅进行结晶，由于上表面中含有较多的B离子，结晶的温度和时间会被降低，所以结晶方向是从上向下进行的，形成远离绝缘层的导体材料和靠近绝缘层的多晶硅材料，将多晶硅材料和导体材料进行图案化处理，则得到半导体层和导体层。
对于本步骤S23可结合图6进行理解，图6是图4所示薄膜晶体管的制造方法步骤S23中形成的玻璃基板的结构示意图，图6中示出半导体层140形成于绝缘层130上，导体层150形成于半导体层140上，其他标号部分与图5中描述相同。
S24：在绝缘层上设置绝缘间隔层，在导体层和绝缘间隔层上设置源漏极层。
S25：在源漏极层和半导体层上设置钝化层。
步骤S24中，在上述步骤S23中得到的玻璃基板上形成的绝缘层上设置绝缘间隔层和源漏极层，在本实施例中，绝缘间隔层的形成方式有多种，且绝缘间隔层的形成涉及到步骤S23和步骤S25的不同，因此下面对步骤S23-S25共同进行说明，以下给出两种形成方式S231-S251和S242-S252。
对于第一种绝缘间隔层的情况，请参阅图7，图7是图4所示薄膜晶体管的制造方法中绝缘间隔层第一种形成方式的流程示意图。
S231：在绝缘层上依次设置半导体层和导体层，导体层上设置有光阻材料。
S241：对半导体层和导体层进行氧化处理，以形成设置于绝缘层上的绝缘间隔层，去除光阻材料，在导体层和绝缘间隔层上设置源漏极层。
具体来说，在步骤S231中依次设置半导体层和导体层，会在导体层上覆盖一层光阻材料，通过光照和干法刻蚀来定义导体层区域，此时光阻材料先不用除去，再在步骤S241中对半导体层和导体层进行氧化处理以形成设置于绝缘层上的绝缘间隔层，在本实施例中，氧化处理是通过氧气等离子体对半导体层的侧壁进行处理，从而形成一层侧壁的氧化硅层，即绝缘间隔层，此时绝缘间隔层还形成在绝缘层上，其中绝缘间隔层的高度大于或等于半导体层侧壁的高度。
在形成绝缘间隔层后，就可以去除光阻材料，再设置源漏极层，具体来说，去除光阻材料后，利用PVD技术沉积一层由钼-铝-钼三层叠加的金属材料，将近其图案化处理以形成源漏极层，此时源漏极层只与导体层的上表面接触，绝缘间隔层位于源漏极层和半导体层之间，源漏极层的侧壁由于绝缘间隔层的阻挡不与半导体层接触。
S251：在源漏极层和半导体层上设置钝化层。
在本步骤S251中，在上述步骤S241中得到的玻璃基板上形成沟道，再在源漏极层和半导体层上设置钝化层，钝化层用来保护形成的薄膜晶体管的沟道。
具体来说，以上述步骤S241中形成的源漏极层为金属电极，将其做为光罩进行对导体层进行干法刻蚀以形成沟道，将沟道上表面的导体层去除掉，留下下部的沟道半导体层，从而得到薄膜晶体管，此时再利用PECVD沉积一层钝化材料，图案化以形成钝化层，钝化材料可以是氧化硅或其他材料，本实施例中钝化材料为氧化硅。
请结合图8，图8是图7所示绝缘间隔层第一种形成方式中步骤S231-S251后形成的薄膜晶体管的结构示意图，半导体层140形成于绝缘层130上背离栅极层120的一侧，导体层150形成于半导体层140上背离绝缘层130的一侧，绝缘间隔层160形成于半导体层140的侧壁，还形成于绝缘层130上，源漏极层170形成在导体层150和绝缘间隔层160的上方，进一步来说，源漏极层170还形成在绝缘层130的上方，钝化层180形成在源漏极层170、半导体层140以及绝缘层130的上方，图8中示出其他标号部分与图6中描述相同。
对于第二种形成绝缘间隔层的情况，请参阅图9，图9是图4所示薄膜晶体管的制造方法中绝缘间隔层第二种形成方式的流程示意图。
S242：在导体层和绝缘层上沉积绝缘材料，对绝缘材料进行图案化处理，去除导体层上的绝缘材料，在绝缘层上形成绝缘间隔层。
具体来说，在上述步骤S23中形成的导体层和在步骤S22中形成绝缘层上沉积一层绝缘材料，在本实施例中绝缘材料可以是氧化硅或者氮化硅，绝缘材料的厚度大于或等于半导体层的厚度，利用光照和干法刻蚀使绝缘材料进行图案化处理，去除导体层上的绝缘材料，以在半导体层的两端形成一层绝缘的氧化硅或氮化硅，即绝缘间隔层，此时绝缘间隔层还形成在绝缘层上。
形成绝缘间隔层后，再设置源漏极层，具体来说，去除光阻材料后，利用PVD技术沉积一层由钼-铝-钼三层叠加的金属材料，将近其图案化处理以形成源漏极层，此时源漏极层只与导体层的上表面接触，绝缘间隔层位于源漏极层和半导体层之间，源漏极层的侧壁由于绝缘间隔层的阻挡不与半导体层接触。
S252：在源漏极层和半导体层上设置钝化层。
在本步骤S252中，在上述步骤S242中得到的玻璃基板上形成沟道，再在源漏极层和半导体层上设置钝化层，钝化层用来保护形成的薄膜晶体管的沟道。
具体来说，以上述步骤S24中形成的源漏极层为金属电极，将其做为光罩进行对导体层进行干法刻蚀以形成沟道，将沟道上表面的导体层去除掉，留下下部的沟道半导体层，从而得到薄膜晶体管，此时再利用PECVD沉积一层钝化材料，图案化以形成钝化层，钝化材料可以是氧化硅或其他材料，本实施例中钝化材料为氧化硅。
请结合图10理解，图10是图9所示绝缘间隔层第二种形成方式中步骤S242-S252后形成的薄膜晶体管的结构示意图。半导体层140形成于绝缘层130上背离栅极层120的一侧，导体层150形成于半导体层140上背离绝缘层130的一侧，绝缘间隔层160形成于半导体层140的两端，源漏极层170形成在导体层150和绝缘间隔层160的上方，钝化层180形成在源漏极层170、半导体层140以及绝缘间隔层160的上方，图10中示出其他标号部分与图6中描述相同。
本实施例薄膜晶体管的制造方法包括准备基板，在基板上设置栅极层及绝缘层，在绝缘层上依次设置半导体层和导体层，在绝缘层上设置绝缘间隔层，在导体层和绝缘间隔层上设置源漏极层，在源漏极层和半导体层上设置钝化层，通过在绝缘层上设置绝缘间隔层，在半导体层的侧壁或两端形成大于或等于半导体层高度的绝缘间隔层，有防止源漏极层与半导体层相接触而导致增大漏电路径的情况发生，有减小漏电流的效果。
请参阅图11和图12，图11是本发明一实施例一种液晶显示面板的结构示意图，图12是本发明另一实施例一种液晶显示面板的结构示意图。
在图11和图12两实施例中，液晶显示面板包含上述薄膜晶体管，且液晶显示面板的区别仅仅在于液晶显示面板上薄膜晶体管上绝缘间隔层形状的不同，因此图11和图12两实施例均采用与图1和图2相同标号。
液晶显示面板200上的薄膜晶体管100为层叠结构，上述各层依次形成在基板110上，基板110可以为玻璃基板。其中，栅极层120形成于基板110上，绝缘层130覆盖于栅极层120，本实施例中薄膜晶体管100为底栅结构。
半导体层140作为薄膜晶体管100的有源层，形成于绝缘层130上；导体层150形成于半导体层140上，用于连接半导体层140和源漏极层170，源漏极层170之间通过导体层150后经由半导体层140形成电流，相较于源漏极层170直接连接半导体层140，本实施例中导体层150电阻较小，能够减少源漏极层170与半导体层140之间的漏电流情况。
本实施例中的绝缘层130上还形成有绝缘间隔层160，即该绝缘间隔层160与半导体层140同层设置；源漏极层170则形成在导体层150和绝缘间隔层160上，且绝缘间隔层160位于半导体层140和源漏极层170之间。
在实施例中半导体层140和源漏极层170之间设置有导体层150和绝缘间隔层160，即半导体层140与源漏极层170之间没有直接接触连接，因而能够有效减少半导体层140与源漏极层170之间的漏电流。
半导体层140具有一沟道区141，沟道区141将半导体层140分为左右部分，导体层150形成在半导体层140的左右部分上，形成两岛体结构。形成在导体层150两岛体结构上的源漏极层170也被区分为源极和漏极。
钝化层180形成于源漏极层170和半导体层140上，具体形成于半导体140的沟道区141上，且形成于导体层150的两岛体结构之间。
对于上述结构的薄膜晶体管100，其中绝缘层130、绝缘间隔层160以及钝化层180均为绝缘材料构，可以为氧化硅或氮化硅。栅极层120和源漏极层170则为金属材料，可以为钼、铝的等金属材料，还可为钼-铝-钼三层组合的金属材料。半导体层140可以为多晶硅，导体层150则可以为掺杂B离子的多晶硅所形成的P+导体层。
此外，本实施例中绝缘间隔层160可以以多种方式形成在绝缘层130上，例如图11和图12所示的两种方式。
图11中，绝缘间隔层160形成在绝缘层130上，且具有第一厚度h1和第二厚度h2，第二厚度h2小于第一厚度h1，并且第二厚度h2大于或等于半导体层140的厚度h3，图11中绝缘间隔层的第二厚度h2等于半导体层140的厚度h3。图11中绝缘间隔层160的结构使得源漏极层170不会形成在绝缘层130上，继而增到了源漏极层170与栅极层120之间的距离，可防止击穿，且能够减少源漏极层170与栅极层120之间的寄生电容。在图11中，所形成的钝化层180进一步设置于绝缘间隔层160上。
图12中，绝缘间隔层160形成于半导体层140和导体层150侧面，位于绝缘层130上，其厚度h可以大于或等于半导体层140的厚度h3，图12中绝缘间隔层160厚度h大于半导体层140厚度h3，且等于半导体层140和导体层150二者的厚度h3+h4。图12中绝缘间隔层160的结构使得源漏极层170进一步设置在绝缘层130上，绝缘间隔层160能够位于导体层150和源漏极层170之间，钝化层180则进一步设置在绝缘层130上。
上述实施例中，液晶显示面板上薄膜晶体管的绝缘间隔层位于源漏极层和半导体层之间，能够阻隔源漏极层和半导体层的直接接触，减少漏电流的问题，从而提高薄膜晶体管的性能。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种液晶显示面板，所述液晶显示面板包括薄膜晶体管，其中，所述薄膜晶体管包括：
    基板、栅极层及绝缘层，所述栅极层形成于所述基板上，所述绝缘层覆盖于所述栅极层；
    半导体层，形成于所述绝缘层上；
    导体层，形成于半导体层上；
    所述半导体层具有一沟道区，所述沟道区将所述半导体层分为左右部分，所述导体层形成于所述半导体层的左右部分上，以形成两岛体结构；
    绝缘间隔层，形成在所述绝缘层上；
    源漏极层，形成在所述导体层和所述绝缘间隔层上；
    钝化层，形成于所述源漏极层和所述半导体层上；
    其中，所述绝缘间隔层位于所述源漏极层和所述半导体层之间；
    所述栅极层和所述源漏极层为金属材料；
    所述绝缘层、所述绝缘间隔层以及所述钝化层均为绝缘材料。
  2. 根据权利要求1所述的液晶显示面板，其中，所述源漏极层进一步设置在所述绝缘层上，所述绝缘间隔层进一步位于所述导体层与所述源漏极层之间，所述钝化层进一步设置在所述绝缘层上。
  3. 根据权利要求2所述的液晶显示面板，其中，所述绝缘间隔层的厚度大于或等于所述半导体层的厚度。
  4. 根据权利要求1所述的液晶显示面板，其中，所述钝化层进一步设置在所述绝缘间隔层上，所述绝缘间隔层至少包括第一厚度和第二厚度，所述第二厚度小于所述第一厚度，并且所述第二厚度大于或等于所述半导体层的厚度。
  5. 根据权利要求1所述的液晶显示面板，其中，所述绝缘间隔层包括氧化硅或氮化硅。
  6. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基板、栅极层及绝缘层，所述栅极层形成于所述基板上，所述绝缘层覆盖于所述栅极层；
    半导体层，形成于所述绝缘层上；
    导体层，形成于半导体层上；
    绝缘间隔层，形成在所述绝缘层上；
    源漏极层，形成在所述导体层和所述绝缘间隔层上；
    钝化层，形成于所述源漏极层和所述半导体层上；
    其中，所述绝缘间隔层位于所述源漏极层和所述半导体层之间。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述源漏极层进一步设置在所述绝缘层上，所述绝缘间隔层进一步位于所述导体层与所述源漏极层之间，所述钝化层进一步设置在所述绝缘层上。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述绝缘间隔层的厚度大于或等于所述半导体层的厚度。
  9. 根据权利要求6所述的薄膜晶体管，其中，所述钝化层进一步设置在所述绝缘间隔层上，所述绝缘间隔层至少包括第一厚度和第二厚度，所述第二厚度小于所述第一厚度，并且所述第二厚度大于或等于所述半导体层的厚度。
  10. 根据权利要求6所述的薄膜晶体管，其中，所述绝缘间隔层包括氧化硅或氮化硅。
  11. 一种薄膜晶体管的制造方法，其中，所述制造方法包括：
    基板；
    在所述基板上设置栅极层及绝缘层，所述绝缘层覆盖于所述栅极层；
    在所述绝缘层上依次设置半导体层和导体层；
    在所述绝缘层上设置绝缘间隔层；
    在所述导体层和所述绝缘间隔层上设置源漏极层；
    其中所述绝缘间隔层位于所述源漏极层和所述半导体层之间；
    在所述源漏极层和所述半导体层上设置钝化层。
  12. 根据权利要求11所述的制造方法，其中，所述制造方法进一步包括：
    在所述绝缘层上依次设置半导体层和导体层，所述导体层上设置有光阻材料；
    对所述半导体层和导体层进行氧化处理，以形成设置于所述绝缘层上的绝缘间隔层；
    去除光阻材料，在所述导体层和所述绝缘间隔层上设置源漏极层。
  13. 根据权利要求11所述的制造方法，其中，所述制造方法进一步包括：
    在所述导体层和所述绝缘层上沉积绝缘材料；
    对所述绝缘材料进行图案化处理，去除所述导体层上的绝缘材料，在所述绝缘层上形成绝缘间隔层。
  14. 根据权利要求12所述的制造方法，其中，所述在所述绝缘层上依次设置半导体层和导体层的步骤包括：
    在所述绝缘层上沉积非晶硅材料；
    在所述非晶硅材料进行掺杂处理以及结晶处理，形成靠近所述绝缘层的多晶硅材料以及远离所述绝缘层的导体材料；
    对所述多晶硅材料和所述导体材料进行图案化处理，得到半导体层和导体层。
  15. 根据权利要求13所述的制造方法，其中，所述在所述绝缘层上依次设置半导体层和导体层的步骤包括：
    在所述绝缘层上沉积非晶硅材料；
    在所述非晶硅材料进行掺杂处理以及结晶处理，形成靠近所述绝缘层的多晶硅材料以及远离所述绝缘层的导体材料；
    对所述多晶硅材料和所述导体材料进行图案化处理，得到半导体层和导体层。
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Publication number Priority date Publication date Assignee Title
CN109240004A (zh) * 2018-10-08 2019-01-18 深圳市华星光电半导体显示技术有限公司 提高显示器对比度的方法及装置
CN109560085A (zh) * 2018-12-10 2019-04-02 武汉华星光电半导体显示技术有限公司 显示面板及显示模组
CN110581177A (zh) 2019-08-13 2019-12-17 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法
CN110993611A (zh) * 2019-11-26 2020-04-10 武汉华星光电半导体显示技术有限公司 一种tft基板的制作方法和tft基板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1335533A (zh) * 2000-07-25 2002-02-13 达碁科技股份有限公司 薄膜晶体管液晶显示器及其制造方法
CN101005083A (zh) * 2006-11-03 2007-07-25 京东方科技集团股份有限公司 一种tft阵列结构及其制造方法
CN101150073A (zh) * 2007-11-07 2008-03-26 友达光电股份有限公司 一种薄膜晶体管及其制造方法
CN104617152A (zh) * 2015-01-27 2015-05-13 深圳市华星光电技术有限公司 氧化物薄膜晶体管及其制作方法
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5743064B2 (ja) * 2011-02-17 2015-07-01 株式会社Ｊｏｌｅｄ 薄膜トランジスタおよびその製造方法、並びに表示装置
US20150214375A1 (en) * 2012-09-12 2015-07-30 Sharp Kabushiki Kaisha Circuit substrate, manufacturing method thereof and display device
US9716183B2 (en) * 2014-03-11 2017-07-25 Sharp Kabushiki Kaisha Semiconductor device and method of manufacturing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1335533A (zh) * 2000-07-25 2002-02-13 达碁科技股份有限公司 薄膜晶体管液晶显示器及其制造方法
CN101005083A (zh) * 2006-11-03 2007-07-25 京东方科技集团股份有限公司 一种tft阵列结构及其制造方法
CN101150073A (zh) * 2007-11-07 2008-03-26 友达光电股份有限公司 一种薄膜晶体管及其制造方法
CN104617152A (zh) * 2015-01-27 2015-05-13 深圳市华星光电技术有限公司 氧化物薄膜晶体管及其制作方法
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法

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