WO2019056517A1 - 薄膜晶体管结构及其制作方法 - Google Patents

薄膜晶体管结构及其制作方法 Download PDF

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Publication number
WO2019056517A1
WO2019056517A1 PCT/CN2017/109826 CN2017109826W WO2019056517A1 WO 2019056517 A1 WO2019056517 A1 WO 2019056517A1 CN 2017109826 W CN2017109826 W CN 2017109826W WO 2019056517 A1 WO2019056517 A1 WO 2019056517A1
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Prior art keywords
metal
layer
angstroms
oxide semiconductor
glass substrate
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PCT/CN2017/109826
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English (en)
French (fr)
Inventor
余明爵
任章淳
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to EP17926191.2A priority Critical patent/EP3686936A4/en
Priority to KR1020207011380A priority patent/KR20200055772A/ko
Priority to US15/578,256 priority patent/US10355021B2/en
Priority to JP2019567645A priority patent/JP2020523787A/ja
Publication of WO2019056517A1 publication Critical patent/WO2019056517A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor structure and a method of fabricating the same.
  • AMOLED Active-matrix organic light emitting Diodes, active matrix organic light emitting diodes
  • the existing AMOLED display device generally adopts a 3T1C AMOLED driving circuit, that is, three thin film transistors and one capacitor constitute the AMOLED driving circuit.
  • the thin film transistors in the existing AMOLED driving circuit may cause unstable operation of devices such as thin film transistors in the AMOLED driving circuit due to the influence of the outgoing light and the external light, thereby affecting the picture display quality of the AMOLED display device.
  • the object of the present invention is to provide a thin film transistor structure and a manufacturing method thereof, which can improve the operational stability of a device such as a thin film transistor, thereby improving the picture display quality of the corresponding AMOLED display device, and to solve the working stability of the existing thin film transistor structure. Poor technical issues.
  • the metal oxide semiconductor layer disposed on the buffer layer, and setting a position of an active driving region of the thin film transistor structure by the metal oxide semiconductor layer, the metal oxide semiconductor layer including a source region and a drain Polar region and channel region;
  • a gate insulating layer disposed on the metal oxide semiconductor layer for isolating the metal oxide semiconductor layer and the gate metal layer;
  • a gate metal layer disposed on the gate insulating layer
  • a source metal layer disposed on the interlayer insulating layer and connected to a source region of the metal oxide semiconductor layer through the source contact hole;
  • drain metal layer disposed on the interlayer insulating layer and connected to a drain region of the metal oxide semiconductor layer through the drain contact hole;
  • a protective layer disposed on the interlayer insulating layer having the source metal layer and the drain metal layer;
  • the light shielding metal layer is further disposed between the glass substrate and the buffer layer.
  • a metal oxide semiconductor layer contact hole penetrating the gate insulating layer and the buffer layer is further disposed on the gate insulating layer, and the gate metal layer passes through the metal oxide semiconductor layer contact hole and the light shielding metal Layer connection
  • the light shielding metal layer has a thickness of 500 angstroms to 2000 angstroms;
  • the buffer layer has a thickness of 1000 angstroms to 5000 angstroms;
  • the metal oxide semiconductor layer has a thickness of 100 angstroms to 1000 angstroms;
  • the gate insulating layer has a thickness of 1000 angstroms to 3000 angstroms;
  • the interlayer insulating layer has a thickness of 2000 ⁇ to 10000 ⁇ ;
  • the source metal layer has a thickness of 2000 angstroms to 8000 angstroms;
  • the drain metal layer has a thickness of 2000 angstroms to 8000 angstroms;
  • the protective layer has a thickness of 1000 angstroms to 5000 angstroms;
  • the material of the light shielding metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the buffer layer is at least one of silicon oxide and silicon nitride
  • the material of the metal oxide semiconductor layer is at least one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide;
  • the material of the gate insulating layer is at least one of silicon oxide and silicon nitride
  • the material of the gate metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the source metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the drain metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the interlayer insulating layer is at least one of silicon oxide and silicon nitride
  • the material of the protective layer is at least one of silicon oxide and silicon nitride.
  • Embodiments of the present invention also provide a thin film transistor structure, including:
  • the metal oxide semiconductor layer disposed on the buffer layer, and setting a position of an active driving region of the thin film transistor structure by the metal oxide semiconductor layer, the metal oxide semiconductor layer including a source region and a drain Polar region and channel region;
  • a gate insulating layer disposed on the metal oxide semiconductor layer for isolating the metal oxide semiconductor layer and the gate metal layer;
  • a gate metal layer disposed on the gate insulating layer
  • a source metal layer disposed on the interlayer insulating layer and connected to a source region of the metal oxide semiconductor layer through the source contact hole;
  • drain metal layer disposed on the interlayer insulating layer and connected to a drain region of the metal oxide semiconductor layer through the drain contact hole;
  • a protective layer disposed on the interlayer insulating layer having the source metal layer and the drain metal layer;
  • the light shielding metal layer is further disposed between the glass substrate and the buffer layer.
  • a metal oxide semiconductor layer contact hole penetrating the buffer layer of the gate insulating layer is further disposed on the gate insulating layer, and the gate metal layer passes through the metal oxide semiconductor layer contact hole and the light shielding metal layer connection.
  • a projection area of the light shielding metal layer on a plane of the glass substrate covers a projection area of the metal oxide semiconductor layer on a plane of the glass substrate.
  • a projection area of the light shielding metal layer on a plane of the glass substrate covers all corresponding regions of the thin film transistor structure on a plane of the glass substrate.
  • the light shielding metal layer has a thickness of 500 angstroms to 2000 angstroms;
  • the buffer layer has a thickness of 1000 angstroms to 5000 angstroms;
  • the metal oxide semiconductor layer has a thickness of 100 angstroms to 1000 angstroms;
  • the gate insulating layer has a thickness of 1000 angstroms to 3000 angstroms;
  • the interlayer insulating layer has a thickness of 2000 ⁇ to 10000 ⁇ ;
  • the source metal layer has a thickness of 2000 angstroms to 8000 angstroms;
  • the drain metal layer has a thickness of 2000 angstroms to 8000 angstroms;
  • the protective layer has a thickness of from 1000 angstroms to 5000 angstroms.
  • the material of the light shielding metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the gate metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the source metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the drain metal layer is at least one of metal molybdenum, metal aluminum, metallic copper, and metallic titanium.
  • the buffer layer is made of at least one of silicon oxide and silicon nitride
  • the material of the gate insulating layer is at least one of silicon oxide and silicon nitride
  • the material of the interlayer insulating layer is at least one of silicon oxide and silicon nitride
  • the material of the protective layer is at least one of silicon oxide and silicon nitride.
  • the material of the metal oxide semiconductor layer is at least one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide.
  • the invention also provides a method for fabricating a thin film transistor structure, comprising:
  • the metal oxide semiconductor layer includes a source region, a drain region, and a channel region;
  • the source metal layer is connected to a source region of the metal oxide semiconductor layer through a source contact hole; the drain metal layer passes a drain contact hole is connected to a drain region of the metal oxide semiconductor layer;
  • a protective layer is deposited on the glass substrate having the source metal layer and the drain metal layer.
  • a projection area of the light shielding metal layer on a plane of the glass substrate covers a projection area of the metal oxide semiconductor layer on a plane of the glass substrate.
  • a projection area of the light shielding metal layer on a plane of the glass substrate covers all corresponding regions of the thin film transistor structure on a plane of the glass substrate.
  • the thickness of the light shielding metal layer is 500 angstroms to 2000 angstroms;
  • the buffer layer has a thickness of 1000 angstroms to 5000 angstroms;
  • the metal oxide semiconductor layer has a thickness of 100 angstroms to 1000 angstroms;
  • the gate insulating layer has a thickness of 1000 angstroms to 3000 angstroms;
  • the interlayer insulating layer has a thickness of 2000 ⁇ to 10000 ⁇ ;
  • the source metal layer has a thickness of 2000 angstroms to 8000 angstroms;
  • the drain metal layer has a thickness of 2000 angstroms to 8000 angstroms;
  • the protective layer has a thickness of from 1000 angstroms to 5000 angstroms.
  • the material of the light shielding metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the gate metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the source metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium;
  • the material of the drain metal layer is at least one of metal molybdenum, metal aluminum, metallic copper, and metallic titanium.
  • the buffer layer is made of at least one of silicon oxide and silicon nitride
  • the material of the gate insulating layer is at least one of silicon oxide and silicon nitride
  • the material of the interlayer insulating layer is at least one of silicon oxide and silicon nitride
  • the material of the protective layer is at least one of silicon oxide and silicon nitride.
  • the material of the metal oxide semiconductor layer is at least one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium tin oxide.
  • the thin film transistor structure and the manufacturing method thereof of the invention improve the working stability of the thin film transistor and the like in the AMOLED driving circuit through the design of the light shielding metal layer, thereby improving the picture display quality of the corresponding AMOLED display device; and solving the existing film A technical problem of poor stability of the transistor structure.
  • 1a is a schematic structural view of an embodiment of a thin film transistor structure of the present invention.
  • Figure 1b is a top cross-sectional view of A-A' of the thin film transistor structure shown in Figure 1a;
  • FIG. 2 is a flow chart of an embodiment of a method of fabricating a thin film transistor structure of the present invention.
  • FIG. 1a is a schematic structural view of an embodiment of a thin film transistor structure of the present invention
  • FIG. 1b is a top cross-sectional view of the A-A' of the thin film transistor structure shown in FIG. 1a
  • the thin film transistor structure 10 of the present embodiment includes a thin film substrate 11, a buffer layer 12, a metal oxide semiconductor layer 13, a gate insulating layer 14, a gate metal layer 15, an interlayer insulating layer 16, a source metal layer 17, and a drain metal.
  • Layer 18 and protective layer 19 19.
  • the buffer layer 12 is disposed on the glass substrate 11.
  • the metal oxide semiconductor layer 13 is disposed on the buffer layer 12, and sets the position of the active driving region of the thin film transistor structure through the metal oxide semiconductor layer 13, and the metal oxide semiconductor layer 13 includes a source region 131, a drain region 132, and Channel region 133.
  • a gate insulating layer 14 is provided on the metal oxide semiconductor layer 13 for isolating the metal oxide semiconductor layer 13 and the gate metal layer 15.
  • the gate metal layer 15 is disposed on the gate insulating layer 14.
  • the interlayer insulating layer 16 is disposed on the glass substrate 11 having the gate metal layer 15 for planarizing the glass substrate 11 having the gate metal layer 15, and the source contact hole 161 is disposed on the interlayer insulating layer 16. And a drain contact hole 162.
  • the source metal layer 161 is disposed on the interlayer insulating layer 16 and is connected to the source region 131 of the MOS layer 13 through the source contact hole 161.
  • the drain metal layer 162 is disposed on the interlayer insulating layer 16 and is connected to the drain region 132 of the MOS layer 13 through the drain contact hole 162.
  • the protective layer 19 is disposed on the interlayer insulating layer 16 having the source metal layer 17 and the drain metal layer 18.
  • a light shielding metal layer 1A is further disposed between the glass substrate 11 and the buffer layer 12, and a metal oxide semiconductor contact hole 141 penetrating the gate insulating layer 14 and the buffer layer 13 is further disposed on the gate insulating layer 14, and the gate metal layer 15 is disposed.
  • the metal oxide semiconductor layer contact hole 141 is connected to the light shielding metal layer 1A.
  • the projection area of the light-shielding metal layer 1A on the plane of the glass substrate 11 covers the projection area of the metal oxide semiconductor layer 13 on the plane of the glass substrate 11. Specifically, the projection area of the light-shielding metal layer 1A on the plane of the glass substrate 11 covers all corresponding regions of the thin film transistor structure 10 on the plane of the glass substrate 11.
  • FIG. 2 is a flow chart of an embodiment of a method for fabricating a thin film transistor structure of the present invention.
  • the manufacturing method of the thin film transistor structure of this embodiment includes:
  • Step S201 providing a glass substrate, and cleaning and baking the glass substrate
  • Step S202 depositing a light shielding metal layer on the glass substrate, and performing image processing on the light shielding metal layer.
  • the light shielding metal layer has a thickness of 500 angstroms to 2000 angstroms, and the material of the light shielding metal layer may be at least one of metal molybdenum (Mo), metallic aluminum (Al), metallic copper (Cu), and metallic titanium (Ti).
  • the projection area of the light-shielding metal layer on the plane of the glass substrate covers the projection area of the metal oxide semiconductor layer on the plane of the glass substrate.
  • the projection area of the light shielding metal layer on the plane of the glass substrate covers all corresponding regions of the thin film transistor structure on the plane of the glass substrate.
  • Step S203 depositing a buffer layer on the glass substrate having the light-shielding metal layer, and the material of the buffer layer may be at least one of silicon oxide (SiO) and silicon nitride (SiN).
  • the buffer layer has a thickness of from 1000 angstroms to 5,000 angstroms.
  • Step S204 depositing a metal oxide semiconductor layer on the buffer layer, and performing image processing on the metal oxide semiconductor layer to set the position of the active driving region of the thin film transistor structure.
  • the metal oxide semiconductor layer includes a source region, a drain region, and a channel region.
  • the material of the metal oxide semiconductor layer is at least one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (IZTO), and indium gallium zinc tin oxide (IGZTO).
  • the metal oxide semiconductor layer has a thickness of 100 angstroms to 1000 angstroms.
  • Step S205 depositing a gate insulating layer on the metal oxide semiconductor layer to isolate the metal oxide semiconductor layer and the gate metal layer; and providing a metal oxide semiconductor layer contact hole penetrating the gate insulating layer and the buffer layer on the gate insulating layer .
  • the material of the gate insulating layer is at least one of silicon oxide and silicon nitride.
  • the gate insulating layer has a thickness of 1000 angstroms to 3,000 angstroms.
  • Step S206 depositing a gate metal layer on the gate insulating layer, and performing image processing on the gate metal layer, so that the gate metal layer is connected to the light shielding metal layer through the metal oxide semiconductor layer contact hole.
  • the material of the gate metal layer is at least one of metal molybdenum, metal aluminum, metallic copper, and metallic titanium.
  • Step S207 depositing an interlayer insulating layer on the entire surface glass substrate to planarize the glass substrate having the gate metal layer. And performing an image processing on the interlayer insulating layer to form a source contact hole and a drain contact hole.
  • the material of the interlayer insulating layer is at least one of silicon oxide and silicon nitride.
  • the interlayer insulating layer has a thickness of from 2,000 angstroms to 10,000 angstroms.
  • Step S208 depositing a source metal layer and a drain metal layer in the interlayer insulating layer, wherein the source metal layer is connected to the source region of the metal oxide semiconductor layer through the source contact hole; the material of the source metal layer is metal molybdenum At least one of metal aluminum, metal copper, and metal titanium; the material of the drain metal layer is at least one of metal molybdenum, metal aluminum, metal copper, and metal titanium; and the source metal layer has a thickness of 2000 angstroms to 8,000 The thickness of the drain metal layer is from 2000 angstroms to 8000 angstroms.
  • Step S209 depositing a protective layer on the entire surface of the glass substrate, the material of the protective layer being at least one of silicon oxide and silicon nitride.
  • the protective layer has a thickness of from 1000 angstroms to 5,000 angstroms.
  • the light-shielding metal layer 1A can block all light rays that are incident on the metal oxide semiconductor layer 13, so that the operational stability of the thin film transistor can be improved.
  • the gate metal layer 15 and the light-shielding metal layer are provided by providing the metal oxide semiconductor layer contact hole 141.
  • the 1A connection reduces the parasitic capacitance generated by the thin film transistor structure 10, so that when the thin film transistor structure 10 operates, it has a two-channel effect, which contributes to improving the performance of the thin film transistor device.
  • the thin film transistor structure and the manufacturing method thereof of the invention improve the working stability of the thin film transistor and the like in the AMOLED driving circuit through the design of the light shielding metal layer, thereby improving the picture display quality of the corresponding AMOLED display device; and solving the existing film A technical problem of poor stability of the transistor structure.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

提供一种薄膜晶体管结构，其包括玻璃基板（11）、缓冲层（12）、金属氧化物半导体层（13）、栅绝缘层（14）、栅极金属层（15）、层间绝缘层（16）、源极金属层（17）、漏极金属层（18）以及保护层（19）。其中玻璃基板（11）和缓冲层（12）之间还设置有遮光金属层（1A），栅绝缘层（14）上还设置有贯通栅绝缘层（14）以及缓冲层（12）的金属氧化物半导体层接触孔（141），栅极金属层（15）通过金属氧化物半导体层接触孔（141）与遮光金属层（1A）连接。

Description

薄膜晶体管结构及其制作方法 技术领域
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管结构及其制作方法。
 背景技术
随着科技的发展，AMOLED（Active-matrix organic light emitting diode，有源矩阵有机发光二极体）显示装置受到越来越多用户的喜爱。现有的AMOLED显示装置一般采用3T1C的AMOLED驱动电路，即三个薄膜晶体管和一个电容构成该AMOLED驱动电路。
现有AMOLED驱动电路中的薄膜晶体管由于出射光以及外界光的影响，会导致AMOLED驱动电路中的薄膜晶体管等器件工作不稳定，从而影响AMOLED显示装置的画面显示品质。
故，有必要提供一种薄膜晶体管结构及其制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种可提高薄膜晶体管等器件的工作稳定性，从而提高对应AMOLED显示装置的画面显示品质的薄膜晶体管结构及其制作方法；以解决现有的薄膜晶体管结构的工作稳定性较差的技术问题。
 技术解决方案
本发明实施例提供一种薄膜晶体管结构，其包括：
玻璃基板，
缓冲层，设置在所述玻璃基板上；
金属氧化物半导体层，设置在所述缓冲层上，并通过所述金属氧化物半导体层设定所述薄膜晶体管结构的主动驱动区的位置，所述金属氧化物半导体层包括源极区域、漏极区域以及沟道区域；
栅绝缘层，设置在所述金属氧化物半导体层上，用于隔离所述金属氧化物半导体层以及栅极金属层；
栅极金属层，设置在所述栅绝缘层上；
层间绝缘层，设置在具有所述栅极金属层的玻璃基板上，用于对具有所述栅极金属层的玻璃基板进行平坦化处理，所述层间绝缘层上设置有源极接触孔以及漏极接触孔；
源极金属层，设置在所述层间绝缘层上，并通过所述源极接触孔与所述金属氧化物半导体层的源极区域连接；
漏极金属层，设置在所述层间绝缘层上，并通过所述漏极接触孔与所述金属氧化物半导体层的漏极区域连接；以及
保护层，设置在具有所述源极金属层和所述漏极金属层的层间绝缘层上；
其中所述玻璃基板和缓冲层之间还设置有遮光金属层，
所述栅绝缘层上还设置有贯通所述栅绝缘层以及所述缓冲层的金属氧化物半导体层接触孔，所述栅极金属层通过所述金属氧化物半导体层接触孔与所述遮光金属层连接；
所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述金属氧化物半导体层在所述玻璃基板所在平面的投影区域；
所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述薄膜晶体管结构在所述玻璃基板所在平面的所有对应区域；
所述遮光金属层的厚度为500埃至2000埃；
所述缓冲层的厚度为1000埃至5000埃；
所述金属氧化物半导体层的厚度为100埃至1000埃；
所述栅绝缘层的厚度为1000埃至3000埃；
所述层间绝缘层的厚度为2000埃至10000埃；
所述源极金属层的厚度为2000埃至8000埃；
所述漏极金属层的厚度为2000埃至8000埃；
所述保护层的厚度为1000埃至5000埃；
所述遮光金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述缓冲层的材料为氧化硅以及氮化硅中的至少一种；
所述金属氧化物半导体层的材料为氧化铟镓锌、氧化铟锡锌以及氧化铟镓锌锡中的至少一种；
所述栅绝缘层的材料为氧化硅以及氮化硅中的至少一种；
所述栅极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述源极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述漏极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述层间绝缘层的材料为氧化硅以及氮化硅中的至少一种；
所述保护层的材料为氧化硅以及氮化硅中的至少一种。
本发明实施例还提供一种薄膜晶体管结构，其包括：
玻璃基板，
缓冲层，设置在所述玻璃基板上；
金属氧化物半导体层，设置在所述缓冲层上，并通过所述金属氧化物半导体层设定所述薄膜晶体管结构的主动驱动区的位置，所述金属氧化物半导体层包括源极区域、漏极区域以及沟道区域；
栅绝缘层，设置在所述金属氧化物半导体层上，用于隔离所述金属氧化物半导体层以及栅极金属层；
栅极金属层，设置在所述栅绝缘层上；
层间绝缘层，设置在具有所述栅极金属层的玻璃基板上，用于对具有所述栅极金属层的玻璃基板进行平坦化处理，所述层间绝缘层上设置有源极接触孔以及漏极接触孔；
源极金属层，设置在所述层间绝缘层上，并通过所述源极接触孔与所述金属氧化物半导体层的源极区域连接；
漏极金属层，设置在所述层间绝缘层上，并通过所述漏极接触孔与所述金属氧化物半导体层的漏极区域连接；以及
保护层，设置在具有所述源极金属层和所述漏极金属层的层间绝缘层上；
其中所述玻璃基板和缓冲层之间还设置有遮光金属层，
所述栅绝缘层上还设置有贯通所述栅绝缘层所述缓冲层的金属氧化物半导体层接触孔，所述栅极金属层通过所述金属氧化物半导体层接触孔与所述遮光金属层连接。
在本发明所述的薄膜晶体管结构中，所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述金属氧化物半导体层在所述玻璃基板所在平面的投影区域。
在本发明所述的薄膜晶体管结构中，所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述薄膜晶体管结构在所述玻璃基板所在平面的所有对应区域。
在本发明所述的薄膜晶体管结构中，所述遮光金属层的厚度为500埃至2000埃；
所述缓冲层的厚度为1000埃至5000埃；
所述金属氧化物半导体层的厚度为100埃至1000埃；
所述栅绝缘层的厚度为1000埃至3000埃；
所述层间绝缘层的厚度为2000埃至10000埃；
所述源极金属层的厚度为2000埃至8000埃；
所述漏极金属层的厚度为2000埃至8000埃；
所述保护层的厚度为1000埃至5000埃。
在本发明所述的薄膜晶体管结构中，所述遮光金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述栅极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述源极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述漏极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种。
在本发明所述的薄膜晶体管结构中，所述缓冲层的材料为氧化硅以及氮化硅中的至少一种；
所述栅绝缘层的材料为氧化硅以及氮化硅中的至少一种；
所述层间绝缘层的材料为氧化硅以及氮化硅中的至少一种；
所述保护层的材料为氧化硅以及氮化硅中的至少一种。
在本发明所述的薄膜晶体管结构中，所述金属氧化物半导体层的材料为氧化铟镓锌、氧化铟锡锌以及氧化铟镓锌锡中的至少一种。
本发明还提供一种薄膜晶体管结构的制作方法，其包括：
提供一玻璃基板；
在所述玻璃基板上沉积遮光金属层，并对所述遮光金属层进行图像化处理；
在具有所述遮光金属层的玻璃基板上沉积缓冲层；
在所述缓冲层上沉积金属氧化物半导体层，并对所述金属氧化物半导体层进行图像化处理，以设定所述薄膜晶体管结构的主动驱动区的位置；所述金属氧化物半导体层包括源极区域、漏极区域以及沟道区域；
在所述金属氧化物半导体层上沉积栅绝缘层，并在所述栅绝缘层上设置贯通所述栅绝缘层以及所述缓冲层的金属氧化物半导体层接触孔；
在所述栅绝缘层栅沉积栅极金属层，并对所述栅极金属层进行图像化处理；所述栅极金属层通过所述金属氧化物半导体层接触孔与所述遮光金属层连接；
在具有所述栅极金属层的玻璃基板上沉积层间绝缘层，并在所述层间绝缘层上设置有源极接触孔以及漏极接触孔；
在所述层间绝缘层上设置源极金属层以及漏极金属层，其中所述源极金属层通过源极接触孔与金属氧化物半导体层的源极区域连接；所述漏极金属层通过漏极接触孔与金属氧化物半导体层的漏极区域连接；以及
在具有所述源极金属层以及所述漏极金属层的玻璃基板上沉积保护层。
在本发明所述的薄膜晶体管结构的制作方法中，所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述金属氧化物半导体层在所述玻璃基板所在平面的投影区域。
在本发明所述的薄膜晶体管结构的制作方法中，所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述薄膜晶体管结构在所述玻璃基板所在平面的所有对应区域。
在本发明所述的薄膜晶体管结构的制作方法中，所述遮光金属层的厚度为500埃至2000埃；
所述缓冲层的厚度为1000埃至5000埃；
所述金属氧化物半导体层的厚度为100埃至1000埃；
所述栅绝缘层的厚度为1000埃至3000埃；
所述层间绝缘层的厚度为2000埃至10000埃；
所述源极金属层的厚度为2000埃至8000埃；
所述漏极金属层的厚度为2000埃至8000埃；
所述保护层的厚度为1000埃至5000埃。
在本发明所述的薄膜晶体管结构的制作方法中，所述遮光金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述栅极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述源极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
所述漏极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种。
在本发明所述的薄膜晶体管结构的制作方法中，所述缓冲层的材料为氧化硅以及氮化硅中的至少一种；
所述栅绝缘层的材料为氧化硅以及氮化硅中的至少一种；
所述层间绝缘层的材料为氧化硅以及氮化硅中的至少一种；
所述保护层的材料为氧化硅以及氮化硅中的至少一种。
在本发明所述的薄膜晶体管结构的制作方法中，所述金属氧化物半导体层的材料为氧化铟镓锌、氧化铟锡锌以及氧化铟镓锡中的至少一种。
 有益效果
本发明的薄膜晶体管结构及其制作方法通过遮光金属层的设计，提高了AMOLED驱动电路中薄膜晶体管等器件的工作稳定性，从而提高了对应AMOLED显示装置的画面显示品质；解决了现有的薄膜晶体管结构的工作稳定性较差的技术问题。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1a为本发明的薄膜晶体管结构的一实施例的结构示意图；
图1b为图1a所示的薄膜晶体管结构的A-A’的俯视截面图；
图2为本发明的薄膜晶体管结构的制作方法的一实施例的流程图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参照图1a，图1a为本发明的薄膜晶体管结构的一实施例的结构示意图，图1b为图1a所示的薄膜晶体管结构的A-A’的俯视截面图。本实施例的薄膜晶体管结构10包括薄膜基板11、缓冲层12、金属氧化物半导体层13、栅绝缘层14、栅极金属层15、层间绝缘层16、源极金属层17、漏极金属层18以及保护层19。
缓冲层12设置在玻璃基板11上。金属氧化物半导体层13设置在缓冲层12上，并通过金属氧化物半导体层13设定薄膜晶体管结构的主动驱动区的位置，金属氧化物半导体层13包括源极区域131、漏极区域132以及沟道区域133。栅绝缘层14设置在金属氧化物半导体层13上，用于隔离金属氧化物半导体层13以及栅极金属层15。栅极金属层15设置在栅绝缘层14上。层间绝缘层16设置在具有栅极金属层15的玻璃基板11上，用于对具有栅极金属层15的玻璃基板11进行平坦化处理，层间绝缘层16上设置有源极接触孔161以及漏极接触孔162。源极金属层161设置在层间绝缘层16上，并通过源极接触孔161与金属氧化物半导体层13的源极区域131连接。漏极金属层162设置在层间绝缘层16上，并通过漏极接触孔162与金属氧化物半导体层13的漏极区域132连接。保护层19设置在具有源极金属层17和漏极金属层18的层间绝缘层16上。其中玻璃基板11和缓冲层12之间还设置有遮光金属层1A，栅极绝缘层14上还设置有贯通栅绝缘层14以及缓冲层13的金属氧化物半导体接触孔141，栅极金属层15通过金属氧化物半导体层接触孔141与遮光金属层1A连接。
遮光金属层1A在玻璃基板11所在平面的投影区域覆盖金属氧化物半导体层13在玻璃基板11所在平面的投影区域。具体的，遮光金属层1A在玻璃基板11所在平面的投影区域覆盖薄膜晶体管结构10在玻璃基板11所在平面的所有对应区域。
请参照图2，图2为本发明的薄膜晶体管结构的制作方法的一实施例的流程图。本实施例的薄膜晶体管结构的制作方法包括：
步骤S201，提供一玻璃基板，并对该玻璃基板进行清洗以及烘烤；
步骤S202，在玻璃基板上沉积遮光金属层，并对该遮光金属层进行图像化处理。遮光金属层的厚度为500埃至2000埃，该遮光金属层的材料可为金属钼（Mo）、金属铝（Al）、金属铜（Cu）以及金属钛（Ti）中的至少一种。
遮光金属层在玻璃基板所在平面的投影区域覆盖金属氧化物半导体层在玻璃基板所在平面的投影区域。优选的，遮光金属层在玻璃基板所在平面的投影区域覆盖所述薄膜晶体管结构在玻璃基板所在平面的所有对应区域。
步骤S203，在具有遮光金属层的玻璃基板上沉积缓冲层，该缓冲层的材料可为氧化硅（SiO）以及氮化硅（SiN）中的至少一种。缓冲层的厚度为1000埃至5000埃。
步骤S204，在缓冲层上沉积金属氧化物半导体层，并对该金属氧化物半导体层进行图像化处理，以设定处薄膜晶体管结构的主动驱动区的位置。该金属氧化物半导体层包括源极区域、漏极区域以及沟道区域。金属氧化物半导体层的材料为氧化铟镓锌（IGZO）、氧化铟锡锌（IZTO）以及氧化铟镓锌锡（IGZTO）中的至少一种。金属氧化物半导体层的厚度为100埃至1000埃。
步骤S205，在金属氧化物半导体层上沉积栅绝缘层，以隔离金属氧化物半导体层以及栅极金属层；并在栅绝缘层上设置贯通栅绝缘层以及缓冲层的金属氧化物半导体层接触孔。所述栅绝缘层的材料为氧化硅以及氮化硅中的至少一种。栅绝缘层的厚度为1000埃至3000埃。
步骤S206，在栅绝缘层上沉积栅极金属层，并对栅极金属层进行图像化处理，使得栅极金属层通过金属氧化物半导体层接触孔与遮光金属层连接。所述栅极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种。
步骤S207，在整面玻璃基板上沉积层间绝缘层，以对具有栅极金属层的玻璃基板进行平坦化处理。并对该层间绝缘层进行图像化处理，以形成源极接触孔以及漏极接触孔。层间绝缘层的材料为氧化硅以及氮化硅中的至少一种。层间绝缘层的厚度为2000埃至10000埃。
步骤S208，在层间绝缘层沉积源极金属层以及漏极金属层，其中源极金属层通过源极接触孔与金属氧化物半导体层的源极区域连接；源极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；漏极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；源极金属层的厚度为2000埃至8000埃；漏极金属层的厚度为2000埃至8000埃。
步骤S209，在整面玻璃基板上沉积保护层，保护层的材料为氧化硅以及氮化硅中的至少一种。保护层的厚度为1000埃至5000埃。
这样即完成了本实施例的薄膜晶体管结构的制作过程。
本实施例的薄膜晶体管结构10使用时，遮光金属层1A可将射向金属氧化物半导体层13的所有光线阻挡掉，因此可以提高该薄膜晶体管工作稳定性。
由于本实施例的薄膜晶体管结构10的遮光金属层1A的面积较大，因此可能会产生较大的寄生电容，这里通过设置金属氧化物半导体层接触孔141将栅极金属层15与遮光金属层1A连接，从而降低由于该薄膜晶体管结构10产生的寄生电容，这样当薄膜晶体管结构10工作时具有双通道效应，有助于提升薄膜晶体管器件的效能。
本发明的薄膜晶体管结构及其制作方法通过遮光金属层的设计，提高了AMOLED驱动电路中薄膜晶体管等器件的工作稳定性，从而提高了对应AMOLED显示装置的画面显示品质；解决了现有的薄膜晶体管结构的工作稳定性较差的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种薄膜晶体管结构，其包括：
    玻璃基板，
    缓冲层，设置在所述玻璃基板上；
    金属氧化物半导体层，设置在所述缓冲层上，并通过所述金属氧化物半导体层设定所述薄膜晶体管结构的主动驱动区的位置，所述金属氧化物半导体层包括源极区域、漏极区域以及沟道区域；
    栅绝缘层，设置在所述金属氧化物半导体层上，用于隔离所述金属氧化物半导体层以及栅极金属层；
    栅极金属层，设置在所述栅绝缘层上；
    层间绝缘层，设置在具有所述栅极金属层的玻璃基板上，用于对具有所述栅极金属层的玻璃基板进行平坦化处理，所述层间绝缘层上设置有源极接触孔以及漏极接触孔；
    源极金属层，设置在所述层间绝缘层上，并通过所述源极接触孔与所述金属氧化物半导体层的源极区域连接；
    漏极金属层，设置在所述层间绝缘层上，并通过所述漏极接触孔与所述金属氧化物半导体层的漏极区域连接；以及
    保护层，设置在具有所述源极金属层和所述漏极金属层的层间绝缘层上；
    其中所述玻璃基板和缓冲层之间还设置有遮光金属层，
    所述栅绝缘层上还设置有贯通所述栅绝缘层以及所述缓冲层的金属氧化物半导体层接触孔，所述栅极金属层通过所述金属氧化物半导体层接触孔与所述遮光金属层连接；
    所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述金属氧化物半导体层在所述玻璃基板所在平面的投影区域；
    所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述薄膜晶体管结构在所述玻璃基板所在平面的所有对应区域；
    所述遮光金属层的厚度为500埃至2000埃；
    所述缓冲层的厚度为1000埃至5000埃；
    所述金属氧化物半导体层的厚度为100埃至1000埃；
    所述栅绝缘层的厚度为1000埃至3000埃；
    所述层间绝缘层的厚度为2000埃至10000埃；
    所述源极金属层的厚度为2000埃至8000埃；
    所述漏极金属层的厚度为2000埃至8000埃；
    所述保护层的厚度为1000埃至5000埃；
    所述遮光金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述缓冲层的材料为氧化硅以及氮化硅中的至少一种；
    所述金属氧化物半导体层的材料为氧化铟镓锌、氧化铟锡锌以及氧化铟镓锌锡中的至少一种；
    所述栅绝缘层的材料为氧化硅以及氮化硅中的至少一种；
    所述栅极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述源极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述漏极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述层间绝缘层的材料为氧化硅以及氮化硅中的至少一种；
    所述保护层的材料为氧化硅以及氮化硅中的至少一种。
  2. 一种薄膜晶体管结构，其包括：
    玻璃基板，
    缓冲层，设置在所述玻璃基板上；
    金属氧化物半导体层，设置在所述缓冲层上，并通过所述金属氧化物半导体层设定所述薄膜晶体管结构的主动驱动区的位置，所述金属氧化物半导体层包括源极区域、漏极区域以及沟道区域；
    栅绝缘层，设置在所述金属氧化物半导体层上，用于隔离所述金属氧化物半导体层以及栅极金属层；
    栅极金属层，设置在所述栅绝缘层上；
    层间绝缘层，设置在具有所述栅极金属层的玻璃基板上，用于对具有所述栅极金属层的玻璃基板进行平坦化处理，所述层间绝缘层上设置有源极接触孔以及漏极接触孔；
    源极金属层，设置在所述层间绝缘层上，并通过所述源极接触孔与所述金属氧化物半导体层的源极区域连接；
    漏极金属层，设置在所述层间绝缘层上，并通过所述漏极接触孔与所述金属氧化物半导体层的漏极区域连接；以及
    保护层，设置在具有所述源极金属层和所述漏极金属层的层间绝缘层上；
    其中所述玻璃基板和缓冲层之间还设置有遮光金属层，
    所述栅绝缘层上还设置有贯通所述栅绝缘层以及所述缓冲层的金属氧化物半导体层接触孔，所述栅极金属层通过所述金属氧化物半导体层接触孔与所述遮光金属层连接。
  3. 根据权利要求2所述的薄膜晶体管结构，其中所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述金属氧化物半导体层在所述玻璃基板所在平面的投影区域。
  4. 根据权利要求3所述的薄膜晶体管结构，其中所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述薄膜晶体管结构在所述玻璃基板所在平面的所有对应区域。
  5. 根据权利要求2所述的薄膜晶体管结构，其中所述遮光金属层的厚度为500埃至2000埃；
    所述缓冲层的厚度为1000埃至5000埃；
    所述金属氧化物半导体层的厚度为100埃至1000埃；
    所述栅绝缘层的厚度为1000埃至3000埃；
    所述层间绝缘层的厚度为2000埃至10000埃；
    所述源极金属层的厚度为2000埃至8000埃；
    所述漏极金属层的厚度为2000埃至8000埃；
    所述保护层的厚度为1000埃至5000埃。
  6. 根据权利要求2所述的薄膜晶体管结构，其中
    所述遮光金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述栅极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述源极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述漏极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种。
  7. 根据权利要求2所述的薄膜晶体管结构，其中所述缓冲层的材料为氧化硅以及氮化硅中的至少一种；
    所述栅绝缘层的材料为氧化硅以及氮化硅中的至少一种；
    所述层间绝缘层的材料为氧化硅以及氮化硅中的至少一种；
    所述保护层的材料为氧化硅以及氮化硅中的至少一种。
  8. 根据权利要求2所述的薄膜晶体管结构，其中所述金属氧化物半导体层的材料为氧化铟镓锌、氧化铟锡锌以及氧化铟镓锌锡中的至少一种。
  9. 一种薄膜晶体管结构的制作方法，其包括：
    提供一玻璃基板；
    在所述玻璃基板上沉积遮光金属层，并对所述遮光金属层进行图像化处理；
    在具有所述遮光金属层的玻璃基板上沉积缓冲层；
    在所述缓冲层上沉积金属氧化物半导体层，并对所述金属氧化物半导体层进行图像化处理，以设定所述薄膜晶体管结构的主动驱动区的位置；所述金属氧化物半导体层包括源极区域、漏极区域以及沟道区域；
    在所述金属氧化物半导体层上沉积栅绝缘层，并在所述栅绝缘层上设置贯通所述栅绝缘层以及所述缓冲层的金属氧化物半导体层接触孔；
    在所述栅绝缘层栅沉积栅极金属层，并对所述栅极金属层进行图像化处理；所述栅极金属层通过所述金属氧化物半导体层接触孔与所述遮光金属层连接；
    在具有所述栅极金属层的玻璃基板上沉积层间绝缘层，并在所述层间绝缘层上设置有源极接触孔以及漏极接触孔；
    在所述层间绝缘层上设置源极金属层以及漏极金属层，其中所述源极金属层通过源极接触孔与金属氧化物半导体层的源极区域连接；所述漏极金属层通过漏极接触孔与金属氧化物半导体层的漏极区域连接；以及
    在具有所述源极金属层以及所述漏极金属层的玻璃基板上沉积保护层。
  10. 根据权利要求9所述的薄膜晶体管结构的制作方法，其中所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述金属氧化物半导体层在所述玻璃基板所在平面的投影区域。
  11. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中所述遮光金属层在所述玻璃基板所在平面的投影区域覆盖所述薄膜晶体管结构在所述玻璃基板所在平面的所有对应区域。
  12. 根据权利要求9所述的薄膜晶体管结构的制作方法，其中所述遮光金属层的厚度为500埃至2000埃；
    所述缓冲层的厚度为1000埃至5000埃；
    所述金属氧化物半导体层的厚度为100埃至1000埃；
    所述栅绝缘层的厚度为1000埃至3000埃；
    所述层间绝缘层的厚度为2000埃至10000埃；
    所述源极金属层的厚度为2000埃至8000埃；
    所述漏极金属层的厚度为2000埃至8000埃；
    所述保护层的厚度为1000埃至5000埃。
  13. 根据权利要求9所述的薄膜晶体管结构的制作方法，其中所述遮光金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述栅极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述源极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种；
    所述漏极金属层的材料为金属钼、金属铝、金属铜以及金属钛中的至少一种。
  14. 根据权利要求9所述的薄膜晶体管结构的制作方法，其中所述缓冲层的材料为氧化硅以及氮化硅中的至少一种；
    所述栅绝缘层的材料为氧化硅以及氮化硅中的至少一种；
    所述层间绝缘层的材料为氧化硅以及氮化硅中的至少一种；
    所述保护层的材料为氧化硅以及氮化硅中的至少一种。
  15. 根据权利要求9所述的薄膜晶体管结构的制作方法，其中所述金属氧化物半导体层的材料为氧化铟镓锌、氧化铟锡锌以及氧化铟镓锡中的至少一种。
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