WO2016206033A1 - 薄膜晶体管阵列基板及其制作方法 - Google Patents

薄膜晶体管阵列基板及其制作方法 Download PDF

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Publication number
WO2016206033A1
WO2016206033A1 PCT/CN2015/082300 CN2015082300W WO2016206033A1 WO 2016206033 A1 WO2016206033 A1 WO 2016206033A1 CN 2015082300 W CN2015082300 W CN 2015082300W WO 2016206033 A1 WO2016206033 A1 WO 2016206033A1
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WO
WIPO (PCT)
Prior art keywords
groove
aperture ratio
depth
thin film
film transistor
Prior art date
Application number
PCT/CN2015/082300
Other languages
English (en)
French (fr)
Inventor
邓竹明
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to BR112017024186-2A priority Critical patent/BR112017024186B1/pt
Priority to JP2017552160A priority patent/JP2018513413A/ja
Priority to US14/767,683 priority patent/US20160380009A1/en
Priority to KR1020177029502A priority patent/KR20170123701A/ko
Priority to GB1717453.3A priority patent/GB2556205B/en
Publication of WO2016206033A1 publication Critical patent/WO2016206033A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a method of fabricating the same.
  • the fabrication process of a conventional thin film transistor array substrate generally requires providing a via hole on the passivation layer, and providing a recess on the passivation layer, and setting a surface on the passivation layer and the recess
  • Pixel electrode layer is connected to the data line layer in the thin film transistor array substrate through the through hole.
  • disposing the through hole on the passivation layer and disposing the groove on the passivation layer are separately performed, that is, setting on the passivation layer The through hole and
  • Providing the recess on the passivation layer is two separate steps.
  • the fabrication efficiency of the substrate is not high.
  • An object of the present invention is to provide a thin film transistor array substrate and a manufacturing method thereof, which can save the manufacturing cost of the thin film transistor array substrate and improve the fabrication efficiency of the thin film transistor array substrate.
  • a thin film transistor array substrate wherein the thin film transistor array substrate comprises: a device combination board, the device combination board includes: a substrate; a first signal line layer; a semiconductor layer;
  • a second signal line layer a passivation layer, the passivation layer is disposed on the device combination board, and the passivation layer is provided with an array of holes and a groove, the groove array including at least one a groove;
  • the hole has a first
  • the first groove has a second depth; the groove array and the hole are both formed in a first mask process; the groove array further includes at least one third groove; Hole, said
  • any two of the first groove and the third groove are formed in the second mask process, and the other of the hole, the first groove, and the third groove Is in the third mask process
  • the mask corresponding to the first mask process includes: a first region, the first region has a first aperture ratio, and the first aperture ratio and the first depth pair
  • the groove array further comprising at least one second groove, the Two groove
  • the mask corresponding to the first mask process further includes: at least one third region, the third region has a third aperture ratio, and the third aperture ratio corresponds to the third depth.
  • a thin film transistor array substrate comprising: a device combination board, the device combination board comprising: a substrate; a first signal line layer; a semiconductor layer;
  • a passivation layer disposed on the device combination board, the passivation layer is provided with an array of holes and grooves, and the groove array includes at least one first groove One pixel
  • the pixel electrode layer is disposed on the passivation layer and the groove array, and the pixel electrode layer is connected to the second signal line layer through the hole.
  • the hole has a first depth, and the first groove has a second depth; the groove array and the hole are both formed in a first mask process.
  • the mask corresponding to the first mask process includes: a first region, the first region has a first aperture ratio, the first aperture ratio and the first depth
  • the second region has a second aperture ratio, and the second aperture ratio corresponds to the second depth.
  • the first depth and the second depth are simultaneously formed by performing the first mask process on the passivation layer by using the first mask, wherein
  • the first mask has the first region and the second region.
  • the first aperture ratio is equal to 100%
  • the second aperture ratio is greater than 0%
  • the second aperture ratio is less than 100%.
  • the groove array further includes at least one second groove, the second groove has a third depth;
  • the mask corresponding to the first mask process further includes: at least one
  • the third region having a third aperture ratio, the third aperture ratio corresponding to the third depth.
  • the first depth, the second depth, and the third depth are performed by performing the first mask process on the passivation layer by using the first mask simultaneously Shape
  • the first mask has the first region, the second region, and the third region.
  • the first aperture ratio is equal to 100%
  • the second aperture ratio and the third aperture ratio are both greater than 0%
  • the second aperture ratio and the third aperture ratio are Small
  • the groove array further includes at least one third groove; any one of the hole, the first groove, and the third groove is in the second Mask process
  • the other of the hole, the first groove, and the third groove is formed in the third mask process.
  • a method of fabricating a thin film transistor array substrate comprising the steps of: A, forming a device combination board, wherein the device combination board comprises a substrate, a first signal line layer, a semiconductor layer, and
  • the groove array includes at least one first groove; D, a pixel electrode layer is disposed in the surface of the passivation layer and the groove array, wherein the pixel electrode layer passes through the hole and the Second
  • the signal line layer is connected.
  • the hole has a first depth, and the first groove has a second depth;
  • the step C includes the following steps: c1, forming in the first mask process
  • the mask corresponding to the first mask process includes: a first region, the first region has a first aperture ratio, and the first aperture ratio
  • the first depth corresponds to at least one second region, the second region has a second aperture ratio, and the second aperture ratio corresponds to the second depth.
  • the step c1 includes the following steps: c11, using the first mask having the first region and the second region, the passivation layer is
  • the first mask process is performed to simultaneously form the first depth and the second depth.
  • the first aperture ratio is equal to 100%
  • the second aperture ratio is greater than 0%
  • the second aperture ratio is less than 100%.
  • the groove array further includes at least one second groove, the second groove has a third depth; and the mask corresponding to the first mask process is further included
  • the third region has a third aperture ratio
  • the third aperture ratio corresponds to the third depth
  • the step c1 includes the following steps: c12, using the first mask having the first region, the second region, and the third region,
  • the first mask process is performed on the passivation layer to simultaneously form the first depth, the second depth, and the third depth.
  • the first aperture ratio is equal to 100%
  • the second aperture ratio and the third aperture ratio are both greater than 0%
  • the aperture ratio is less than 100%.
  • the groove array further includes at least one third groove; the step C includes the following steps: c2, forming the hole in the second mask process
  • the present invention can save a mask process, save the manufacturing cost of the thin film transistor array substrate, and improve the fabrication efficiency of the thin film transistor array substrate.
  • FIG. 4 are schematic views showing a first embodiment of a method of fabricating a thin film transistor array substrate according to the present invention
  • FIGS. 1 to 4 is a schematic view of a mask used in the fabrication process of the thin film transistor array substrate shown in FIGS. 1 to 4;
  • FIG. 6 is a schematic view showing a second embodiment of a thin film transistor array substrate of the present invention.
  • FIG. 7 is a schematic view showing a mask used in the process of fabricating the thin film transistor array substrate shown in FIG. 6;
  • FIG. 8 is a flow chart of a first embodiment of a method of fabricating a thin film transistor array substrate of the present invention.
  • FIG. 9 is a flow chart showing a third embodiment of a method of fabricating a thin film transistor array substrate of the present invention.
  • FIG. 4 is a schematic view showing a first embodiment of a thin film transistor array substrate fabricated by a method of fabricating a thin film transistor array substrate according to the present invention.
  • the thin film transistor array substrate of the present embodiment includes a device combination board 101, a passivation layer 201, and a pixel electrode layer 401.
  • the device assembly board 101 includes a substrate 1011, a first signal line layer 1012, and a semiconductor
  • the device assembly board 101 further includes a first insulating layer 1013, a second insulating layer 1015, and a drain line layer 1016.
  • the first signal line layer 1012 may be a scan line layer
  • the semiconductor layer 1014 may be an amorphous silicon layer or a polysilicon layer
  • the second signal line layer 1017 may be a data line layer.
  • the first insulating layer 1013 is disposed between the scan line layer and the amorphous silicon layer under the semiconductor layer (the semiconductor layer 1014 is the amorphous silicon layer) 1014.
  • the data line layer 1015 is disposed above the amorphous silicon layer, the data line layer is disposed above the second insulating layer 1015, and the data line layer passes through the second insulating layer 1015 and the amorphous silicon Layer connected
  • the scan line layer is disposed above the semiconductor layer (the semiconductor layer 1014 is the polysilicon layer) 1014, and the first layer is disposed between the polysilicon layer and the scan line layer
  • the second insulating layer 1015 is disposed above the scan line layer
  • the data line layer is disposed above the second insulating layer 1015
  • the data line layer passes through the first layer insulation
  • a layer 1013 and the second insulating layer 1015 are connected to the polysilicon layer.
  • the passivation layer 201 is disposed on the device assembly board 101.
  • the passivation layer 201 is provided with a hole 302 and a groove array 301.
  • the groove array 301 includes at least one first groove 3011.
  • the pixel electrode layer 401 is disposed on the passivation layer 201 and in the groove array 301, and the pixel electrode layer 401 is connected to the second signal line layer 1017 through the hole 302.
  • the hole 302 has a first depth H1
  • the first groove 3011 has a second depth H2.
  • the groove array 301 (the first groove 3011) and the hole 302 are both formed in the first mask process. That is, the groove array 301 and the hole 302 are both in the same mask.
  • the above technical solution can save a mask process (Normal) Mask, common mask), which is advantageous for saving the manufacturing cost of the thin film transistor array substrate and improving
  • FIG. 5 is a schematic view of a mask used in the fabrication process of the thin film transistor array substrate shown in FIGS. 1 to 4.
  • the mask (first mask 501) corresponding to the first mask process includes a first region 5011 and at least a second region 5012.
  • the first region 5011 has a first aperture ratio
  • the first aperture ratio corresponds to the first depth H1.
  • the second region 5012 has a second aperture ratio, and the second aperture ratio corresponds to the second depth H2.
  • the depth of the first groove 3011 (the
  • the second depth H2) can be based on GTM (Gray Tone Mask, gray tone mask)
  • GTM Gram Tone Mask, gray tone mask
  • the aperture ratio (0-100% open interval) is set.
  • the first depth H1 and the second depth H2 in the passivation layer 201 are formed in such a manner as to:
  • the first mask process is performed on the passivation layer 201 by using the first mask 501 having the first region 5011 and the second region 5012 to simultaneously form the first depth H1 and The first
  • first region 5011 has the first aperture ratio
  • second region 5012 has the second aperture ratio.
  • first aperture ratio is 100%
  • second aperture ratio is 100%
  • (a%) is in the range of 0% to 100% (open interval), for example, the a% is 66.7% or 60%.
  • FIG. 6 is a schematic view of a second embodiment of the thin film transistor array substrate of the present invention
  • FIG. 7 is a schematic view of a mask used in the fabrication process of the thin film transistor array substrate shown in FIG.
  • This embodiment is similar to the first embodiment described above, except that:
  • the grooves in the groove array 301 have two different depths. That is, the groove array 301 further includes at least one second groove 3012, and the second groove 3012 has a
  • the first mask process corresponds to Mask
  • the first mask 501) further includes at least one third region 701.
  • the third region 701 has a third aperture ratio, and the third aperture ratio corresponds to the third depth H2.
  • the depth of the second groove 3012 (the third depth H2) may be set according to an aperture ratio of the GTM (an open interval of 0-100%).
  • the first depth H1, the second depth H2, and the third depth H2 in the passivation layer 201 are formed in such a manner as to:
  • the first mask process is performed on the passivation layer 201 by using the first mask 501 having the first region 5011, the second region 5012, and the third region 701 to simultaneously form The first
  • Field 701 has the third aperture ratio.
  • the first aperture ratio is 100%
  • the second aperture ratio (a%) and the third aperture ratio (b%) are both in a range of 0% to 100% (open interval), a
  • the a%, the b% are each one of 66.7% or 60%.
  • the third embodiment of the thin film transistor array substrate of the present invention is similar to the first embodiment described above, except that:
  • the grooves in the groove array 301 have two different depths. That is, the groove array 301 further includes at least one third groove, the third groove having a fourth depth.
  • any one of the hole 302, the first groove 3011, and the third groove is formed in the second mask process, the hole 302, the first groove 3011, In the third groove
  • the other is formed in the third mask process.
  • the mask corresponding to the second mask process is a gray tone mask (GTM), and the mask corresponding to the third mask process is a mask different from the gray tone mask, for example, a common mask Mode (Normal
  • the pixel electrode layer 401 includes at least two first portions and at least two second portions.
  • the first portion covers the surface of the passivation layer 201.
  • the second portion is from a surface of the passivation layer 201 to a groove in the groove array 301 (the first groove 3011, the second groove)
  • the first portion is connected to the second portion.
  • the passivation layer 201201 is provided in an uneven shape, and the passivation layer 201 is entirely attached to the unevenness of the passivation layer 201, that is, the pixel electrode layer 401 is attached to the entire surface.
  • the blunt edge of the passivation layer 201201 is provided in an uneven shape, and the passivation layer 201 is entirely attached to the unevenness of the passivation layer 201, that is, the pixel electrode layer 401 is attached to the entire surface.
  • the surface of the layer 201 and the recess are such that the display corresponding to the thin film transistor array substrate is facilitated panel
  • Has a higher display quality for example, has a higher penetration rate.
  • FIG. 1 to FIG. 4 are schematic diagrams showing a first embodiment of a method for fabricating a thin film transistor array substrate according to the present invention
  • FIG. 8 is a diagram of a method for fabricating a thin film transistor array substrate according to the present invention.
  • step 801 forming a device assembly board 101, wherein the device combination board 101 includes a substrate 1011, a first signal line layer 1012, a semiconductor layer 1014, and a second signal line layer 1017.
  • a passivation layer 201 is provided on the device combination board 101.
  • step 803 performing a mask process on the passivation layer 201 such that a hole 302 and a groove array 301 are formed on the surface of the passivation layer 201, wherein the groove array 301 includes at least One
  • step 804 providing a pixel electrode layer 401 in the surface of the passivation layer 201 and the groove array 301, wherein the pixel electrode layer 401 passes through the hole 302 and the second signal line
  • the hole 302 has a first depth H1
  • the first groove 3011 has a second depth H2.
  • the step C includes the following steps:
  • the groove array 301 (the first groove 3011) and the hole 302 are formed in a first mask process. That is, in the same mask process (Gray Tone Mask, gray tone mask) formed
  • the groove array 301 (the first groove 3011) and the hole 302.
  • the mask (first mask 501) corresponding to the first mask process includes a first region 5011 and at least a second region 5012.
  • the first region 5011 has a first aperture ratio
  • the first aperture ratio corresponds to the first depth H1.
  • the second region 5012 has a second aperture ratio, and the second aperture ratio corresponds to the second depth H2.
  • the second depth H2) can be based on GTM (Gray Tone) Mask, gray tone mask)
  • GTM Gram Tone
  • gray tone mask The aperture ratio (0-100% open interval) is set.
  • the first depth H1 and the second depth H2 in the passivation layer 201 are formed in such a manner as to:
  • the first mask process is performed on the passivation layer 201 by using the first mask 501 having the first region 5011 and the second region 5012 to simultaneously form the first depth H1 and The first
  • first region 5011 has the first aperture ratio
  • second region 5012 has the second aperture ratio.
  • first aperture ratio is 100%
  • second aperture ratio is 100%
  • (a%) is in the range of 0% to 100% (open interval), for example, the a% is 66.7% or 60%.
  • the above technical solution can save a mask process (Normal) Mask, common mask), which is advantageous for saving the manufacturing cost of the thin film transistor array substrate and improving
  • the second embodiment of the method of fabricating the thin film transistor array substrate of the present invention is similar to the first embodiment described above, except that:
  • the grooves in the groove array 301 have two different depths. That is, the groove array 301 further includes at least one second groove 3012, and the second groove 3012 has a
  • the first mask process corresponds to Mask
  • the first mask 501) further includes at least one third region 701.
  • the third region 701 has a third aperture ratio, and the third aperture ratio corresponds to the third depth H2.
  • the depth of the second groove 3012 (the third depth H2) may be set according to an aperture ratio of the GTM (an open interval of 0-100%).
  • the first depth H1, the second depth H2, and the third depth H2 in the passivation layer 201 are formed in such a manner as to:
  • the first mask process is performed on the passivation layer 201 by using the first mask 501 having the first region 5011, the second region 5012, and the third region 701 to simultaneously form The first
  • Field 701 has the third aperture ratio.
  • the first aperture ratio is 100%
  • the second aperture ratio (a%) and the third aperture ratio (b%) are both in a range of 0% to 100% (open interval), a
  • the a%, the b% are each one of 66.7% or 60%.
  • FIG. 9 is a flow chart showing a third embodiment of a method of fabricating a thin film transistor array substrate of the present invention. This embodiment is similar to the first embodiment described above, except that:
  • the grooves in the groove array 301 have two different depths. That is, the groove array 301 further includes at least one third groove, the third groove having a fourth depth.
  • the step C includes the following steps:
  • step 901 forming any one of the hole 302, the first groove 3011, and the third groove in the second mask process.
  • step 902 forming the other of the hole 302, the first groove 3011, and the third groove in the third mask process.
  • the mask corresponding to the second mask process is a gray tone mask (GTM), and the mask corresponding to the third mask process is a mask different from the gray tone mask, for example, a common mask Mode (Normal

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Abstract

一种薄膜晶体管阵列基板及其制作方法，薄膜晶体管阵列基板包括器件组合板（101）、钝化层（201）、像素电极层（401）。钝化层（201）设置在器件组合板（101）上，钝化层（201）上设置有孔洞（302）和第一凹槽（3011）；像素电极层（401）设置在钝化层（201）上以及第一凹槽（3011）内，像素电极层（401）通过孔洞（302）与第二信号线层（1017）连接。从而，能节省制作成本以及提高制作效率。

Description

薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管阵列基板及其制作方法。
 背景技术
传统的薄膜晶体管阵列基板的制作过程一般都需要在钝化层上设置通孔，以及在所述钝化层上设置凹槽，并在所述钝化层上的表面和所述凹槽内设置
像素电极层。其中，该像素电极层通过所述通孔与所述薄膜晶体管阵列基板中的数据线层连接。
在上述传统的技术方案中，在所述钝化层上设置所述通孔和在所述钝化层上设置所述凹槽是分开实施的，也就是说，在所述钝化层上设置所述通孔和
在所述钝化层上设置所述凹槽是两个独立的步骤。
针对上述两个独立的步骤，需要两次不同的Normal Mask（普通掩模）光罩制程，这导致上述技术方案具有较高的成本，并且使得所述薄膜晶体管阵列
基板的制作效率不高。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列基板及其制作方法，其能节省薄膜晶体管阵列基板的制作成本以及提高薄膜晶体管阵列基板的制作效率。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：一器件组合板，所述器件组合板包括：一基板；一第一信号线层；一半导体层；以
及一第二信号线层；一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一第一凹槽；一
像素电极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接；所述孔洞具有第一
深度，所述第一凹槽具有第二深度；所述凹槽阵列与所述孔洞均是在第一光罩制程中形成的；所述凹槽阵列还包括至少一第三凹槽；所述孔洞、所述
第一凹槽、所述第三凹槽中的任意两者是在所述第二光罩制程中形成的，所述孔洞、所述第一凹槽、所述第三凹槽中的另一者是在所述第三光罩制程
中形成的。
在上述薄膜晶体管阵列基板中，所述第一光罩制程所对应掩模包括：一第一区域，所述第一区域具有第一开口率，所述第一开口率与所述第一深度对
应；至少一第二区域，所述第二区域具有第二开口率，所述第二开口率与所述第二深度对应；所述凹槽阵列还包括至少一第二凹槽，所述第二凹槽具
有第三深度；所述第一光罩制程所对应掩模还包括：至少一第三区域，所述第三区域具有第三开口率，所述第三开口率与所述第三深度对应。
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一器件组合板，所述器件组合板包括：一基板；一第一信号线层；一半导体层；以及一第
二信号线层；一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一第一凹槽；一像素电
极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接。
在上述薄膜晶体管阵列基板中，所述孔洞具有第一深度，所述第一凹槽具有第二深度；所述凹槽阵列与所述孔洞均是在第一光罩制程中形成的。
在上述薄膜晶体管阵列基板中，所述第一光罩制程所对应的掩模包括：一第一区域，所述第一区域具有第一开口率，所述第一开口率与所述第一深度
对应；至少一第二区域，所述第二区域具有第二开口率，所述第二开口率与所述第二深度对应。
在上述薄膜晶体管阵列基板中，所述第一深度和所述第二深度是通过利用所述第一掩模对所述钝化层实施所述第一光罩制程来同时形成的，其中，所
述第一掩模具有所述第一区域和所述第二区域。
在上述薄膜晶体管阵列基板中，所述第一开口率等于100%，所述第二开口率大于0%，并且所述第二开口率小于100%。
在上述薄膜晶体管阵列基板中，所述凹槽阵列还包括至少一第二凹槽，所述第二凹槽具有第三深度；所述第一光罩制程所对应的掩模还包括：至少一
第三区域，所述第三区域具有第三开口率，所述第三开口率与所述第三深度对应。
在上述薄膜晶体管阵列基板中，所述第一深度、所述第二深度和所述第三深度是通过利用所述第一掩模对所述钝化层实施所述第一光罩制程来同时形
成的，其中，所述第一掩模具有所述第一区域、所述第二区域和所述第三区域。
在上述薄膜晶体管阵列基板中，所述第一开口率等于100%，所述第二开口率和所述第三开口率均大于0%，并且所述第二开口率和所述第三开口率均小
于100%。
在上述薄膜晶体管阵列基板中，所述凹槽阵列还包括至少一第三凹槽；所述孔洞、所述第一凹槽、所述第三凹槽中的任意两者是在所述第二光罩制程
中形成的，所述孔洞、所述第一凹槽、所述第三凹槽中的另一者是在所述第三光罩制程中形成的。
一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：A、形成器件组合板，其中，所述器件组合板包括基板、第一信号线层、半导体层以及
第二信号线层；B、在所述器件组合板上设置钝化层；C、对所述钝化层实施光罩制程，以使所述钝化层的表面上形成有一孔洞和一凹槽阵列，其中，
所述凹槽阵列包括至少一第一凹槽；D、在所述钝化层的所述表面和所述凹槽阵列内设置像素电极层，其中，所述像素电极层通过所述孔洞与所述第二
信号线层连接。
在上述薄膜晶体管阵列基板的制作方法中，所述孔洞具有第一深度，所述第一凹槽具有第二深度；所述步骤C包括以下步骤：c1、在第一光罩制程中形
成所述凹槽阵列与所述孔洞。
在上述薄膜晶体管阵列基板的制作方法中，所述第一光罩制程所对应的掩模包括：一第一区域，所述第一区域具有第一开口率，所述第一开口率与所
述第一深度对应；至少一第二区域，所述第二区域具有第二开口率，所述第二开口率与所述第二深度对应。
在上述薄膜晶体管阵列基板的制作方法中，所述步骤c1包括以下步骤：c11、利用具有所述第一区域和所述第二区域的所述第一掩模，对所述钝化层实
施所述第一光罩制程，以同时形成所述第一深度和所述第二深度。
在上述薄膜晶体管阵列基板的制作方法中，所述第一开口率等于100%，所述第二开口率大于0%，并且所述第二开口率小于100%。
在上述薄膜晶体管阵列基板的制作方法中，所述凹槽阵列还包括至少一第二凹槽，所述第二凹槽具有第三深度；所述第一光罩制程所对应的掩模还包
括：至少一第三区域，所述第三区域具有第三开口率，所述第三开口率与所述第三深度对应。
在上述薄膜晶体管阵列基板的制作方法中，所述步骤c1包括以下步骤：c12、利用具有所述第一区域、所述第二区域和所述第三区域的所述第一掩模，
对所述钝化层实施所述第一光罩制程，以同时形成所述第一深度、所述第二深度和所述第三深度。
在上述薄膜晶体管阵列基板的制作方法中，所述第一开口率等于100%，所述第二开口率和所述第三开口率均大于0%，并且所述第二开口率和所述第三
开口率均小于100%。
在上述薄膜晶体管阵列基板的制作方法中，所述凹槽阵列还包括至少一第三凹槽；所述步骤C包括以下步骤：c2、在所述第二光罩制程中形成所述孔洞
、所述第一凹槽、所述第三凹槽中的任意两者；以及c3、在所述第三光罩制程中形成所述孔洞、所述第一凹槽、所述第三凹槽中的另一者。
 有益效果
相对现有技术，本发明可以节约一道光罩制程，有利于节省所述薄膜晶体管阵列基板的制作成本，以及提高所述薄膜晶体管阵列基板的制作效率。
附图说明
图1至图4为本发明的薄膜晶体管阵列基板的制作方法的第一实施例的示意图；
图5为图1至图4所示的薄膜晶体管阵列基板的制作过程中所使用的掩模的示意图；
图6为本发明的薄膜晶体管阵列基板的第二实施例的示意图；
图7为图6所示的薄膜晶体管阵列基板的制作过程中所使用掩模的示意图；
图8为本发明的薄膜晶体管阵列基板的制作方法的第一实施例的流程图；
图9为本发明的薄膜晶体管阵列基板的制作方法的第三实施例的流程图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个
”，除非另外指定或从上下文可以清楚确定单数形式。
参考图4，图4为根据本发明的薄膜晶体管阵列基板的制作方法所制作成的薄膜晶体管阵列基板的第一实施例的示意图。
本实施例的薄膜晶体管阵列基板包括器件组合板101、钝化层201以及像素电极层401。所述器件组合板101包括基板1011、第一信号线层1012、半导体
层1014以及第二信号线层1017。所述器件组合板101还包括第一绝缘层1013、第二绝缘层1015和漏极线层1016。
所述第一信号线层1012可以是扫描线层，所述半导体层1014可以是非晶硅层或多晶硅层，所述第二信号线层1017可以是数据线层。所述扫描线层设置
在所述半导体层（所述半导体层1014为所述非晶硅层）1014的下方，所述扫描线层与所述非晶硅层之间设置有所述第一绝缘层1013，所述第二绝缘层
1015设置在所述非晶硅层的上方，所述数据线层设置在所述第二绝缘层1015的上方，并且所述数据线层穿过所述第二绝缘层1015与所述非晶硅层相连
；或者，所述扫描线层设置在所述半导体层（所述半导体层1014为所述多晶硅层）1014的上方，所述多晶硅层与所述扫描线层之间设置有所述第一绝
缘层1013，所述第二绝缘层1015设置在所述扫描线层的上方，所述数据线层设置在所述第二绝缘层1015的上方，并且所述数据线层穿过所述第一绝缘
层1013和所述第二绝缘层1015与所述多晶硅层相连。
所述钝化层201设置在所述器件组合板101上，所述钝化层201上设置有孔洞302和凹槽阵列301，所述凹槽阵列301包括至少一第一凹槽3011。
所述像素电极层401设置在所述钝化层201上以及所述凹槽阵列301内，所述像素电极层401通过所述孔洞302与所述第二信号线层1017连接。
在本实施例中，所述孔洞302具有第一深度H1，所述第一凹槽3011具有第二深度H2。
所述凹槽阵列301（所述第一凹槽3011）与所述孔洞302均是在第一光罩制程中形成的。也就是说，所述凹槽阵列301与所述孔洞302均是在同一道光罩
制程（Gray Tone Mask，灰色调掩模）中形成的。
相比传统的技术方案，上述技术方案可以节约一道光罩制程（Normal Mask，普通掩模），有利于节省所述薄膜晶体管阵列基板的制作成本，以及提高
所述薄膜晶体管阵列基板的制作效率。
参考图5，图5为图1至图4所示的薄膜晶体管阵列基板的制作过程中所使用的掩模的示意图。
在本实施例中，所述第一光罩制程所对应的掩模（第一掩模501）包括一第一区域5011和至少一第二区域5012。所述第一区域5011具有第一开口率，所
述第一开口率与所述第一深度H1对应。所述第二区域5012具有第二开口率，所述第二开口率与所述第二深度H2对应。所述第一凹槽3011的深度（所述
第二深度H2）可根据GTM（Gray Tone Mask，灰色调掩模）的开口率（0-100%的开区间）来设置。
也就是说，所述钝化层201中的所述第一深度H1和所述第二深度H2是通过这样的方式来形成的：
利用具有所述第一区域5011和所述第二区域5012的所述第一掩模501，对所述钝化层201实施所述第一光罩制程，以同时形成所述第一深度H1和所述第
二深度H2，其中，所述第一区域5011具有所述第一开口率，所述第二区域5012具有所述第二开口率。例如，所述第一开口率为100%，所述第二开口率
（a%）处于0%至100%的范围（开区间）内，例如，所述a%为66.7%或60%。
参考图6和图7，图6为本发明的薄膜晶体管阵列基板的第二实施例的示意图，图7为图6所示的薄膜晶体管阵列基板的制作过程中所使用掩模的示意图。
本实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述凹槽阵列301中的凹槽具有两种不同的深度。也就是说，所述凹槽阵列301还包括至少一第二凹槽3012，所述第二凹槽3012具有第
三深度H2。
为了在同一道光罩制程（所述第一光罩制程）中一次性形成所述第一深度H1、所述第二深度H2和所述第三深度H2，所述第一光罩制程所对应的掩模（
所述第一掩模501）还包括至少一第三区域701。所述第三区域701具有第三开口率，所述第三开口率与所述第三深度H2对应。
所述第二凹槽3012的深度（所述第三深度H2）可根据GTM的开口率（0-100%的开区间）来设置。
也就是说，所述钝化层201中的所述第一深度H1、所述第二深度H2和所述第三深度H2是通过这样的方式来形成的：
利用具有所述第一区域5011、所述第二区域5012和所述第三区域701的所述第一掩模501，对所述钝化层201实施所述第一光罩制程，以同时形成所述第
一深度H1、所述第二深度H2和所述第三深度H2，其中，所述第一区域5011具有所述第一开口率，所述第二区域5012具有所述第二开口率，所述第三区
域701具有所述第三开口率。例如，所述第一开口率为100%，所述第二开口率（a%）和所述第三开口率（b%）均处于0%至100%的范围（开区间）内，a
不等于b，例如，所述a%、所述b%分别为66.7%或60%中的一者。
本发明的薄膜晶体管阵列基板的第三实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述凹槽阵列301中的凹槽具有两种不同的深度。也就是说，所述凹槽阵列301还包括至少一第三凹槽，所述第三凹槽具有第四深度。
所述孔洞302、所述第一凹槽3011、所述第三凹槽中的任意两者是在所述第二光罩制程中形成的，所述孔洞302、所述第一凹槽3011、所述第三凹槽中
的另一者是在所述第三光罩制程中形成的。
所述第二光罩制程所对应的掩模为灰色调掩模（GTM），所述第三光罩制程所对应的掩模为与所述灰色调掩模不同的掩模，例如，普通掩模（Normal
Mask）。
在上述第一至第三实施例中的任意一个实施例中，所述像素电极层401包括至少两第一部分以及至少两第二部分。
所述第一部分覆盖在所述钝化层201的表面上。所述第二部分从所述钝化层201的表面向所述凹槽阵列301中的凹槽（所述第一凹槽3011、所述第二凹槽
3012/所述第三凹槽）弯折并延伸至所述凹槽内，以及从所述凹槽内向所述钝化层201的所述表面弯折并延伸至所述钝化层201的所述表面。其中，所述
第一部分与所述第二部分相连。
也就是说，所述钝化层201201设置为凹凸不平状，所述钝化层201整面贴附于凹凸不平的所述钝化层201上，即，所述像素电极层401整面贴附于所述钝
化层201的表面和所述凹槽（所述第一凹槽3011、所述第二凹槽3012/所述第三凹槽）内，这样有利于使得所述薄膜晶体管阵列基板所对应的显示面板
具有较高的显示质量（例如，具有较高的穿透率）。
参考图1至图4、图8，图1至图4为本发明的薄膜晶体管阵列基板的制作方法的第一实施例的示意图，图8为本发明的薄膜晶体管阵列基板的制作方法的
第一实施例的流程图。
本实施例的薄膜晶体管阵列基板的制作方法包括以下步骤：
A（步骤801）、形成器件组合板101，其中，所述器件组合板101包括基板1011、第一信号线层1012、半导体层1014以及第二信号线层1017。
B（步骤802）、在所述器件组合板101上设置钝化层201。
C（步骤803）、对所述钝化层201实施光罩制程，以使所述钝化层201的表面上形成有一孔洞302和一凹槽阵列301，其中，所述凹槽阵列301包括至少一
第一凹槽3011。
D（步骤804）、在所述钝化层201的所述表面和所述凹槽阵列301内设置像素电极层401，其中，所述像素电极层401通过所述孔洞302与所述第二信号线
层1017连接。
在本实施例中，所述孔洞302具有第一深度H1，所述第一凹槽3011具有第二深度H2。
所述步骤C（步骤803）包括以下步骤：
c1、在第一光罩制程中形成所述凹槽阵列301（所述第一凹槽3011）与所述孔洞302。即，在同一道光罩制程（Gray Tone Mask，灰色调掩模）中形成
所述凹槽阵列301（所述第一凹槽3011）与所述孔洞302。
在本实施例中，所述第一光罩制程所对应的掩模（第一掩模501）包括一第一区域5011以及至少一第二区域5012。所述第一区域5011具有第一开口率，
所述第一开口率与所述第一深度H1对应。所述第二区域5012具有第二开口率，所述第二开口率与所述第二深度H2对应。所述第一凹槽3011的深度（所
述第二深度H2）可根据GTM（Gray Tone Mask，灰色调掩模）的开口率（0-100%的开区间）来设置。
也就是说，所述钝化层201中的所述第一深度H1和所述第二深度H2是通过这样的方式来形成的：
利用具有所述第一区域5011和所述第二区域5012的所述第一掩模501，对所述钝化层201实施所述第一光罩制程，以同时形成所述第一深度H1和所述第
二深度H2，其中，所述第一区域5011具有所述第一开口率，所述第二区域5012具有所述第二开口率。例如，所述第一开口率为100%，所述第二开口率
（a%）处于0%至100%的范围（开区间）内，例如，所述a%为66.7%或60%。
相比传统的技术方案，上述技术方案可以节约一道光罩制程（Normal Mask，普通掩模），有利于节省所述薄膜晶体管阵列基板的制作成本，以及提高
所述薄膜晶体管阵列基板的制作效率。
本发明的薄膜晶体管阵列基板的制作方法的第二实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述凹槽阵列301中的凹槽具有两种不同的深度。也就是说，所述凹槽阵列301还包括至少一第二凹槽3012，所述第二凹槽3012具有第
三深度H2。
为了在同一道光罩制程（所述第一光罩制程）中一次性形成所述第一深度H1、所述第二深度H2和所述第三深度H2，所述第一光罩制程所对应的掩模（
所述第一掩模501）还包括至少一第三区域701。所述第三区域701具有第三开口率，所述第三开口率与所述第三深度H2对应。
所述第二凹槽3012的深度（所述第三深度H2）可根据GTM的开口率（0-100%的开区间）来设置。
也就是说，所述钝化层201中的所述第一深度H1、所述第二深度H2和所述第三深度H2是通过这样的方式来形成的：
利用具有所述第一区域5011、所述第二区域5012和所述第三区域701的所述第一掩模501，对所述钝化层201实施所述第一光罩制程，以同时形成所述第
一深度H1、所述第二深度H2和所述第三深度H2，其中，所述第一区域5011具有所述第一开口率，所述第二区域5012具有所述第二开口率，所述第三区
域701具有所述第三开口率。例如，所述第一开口率为100%，所述第二开口率（a%）和所述第三开口率（b%）均处于0%至100%的范围（开区间）内，a
不等于b，例如，所述a%、所述b%分别为66.7%或60%中的一者。
参考图9，图9为本发明的薄膜晶体管阵列基板的制作方法的第三实施例的流程图。本实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述凹槽阵列301中的凹槽具有两种不同的深度。也就是说，所述凹槽阵列301还包括至少一第三凹槽，所述第三凹槽具有第四深度。
所述步骤C（步骤803）包括以下步骤：
c2（步骤901）、在所述第二光罩制程中形成所述孔洞302、所述第一凹槽3011、所述第三凹槽中的任意两者。
c3（步骤902）、在所述第三光罩制程中形成所述孔洞302、所述第一凹槽3011、所述第三凹槽中的另一者。
所述第二光罩制程所对应的掩模为灰色调掩模（GTM），所述第三光罩制程所对应的掩模为与所述灰色调掩模不同的掩模，例如，普通掩模（Normal
Mask）。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发
明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于
执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中
的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应
用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利
要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内
，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    一器件组合板，所述器件组合板包括：
    一基板；
    一第一信号线层；
    一半导体层；以及
    一第二信号线层；
    一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一第一凹槽；
    一像素电极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接；
    所述孔洞具有第一深度，所述第一凹槽具有第二深度；
    所述凹槽阵列与所述孔洞均是在第一光罩制程中形成的；
    所述凹槽阵列还包括至少一第三凹槽；
    所述孔洞、所述第一凹槽、所述第三凹槽中的任意两者是在所述第二光罩制程中形成的，所述孔洞、所述第一凹槽、所述第三凹槽中的另一者是在所
    述第三光罩制程中形成的。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述第一光罩制程所对应掩模包括：
    一第一区域，所述第一区域具有第一开口率，所述第一开口率与所述第一深度对应；
    至少一第二区域，所述第二区域具有第二开口率，所述第二开口率与所述第二深度对应；
    所述凹槽阵列还包括至少一第二凹槽，所述第二凹槽具有第三深度；
    所述第一光罩制程所对应掩模还包括：
    至少一第三区域，所述第三区域具有第三开口率，所述第三开口率与所述第三深度对应。
  3. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    一器件组合板，所述器件组合板包括：
    一基板；
    一第一信号线层；
    一半导体层；以及
    一第二信号线层；
    一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一第一凹槽；
    一像素电极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接。
  4. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述孔洞具有第一深度，所述第一凹槽具有第二深度；
    所述凹槽阵列与所述孔洞均是在第一光罩制程中形成的。
  5. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述第一光罩制程所对应的掩模包括：
    一第一区域，所述第一区域具有第一开口率，所述第一开口率与所述第一深度对应；
    至少一第二区域，所述第二区域具有第二开口率，所述第二开口率与所述第二深度对应。
  6. 根据权利要求5所述的薄膜晶体管阵列基板，其中，所述第一深度和所述第二深度是通过利用所述第一掩模对所述钝化层实施所述第一光罩制程来
    同时形成的，其中，所述第一掩模具有所述第一区域和所述第二区域。
  7. 根据权利要求5所述的薄膜晶体管阵列基板，其中，所述第一开口率等于100%，所述第二开口率大于0%，并且所述第二开口率小于100%。
  8. 根据权利要求5所述的薄膜晶体管阵列基板，其中，所述凹槽阵列还包括至少一第二凹槽，所述第二凹槽具有第三深度；
    所述第一光罩制程所对应的掩模还包括：
    至少一第三区域，所述第三区域具有第三开口率，所述第三开口率与所述第三深度对应。
  9. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述第一深度、所述第二深度和所述第三深度是通过利用所述第一掩模对所述钝化层实施所述
    第一光罩制程来同时形成的，其中，所述第一掩模具有所述第一区域、所述第二区域和所述第三区域。
  10. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述第一开口率等于100%，所述第二开口率和所述第三开口率均大于0%，并且所述第二开口率
    和所述第三开口率均小于100%。
  11. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述凹槽阵列还包括至少一第三凹槽；
    所述孔洞、所述第一凹槽、所述第三凹槽中的任意两者是在所述第二光罩制程中形成的，所述孔洞、所述第一凹槽、所述第三凹槽中的另一者是在所
    述第三光罩制程中形成的。
  12. 一种薄膜晶体管阵列基板的制作方法，其中，所述方法包括以下步骤：
    A、形成器件组合板，其中，所述器件组合板包括基板、第一信号线层、半导体层以及第二信号线层；
    B、在所述器件组合板上设置钝化层；
    C、对所述钝化层实施光罩制程，以使所述钝化层的表面上形成有一孔洞和一凹槽阵列，其中，所述凹槽阵列包括至少一第一凹槽；
    D、在所述钝化层的所述表面和所述凹槽阵列内设置像素电极层，其中，所述像素电极层通过所述孔洞与所述第二信号线层连接。
  13. 根据权利要求12所述的薄膜晶体管阵列基板的制作方法，其中，所述孔洞具有第一深度，所述第一凹槽具有第二深度；
    所述步骤C包括以下步骤：
    c1、在第一光罩制程中形成所述凹槽阵列与所述孔洞。
  14. 根据权利要求13所述的薄膜晶体管阵列基板的制作方法，其中，所述第一光罩制程所对应的掩模包括：
    一第一区域，所述第一区域具有第一开口率，所述第一开口率与所述第一深度对应；
    至少一第二区域，所述第二区域具有第二开口率，所述第二开口率与所述第二深度对应。
  15. 根据权利要求14所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤c1包括以下步骤：
    c11、利用具有所述第一区域和所述第二区域的所述第一掩模，对所述钝化层实施所述第一光罩制程，以同时形成所述第一深度和所述第二深度。
  16. 根据权利要求14所述的薄膜晶体管阵列基板的制作方法，其中，所述第一开口率等于100%，所述第二开口率大于0%，并且所述第二开口率小于
    100%。
  17. 根据权利要求14所述的薄膜晶体管阵列基板的制作方法，其中，所述凹槽阵列还包括至少一第二凹槽，所述第二凹槽具有第三深度；
    所述第一光罩制程所对应的掩模还包括：
    至少一第三区域，所述第三区域具有第三开口率，所述第三开口率与所述第三深度对应。
  18. 根据权利要求17所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤c1包括以下步骤：
    c12、利用具有所述第一区域、所述第二区域和所述第三区域的所述第一掩模，对所述钝化层实施所述第一光罩制程，以同时形成所述第一深度、所述
    第二深度和所述第三深度。
  19. 根据权利要求17所述的薄膜晶体管阵列基板的制作方法，其中，所述第一开口率等于100%，所述第二开口率和所述第三开口率均大于0%，并且所
    述第二开口率和所述第三开口率均小于100%。
  20. 根据权利要求12所述的薄膜晶体管阵列基板的制作方法，其中，所述凹槽阵列还包括至少一第三凹槽；
    所述步骤C包括以下步骤：
    c2、在所述第二光罩制程中形成所述孔洞、所述第一凹槽、所述第三凹槽中的任意两者；以及
    c3、在所述第三光罩制程中形成所述孔洞、所述第一凹槽、所述第三凹槽中的另一者。
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