WO2017031780A1 - 一种阵列基板和液晶显示面板 - Google Patents

一种阵列基板和液晶显示面板 Download PDF

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Publication number
WO2017031780A1
WO2017031780A1 PCT/CN2015/088964 CN2015088964W WO2017031780A1 WO 2017031780 A1 WO2017031780 A1 WO 2017031780A1 CN 2015088964 W CN2015088964 W CN 2015088964W WO 2017031780 A1 WO2017031780 A1 WO 2017031780A1
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WIPO (PCT)
Prior art keywords
pixel electrode
electrode region
data line
scan line
region
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PCT/CN2015/088964
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English (en)
French (fr)
Inventor
邓竹明
张君恺
林永伦
叶岩溪
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深圳市华星光电技术有限公司
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Publication of WO2017031780A1 publication Critical patent/WO2017031780A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • the liquid crystal alignment is not controlled, and light leakage occurs, so that a black matrix is provided at a position corresponding to the non-driving region to shield the light.
  • FIG. 1 it is a top view of a prior art array substrate; the prior art array substrate 10 includes a thin film transistor 100. a data line 101, a scan line 102, and a pixel unit interleaved by the data line 101 and the scan line 102; wherein the pixel unit 103 includes: a plurality of scan lines 101 The extended pixel electrode region 103 and the storage capacitor 104; the storage capacitor 104 is located between the pixel electrode region 103 and the scan line 102, as shown in FIG. There is a gap 106 between the scanning line 102 and the scanning line 102. Since the gap 106 may cause light leakage to affect the screen display, it is necessary to shield the slit by BM (black matrix).
  • BM black matrix
  • the commonly used shading method is to use a red color resist and a blue color resist to overlap the storage capacitor.
  • the gap between the scanning line 102 and the scanning line 102 is shielded.
  • the principle of color resistance overlap shading can be referred to Figure 2, as shown in Figure 2, giving R (red), G (green), B (Blue) Schematic diagram of the relationship between the stimulus values of the three primary colors and the wavelength, the abscissa indicates the wavelength length (in nanometers), the ordinate indicates the stimulus values of the three primary colors, and 201 indicates the wavelength of B is 435.8, 202 Indicates that the wavelength of G is 546.1203, indicating that the wavelength of R is 700;
  • the color resist R and the color resist B are utilized. By overlapping, the effect of shading can be achieved, and the manufacturing cost of the black matrix can be eliminated.
  • the areas where the color resists overlap are two kinds of color resists (R&B).
  • the thickness of the film will form a convex wall structure with respect to the display area at the center of the pixel, thus making the surface of the color filter substrate uneven, which is disadvantageous for liquid crystal and polyimide (PI).
  • PI liquid crystal and polyimide
  • first data line and a second data line wherein the first data line and the second data line are used to transmit a data signal
  • a first scan line, a second scan line, the first scan line and the second scan line for transmitting a scan signal
  • a pixel unit which is formed by staggering the first data line, the second data line, the first scan line, and the second scan line;
  • the pixel unit includes:
  • a thin film transistor having a gate connected to the first scan line, a source of the thin film transistor being connected to the first data signal for receiving the data signal; and the thin film transistor Controlling the pixel unit to perform screen display according to the data signal and the scan signal;
  • the patterned pixel electrode region is connected to the drain of the thin film transistor, and includes: a first pixel electrode region and a second pixel electrode region; a transmittance of the first pixel electrode region is greater than that of the second pixel electrode region Transmittance; the first pixel electrode region includes: a first strip electrode extending toward the first scan line;
  • a storage capacitor located below the second pixel electrode region, overlapping the second pixel electrode region for maintaining a screen display of the pixel unit;
  • the first strip electrode has an extension start end and an extension end end, the extension end end extending above the first scan line and overlapping the first scan line;
  • the patterned pixel electrode region being connected to a drain of the thin film transistor through the via hole;
  • the via is located above the storage capacitor and overlaps the storage capacitor.
  • the first pixel electrode region is a branched pixel electrode region
  • the second pixel electrode region is a main pixel electrode region
  • the trunk pixel electrode region includes: a plurality of stem electrodes.
  • the main pixel electrode region includes: a first trunk electrode and a second trunk electrode, the first trunk electrode and the second trunk electrode intersect to form an intersection region;
  • the storage capacitor is located directly below the intersection region and overlaps the intersection region.
  • the first pixel electrode region further includes: a second strip electrode extending toward the first data line; the second strip electrode has an extension start end and an extension end end, The extension end extends over the first data line and overlaps the first data line.
  • the first pixel electrode region further includes: a third strip electrode extending toward the second data line; the third strip electrode has an extension start end and an extension end end, The extension end extends over the second data line and overlaps the second data line.
  • the first pixel electrode region further includes: a third strip electrode extending toward the second data line; the third strip shape The electrode has an extension start end and an extension end end that extends above the second data line and overlaps the second data line.
  • the array substrate comprises:
  • a first metal layer including: the first scan line, the second scan line, a gate of the thin film transistor, and a first capacitor electrode of the storage capacitor;
  • a second metal layer over the first metal layer including: the first data line, the second data line, a source and a drain of the thin film transistor, and a second of the storage capacitor Capacitor electrode.
  • An embodiment of the present invention further provides another array substrate, including:
  • first data line and a second data line wherein the first data line and the second data line are used to transmit a data signal
  • first scan line and a second scan line wherein the first scan line and the second scan line are used to transmit a scan signal
  • a pixel unit which is formed by staggering the first data line, the second data line, the first scan line, and the second scan line;
  • the pixel unit includes:
  • a thin film transistor having a gate connected to the first scan line, a source of the thin film transistor being connected to the first data signal for receiving the data signal; and the thin film transistor Controlling the pixel unit to perform screen display according to the data signal and the scan signal;
  • the patterned pixel electrode region is connected to the drain of the thin film transistor, and includes: a first pixel electrode region and a second pixel electrode region; a transmittance of the first pixel electrode region is greater than that of the second pixel electrode region Transmittance; the first pixel electrode region includes: a first strip electrode extending toward the first scan line;
  • a storage capacitor located below the second pixel electrode region, overlapping the second pixel electrode region for maintaining a screen display of the pixel unit;
  • the first strip electrode has an extension start end and an extension end end, and the extension end end extends above the first scan line and overlaps the first scan line.
  • the first pixel electrode region is a branched pixel electrode region
  • the second pixel electrode region is a main pixel electrode region
  • the trunk pixel electrode region includes: a plurality of stem electrodes.
  • the main pixel electrode region includes: a first trunk electrode and a second trunk electrode, the first trunk electrode and the second trunk electrode intersect to form an intersection region;
  • the storage capacitor is located directly below the intersection region and overlaps the intersection region.
  • the pixel unit further includes: a via hole between the patterned pixel electrode region and the drain;
  • the patterned pixel electrode region is connected to a drain of the thin film transistor through the via hole;
  • the via is located above the storage capacitor and overlaps the storage capacitor.
  • the first pixel electrode region further includes: a second strip electrode extending toward the first data line; the second strip electrode has an extension start end and an extension end end, The extension end extends over the first data line and overlaps the first data line.
  • the first pixel electrode region further includes: a third strip electrode extending toward the second data line; the third strip electrode has an extension start end and an extension end end, The extension end extends over the second data line and overlaps the second data line.
  • the method includes:
  • a first metal layer including: the first scan line, the second scan line, a gate of the thin film transistor, and a first capacitor electrode of the storage capacitor;
  • a second metal layer over the first metal layer including: the first data line, the second data line, a source and a drain of the thin film transistor, and a second of the storage capacitor Capacitor electrode.
  • an embodiment of the present invention further provides a liquid crystal display panel, including:
  • the array substrate includes:
  • first data line and a second data line wherein the first data line and the second data line are used to transmit a data signal
  • first scan line and a second scan line wherein the first scan line and the second scan line are used to transmit a scan signal
  • a pixel unit which is formed by staggering the first data line, the second data line, the first scan line, and the second scan line;
  • the pixel unit includes:
  • a thin film transistor having a gate connected to the first scan line, a source of the thin film transistor being connected to the first data signal for receiving the data signal; and the thin film transistor Controlling the pixel unit to perform screen display according to the data signal and the scan signal;
  • the patterned pixel electrode region is connected to the drain of the thin film transistor, and includes: a first pixel electrode region and a second pixel electrode region; a transmittance of the first pixel electrode region is greater than that of the second pixel electrode region Transmittance; the first pixel electrode region includes: a first strip electrode extending toward the first scan line;
  • a storage capacitor located below the second pixel electrode region, overlapping the second pixel electrode region for maintaining a screen display of the pixel unit;
  • the first strip electrode has an extension start end and an extension end end, and the extension end end extends above the first scan line and overlaps the first scan line.
  • the first pixel electrode region is a branch pixel electrode region
  • the second pixel electrode region is a main pixel electrode region
  • the trunk pixel electrode region includes: a plurality of stem electrodes.
  • the main pixel electrode region includes: a first trunk electrode and a second trunk electrode, the first trunk electrode and the second trunk electrode intersect to form an intersection region;
  • the storage capacitor is located directly below the intersection region and overlaps the intersection region.
  • the pixel unit further includes: a via hole between the patterned pixel electrode region and the drain;
  • the patterned pixel electrode region is connected to a drain of the thin film transistor through the via hole;
  • the via is located above the storage capacitor and overlaps the storage capacitor.
  • the first pixel electrode region further includes: a second strip electrode extending toward the first data line; the second strip electrode has an extension start end and an extension end end, The extension end extends above the first data line and overlaps the first data line.
  • the first pixel electrode region further includes: a third strip electrode extending toward the second data line; the third strip electrode has an extension start end and an extension end end, The extension end extends over the second data line and overlaps the second data line.
  • Embodiments of the present invention provide an array substrate and a liquid crystal display panel.
  • the gap between the scan line and the storage capacitor is eliminated, thereby eliminating the direction of the scan line.
  • the overlapping areas of the color resistance that is, the raised wall structure, thereby improving the flow of the liquid crystal and the PI, improving the display effect and reducing the cost.
  • the storage capacitor in the array substrate of the present invention is located below the second pixel electrode region with low transmittance, which can avoid the storage capacitor occupying the light transmission area and improve the aperture ratio of the liquid crystal display panel.
  • FIG. 1 is a top plan view of a prior art array substrate
  • 2 is a schematic diagram showing the relationship between the stimulus values of the three primary colors and the wavelength
  • FIG. 3 is a schematic structural diagram of a first array substrate according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic structural diagram of a second array substrate according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of a third array substrate according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display panel according to Embodiment 2 of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the embodiment provides an array substrate, including:
  • a first data line 301, a second data line 302, the first data line 301 and the second data line 302 are used for transmitting a data signal;
  • a pixel unit which is formed by interleaving the first data line 301, the second data line 302, the first scan line 303, and the second scan line 304;
  • the pixel unit includes:
  • a thin film transistor 305 a gate electrode 3051 of the thin film transistor 305 is connected to the first scan line 303, and a source of the thin film transistor 3052 is connected to the first data signal 301 for receiving the data signal;
  • the thin film transistor 305 is configured to control the pixel unit to perform screen display according to the data signal and the scan signal;
  • the patterned pixel electrode region 306 is connected to the drain electrode 3053 of the thin film transistor 305, and includes: a first pixel electrode region and a second pixel electrode region; the first pixel electrode region includes: toward the first scan line 303 The extended first strip electrode 3061, the second strip electrode 3062 extending toward the first data line 301, the third strip electrode 3063 extending toward the second data extension 302, and the fourth strip extending toward the second scan line 304 Electrode 3064;
  • the patterned pixel electrode region 306 in this embodiment may include two kinds of pixel electrode regions; one is a first pixel electrode region, for example, a branched pixel electrode region composed of branched pixel electrodes, and the other is that the light transmittance is less than a second pixel electrode region of light transmittance of the first pixel electrode region, for example, a trunk pixel electrode region composed of a plurality of main pixel electrodes.
  • the light transmittance of the main pixel electrode region is smaller than the branch pixel electrode region. of.
  • the branch pixel electrode region includes: a first strip electrode 3061, a second strip electrode 3062, a third strip electrode 3063, and a fourth strip electrode 3064.
  • the main pixel electrode region includes: a first stem electrode The first strip electrode 3061, the second strip electrode 3062, the third strip electrode 3063, and the fourth strip electrode 3064 are electrically connected to the corresponding trunk electrodes, respectively.
  • the first trunk electrode 3065 and the second stem electrode 3066 intersect to form an intersection region 3067.
  • the array substrate of this embodiment further includes: a storage capacitor 307 located below the second pixel electrode region and overlapping with the second pixel electrode region for maintaining a screen display of the pixel unit; specifically, as shown in FIG.
  • the storage capacitor 307 is located directly below the intersection region 3067 and overlaps the intersection region 3067. Since the intersection region 3067 is the pixel region with the lowest transmittance in the patterned pixel electrode region 306, it can maximize Increase the aperture ratio.
  • the storage capacitor 307 may be located below and overlap the pixel region in which the light transmittance is the smallest in the patterned pixel electrode region.
  • the first strip electrode 3061 has an extension start end and an extension end end, and the extension end end extends above the first scan line 303 and overlaps with the first scan line 303; specifically, As shown in FIG. 3, the first strip electrode 3061 extends toward the first scan line 303, and the end is placed on the first scan line 303.
  • the array substrate of the present embodiment eliminates the gap between the existing first scan line 303 and the storage capacitor 307 by changing the position of the storage capacitor 307 in the pixel unit and extending the first strip electrode 3061 (ie, the figure is eliminated).
  • the slit 106 in 1 eliminates the overlapping area of the color resistance in the direction of the scanning line, that is, the convex wall structure, thereby improving the flow of the liquid crystal and the PI, improving the display effect and reducing the cost.
  • the storage capacitor in the array substrate of the embodiment is located below the main pixel electrode region with low transmittance, specifically under the intersection region 3067, which can prevent the storage capacitor from occupying the light transmission area of the pixel unit and increase the aperture ratio of the array substrate.
  • the opaque vias for patterning the pixel electrode regions 306 and the drain electrodes 3053 in the array substrate may occupy a certain light transmissive area and reduce the aperture ratio in the pixel electrode region with high transmittance;
  • at least a portion of the via is disposed above the storage capacitor 307 and overlaps the storage capacitor 307.
  • the array substrate further includes: a via 308 between the patterned pixel electrode region 306 and the drain 3053; and the patterned pixel electrode region 306 passes through the via 308.
  • the via 308 Connected to the drain 3053 of the thin film transistor 305; wherein the via 308 is located above the storage capacitor 307, overlapping the storage capacitor 308, preferably between the intersection region 3067 and the storage capacitor 307.
  • the storage capacitor 307 since the storage capacitor 307 is opaque, it originally occupies a certain light transmissive area, and the via 308 is disposed above the storage capacitor 308 to overlap with the storage capacitor 308, so that the via 308 does not occupy additional
  • the light transmission area further increases the aperture ratio.
  • the prior art generally shields the gap by using a color group overlapping manner, so that there is a color group overlapping area in the data line direction.
  • a convex wall structure is formed with respect to the display area at the center of the pixel, which may cause the surface of the color filter substrate to be uneven, which is disadvantageous for the flow of liquid crystal and polyimide (PI), thereby affecting optical performance and reducing display effect.
  • the second strip electrode 3062 may be extended to the first data line 301 and placed on the first data.
  • the second strip electrode 3062 has an extension start end and an extension end end that extends above the first data line 301 and overlaps the first data line 301.
  • the wall structure in the direction of the second data line 302 is further eliminated.
  • the third strip electrode 3063 extends to the second data line 302, and the end is placed on the second data line 3062;
  • the third strip electrode 3063 has an extension start end and an extension end end extending above the second data line and overlapping the second data line.
  • the ends of the second strip electrode 3062 and the third strip electrode 3063 in the array substrate of the embodiment are all on the data line, the gap between the data line and the patterned pixel electrode region is eliminated, and the data is avoided.
  • the color direction overlap is used to shield the light in the line direction, thereby eliminating the convex wall structure, thereby improving the flow of the liquid crystal and the PI, and suggesting the display effect.
  • the storage capacitor 307 in particular, the pixel voltage signal is maintained during the opening of the thin film transistor 305 to maintain the screen display of the pixel unit; in this embodiment, the storage capacitor 307 is formed in various manners; preferably, the implementation
  • the storage capacitor 307 is composed of a first capacitor electrode on the first metal layer in the array substrate and a second capacitor electrode on the second metal layer; specifically:
  • a first metal layer including: the first scan line 303, the second scan line 304, the gate 302 of the thin film transistor 305, and a first capacitor electrode of the storage capacitor 307;
  • a second metal layer over the first metal layer including: the first data line 301, the second data line 302, a source 3051 and a drain 3053 of the thin film transistor 305, and the A second capacitor electrode of the storage capacitor 307.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the embodiment provides a liquid crystal display panel, including:
  • liquid crystal layer 62 between the array substrate 61 and the color filter substrate 63;
  • the array substrate 61 is the array substrate of the first embodiment. Referring to FIG. 3-5, the method may include:
  • a first data line 301, a second data line 302, the first data line 301 and the second data line 302 are used for transmitting a data signal;
  • a pixel unit which is formed by interleaving the first data line 301, the second data line 302, the first scan line 303, and the second scan line 304;
  • a thin film transistor 305 a gate electrode 3051 of the thin film transistor 305 is connected to the first scan line 303, and a source of the thin film transistor 3052 is connected to the first data signal 301 for receiving the data signal;
  • the thin film transistor 305 is configured to control the pixel unit to perform screen display according to the data signal and the scan signal;
  • the patterned pixel electrode region 306 is connected to the drain electrode 3053 of the thin film transistor 305, and includes: a first pixel electrode region and a second pixel electrode region; the first pixel electrode region includes: toward the first scan line 303 Extended first strip electrode 3061;
  • a storage capacitor 307 is located below the second pixel electrode region and overlaps the second pixel electrode region for maintaining a screen display of the pixel unit;
  • the first strip electrode 3061 has an extension start end and an extension end end, and the extension end end extends above the first scan line 303.
  • the main pixel electrode region in the liquid crystal display panel of the embodiment includes: a first trunk electrode and a second trunk electrode, wherein the first trunk electrode and the second trunk electrode intersect to form an intersection region;
  • the storage capacitor is located directly below the intersection region and overlaps the intersection region.
  • the main pixel electrode region includes: a first trunk electrode and a second trunk electrode, the first trunk electrode and the second trunk electrode intersect to form an intersection region;
  • the storage capacitor is located directly below the intersection region and overlaps the intersection region.
  • Embodiments of the present invention provide a liquid crystal display panel that eliminates a gap between a scan line and a storage capacitor by changing a position of a storage capacitor in a pixel unit and extending the pixel electrode, thereby eliminating color-resistance overlap in the direction of the scan line.
  • the area that is, the raised wall structure, improves the flow of liquid crystal and PI, improves display performance and reduces cost.
  • the storage capacitor is located below the second pixel electrode region with low transmittance, which can avoid the storage capacitor occupying the light transmission area and improve the aperture ratio of the liquid crystal display panel.

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Abstract

一种阵列基板和液晶显示面板，阵列基板通过改变像素单元中存储电容（307）位置以及延长像素电极（3061，3062，3063），消除了扫描线（303）与存储电容（307）之间的缝隙，从而省去了扫描线（303）方向上的色阻重叠的区域，即凸起的围墙结构，进而改善了液晶和PI的流动，提高了显示效果以及降低了成本。

Description

一种阵列基板和液晶显示面板 技术领域
本发明涉及液晶显示器技术领域，特别是涉及一种阵列基板和液晶显示面板。
 背景技术
在现有的液晶显示面板中，相邻像素之间存在非驱动区域，液晶排列不受控制，会出现漏光，所以与非驱动区域相应位置设置有黑色矩阵对其进行遮光。
如图 1 所示，为现有技术的阵列基板的俯视图； 现有技术的阵列基板 10 包括薄膜晶体管 100 、数据线 101 ，扫描线 102 ，以及由数据线 101 和扫描线 102 交错构成像素单元；其中像素单元 103 包括：多条向扫描线 101 延伸的像素电极区域 103 、以及存储电容 104 ；存储电容 104 位于像素电极区域 103 与扫描线 102 之间，如图 1 所示，存储电容 104 与扫描线 102 之间会存在缝隙 106 ；由于该缝隙 106 会漏光影响画面显示，因此需要采用 BM （黑色矩阵）对该缝隙进行遮光。
考虑到 BM 制作成本比较大，目前常用的遮光方式为：采用红色色阻和蓝色色阻进行重叠来对存储电容 104 与扫描线 102 之间的缝隙进行遮光。具体地色阻重叠遮光的原理可以参考图 2 ，如图 2 所示，给出 R( 红 ) 、 G （绿）、 B （蓝）三原色的刺激值与波长的图谱关系示意图，横坐标表示波长长度（单位为纳米），纵坐标表示三原色的刺激值； 201 表示 B 的波长为 435.8 ， 202 表示 G 的波长为 546.1203 表示 R 的波长为 700 ；
由于人眼的可见光的波长范围介于 390-700 纳米范围，利用色阻 R 与色阻 B 进行重叠，可以达到遮光的效果，便省去黑色矩阵的制程成本。
然而采用色阻重叠遮光时，色阻交叠的区域为两种色阻（ R&B ）的厚度，相对于像素中央的显示区域会形成凸起的围墙结构，因此会使彩膜基板的表面不平整，不利于液晶和聚酰亚胺 (PI) 的流动，从而影响光学性能，降低显示效果。
因此，有必要提供一种阵列基板和液晶显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种液晶显示面板及装置，以解决现显示面板采用色阻重叠的遮光方式会导致彩膜基板表面不平整，影响显示效果的技术问题。
 技术解决方案
本发明的实施例提供了一种阵列基板，其包括：
第一数据线、第二数据线，所述第一数据线和所述第二数据线用于传输数据信号；
第一扫描线、第二扫描线，所述第一扫描线和所述第二扫描线用于传输扫描信号；以及
像素单元，由所述第一数据线、所述第二数据线、所述第一扫描线以及所述第二扫描线交错构成；
所述像素单元包括：
薄膜晶体管，所述薄膜晶体管的栅极与所述第一扫描线连接，所述薄膜晶体管的源极与所述第一数据信号连接，用于接收所述数据信号；所述薄膜晶管，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
图案化像素电极区域，与所述薄膜晶体管的漏极连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域的透光率大于所述第二像素电极区域的透光率；所述第一像素电极区域包括：向所述第一扫描线延伸的第一条状电极；
存储电容，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；
其中，所述第一条状电极具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线上方，且与所述第一扫描线重叠；
位于图案化像素电极区域与所述漏极之间的过孔，所述图案化像素电极区域通过所述过孔与所述薄膜晶体管的漏极连接；以及
所述过孔位于所述存储电容的上方，与所述存储电容重叠。
在本发明的阵列基板中，所述第一像素电极区域为分支像素电极区域，所述第二像素电极区域为主干像素电极区域，所述主干像素电极区域包括：多条主干电极。
在本发明的阵列基板中，所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
在本发明的阵列基板中，所述第一像素电极区域还包括：向所述第一数据线延伸的第二条状电极；所述第二条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第一数据线上方，且与所述第一数据线重叠。
在本发明的阵列基板中，所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
在本发明的阵列基板中，阵列基板存在第二条状电极情况下，所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
在本发明的阵列基板中，所述阵列基板包括：
第一金属层，其包括：所述第一扫描线、所述第二扫描线、所述薄膜晶体管的栅极、以及所述存储电容的第一电容电极；
第二金属层，位于所述第一金属层上方，其包括：所述第一数据线、所述第二数据线、所述薄膜晶体管的源极和漏极、以及所述存储电容的第二电容电极。
本发明的实施例还提供了另一种阵列基板，包括：
第一数据线、第二数据线，所述第一数据线和所述第二数据线用于传输数据信号；
第一扫描线、第二扫描线，所述第一扫描线和所述第二扫描线用于传输扫描信号；
像素单元，由所述第一数据线、所述第二数据线、所述第一扫描线以及所述第二扫描线交错构成；
所述像素单元包括：
薄膜晶体管，所述薄膜晶体管的栅极与所述第一扫描线连接，所述薄膜晶体管的源极与所述第一数据信号连接，用于接收所述数据信号；所述薄膜晶管，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
图案化像素电极区域，与所述薄膜晶体管的漏极连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域的透光率大于所述第二像素电极区域的透光率；所述第一像素电极区域包括：向所述第一扫描线延伸的第一条状电极；
存储电容，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；
其中，所述第一条状电极具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线上方，且与所述第一扫描线重叠。
在本发明的阵列基板中，所述第一像素电极区域为分支像素电极区域，所述第二像素电极区域为主干像素电极区域，所述主干像素电极区域包括：多条主干电极。
在本发明的阵列基板中，所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
在本发明的阵列基板中，所述像素单元还包括：位于图案化像素电极区域与所述漏极之间的过孔；
所述图案化像素电极区域通过所述过孔与所述薄膜晶体管的漏极连接；
其中，所述过孔位于所述存储电容的上方，与所述存储电容重叠。
在本发明的阵列基板中，所述第一像素电极区域还包括：向所述第一数据线延伸的第二条状电极；所述第二条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第一数据线上方，且与所述第一数据线重叠。
在本发明的阵列基板中，所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
在本发明的阵列基板中，包括：
第一金属层，其包括：所述第一扫描线、所述第二扫描线、所述薄膜晶体管的栅极、以及所述存储电容的第一电容电极；
第二金属层，位于所述第一金属层上方，其包括：所述第一数据线、所述第二数据线、所述薄膜晶体管的源极和漏极、以及所述存储电容的第二电容电极。
同样为了解决上述技术问题，本发明的实施例还提供了一种液晶显示面板，包括：
阵列基板；
彩膜基板；
位于所述阵列基板和所述彩膜基板之间的液晶层；
所述阵列基板，包括：
第一数据线、第二数据线，所述第一数据线和所述第二数据线用于传输数据信号；
第一扫描线、第二扫描线，所述第一扫描线和所述第二扫描线用于传输扫描信号；
像素单元，由所述第一数据线、所述第二数据线、所述第一扫描线以及所述第二扫描线交错构成；
所述像素单元包括：
薄膜晶体管，所述薄膜晶体管的栅极与所述第一扫描线连接，所述薄膜晶体管的源极与所述第一数据信号连接，用于接收所述数据信号；所述薄膜晶管，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
图案化像素电极区域，与所述薄膜晶体管的漏极连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域的透光率大于所述第二像素电极区域的透光率；所述第一像素电极区域包括：向所述第一扫描线延伸的第一条状电极；
存储电容，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；
其中，所述第一条状电极具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线上方，且与所述第一扫描线重叠。
在本发明的液晶显示面板中，第一像素电极区域为分支像素电极区域，所述第二像素电极区域为主干像素电极区域，所述主干像素电极区域包括：多条主干电极。
在本发明的液晶显示面板中，所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
在本发明的液晶显示面板中，所述像素单元还包括：位于图案化像素电极区域与所述漏极之间的过孔；
所述图案化像素电极区域通过所述过孔与所述薄膜晶体管的漏极连接；
其中，所述过孔位于所述存储电容的上方，与所述存储电容重叠。
在本发明的液晶显示面板中，所述第一像素电极区域还包括：向所述第一数据线延伸的第二条状电极；所述第二条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第一数据线上方，且与所述第一数据线重叠。
在本发明的液晶显示面板中，所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
 有益效果
本发明的实施例提供了一种阵列基板和液晶显示面板，通过改变像素单元中存储电容位置以及延长像素电极，消除了扫描线与存储电容之间的缝隙，从而省去了扫描线方向上的色阻重叠的区域，即凸起的围墙结构，进而改善了液晶和PI的流动，提高了显示效果以及降低了成本。
另外，本发明阵列基板中存储电容位于透光率低的第二像素电极区域下方，可以避免存储电容占用透光面积，提高液晶显示面板的开口率。
 附图说明
图1为现有技术的阵列基板的俯视图；
图2为三原色的刺激值与波长的图谱关系示意图；
图3为本发明实施例一提供的第一种阵列基板的结构示意图；
图4为本发明实施例一提供的第二种阵列基板的结构示意图；
图5为本发明实施例一提供的第三种阵列基板的结构示意图；
图6为本发明实施例二提供的一种液晶显示面板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一：
如图3所示，本实施例提供了一种阵列基板，包括：
第一数据线301、第二数据线302，所述第一数据线301和所述第二数据线302用于传输数据信号；
第一扫描线303、第二扫描线304，第一扫描线302和第二扫描线304用于传输扫描信号；
像素单元，由第一数据线301、第二数据线302、第一扫描线303以及第二扫描线304交错构成；
所述像素单元包括：
薄膜晶体管305，所述薄膜晶体管305的栅极3051与所述第一扫描线303连接，所述薄膜晶体管3052的源极与所述第一数据信号301连接，用于接收所述数据信号；所述薄膜晶管305，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
图案化像素电极区域306，与所述薄膜晶体管305的漏极3053连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域包括：向所述第一扫描线303延伸的第一条状电极3061，向第一数据线301延伸的第二条状电极3062，向第二数据延伸302的第三条状电极3063以及向第二扫描线304延伸的第四条状电极3064；
具体地，本实施例中图案化像素电极区域306可以包括两种像素电极区域；一种是第一像素电极区域，例如由分支像素电极构成的分支像素电极区域，另一种是透光率小于第一像素电极区域的透光率的第二像素电极区域，例如由多条主干像素电极构成的主干像素电极区域，在实际应用中，一般主干像素电极区域的透光率是小于分支像素电极区域的。
如图3所示，分支像素电极区域包括：第一条状电极3061，第二条状电极3062，第三条状电极3063，第四条状电极3064；主干像素电极区域包括：第一主干电极3065和第二主干电极3066；第一条状电极3061，第二条状电极3062，第三条状电极3063，第四条状电极3064分别与对应的主干电极电性连接。
优选地，本实施例中，第一主干电极3065与第二主干电极3066相交形成一个相交区域3067。
本实施例阵列基板还包括：存储电容307，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；具体地如图3所示，本实施例中存储电容307位于相交区域3067的正下方，且与相交区域3067重叠，由于该相交区域3067为图案化像素电极区域306中透光率最低的像素区域，其可以最大限度地提高开口率。优选地，存储电容307可以位于图案化像素电极区域中透光率最小的像素区域下方，并与该区域重叠。
本实施例中，第一条状电极3061具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线303上方，且与所述第一扫描线303重叠；具体地，如图3所示，第一条状电极3061向第一扫描线303延伸，并且末端搭在第一扫描线303上。
由上可知，本实施例的阵列基板通过改变像素单元中存储电容307位置以及延长第一条状电极3061，消除了现有第一扫描线303与存储电容307之间的缝隙（即消除了图1中的缝隙106），从而省去了扫描线方向上的色阻重叠的区域，即凸起的围墙结构，进而改善了液晶和PI的流动，提高了显示效果以及降低了成本。
另外，本实施例阵列基板中存储电容位于透光率低的主干像素电极区域下方，具体地位于相交区域3067下方，可以避免存储电容占用像素单元的透光面积，提高阵列基板的开口率。
考虑到阵列基板中用于图案化像素电极区域306与漏极3053连接的不透光的过孔如果在透光率高的像素电极区域，会占一定的透光面积，降低开口率；本实施例中将该过孔的至少一部分设置在存储电容307的上方，与存储电容307重叠。
具体地，如图4所示，本实施例中阵列基板还包括：位于图案化像素电极区域306与所述漏极3053之间的过孔308；图案化像素电极区域306通过所述过孔308与所述薄膜晶体管305的漏极3053连接；其中过孔308位于存储电容307的上方，与存储电容308重叠，优选地，位于相交区域3067与存储电容307之间。
本实施例中由于存储电容307不透光，其本来就占用一定的透光面积，将过孔308设置在存储电容308的上方，与存储电容308重叠，这样过孔308就不会占用额外的透光面积，进一步提升开口率。
考虑到现有数据线方向上数据线与图案像素电极区域之间会存在缝隙，现有技术一般采用色组重叠的方式对该缝隙遮光，因此会在数据线方向上存在色组交叠区域，相对于像素中央的显示区域会形成凸起的围墙结构，会使彩膜基板的表面不平整，不利于液晶和聚酰亚胺(PI)的流动，从而影响光学性能，降低显示效果。
为了进一步消除第一数据线301方向上的围墙结构，如图5所示，在本实施例阵列基板中，可以使第二条状电极3062延伸至第一数据线301，并搭在第一数据线301上 ；具体地，第二条状电极3062具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第一数据线301上方，且与所述第一数据线301重叠。
参考图5，同样，进一步消除第二数据线302方向上的围墙结构，本实施例中第三条状电极3063延伸至第二数据线302上，且末端搭在第二数据线3062上；具体地，第三条状电极3063具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
由于，本实施例阵列基板中第二条状电极3062和第三条状电极3063的末端均搭在数据线上，因此，消除了数据线与图案像素电极区域之间的缝隙，避免了在数据线方向上采用色组重叠来遮光，从而消除了凸起的围墙结构，进而改善了液晶和PI的流动，提示了显示效果。
在本实施例中存储电容307具体地，薄膜晶体管305打开的期间，维持像素电压信号，以维持像素单元的画面显示；本实施例中存储电容307的形成有多种方式；优选地，本实施例中存储电容307由阵列基板中第一金属层上的第一电容电极和第二金属层上的第二电容电极构成；具体地：
本实施例中阵列基板包括：
第一金属层，其包括：所述第一扫描线303、所述第二扫描线304、所述薄膜晶体管305的栅极302、以及所述存储电容307的第一电容电极；
第二金属层，位于所述第一金属层上方，其包括：所述第一数据线301、所述第二数据线302、所述薄膜晶体管305的源极3051和漏极3053、以及所述存储电容307的第二电容电极。
实施例二：
参考图6，本实施例提供了一种液晶显示面板，包括：
阵列基板61；
彩膜基板63；
位于所述阵列基板61和所述彩膜基板63之间的液晶层62；
阵列基板61，为实施例一所述的阵列基板，参考图3-5，其可以包括：
第一数据线301、第二数据线302，所述第一数据线301和所述第二数据线302用于传输数据信号；
第一扫描线303、第二扫描线304，第一扫描线302和第二扫描线304用于传输扫描信号；
像素单元，由第一数据线301、第二数据线302、第一扫描线303以及第二扫描线304交错构成；
薄膜晶体管305，所述薄膜晶体管305的栅极3051与所述第一扫描线303连接，所述薄膜晶体管3052的源极与所述第一数据信号301连接，用于接收所述数据信号；所述薄膜晶管305，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
图案化像素电极区域306，与所述薄膜晶体管305的漏极3053连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域包括：向所述第一扫描线303延伸的第一条状电极3061；
存储电容307，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；
本实施例中，第一条状电极3061具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线303上方。
优选地，本实施例液晶显示面板中所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
优选地，所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
本发明的实施例提供了一种液晶显示面板，通过改变像素单元中存储电容位置以及延长像素电极，消除了扫描线与存储电容之间的缝隙，从而省去了扫描线方向上的色阻重叠的区域，即凸起的围墙结构，进而改善了液晶和PI的流动，提高了显示效果以及降低了成本。
另外，本实施例液晶显示面板中存储电容位于透光率低的第二像素电极区域下方，可以避免存储电容占用透光面积，提高液晶显示面板的开口率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    第一数据线、第二数据线，所述第一数据线和所述第二数据线用于传输数据信号；
    第一扫描线、第二扫描线，所述第一扫描线和所述第二扫描线用于传输扫描信号；
    像素单元，由所述第一数据线、所述第二数据线、所述第一扫描线以及所述第二扫描线交错构成；
    所述像素单元包括：
    薄膜晶体管，所述薄膜晶体管的栅极与所述第一扫描线连接，所述薄膜晶体管的源极与所述第一数据信号连接，用于接收所述数据信号；所述薄膜晶管，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
    图案化像素电极区域，与所述薄膜晶体管的漏极连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域的透光率大于所述第二像素电极区域的透光率；所述第一像素电极区域包括：向所述第一扫描线延伸的第一条状电极；
    存储电容，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；
    其中，所述第一条状电极具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线上方，且与所述第一扫描线重叠；
    位于图案化像素电极区域与所述漏极之间的过孔，所述图案化像素电极区域通过所述过孔与所述薄膜晶体管的漏极连接；以及
    所述过孔位于所述存储电容的上方，与所述存储电容重叠。
  2. 如权利要求1所述的阵列基板，其中所述第一像素电极区域为分支像素电极区域，所述第二像素电极区域为主干像素电极区域，所述主干像素电极区域包括：多条主干电极。
  3. 如权利要求2所述的阵列基板，其中所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
    所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
  4. 如权利要求1所述的阵列基板，其中所述第一像素电极区域还包括：向所述第一数据线延伸的第二条状电极；所述第二条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第一数据线上方，且与所述第一数据线重叠。
  5. 如权利要求4所述的阵列基板，其中所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
  6. 如权利要求1所述的阵列基板，其中所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
  7. 如权利要求1所述的阵列基板，其中所述阵列基板包括：
    第一金属层，其包括：所述第一扫描线、所述第二扫描线、所述薄膜晶体管的栅极、以及所述存储电容的第一电容电极；
    第二金属层，位于所述第一金属层上方，其包括：所述第一数据线、所述第二数据线、所述薄膜晶体管的源极和漏极、以及所述存储电容的第二电容电极。
  8. 一种阵列基板，其中包括：
    第一数据线、第二数据线，所述第一数据线和所述第二数据线用于传输数据信号；
    第一扫描线、第二扫描线，所述第一扫描线和所述第二扫描线用于传输扫描信号；
    像素单元，由所述第一数据线、所述第二数据线、所述第一扫描线以及所述第二扫描线交错构成；
    所述像素单元包括：
    薄膜晶体管，所述薄膜晶体管的栅极与所述第一扫描线连接，所述薄膜晶体管的源极与所述第一数据信号连接，用于接收所述数据信号；所述薄膜晶管，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
    图案化像素电极区域，与所述薄膜晶体管的漏极连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域的透光率大于所述第二像素电极区域的透光率；所述第一像素电极区域包括：向所述第一扫描线延伸的第一条状电极；
    存储电容，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；以及
    其中，所述第一条状电极具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线上方，且与所述第一扫描线重叠。
  9. 如权利要求8所述的阵列基板，其中所述第一像素电极区域为分支像素电极区域，所述第二像素电极区域为主干像素电极区域，所述主干像素电极区域包括：多条主干电极。
  10. 如权利要求9所述的阵列基板，其中所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
    所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
  11. 如权利要求8所述的阵列基板，其中所述像素单元还包括：位于图案化像素电极区域与所述漏极之间的过孔；
    所述图案化像素电极区域通过所述过孔与所述薄膜晶体管的漏极连接；
    其中，所述过孔位于所述存储电容的上方，与所述存储电容重叠。
  12. 如权利要求8所述的阵列基板，其中所述第一像素电极区域还包括：向所述第一数据线延伸的第二条状电极；所述第二条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第一数据线上方，且与所述第一数据线重叠。
  13. 如权利要求12所述的阵列基板，其中所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
  14. 如权利要求8所述的阵列基板，其中所述阵列基板包括：
    第一金属层，其包括：所述第一扫描线、所述第二扫描线、所述薄膜晶体管的栅极、以及所述存储电容的第一电容电极；
    第二金属层，位于所述第一金属层上方，其包括：所述第一数据线、所述第二数据线、所述薄膜晶体管的源极和漏极、以及所述存储电容的第二电容电极。
  15. 一种液晶显示面板，其包括：
    阵列基板；
    彩膜基板；
    位于所述阵列基板和所述彩膜基板之间的液晶层；
    所述阵列基板，包括：
    第一数据线、第二数据线，所述第一数据线和所述第二数据线用于传输数据信号；
    第一扫描线、第二扫描线，所述第一扫描线和所述第二扫描线用于传输扫描信号；
    像素单元，由所述第一数据线、所述第二数据线、所述第一扫描线以及所述第二扫描线交错构成；
    所述像素单元包括：
    薄膜晶体管，所述薄膜晶体管的栅极与所述第一扫描线连接，所述薄膜晶体管的源极与所述第一数据信号连接，用于接收所述数据信号；所述薄膜晶管，用于根据所述数据信号以及所述扫描信号控制所述像素单元进行画面显示；
    图案化像素电极区域，与所述薄膜晶体管的漏极连接，包括：第一像素电极区域和第二像素电极区域；所述第一像素电极区域的透光率大于所述第二像素电极区域的透光率；所述第一像素电极区域包括：向所述第一扫描线延伸的第一条状电极；
    存储电容，位于所述第二像素电极区域的下方，与所述第二像素电极区域重叠，用于维持所述像素单元的画面显示；以及
    其中，所述第一条状电极具有延伸起始端和延伸结束端，所述延伸结束端延伸至所述第一扫描线上方，且与所述第一扫描线重叠。
  16. 如权利要求15所述的液晶显示面板，其中所述第一像素电极区域为分支像素电极区域，所述第二像素电极区域为主干像素电极区域，所述主干像素电极区域包括：多条主干电极。
  17. 如权利要求16所述的液晶显示面板，其中所述主干像素电极区域包括：第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极相交形成一个相交区域；
    所述存储电容位于所述相交区域的正下方，与所述相交区域重叠。
  18. 如权利要求15所述的液晶显示面板，其中所述像素单元还包括：位于图案化像素电极区域与所述漏极之间的过孔；
    所述图案化像素电极区域通过所述过孔与所述薄膜晶体管的漏极连接；
    其中，所述过孔位于所述存储电容的上方，与所述存储电容重叠。
  19. 如权利要求15所述的液晶显示面板，其中所述第一像素电极区域还包括：向所述第一数据线延伸的第二条状电极；所述第二条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第一数据线上方，且与所述第一数据线重叠。
  20. 如权利要求18所述的液晶显示面板，其中所述第一像素电极区域还包括：向所述第二数据线延伸的第三条状电极；所述第三条状电极具有延伸起始端和延伸结束端，该延伸结束端延伸至所述第二数据线上方，且与所述第二数据线重叠。
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CN107065351B (zh) * 2017-04-11 2019-01-15 惠科股份有限公司 一种显示面板和显示装置
CN209343100U (zh) * 2018-11-06 2019-09-03 惠科股份有限公司 一种显示面板和显示装置
CN109658895B (zh) * 2019-02-19 2020-03-24 深圳市华星光电半导体显示技术有限公司 液晶显示面板及其驱动方法
CN109917597B (zh) * 2019-04-09 2021-01-08 惠科股份有限公司 像素结构及显示面板
CN110376813A (zh) * 2019-07-09 2019-10-25 深圳市华星光电半导体显示技术有限公司 一种像素结构及显示面板
CN111258144A (zh) * 2020-03-31 2020-06-09 深圳市华星光电半导体显示技术有限公司 显示面板、显示装置

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