WO2012097564A1 - 一种自对准薄膜晶体管的制作方法 - Google Patents

一种自对准薄膜晶体管的制作方法 Download PDF

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WO2012097564A1
WO2012097564A1 PCT/CN2011/075653 CN2011075653W WO2012097564A1 WO 2012097564 A1 WO2012097564 A1 WO 2012097564A1 CN 2011075653 W CN2011075653 W CN 2011075653W WO 2012097564 A1 WO2012097564 A1 WO 2012097564A1
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layer
metal oxide
oxide semiconductor
photoresist
substrate
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PCT/CN2011/075653
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English (en)
French (fr)
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张盛东
贺鑫
王漪
韩德栋
韩汝琦
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北京大学深圳研究生院
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Priority to US13/376,836 priority Critical patent/US8956926B2/en
Publication of WO2012097564A1 publication Critical patent/WO2012097564A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to a method of fabricating a thin film transistor, and more particularly to a method of fabricating a self-aligned metal oxide semiconductor thin film transistor.
  • Thin-film transistors are used in the switching control elements of various displays or integrated components of peripheral driving circuits.
  • Currently widely used thin film transistors mainly include amorphous silicon thin film transistors and polysilicon thin film transistors, but low mobility due to amorphous silicon thin film transistors.
  • the shortcomings such as easy degradation of performance, have been greatly limited in the application of OLED pixel drive and LCD and OLED peripheral drive circuit integration.
  • the process temperature of the polysilicon thin film transistor is high, the fabrication cost is high, and the uniformity of the transistor performance is poor, which is not suitable for large-size flat panel display applications. Therefore, in order to develop flat panel display technology, it is urgent to develop more advanced thin film transistor technology.
  • the novel thin film transistor technologies currently under research and development mainly include metal oxide semiconductor thin film transistors represented by zinc oxide, microcrystalline silicon thin film transistors and organic semiconductor thin film transistors.
  • zinc oxide-based and indium oxide-based thin film transistors have low process temperatures, low process cost, high carrier mobility, and uniform and stable device performance, that is, a combination of amorphous silicon and polycrystalline silicon thin film transistors.
  • the advantage is a very promising large size microelectronic device.
  • a major problem with the fabrication of zinc oxide thin film transistors is that the transistor structures formed are non-self-aligned, which results in the presence of large parasitic elements and uncontrolled dispersion of characteristics.
  • the parasitic capacitance is very harmful to the performance of the pixel driving unit and the peripheral circuit driving circuit. In order to eliminate the influence of parasitic capacitance, existing methods often lead to an increase in the structure of the transistor and the complexity of the fabrication process steps.
  • Another major problem with zinc oxide thin film transistors is that the resulting semiconductor channel layer tends to have a very high carrier concentration, making the threshold voltage of the transistor low or even negative (for n-type transistors), ie at the gate In the zero-bias state, the transistor cannot be sufficiently turned off; if the channel layer is made into a low-concentration high-resistance layer, the parasitic resistance of the source and drain portions will increase accordingly, so an additional low-resistance metal is required.
  • the layer process leads to an increase in the complexity of the preparation process.
  • the main technical problem to be solved by the present invention is to provide a method for fabricating a self-aligned metal oxide thin film transistor having a high carrier concentration active channel in the source and drain regions of the active layer of the transistor.
  • the region has a low carrier concentration in the zero gate bias state while ensuring that the fabricated transistor has a self-aligned structure.
  • a method of fabricating a self-aligned thin film transistor comprising:
  • a gate electrode generating step generating a metal gate electrode on the substrate
  • a gate dielectric layer generating step generating a gate dielectric layer overlying the gate electrode on the substrate;
  • Active region generation and processing steps forming a metal oxide semiconductor layer having a high carrier concentration on the gate dielectric layer, processing it to form an active region including a source region, a drain region, and a channel region, and then Coating a photoresist layer on the metal oxide semiconductor layer, exposing and developing a photoresist pattern from the back surface of the substrate by using the gate electrode as a mask, and correspondingly forming the photoresist pattern Processing to expose a channel region on the metal oxide semiconductor layer, and oxidizing the channel region by a plasma having an oxidizing function in a temperature range lower than a highest temperature that the substrate can withstand ;
  • Electrode extraction step electrode leads for generating a source region, a drain region, and a gate electrode.
  • the method before the processing the metal oxide semiconductor layer to form an active region in the active region generating and processing step, the method further includes: forming the active region of the metal oxide semiconductor layer in an oxygen-free environment Heat treatment is carried out.
  • the channel region is oxidized by a plasma having an oxidizing function at a temperature of 25-180 degrees.
  • the method before applying the photoresist layer on the metal oxide semiconductor layer forming the active region, the method further includes: forming a dielectric protective layer on the metal oxide semiconductor layer, and then The photoresist is coated on the dielectric protective layer and treated to expose a channel region on the metal oxide semiconductor layer.
  • the photoresist layer is a negative photoresist layer
  • the process of processing the photoresist layer is as follows: from the back side of the substrate, the gate electrode is The mask is exposed and developed to form a photoresist pattern to expose a channel region on the metal oxide semiconductor layer.
  • the photoresist layer is a negative photoresist layer
  • the process of processing the photoresist layer is as follows: from the back side of the substrate, the gate electrode is The mask is exposed and developed to form a photoresist pattern, and then the dielectric protective layer of the channel region is removed by using the photoresist pattern as a mask to expose the channel region on the metal oxide semiconductor layer.
  • the photoresist layer is a positive photoresist layer
  • the process of processing the photoresist layer is as follows: from the back side of the substrate, the gate electrode is The mask is exposed and developed to form a photoresist pattern, and then a dielectric protective layer is formed on the upper surface thereof and treated to expose the channel region on the metal oxide semiconductor layer.
  • the photoresist layer is a positive photoresist layer
  • the process of processing the photoresist layer is as follows: from the back side of the substrate, the gate electrode is The mask is exposed and developed to form a photoresist pattern, and then a metal thin film layer is formed on the upper surface thereof and treated to expose the channel region on the metal oxide semiconductor layer.
  • the present invention has a high carrier concentration in a source region and a drain region of a thin film transistor by growing a metal oxide semiconductor layer having a high carrier concentration, and is coated on a metal oxide semiconductor layer defining an active region.
  • the adhesive layer is then exposed and developed from the back surface of the substrate with the gate electrode as a mask to form a photoresist pattern, and the photoresist pattern is processed correspondingly to expose the channel region on the metal oxide semiconductor layer.
  • Self-aligned with the gate electrode, and then the exposed channel region is oxidized by a plasma having an oxidizing function at a temperature lower than that of the substrate, so that the source region and the drain region maintain a high current carrying current.
  • the sub-concentration also makes the channel region have a low carrier concentration in the zero gate bias state; in addition, the threshold voltage of the transistor is controlled by plasma processing conditions having an oxidation function at a subsequent low temperature, and thus the transistor characteristics
  • the controllability is greatly improved.
  • the conventional preparation method is to achieve threshold voltage control by adjusting the partial pressure ratio of oxygen and argon in the sputtering atmosphere. Since the threshold voltage is very sensitive to the partial pressure ratio, the controllability is poor.
  • the active region is processed, it is exposed from the back side of the substrate, and the gate electrode functions as a natural mask. In this way, on the one hand, the cost of separately manufacturing the mask is omitted, and the process steps are simplified; on the other hand, since the gate electrode is used as a mask, the channel region and the gate electrode can be precisely aligned and reduced. The generation of parasitic components improves the uniformity of the device performance and the operating speed.
  • the oxygen plasma has high activity and has the ability to oxidize the channel region even at low temperatures, so the processing environment does not need to be heated to a certain high temperature, so that the manufacturing process temperature of the device can be greatly reduced, and also It is possible to apply a low temperature substrate such as a plastic substrate to the fabrication of a transistor.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor of the present invention
  • Figure 3 is a process step of forming a gate dielectric layer
  • Figure 5 is a process step of treating a metal oxide to form an active layer
  • 6 is a process step of coating a photoresist, patterning the photoresist, and then oxidizing the channel region;
  • Figure 7 is a process step of depositing and opening a contact hole in a passivation layer
  • Figure 8 is a process step of generating source and drain electrode leads
  • Figure 9 is a process step of forming a gate electrode
  • Figure 10 is a process step of forming a gate dielectric layer
  • Figure 11 is a process step of forming a metal oxide semiconductor layer and subjecting it to heat treatment
  • FIG. 13 is a process step diagram of front side coating of a negative photoresist, back exposure, and development to form a photoresist pattern
  • Figure 14 is a process step of removing the dielectric protective layer on the channel region and treating the channel region by oxygen plasma;
  • Figure 15 is a process step of depositing and opening a contact hole in a passivation layer
  • Figure 16 is a process step of generating a source-drain electrode lead
  • Figure 17 is a process step of forming a gate electrode
  • Figure 18 is a process step of forming a gate dielectric layer
  • Figure 19 is a metal oxide semiconductor layer and a process step of heat-treating it
  • Figure 20 is a process step of treating a metal oxide to form an active layer
  • 21 is a process step diagram of front-facing positive photoresist, back exposure, and development to form a photoresist pattern
  • Figure 22 is a process step of forming a dielectric protective layer
  • Figure 23 is a process step of oxidation treatment of a channel region by oxygen plasma
  • Figure 24 is a process step of depositing and opening a contact hole in a passivation layer
  • Figure 25 is a process step of generating source and drain electrode leads
  • 26-34 sequentially show the main manufacturing process steps of the thin film transistor in the fourth embodiment of the present invention, wherein:
  • Figure 26 is a process step of forming a gate electrode
  • Figure 27 is a process step of forming a gate dielectric layer
  • Figure 29 is a process step of treating a metal oxide to form an active layer
  • FIG. 30 is a process step diagram of front side positive resist, back exposure, and development to form a photoresist pattern
  • Figure 31 is a process step of forming a thin metal layer
  • Figure 32 is a process step of oxidation treatment of a channel region by oxygen plasma
  • Figure 33 is a process step of depositing and opening a contact hole in a passivation layer
  • Figure 34 is a process step for generating source and drain electrode leads.
  • the active layer of the thin film transistor is formed by using a metal oxide semiconductor layer having a high carrier concentration.
  • the source and drain regions are protected, and the gate electrode is self-aligned.
  • the channel region is exposed to a plasma atmosphere having an oxidizing function in a temperature range at which the substrate can withstand the highest temperature.
  • the plasma having an oxidizing function may be an oxygen plasma or the like, so that the oxygen vacancy concentration in the channel region is significantly reduced. Become a high resistance layer with low carrier concentration.
  • FIG. 1 is a cross-sectional structural view of a thin film transistor in an embodiment.
  • the thin film transistor comprises a gate electrode 2, a gate dielectric layer 3, a metal oxide semiconductor layer 4, and the metal oxide semiconductor layer 4 is composed of a channel region 5, a source region 6 and a drain region 7, and a gate electrode.
  • 2 is located above the substrate 1
  • the gate dielectric layer 3 is over the substrate 1 and the gate electrode 2 and covers the gate electrode 2
  • the metal oxide semiconductor layer 4 is over the gate dielectric 3
  • the channel region 5 is a metal oxide.
  • the intermediate portion of the semiconductor layer 4 is located above the gate dielectric 3 covering the gate electrode 2 and aligned with the gate electrode 2.
  • the source region 6 and the drain region 7 are both end portions of the metal oxide semiconductor layer 4, which are also respectively located in the gate dielectric. Above 3, and connected to the channel region 5, respectively.
  • the gate electrode 2 is made of a metal material, such as chromium, molybdenum, titanium or aluminum.
  • the method for generating the film can be, for example, a magnetron sputtering method or a thermal evaporation method; the thickness of the gate electrode 2 is generally 100 to 300 nm. And it is an opaque layer.
  • the gate dielectric 3 is an insulating medium such as silicon nitride or silicon oxide, and the formation method thereof may be, for example, a method of plasma enhanced chemical vapor deposition PECVD or magnetron sputtering; in another embodiment, the gate dielectric 3 may also be oxidized.
  • a metal oxide such as aluminum, cerium oxide or cerium oxide can be produced by a magnetron sputtering method.
  • the thickness of the gate dielectric 3 is generally from 100 to 400 nm.
  • the metal oxide semiconductor layer 4 is an amorphous or polycrystalline metal oxide semiconductor material, such as a zinc oxide-based or indium oxide-based thin film material, and the method for generating the same may be, for example, a magnetron sputtering method having a thickness of 50 to 200 nm;
  • the channel region 5 is an intermediate portion of the active layer 4, which has a low carrier concentration in an unbiased state, i.e., a zero gate bias state, exhibiting a high resistance state.
  • the source region 6 and the drain region 7 are both end portions of the active layer 4, and have a high carrier concentration and are in a low resistance state.
  • the material of the gate dielectric layer is a transparent material
  • the substrate is a high temperature resistant transparent substrate or a low temperature transparent substrate.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • steps of the method for fabricating the thin film transistor of this embodiment are specifically shown in FIG. 2 to FIG. 8 and include the following steps:
  • a metal film of 100 to 300 nm thick is formed on one side (for example, the front surface) of the substrate 1.
  • the method for forming the metal film may be a magnetron sputtering method, and the material may be chromium. Molybdenum, titanium or aluminum, etc., and then correspondingly processed to form the gate electrode 2, which can be formed by photolithography and etching;
  • the substrate 1 in this embodiment can be a high temperature resistant substrate
  • a glass substrate may also be a non-high temperature resistant substrate such as a transparent plastic substrate.
  • a 100-400 nm thick insulating film is formed on the front surface of the substrate 1, and the insulating film may be an insulating medium such as silicon nitride or silicon oxide, and plasma enhanced chemical vapor deposition may be used ( The film is formed by a PECVD method and overlaid on the gate electrode 2 as the gate dielectric layer 3.
  • a metal oxide semiconductor layer 4 is formed on the gate dielectric layer 3, and may have a thickness of 50 to 200 nm.
  • the metal oxide semiconductor layer 4 is an amorphous or polycrystalline metal oxide semiconductor material, and the semiconductor layer may be deposited by magnetron sputtering; for example, a zinc oxide-based or indium oxide-based thin film material;
  • the target used is composed of a mixed material of gallium oxide, indium oxide, and zinc oxide.
  • the molar ratio of the three materials is X:Y:Z, X>40%, Y>40, Z ⁇ 20%, and its preferred value is 3:3:1.
  • the target used is an indium oxide ceramic target having a purity equal to or better than 99.99%.
  • Sputtering pressure is 0.5 ⁇ 2.5 Between Pa, The gas is pure argon.
  • the entire metal oxide semiconductor layer 4 which is formed appears as a low-resistance material having a high carrier concentration due to generation of a large amount of oxygen vacancies. If a more low-resistance material is required, it can be heat-treated in an oxygen-free environment, such as by subjecting it to hydrogen, nitrogen or vacuum for heat treatment at a temperature below the maximum temperature that substrate 1 can withstand.
  • the metal oxide semiconductor layer 4 is subjected to corresponding processing to form an active region of the transistor, and the active region includes a source region 6, a drain region 7, and a channel region 5, and the processing manner may be light. Engraving and etching.
  • a photoresist layer is coated on the processed metal oxide semiconductor layer 4, the photoresist layer is a negative photoresist layer, and after the negative photoresist layer is coated, Exposing from the back side of the substrate 1 without the component, at this time using the gate electrode 2 at the bottom as a mask, and then performing development, because the photoresist layer is not blocked by the bottom gate electrode 2 mask. The portion is exposed without being dissolved in the developing solution, and the photoresist layer blocked by the gate electrode 2 is dissolved in the developing solution without being exposed to form a photoresist pattern 51, and the channel region of the intermediate portion of the metal oxide semiconductor layer 4 is formed.
  • the gate electrode 5 is exposed and self-aligned with the gate electrode, and then oxidized by oxygen plasma for 5 to 60 minutes at a low temperature, and the channel region 5 is exposed to oxygen plasma oxidation, and the concentration of oxygen vacancies is reduced to become low. Carrier concentration.
  • it since it is treated by oxygen plasma, it can be selected to be carried out at a low temperature, such as 25 to 180 degrees.
  • the upper limit of the temperature of the oxidation treatment is the highest temperature that the photoresist and the substrate 1 can withstand.
  • a 100-300 nm thick silicon nitride layer 8 is deposited by plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering, and then photolithographically and etched to form an electrode.
  • PECVD plasma enhanced chemical vapor deposition
  • Magnetron sputtering magnetron sputtering
  • a 100-300 nm thick metal aluminum film is deposited by magnetron sputtering, and then photolithography and etching are performed to form metal extraction electrodes and interconnection lines 11 of the electrodes of the thin film transistor. 12.
  • the channel region 5 is oxidized by oxygen plasma at a low temperature because the radicals in the plasma are much more active than the corresponding gases, such as oxygen radicals in the oxygen plasma.
  • the activity of the oxygen molecule is much higher than that of the oxygen molecule. Therefore, even when the temperature is low, the channel region 5 can be sufficiently oxidized and the oxygen vacancy concentration is reduced, so that the oxygen vacancy concentration is reduced.
  • the substrate 1 can be used not only of a substrate material resistant to high temperatures but also a substrate material of a low temperature.
  • the photoresist layer formed by coating in step 15) may be a negative photoresist layer, and after the negative photoresist layer is coated, there is no component from the back side of the substrate 1. Facing the exposure, at this time, the gate electrode 2 at the bottom is used as a mask, and then development is performed.
  • the gate electrode Since the portion of the photoresist layer which is not blocked by the mask of the bottom gate electrode 2 is exposed and is not dissolved in the developer, the gate electrode is The photoresist layer blocked by 2 is dissolved in the developing solution without being exposed, a photoresist pattern 51 is formed, the channel region 5 of the intermediate portion of the metal oxide semiconductor layer 4 is exposed, and then oxidized, thereby obtaining
  • the structure of the transistor is a self-aligned structure, and its manufacturing process flow is simpler than the existing non-self-aligned workflow.
  • the method provided in this embodiment can also produce a non-self-aligned transistor.
  • the photoresist layer in step 15) is a positive photoresist layer, it is directly photolithographically and etched to make the channel. The area is exposed and then oxidized.
  • the transistors produced at this time do not have a self-aligned structure.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the present invention oxidizes the channel region 5 by oxygen plasma at a low temperature, it is not necessary to form a dielectric protective layer, which simplifies the fabrication process of the transistor.
  • oxygen plasma has a certain influence on the protective photoresist layer.
  • the advantage of directly using the photoresist layer as a protective layer is that the process is simple, but some photoresist may be destroyed by oxygen plasma during the process. All areas of the source and drain regions cannot be strictly protected from oxidation; therefore, in order to further achieve more precise protection of the source and drain regions, a dielectric protective layer can be grown to protect the source and drain regions, and the resulting medium
  • the protective layer can also enter a high temperature environment to facilitate the subsequent process production. The specific production steps are as follows:
  • a metal film of 100 to 300 nm thick is formed on the front surface of the substrate 1, and the metal film may be chromium, molybdenum, titanium or aluminum, etc., and the generation method may be magnetron sputtering, and then
  • the gate electrode 2 is formed by photolithography and etching.
  • the substrate 1 in this embodiment may be a high temperature resistant substrate or a low temperature substrate.
  • a 100-400 nm thick insulating film is formed on the front surface of the substrate 1 by a plasma enhanced chemical vapor deposition (PECVD) method, and the film may be an insulating medium such as silicon nitride or silicon oxide. And overlying the gate electrode 2 as the gate dielectric layer 3.
  • PECVD plasma enhanced chemical vapor deposition
  • a metal oxide semiconductor layer 4 is formed on the gate dielectric layer 3 by RF magnetron sputtering, and the thickness thereof may be 50 to 200 nm; wherein the metal oxide semiconductor layer 4 is An amorphous or polycrystalline metal oxide semiconductor material, such as a zinc oxide-based or indium oxide-based thin film material; when indium gallium zinc oxide (IGZO), the target used is a mixed material of gallium oxide, indium oxide, and zinc oxide. Composition. The molar ratio of the three materials is X:Y:Z, X>40%, Y>40, Z ⁇ 20%, and its preferred value is 3:3:1.
  • the target used is an indium oxide ceramic target having a purity equal to or better than 99.99%.
  • Sputtering pressure is 0.5 ⁇ 2.5 Between Pa, The gas is pure argon.
  • the entire metal oxide semiconductor layer 4 which is formed appears as a low-resistance material having a high carrier concentration due to generation of a large amount of oxygen vacancies. If a more low-resistance material is required, it can be heat-treated in an oxygen-free environment, such as by subjecting it to hydrogen, nitrogen or vacuum for heat treatment at a temperature below the maximum temperature that substrate 1 can withstand.
  • a dielectric protective film is formed on the metal oxide semiconductor layer 4 treated in step 23.
  • the dielectric protective film may be silicon oxide or silicon nitride, and the method of generating plasma-enhanced chemistry may be employed.
  • a method of vapor deposition (PECVD) or magnetron sputtering having a thickness of 20 to 80 nm, photolithography and etching of the dielectric protective layer and the metal oxide semiconductor layer 4 to form an active region protective layer 41 of the transistor and
  • the active region includes a source region 6, a drain region 7, and a channel region 5.
  • a negative photoresist layer is coated on the above-described photolithographically and etched active region protective layer 41, as indicated by the arrow on the back side of the substrate, that is, in FIG. Exposing it in the direction, at this time, using the gate electrode 2 at the bottom as a mask, and then performing development, since the portion of the photoresist layer which is not blocked by the mask of the bottom gate electrode 2 is exposed and is not dissolved in the developer, the gate electrode is The photoresist layer blocked by 2 is dissolved in the developing solution without being exposed to form a photoresist pattern 51, and the dielectric protective film is etched according to the formed photoresist pattern 51 to make the intermediate portion of the metal oxide semiconductor layer 4 The channel region 5 is revealed and the remainder of the active region is still protected by the dielectric protective film.
  • an oxygen plasma can be selected for oxidation treatment for 5 to 60 minutes, and the oxygen is oxidized by oxygen plasma, and the oxygen is removed from the channel region 5 The concentration of the vacancies is reduced to a low carrier concentration.
  • it since it is treated with an oxygen plasma, it can be treated at a low temperature, such as a temperature of 25 to 180 degrees. It is worth noting that, before the oxygen plasma treatment, if the photoresist on the dielectric layer of the source and drain regions is retained, the maximum temperature of the oxidation treatment must be lower than the maximum temperature that the substrate 1 and the photoresist can withstand. If the photoresist has been removed, the maximum temperature of the oxidation treatment must be lower than the highest temperature that the substrate 1 can withstand.
  • a 100-300 nm thick silicon nitride layer 8 is deposited by plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering, and then photolithographically and etched to form an electrode.
  • PECVD plasma enhanced chemical vapor deposition
  • Magnetron sputtering magnetron sputtering
  • a 100-300 nm thick metal aluminum film is deposited by magnetron sputtering, and then photolithography and etching are performed to form metal extraction electrodes and interconnection lines 11 of the electrodes of the thin film transistor. 12.
  • the photoresist in the step 25) is a positive photoresist, and when it is exposed and developed from the front surface of the substrate 1, the resulting transistor does not have a self-aligned structure.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • a positive photoresist layer may also be applied, and then exposed, developed, etc., and the specific steps may be as follows:
  • a metal film of 100 to 300 nm thick is formed on the front surface of the substrate 1.
  • the method for forming the metal film may be magnetron sputtering, and the material may be chromium, molybdenum, titanium or Aluminum or the like, and then correspondingly processed to form the gate electrode 2, which can be formed by photolithography and etching;
  • the substrate 1 in this embodiment can be a high temperature resistant substrate such as a glass substrate. It can also be a non-high temperature resistant substrate such as a plastic substrate.
  • a 100-400 nm thick insulating film is formed on the front surface of the substrate 1, and the insulating film may be an insulating medium such as silicon nitride or silicon oxide, and plasma enhanced chemical vapor deposition may be used ( The film is formed by a PECVD method and overlaid on the gate electrode 2 as the gate dielectric layer 3.
  • a metal oxide semiconductor layer 4 having a thickness of 50 to 200 nm is formed on the gate dielectric layer 3.
  • the metal oxide semiconductor layer 4 is an amorphous or polycrystalline metal oxide semiconductor material, and the semiconductor layer can be deposited by radio frequency magnetron sputtering; such as a zinc oxide-based or indium oxide-based thin film material;
  • the target used is composed of a mixed material of gallium oxide, indium oxide, and zinc oxide.
  • the molar ratio of the three materials is X:Y:Z, X>40%, Y>40, Z ⁇ 20%, and its preferred value is 3:3:1.
  • the target used is an indium oxide ceramic target having a purity equal to or better than 99.99%.
  • Sputtering pressure is 0.5 ⁇ 2.5 Between Pa, The gas is pure argon.
  • the entire metal oxide semiconductor layer 4 which is formed appears as a low-resistance material having a high carrier concentration due to generation of a large amount of oxygen vacancies. If a more low-resistance material is required, it can be heat-treated in an oxygen-free environment, such as by subjecting it to hydrogen, nitrogen or vacuum for heat treatment at a temperature below the maximum temperature that substrate 1 can withstand.
  • the metal oxide semiconductor layer 4 is photolithographically and etched to form an active region of the transistor, and the active region includes a source region 6, a drain region 7, and a channel region 5.
  • a positive photoresist layer is applied onto the metal oxide semiconductor layer 4 after the above treatment, and then exposed from the back surface of the substrate 1 (in the direction indicated by the arrow in the figure).
  • the gate electrode 2 serves as a mask and is then developed.
  • the photoresist blocked by the gate electrode 2 is not dissolved in the developer due to exposure, and the photoresist not blocked by the gate electrode 2 is dissolved in the developer due to exposure. Forming a photoresist pattern as shown.
  • the dielectric protective layer 41 may be silicon oxide or silicon nitride, and has a thickness of 20 to 80. Nano, can be generated by magnetron sputtering.
  • the photoresist layer 52 and the dielectric protective layer 41 on the surface of the photoresist layer 52 are removed by a lift-off technique, so that the channel region 5 of the intermediate portion of the metal oxide semiconductor layer 4 is exposed, and the rest remains.
  • Protected by a dielectric protective layer to obtain a dielectric protective layer pattern.
  • it is oxidized by a plasma having an oxidizing function at a low temperature.
  • an oxygen plasma can be selected for oxidation treatment for 5 to 60 minutes, and the oxygen is oxidized by oxygen plasma, and the oxygen is removed from the channel region 5
  • the concentration of the vacancies is reduced to a low carrier concentration.
  • since it is treated by oxygen plasma it can be selected to be carried out at a low temperature, such as 25 to 180 degrees.
  • the upper limit of the temperature of the oxidation treatment is the highest temperature that the substrate 1 can withstand.
  • a 100-300 nm thick silicon nitride layer 8 is deposited by plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering, and then photolithographically and etched to form an electrode.
  • PECVD plasma enhanced chemical vapor deposition
  • Magnetron sputtering magnetron sputtering
  • a metal aluminum film of 100 to 300 nm thick is deposited by magnetron sputtering, and then photolithography and etching are performed to form metal extraction electrodes and interconnection lines 11 of the electrodes of the thin film transistor. 12.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • a metal film may also be grown to form a better ohmic contact between the source and drain, and then correspondingly processed.
  • the specific steps may be as follows :
  • a metal film of 100 to 300 nm thick is formed on the front surface of the substrate 1.
  • the method for forming the metal film may be magnetron sputtering, and the material may be chromium, molybdenum, titanium or Aluminum or the like, and then correspondingly processed to form the gate electrode 2, which can be formed by photolithography and etching;
  • the substrate 1 in this embodiment can be a high temperature resistant substrate such as a glass substrate. It can also be a non-high temperature resistant substrate such as a plastic substrate.
  • a 100-400 nm thick insulating film is formed on the front surface of the substrate 1, and the insulating film may be an insulating medium such as silicon nitride or silicon oxide, and plasma enhanced chemical vapor deposition may be used ( The film is formed by a PECVD method and overlaid on the gate electrode 2 as the gate dielectric layer 3.
  • a metal oxide semiconductor layer 4 having a thickness of 50 to 200 nm is formed on the gate dielectric layer 3.
  • the metal oxide semiconductor layer 4 is an amorphous or polycrystalline metal oxide semiconductor material, and the semiconductor layer can be deposited by radio frequency magnetron sputtering; such as a zinc oxide-based or indium oxide-based thin film material;
  • the target used is composed of a mixed material of gallium oxide, indium oxide, and zinc oxide.
  • the molar ratio of the three materials is X:Y:Z, X>40%, Y>40, Z ⁇ 20%, and its preferred value is 3:3:1.
  • the target used is an indium oxide ceramic target having a purity equal to or better than 99.99%.
  • Sputtering pressure is 0.5 ⁇ 2.5 Between Pa, the gas is pure argon.
  • the entire metal oxide semiconductor layer 4 which is formed appears as a low-resistance material having a high carrier concentration due to generation of a large amount of oxygen vacancies. If a more low-resistance material is required, it can be heat-treated in an oxygen-free environment, such as by subjecting it to hydrogen, nitrogen or vacuum for heat treatment at a temperature below the maximum temperature that substrate 1 can withstand.
  • the metal oxide semiconductor layer 4 is photolithographically and etched to form an active region of the transistor, and the active region includes a source region 6, a drain region 7, and a channel region 5.
  • a positive photoresist layer is applied onto the processed metal oxide semiconductor layer 4, and then exposed from the back surface of the substrate 1 (in the direction indicated by the arrow in the figure).
  • the gate electrode 2 serves as a mask and is then developed.
  • the photoresist blocked by the gate electrode 2 is not dissolved in the developer due to exposure, and the photoresist not blocked by the gate electrode 2 is dissolved in the developer due to exposure.
  • a photoresist pattern 52 as shown is formed.
  • a metal thin film 42 is formed, and the metal thin film 42 may be chromium, molybdenum, titanium or aluminum, etc., and has a thickness of 20 to 100. Nano, can be generated by magnetron sputtering.
  • the photoresist film 52 and the metal thin film 42 on the surface of the photoresist layer 52 are removed by a lift-off technique to expose the channel region 5 of the intermediate portion of the metal oxide semiconductor layer 4, and the rest is still
  • the metal film 42 is protected, and the metal film 42 is photolithographically and etched to obtain a metal film pattern.
  • it is oxidized by a plasma having an oxidizing function at a low temperature.
  • an oxygen plasma can be selected for oxidation treatment for 5 to 60 minutes, and the oxygen is oxidized by oxygen plasma, and the oxygen is removed from the channel region 5
  • the concentration of the vacancies is reduced to a low carrier concentration.
  • since it is treated by oxygen plasma it can be selected to be carried out at a low temperature, such as 25 to 180 degrees.
  • the upper limit of the temperature of the oxidation treatment is the highest temperature that the substrate 1 can withstand.
  • a 100-300 nm thick silicon nitride layer 8 is deposited by plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering, and then photolithographically and etched to form an electrode.
  • PECVD plasma enhanced chemical vapor deposition
  • Magnetron sputtering magnetron sputtering
  • a metal aluminum film having a thickness of 100 to 300 nm is deposited by magnetron sputtering, and then photolithography and etching are performed to form metal extraction electrodes and interconnection lines 11 of the electrodes of the thin film transistor. 12.
  • the method for fabricating a metal oxide thin film transistor according to the present invention which uses an oxygen plasma treatment method for oxidizing a channel region. Since the oxygen radicals in the plasma are extremely active even at low temperatures, the process can be carried out at a low temperature, so that the substrate can also be selected from inexpensive low-temperature materials, thereby saving manufacturing costs.

Description

一种自对准薄膜晶体管的制作方法 技术领域
本发明涉及一种薄膜晶体管的制作方法，尤其涉及一种自对准的金属氧化物半导体薄膜晶体管的制作方法。
 背景技术
各种显示器中的开关控制元件或周边驱动电路的集成元件都采用薄膜晶体管，目前被广泛采用的薄膜晶体管主要有非晶硅薄膜晶体管和多晶硅薄膜晶体管，但由于非晶硅薄膜晶体管低的迁移率和性能易退化等缺点，在OLED像素驱动以及LCD和OLED周边驱动电路集成等方面的应用上受到了很大的限制。而多晶硅薄膜晶体管的工艺温度较高，制作成本高，而且晶体管性能的均匀性较差，不太适合大尺寸平板显示应用。因此为了平板显示技术的发展，迫切需要开发更为先进的薄膜晶体管技术。目前处于研究开发之中的新型薄膜晶体管技术主要有以氧化锌为代表的金属氧化物半导体薄膜晶体管，微晶硅薄膜晶体管和有机半导体薄膜晶体管等。
其中的氧化锌基和氧化铟基薄膜晶体管具有低的工艺温度，低的工艺成本，高的载流子迁移率以及均匀且稳定的器件性能，即汇集了非晶硅和多晶硅薄膜晶体管两者的优点，是一种非常有希望的大尺寸微电子器件。但氧化锌薄膜晶体管的制备方法的一个主要问题是形成的晶体管结构是非自对准的，这导致晶体管存在大的寄生元件和难以控制的特性离散。而寄生电容对像素驱动单元和周边电路驱动电路的性能的危害都是非常大的。为了消除寄生电容的影响，现有的做法往往导致晶体管的结构以及制作的工艺步骤的复杂性提高。氧化锌薄膜晶体管的另一个主要问题是生成的半导体沟道层往往具有很高的载流子浓度，使得晶体管的阈值电压很低甚至为负值（对n型晶体管而言），即在栅极为零偏压状态时，晶体管不能充分的关断；如果将沟道层制成低浓度的高阻层，则源漏部分的寄生电阻也会相应的增加，因此需要另加一层低阻的金属层工艺，导致了制备工艺的复杂度增加。
 技术问题
本发明要解决的主要技术问题是，提供一种自对准金属氧化物薄膜晶体管的制造方法，在满足晶体管的有源层的源、漏区具有高的载流子浓度有源层的沟道区在零栅偏压状态下为低载流子浓度的同时，又能保证制造出的晶体管具有自对准的结构。
技术解决方案
根据本发明的一方面，提供一种自对准薄膜晶体管的制作方法，包括：
栅电极生成步骤：在衬底上生成金属栅电极；
栅介质层生成步骤：在衬底上生成覆盖在所述栅电极之上的栅介质层；
有源区生成及处理步骤：在栅介质层上生成一层具有高载流子浓度的金属氧化物半导体层，对其进行处理形成包括源区、漏区以及沟道区的有源区，然后在所述金属氧化物半导体层上涂光刻胶层，从所述衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，对所述光刻胶图形做相应的处理，使所述金属氧化物半导体层上的沟道区露出，将所述沟道区在低于所述衬底所能承受的最高温度的温度范围内通过具有氧化功能的等离子体进行氧化处理；
电极引出步骤：生成源区、漏区和栅电极的电极引线。
在本发明的一种实施例中，所述有源区生成及处理步骤中对所述金属氧化物半导体层进行处理形成有源区之前，还包括对所述金属氧化物半导体层在无氧环境中进行热处理。
在本发明的一种实施例中，将所述沟道区在25-180度的温度下通过具有氧化功能的等离子体对其进行氧化处理。
在本发明的一种实施例中，在形成有源区的金属氧化物半导体层上涂光刻胶层之前还包括：在所述金属氧化物半导体层上生成一层介质保护层，然后在该介质保护层上涂所述光刻胶，并对其进行处理使所述金属氧化物半导体层上的沟道区露出。
在本发明的一种实施例中，所述光刻胶层为负性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，使所述金属氧化物半导体层上的沟道区露出。
在本发明的一种实施例中，所述光刻胶层为负性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，然后以该光刻胶图形为掩膜去除沟道区的介质保护层，使所述金属氧化物半导体层上的沟道区露出。
在本发明的一种实施例中，所述光刻胶层为正性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，然后在其上表面生成一层介质保护层，并对其进行处理使所述金属氧化物半导体层上的沟道区露出。
在本发明的一种实施例中，所述光刻胶层为正性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，然后在其上表面生成一层金属薄膜层，并对其进行处理使所述金属氧化物半导体层上的沟道区露出。
本发明通过生长具有高载流子浓度的金属氧化物半导体层，使薄膜晶体管的源区、漏区具有高载流子浓度，并通过在定义有有源区的金属氧化物半导体层上涂光刻胶层，然后从衬底的背面以栅电极为掩膜进行曝光并显影形成光刻胶图形，对光刻胶图形做相应的处理，使金属氧化物半导体层上的沟道区裸露出来并与栅电极形成自对准，然后将裸露出的沟道区在低于衬底所能承受的温度下，通过具有氧化功能的等离子体进行氧化处理，使源区、漏区保持高的载流子浓度的同时，也使沟道区在零栅偏压状态下具有低的载流子浓度；另外，晶体管的阈值电压由后续低温下具有氧化功能的等离子体处理条件所控制，因此晶体管特性的可控性大为提高。而常规的制备方法是通过调节溅射气氛中的氧气和氩气的分压比实现阈值电压控制的，由于阈值电压对分压比非常灵敏，因此可控性差。
另外，由于对有源区进行处理时，从衬底的背面曝光，栅电极起了天然掩膜版的作用。此种方式，一方面省去了另外制作掩膜版的成本，同时简化了工艺步骤；另一方面，由于栅电极作为掩膜版，使得沟道区与栅电极能够精确的对准，减小了寄生元件的产生，提高了器件性能的均匀性和工作速度。
进一步的，氧等离子体具有很高的活性，即使在低温下也具有对沟道区进行氧化的能力，因此处理环境不需加热到一定的高温，使器件的制作工艺温度可以大大降低，同时也使低温衬底（如塑料衬底）应用到晶体管的制作中成为可能。
 附图说明
图1为本发明薄膜晶体管的剖面结构示意图；
图2-8依次示出了本发明实施例一中的薄膜晶体管的主要制作工艺步骤，其中：
图2为栅电极形成的工艺步骤；
图3为栅介质层形成的工艺步骤；
图4为形成金属氧化物半导体层及将其进行热处理的工艺步骤；
图5对金属氧化物进行处理形成有源层的工艺步骤；
图6为涂布光刻胶，光刻胶图形化然后将沟道区进行氧化处理的工艺步骤；
图7为钝化层淀积和开接触孔的工艺步骤；
图8为生成源漏电极引线的工艺步骤；
图9-17依次示出了本发明实施例二中的薄膜晶体管的主要制作工艺步骤，其中：
图9为栅电极形成的工艺步骤；
图10为栅介质层形成的工艺步骤；
图11为形成金属氧化物半导体层及将其进行热处理的工艺步骤；
图12为介质保护层淀积及金属氧化物半导体层和介质保护层图形化的工艺步骤；
图13为正面涂布负性光刻胶，背面曝光，显影形成光刻胶图形的工艺步骤图；
图14为去掉沟道区上的介质保护层并对沟道区通过氧等离子体进行处理的工艺步骤；
图15为钝化层淀积和开接触孔的工艺步骤；
图16为生成源漏电极引线的工艺步骤；
图17-25依次示出了本发明实施例三中的薄膜晶体管的主要制作工艺步骤，其中：
图17为栅电极形成的工艺步骤；
图18为栅介质层形成的工艺步骤；
图19为金属氧化物半导体层及将其进行热处理的工艺步骤；
图20为对金属氧化物进行处理形成有源层的工艺步骤；
图21为正面涂布正性光刻胶，背面曝光，显影形成光刻胶图形的工艺步骤图；
图22为介质保护层的生成工艺步骤；
图23为沟道区通过氧等离子体进行氧化处理的工艺步骤；
图24为钝化层淀积和开接触孔的工艺步骤；
图25为生成源漏电极引线的工艺步骤；
图26-34依次示出了本发明实施例四中的薄膜晶体管的主要制作工艺步骤，其中：
图26为栅电极形成的工艺步骤；
图27为栅介质层形成的工艺步骤；
图28为形成金属氧化物半导体层及将其进行热处理的工艺步骤；
图29为对金属氧化物进行处理形成有源层的工艺步骤；
图30为正面涂布正性光刻胶，背面曝光，显影形成光刻胶图形的工艺步骤图；
图31为金属薄层的生成工艺步骤；
图32为沟道区通过氧等离子体进行氧化处理的工艺步骤；
图33为钝化层淀积和开接触孔的工艺步骤；
图34为生成源漏电极引线的工艺步骤。
 本发明的实施方式
在本发明实施例中，薄膜晶体管的有源层采用具有高载流子浓度金属氧化物半导体层形成，生成有源层后，将源漏区保护起来，而将与栅电极形成自对准的沟道区在衬底所能承受的最高温度的温度范围内裸露于具有氧化功能的等离子体气氛中，例如具有氧化功能的等离子体可为氧等离子或其他，使得沟道区氧空位浓度显著减少，成为低载流子浓度的高阻层。
下面通过具体实施方式结合附图对本发明作进一步详细说明。
请参考图1，图1所示为一种实施例中的薄膜晶体管的剖面结构示意图，
薄膜晶体管包括一栅电极2，一栅介质层3，一金属氧化物半导体层4，金属氧化物半导体层4由一沟道区5，一源区6和一漏区7三部分组成，栅电极2位于衬底1之上，栅介质层3位于衬底1和栅电极2之上且将栅电极2覆盖，金属氧化物半导体层4位于栅介质3之上，沟道区5为金属氧化物半导体层4的中间部分，位于覆盖栅电极2的栅介质3之上且与栅电极2对准，源区6和漏区7为金属氧化物半导体层4的两端部分，也分别位于栅介质3之上，且分别与沟道区5相连接。
本实施例中，栅电极2为金属材料，如铬、钼、钛或铝等，其生成方法例如可采用磁控溅射方法或热蒸发方法；栅电极2的厚度一般为100～300纳米，且为不透光层。栅介质3为氮化硅、氧化硅等绝缘介质，其生成方法例如可采用等离子增强化学汽相淀积PECVD或磁控溅射的方法；在另一实施例中，栅介质3也可为氧化铝、氧化钽或氧化铪等金属氧化物，其生成方法例如可采用磁控溅射方法。栅介质3的厚度一般为100～400纳米。金属氧化物半导体层4为非晶或多晶的金属氧化物半导体材料，如氧化锌基或氧化铟基的薄膜材料，其生成方法例如可采用磁控溅射方法，厚度为50～200纳米；沟道区5为有源层4的中间部分，其在未偏置状态下即零栅偏压状态下载流子浓度很低，呈现高电阻状态。源区6和漏区7为有源层4的两端部分，其载流子浓度很高，为低阻状态。
在一种实施例中，所述栅介质层的材料为透明材料，所述衬底为耐高温透明衬底或者低温透明衬底。
实施例一：
本实施例的薄膜晶体管的制作方法的步骤具体由图2至图8所示，包括以下步骤：
11）如图2所示，在衬底1的一面（例如正面）上生成一层100至300纳米厚的金属薄膜，生成该金属薄膜的方法可为磁控溅射法，其材料可为铬、钼、钛或铝等，然后将其进行相应的处理形成栅电极2，如可将其通过光刻和刻蚀形成栅电极2；本实施例中的衬底1可为耐高温的衬底，如玻璃衬底，也可为非耐高温的衬底，如透明的塑料衬底。为描述方便，我们将衬底的制作薄膜晶体管的一面称为正面。
12）如图3所示，在衬底1正面上生成一层100至400纳米厚绝缘薄膜，该绝缘薄膜可为氮化硅、氧化硅等绝缘介质，可采用等离子增强化学汽相淀积（PECVD）方法生成该薄膜，并使其覆盖在上述栅电极2之上作为栅介质层3。
13）如图4所示，在栅介质层3上生成一层金属氧化物半导体层4，其厚度可为50至200纳米。其中，金属氧化物半导体层4为非晶或多晶的金属氧化物半导体材料，可采用磁控溅射法淀积该半导体层；如氧化锌基或氧化铟基的薄膜材料；当为氧化铟镓锌（IGZO）时，使用的靶由氧化镓、氧化铟和氧化锌的混合材料构成。三种材料的摩尔比为X:Y:Z，X>40%, Y>40, Z<20%, 其优选值为3:3:1。当为氧化铟时，所用的靶材为纯度等于或优于99.99%的氧化铟陶瓷靶。溅射气压在0.5～2.5 Pa之间， 气体为纯氩气。此时，所生成的整个金属氧化物半导体层4由于产生大量的氧空位，而呈现为高载流子浓度的低阻材料。若需要更加低阻的材料，可将其在无氧环境中进行热处理，如可将其置于氢气、氮气或真空中进行热处理，处理温度须低于衬底1所能承受的最高温度。
14）如图5所示，对金属氧化物半导体层4进行相应的处理以形成晶体管的有源区，有源区包括源区6、漏区7和沟道区5，处理方式可选为光刻和刻蚀方式。
15）如图6所示，在上述处理后的金属氧化物半导体层4上涂布光刻胶层，该光刻胶层为负性光刻胶层，负性光刻胶层涂布完成之后，从衬底1的背面即没有元器件的一面对其进行曝光，此时以底部的栅电极2作为掩膜，然后进行显影，由于未被底部栅电极2掩膜挡住的光刻胶层部分被曝光而不溶解于显影液，被栅电极2挡住的光刻胶层由于未被曝光而溶解于显影液，形成光刻胶图形51，使金属氧化物半导体层4中间部分的沟道区5显露出来且与栅电极自对准，然后在低温下通过氧等离子体中进行氧化处理5～60分钟，由于沟道区5裸露在外被氧等离子氧化，其氧空位的浓度减低而转变成低载流子浓度。本实施例中由于采用氧等离子体对其处理，可选择在低温下进行，如25到180度。氧化处理的温度的上限为光刻胶和衬底1能承受的最高温度。
16）如图7所示，用等离子增强化学汽相淀积（PECVD）或磁控溅射方法淀积一层100～300纳米厚的氮化硅层8，然后光刻和刻蚀形成电极的接触孔9和10。
17）如图8所示，用磁控溅射方法淀积一层100～300纳米厚的金属铝膜，然后光刻和刻蚀制成薄膜晶体管各电极的金属引出电极和互连线11和12。
本实施例中将沟道区5在低温下通过氧等离子体对其进行氧化处理，因为等离子体中的自由基比与之相应的气体的活性高得多，如氧等离子体中的氧自由基的活性就比氧气分子的活性高出许多，因此在采用等离子体对沟道区5进行氧化处理时即使在低温下，沟道区5也能够被充分氧化，氧空位浓度减少，因此本实施例中的衬底1不仅可采用耐高温的衬底材料，还可采用低温的衬底材料。
常规的非自对准技术不可避免导致晶体管存在大的寄生电容和晶体管特性的不均匀，而寄生电容对像素驱动单元和周边电路驱动电路的性能的危害都是非常大的。为了消除寄生电容的影响，现有的做法往往导致晶体管的结构以及制作的工艺步骤的复杂性提高。在本实施例中，步骤15）中涂布生成的光刻胶层可为负性光刻胶层，负性光刻胶层涂布完成之后，从衬底1的背面即没有元器件的一面对其进行曝光，此时以底部的栅电极2作为掩膜，然后进行显影，由于未被底部栅电极2掩膜挡住的光刻胶层部分被曝光而不溶解于显影液，被栅电极2挡住的光刻胶层由于未被曝光而溶解于显影液，形成光刻胶图形51，使金属氧化物半导体层4中间部分的沟道区5显露出来，然后将其进行氧化处理，这样得到的晶体管的结构为自对准的结构，且其制造工艺流程比现有的非自对准的工作流程还要简单。
本实施例提供的方法也可制作出非自对准的晶体管，例如在步骤15）中的光刻胶层为正性光刻胶层时，直接对其进行光刻和刻蚀，使沟道区露出，然后对其进行氧化处理即可。但此时制得的晶体管就不具有自对准结构。
实施例二：
由于本发明将沟道区5在低温下通过氧等离子体对其进行氧化处理，因此无需再生成介质保护层，简化了晶体管的制作工艺。但是氧等离子对起到保护作用的光刻胶层有一定的影响，直接利用光刻胶层作为保护层的优点在于工艺简单，但在处理过程中部分光刻胶可能会被氧等离子体打掉，不能严格保护源区和漏区的所有区域不被氧化到；因此，为了进一步实现对源漏区更精确的保护，可生长一层介质保护层以保护源区和漏区，且生成的介质保护层还可进入高温环境，便于后续的工艺的制作，具体制作步骤如下：
21）如图9所示，在衬底1正面上生成一层100至300纳米厚的金属薄膜，该金属薄膜可为铬、钼、钛或铝等，生成方式可为磁控溅射，然后将其光刻和刻蚀形成栅电极2，本实施例中的衬底1可为耐高温衬底，也可为低温衬底。
22）如图10所示，在衬底1正面上采用等离子增强化学汽相淀积（PECVD）方法生成一层100至400纳米厚绝缘薄膜，该薄膜可为氮化硅、氧化硅等绝缘介质，并使其覆盖在上述栅电极2之上作为栅介质层3。
23）如图11所示，在栅介质层3上采用射频磁控溅射淀积生成一层金属氧化物半导体层4，其厚度可为50至200纳米；其中，金属氧化物半导体层4为非晶或多晶的金属氧化物半导体材料，如氧化锌基或氧化铟基的薄膜材料；当为氧化铟镓锌（IGZO）时，使用的靶由氧化镓、氧化铟和氧化锌的混合材料构成。三种材料的摩尔比为X:Y:Z，X>40%, Y>40, Z<20%, 其优选值为3:3:1。当为氧化铟时，所用的靶材为纯度等于或优于99.99%的氧化铟陶瓷靶。溅射气压在0.5～2.5 Pa之间， 气体为纯氩气。此时，所生成的整个金属氧化物半导体层4由于产生大量的氧空位，而呈现为高载流子浓度的低阻材料。若需要更加低阻的材料，可将其在无氧环境中进行热处理，如可将其置于氢气、氮气或真空中进行热处理，处理温度须低于衬底1能承受的最高温度。
24）如图12所示，在经步骤23处理后的金属氧化物半导体层4上生成一层介质保护膜，该介质保护膜可为氧化硅或氮化硅，生成的方法可采用等离子增强化学汽相淀积（PECVD）或磁控溅射的方法，其厚度为20至80纳米，光刻和刻蚀该介质保护层和金属氧化物半导体层4以形成晶体管的有源区保护层41和有源区，有源区包括源区6、漏区7和沟道区5。
25）如图13和14所示，在上述经光刻和刻蚀后的有源区保护层41上涂布负性光刻胶层，从衬底的背面即图14中的箭头所指的方向对其进行曝光，此时以底部的栅电极2作为掩膜，然后进行显影，由于未被底部栅电极2掩膜挡住的光刻胶层部分被曝光而不溶解于显影液，被栅电极2挡住的光刻胶层由于未被曝光而溶解于显影液，形成光刻胶图形51，根据形成的光刻胶图形51对介质保护膜进行刻蚀，使金属氧化物半导体层4中间部分的沟道区5显露出来有源区的其余部分仍然被介质保护膜保护。然后在低温下通过具有氧化功能的等离子体对其进行氧化处理，本实施例中可选取氧等离子体对其进行氧化处理5至60分钟，由于沟道区5裸露在外被氧等离子氧化，其氧空位的浓度减少而转变成低载流子浓度。本实施例中由于采用氧等离子体对其处理，因此可在选择在低温下处理，如25到180度的温度下对其进行处理。值得注意的是，氧等离子体处理前，源漏区介质层上的光刻胶如果保留，则氧化处理的最高温度须低于衬底1和光刻胶能承受的最高温度。如光刻胶已去除，则氧化处理的最高温度须低于衬底1能承受的最高温度。
26）如图15所示，用等离子增强化学汽相淀积（PECVD）或磁控溅射方法淀积一层100～300纳米厚的氮化硅层8，然后光刻和刻蚀形成电极的接触孔9和10。
27）如图16所示，用磁控溅射方法淀积一层100～300纳米厚的金属铝膜，然后光刻和刻蚀制成薄膜晶体管各电极的金属引出电极和互连线11和12。
在本实施例中，当步骤25）中的光刻胶为正性光刻胶，且当从衬底1的正面对其进行曝光、显影时，制得的晶体管就不具有自对准结构。
实施例三：
为了制得具有自对准的晶体管结构，在实施例二的步骤25）中，也可涂布正性光刻胶层，然后对其曝光、显影等处理，具体步骤可如下：
31）如图17所示，在衬底1正面上生成一层100至300纳米厚的金属薄膜，生成该金属薄膜的方法可为磁控溅射法，其材料可为铬、钼、钛或铝等，然后将其进行相应的处理形成栅电极2，如可将其通过光刻和刻蚀形成栅电极2；本实施例中的衬底1可为耐高温的衬底，如玻璃衬底，也可为非耐高温的衬底，如塑料衬底。
32）如图18所示，在衬底1正面上生成一层100至400纳米厚绝缘薄膜，该绝缘薄膜可为氮化硅、氧化硅等绝缘介质，可采用等离子增强化学汽相淀积（PECVD）方法生成该薄膜，并使其覆盖在上述栅电极2之上作为栅介质层3。
33）如图19所示，在栅介质层3上生成一层金属氧化物半导体层4，其厚度可为50至200纳米。其中，金属氧化物半导体层4为非晶或多晶的金属氧化物半导体材料，可采用射频磁控溅射法淀积该半导体层；如氧化锌基或氧化铟基的薄膜材料；当为氧化铟镓锌（IGZO）时，使用的靶由氧化镓、氧化铟和氧化锌的混合材料构成。三种材料的摩尔比为X:Y:Z，X>40%, Y>40, Z<20%, 其优选值为3:3:1。当为氧化铟时，所用的靶材为纯度等于或优于99.99%的氧化铟陶瓷靶。溅射气压在0.5～2.5 Pa之间， 气体为纯氩气。此时，所生成的整个金属氧化物半导体层4由于产生大量的氧空位，而呈现为高载流子浓度的低阻材料。若需要更加低阻的材料，可将其在无氧环境中进行热处理，如可将其置于氢气、氮气或真空中进行热处理，处理温度须低于衬底1能承受的最高温度。
34）如图20所示，对金属氧化物半导体层4进行光刻和刻蚀以形成晶体管的有源区，有源区包括源区6、漏区7和沟道区5。
35）如图21所示，在上述处理后的金属氧化物半导体层4上涂布正性光刻胶层，然后从衬底1的背面（图中箭头所示方向）进行曝光，此时以栅电极2作为掩膜，然后对其进行显影，被栅电极2遮挡的光刻胶由于未被曝光而不溶于显影液，未被栅电极2遮挡的光刻胶由于被曝光而溶于显影液，形成如图所示的光刻胶图形。
36）如图22所示，在光刻胶层52和金属氧化物半导体层4上，生成一层介质保护层41，介质保护层41可为氧化硅或氮化硅，其厚度为20至80纳米，可采用磁控溅射的方法生成。
37）如图23所示，采用剥离技术去除光刻胶层52以及光刻胶层52表面的介质保护层41，使金属氧化物半导体层4中间部分的沟道区5显露出来，其余部分仍然被介质保护层保护，得到介质保护层图案。然后在低温下通过具有氧化功能的等离子体对其进行氧化处理，本实施例中可选取氧等离子体对其进行氧化处理5至60分钟，由于沟道区5裸露在外被氧等离子氧化，其氧空位的浓度减少而转变成低载流子浓度。本实施例中由于采用氧等离子体对其处理，可选择在低温下进行，如25到180度。氧化处理的温度的上限为衬底1能承受的最高温度。
38）如图24所示，用等离子增强化学汽相淀积（PECVD）或磁控溅射方法淀积一层100～300纳米厚的氮化硅层8，然后光刻和刻蚀形成电极的接触孔9和10。
39）如图25所示，用磁控溅射方法淀积一层100～300纳米厚的金属铝膜，然后光刻和刻蚀制成薄膜晶体管各电极的金属引出电极和互连线11和12。
实施例四：
为了制得具有自对准的晶体管结构，在实施例三的步骤36）中，也可生长一层金属薄膜，使源漏形成更好的欧姆接触，然后对其进行相应处理，具体步骤可如下：
41）如图26所示，在衬底1正面上生成一层100至300纳米厚的金属薄膜，生成该金属薄膜的方法可为磁控溅射法，其材料可为铬、钼、钛或铝等，然后将其进行相应的处理形成栅电极2，如可将其通过光刻和刻蚀形成栅电极2；本实施例中的衬底1可为耐高温的衬底，如玻璃衬底，也可为非耐高温的衬底，如塑料衬底。
42）如图27所示，在衬底1正面上生成一层100至400纳米厚绝缘薄膜，该绝缘薄膜可为氮化硅、氧化硅等绝缘介质，可采用等离子增强化学汽相淀积（PECVD）方法生成该薄膜，并使其覆盖在上述栅电极2之上作为栅介质层3。
43）如图28所示，在栅介质层3上生成一层金属氧化物半导体层4，其厚度可为50至200纳米。其中，金属氧化物半导体层4为非晶或多晶的金属氧化物半导体材料，可采用射频磁控溅射法淀积该半导体层；如氧化锌基或氧化铟基的薄膜材料；当为氧化铟镓锌（IGZO）时，使用的靶由氧化镓、氧化铟和氧化锌的混合材料构成。三种材料的摩尔比为X:Y:Z，X>40%, Y>40, Z<20%, 其优选值为3:3:1。当为氧化铟时，所用的靶材为纯度等于或优于99.99%的氧化铟陶瓷靶。溅射气压在0.5～2.5 Pa之间，气体为纯氩气。此时，所生成的整个金属氧化物半导体层4由于产生大量的氧空位，而呈现为高载流子浓度的低阻材料。若需要更加低阻的材料，可将其在无氧环境中进行热处理，如可将其置于氢气、氮气或真空中进行热处理，处理温度须低于衬底1能承受的最高温度。
44）如图29所示，对金属氧化物半导体层4进行光刻和刻蚀以形成晶体管的有源区，有源区包括源区6、漏区7和沟道区5。
45）如图30所示，在上述处理后的金属氧化物半导体层4上涂布正性光刻胶层，然后从衬底1的背面（图中箭头所示方向）进行曝光，此时以栅电极2作为掩膜，然后对其进行显影，被栅电极2遮挡的光刻胶由于未被曝光而不溶于显影液，未被栅电极2遮挡的光刻胶由于被曝光而溶于显影液，形成如图所示的光刻胶图形52。
46）如图31所示，在光刻胶层52和金属氧化物半导体层4上，生成一层金属薄膜42，金属薄膜42可为铬、钼、钛或铝等，其厚度为20至100纳米，可采用磁控溅射的方法生成。
47）如图32所示，采用剥离技术去除光刻胶层52以及光刻胶层52表面的金属薄膜42，使金属氧化物半导体层4中间部分的沟道区5显露出来，其余部分仍然被金属薄膜42保护，再对金属薄膜42进行光刻和刻蚀，得到金属薄膜图案。然后在低温下通过具有氧化功能的等离子体对其进行氧化处理，本实施例中可选取氧等离子体对其进行氧化处理5至60分钟，由于沟道区5裸露在外被氧等离子氧化，其氧空位的浓度减少而转变成低载流子浓度。本实施例中由于采用氧等离子体对其处理，可选择在低温下进行，如25到180度。氧化处理的温度的上限为衬底1能承受的最高温度。
48）如图33所示，用等离子增强化学汽相淀积（PECVD）或磁控溅射方法淀积一层100～300纳米厚的氮化硅层8，然后光刻和刻蚀形成电极的接触孔9和10。
49）如图34所示，用磁控溅射方法淀积一层100～300纳米厚的金属铝膜，然后光刻和刻蚀制成薄膜晶体管各电极的金属引出电极和互连线11和12。
本发明提供的薄膜晶体管制作方法具有如下优点：
1、本发明提供的金属氧化物薄膜晶体管的制造方法，在满足晶体管的有源层在源、漏区具有高的载流子浓度，而沟道区在零栅偏状态下为低载流子浓度的同时，又能保证晶体管的源、漏区和栅电极之间形成自对准，一方面节省了成本，简化了工艺步骤；另一方面减小寄生效应，进而可提高薄膜晶体管的生产合格率以减低生产成本。
2、本发明提供的金属氧化物薄膜晶体管的制造方法，对沟道区进行氧化处理时采用的是氧等离子体的处理方式。因等离子体中的氧自由基即使在低温下也有极强的活性，因此处理过程可以在低温状态下进行，这样衬底也可以选用廉价的低温材料，节省制造成本。
以上内容是结合具体的实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (12)

  1. 一种自对准薄膜晶体管的制作方法，其特征在于包括：
    栅电极生成步骤：在衬底上生成金属栅电极；
    栅介质层生成步骤：在衬底上生成覆盖在所述栅电极之上的栅介质层；
    有源区生成及处理步骤：在栅介质层上生成一层具有高载流子浓度的金属氧化物半导体层，对其进行处理形成包括源区、漏区以及沟道区的有源区，然后在所述金属氧化物半导体层上涂光刻胶层，从所述衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，对所述光刻胶图形做相应的处理，使所述金属氧化物半导体层上的沟道区露出，将所述沟道区在低于所述衬底所能承受的最高温度的温度范围内通过具有氧化功能的等离子体进行氧化处理；
    电极引出步骤：生成源区、漏区和栅电极的电极引线。
  2. 如权利要求1所述的方法，其特征在于，所述具有氧化功能的等离子体为氧等离子体。
  3. 如权利要求1所述的方法，其特征在于，所述金属栅电极为不透光层。
  4. 如权利要求1所述的方法，其特征在于，所述有源区生成及处理步骤中对所述金属氧化物半导体层进行处理形成有源区之前，还包括对所述金属氧化物半导体层在无氧环境中进行热处理。
  5. 如权利要求1所述的方法，其特征在于，将所述沟道区在25-180度的温度下通过具有氧化功能的等离子体对其进行氧化处理。
  6. 如权利要求1所述的方法，其特征在于，在形成有源区的金属氧化物半导体层上涂光刻胶层之前还包括：在所述金属氧化物半导体层上生成一层介质保护层，然后在该介质保护层上涂所述光刻胶，并对其进行处理使所述金属氧化物半导体层上的沟道区露出。
  7. 如权利要求5所述的方法，其特征在于，所述光刻胶层为负性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，然后以该光刻胶图形为掩膜去除沟道区的介质保护层，使所述金属氧化物半导体层上的沟道区露出。
  8. 如权利要求1所述的方法，其特征在于，所述光刻胶层为负性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，使所述金属氧化物半导体层上的沟道区露出。
  9. 如权利要求1所述的方法，其特征在于，所述光刻胶层为正性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，然后在其上表面生成一层介质保护层，并对其进行处理使所述金属氧化物半导体层上的沟道区露出。
  10. 如权利要求1所述的方法，其特征在于，所述光刻胶层为正性光刻胶层，生成所述光刻胶层之后对其处理的过程如下：从衬底的背面以所述栅电极为掩膜进行曝光并显影形成光刻胶图形，然后在其上表面生成一层金属薄膜层，并对其进行处理使所述金属氧化物半导体层上的沟道区露出。
  11. 如权利要求1所述的方法，其特征在于，所述栅介质层的材料为透明材料。
  12. 如权利要求1所述的方法，其特征在于，所述衬底为耐高温透明衬底或者低温透明衬底。
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