WO2013116992A1 - 一种薄膜晶体管阵列基板及其制作方法 - Google Patents

一种薄膜晶体管阵列基板及其制作方法 Download PDF

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WO2013116992A1
WO2013116992A1 PCT/CN2012/070946 CN2012070946W WO2013116992A1 WO 2013116992 A1 WO2013116992 A1 WO 2013116992A1 CN 2012070946 W CN2012070946 W CN 2012070946W WO 2013116992 A1 WO2013116992 A1 WO 2013116992A1
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metal layer
layer
thin film
film transistor
array substrate
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PCT/CN2012/070946
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English (en)
French (fr)
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贾沛
杨流洋
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深圳市华星光电技术有限公司
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Priority to US13/498,470 priority Critical patent/US8563341B2/en
Publication of WO2013116992A1 publication Critical patent/WO2013116992A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • the present invention relates to the field of liquid crystal production technologies, and in particular, to a thin film transistor array substrate and a method of fabricating the same.
  • Boundary field switching technology Feringe Field Switching (FS) is increasingly used in the field of liquid crystal display due to its high transparency and large viewing angle.
  • TFT Thin Film Transistor
  • the process of forming the thin film transistor array substrate of the FFS type liquid crystal display through multiple photomasks is complicated, the manufacturing difficulty and the manufacturing cost are high, and the production difficulty of the liquid crystal display is increased.
  • An object of the present invention is to provide a method for fabricating a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art.
  • the difficulty and production cost are high, which increases the technical difficulty of the production difficulty of the liquid crystal display.
  • Another object of the present invention is to provide a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art, and is difficult to manufacture.
  • the production cost is high, which increases the technical problem of the production difficulty of the liquid crystal display.
  • the invention provides a method for fabricating a thin film transistor array substrate, the method comprising the following steps:
  • the gate includes a transparent conductive layer and a first metal layer, and the common electrode is formed of a transparent conductive layer;
  • a planarization layer is deposited on the pixel electrode and the source, drain, and semiconductor layers constituting the thin film transistor, and the planarization layer is formed of a transparent insulating material.
  • the multi-stage adjustment mask is a gray-scale tone mask, a stack layer mask or a halftone mask.
  • the gate insulating layer and the semiconductor layer are sequentially deposited by a chemical vapor deposition method.
  • the second metal layer is deposited by a sputtering method.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer
  • the second metal layer is sequentially composed of a second molybdenum metal layer, A two-aluminum metal layer and a third molybdenum metal layer are combined.
  • the transparent conductive layer and the first metal layer in the process of patterning the transparent conductive layer and the first metal layer to form a gate electrode and a common electrode by using the multi-stage adjustment mask, nitric acid, phosphoric acid, and the like are used.
  • the first metal layer is wet etched with a mixture of acetic acid, and the transparent conductive layer is wet etched using oxalic acid.
  • the process of fabricating the thin film transistor array substrate of the present invention in the process of forming the source, the drain, and the pixel electrode including the second metal layer on the semiconductor layer by using the third photomask, nitric acid, phosphoric acid, and acetic acid are used.
  • the second metal layer is wet etched by the mixed solution.
  • Another object of the present invention is to provide a method for fabricating a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art.
  • the difficulty in production and the high production cost increase the technical problems of the production difficulty of the liquid crystal display.
  • the present invention provides a method of fabricating a thin film transistor array substrate, the method comprising the following steps:
  • a transparent conductive layer and a first metal layer on the substrate, patterning the transparent conductive layer and the first metal layer by using a multi-stage adjustment mask to form a gate and a common electrode, the gate
  • the transparent conductive layer and the first metal layer are formed, and the common electrode is formed of a transparent conductive layer;
  • a pixel electrode is formed on the insulating layer by the second metal layer.
  • the method further includes the following steps:
  • a planarization layer is deposited on the pixel electrode and the source, drain, and semiconductor layers constituting the thin film transistor, and the planarization layer is formed of a transparent insulating material.
  • the multi-stage adjustment mask is a gray-scale tone mask, a stack layer mask or a halftone mask.
  • the transparent conductive layer and the first metal layer are sequentially deposited by a sputtering method.
  • the gate insulating layer and the semiconductor layer are sequentially deposited by a chemical vapor deposition method.
  • the second metal layer is deposited by a sputtering method.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer
  • the second metal layer is sequentially composed of a second molybdenum metal layer, A two-aluminum metal layer and a third molybdenum metal layer are combined.
  • the transparent conductive layer and the first metal layer in the process of patterning the transparent conductive layer and the first metal layer to form a gate electrode and a common electrode by using the multi-stage adjustment mask, nitric acid, phosphoric acid, and the like are used.
  • the first metal layer is wet etched with a mixture of acetic acid, and the transparent conductive layer is wet etched using oxalic acid.
  • the process of fabricating the thin film transistor array substrate of the present invention in the process of forming the source, the drain, and the pixel electrode including the second metal layer on the semiconductor layer by using the third photomask, nitric acid, phosphoric acid, and The second metal layer is wet etched by a mixture of acetic acid.
  • Another object of the present invention is to provide a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art, and is difficult to manufacture.
  • the production cost is high, which increases the technical problem of the production difficulty of the liquid crystal display.
  • the present invention provides a thin film transistor array substrate, the thin film transistor array substrate comprising:
  • each of the thin film transistors includes a gate, a gate insulating layer, a semiconductor layer, a source and a drain, the gate, the gate insulating layer, and the semiconductor a layer, the source and the drain are sequentially formed on the substrate;
  • the gate includes a transparent conductive layer and a first metal layer, and the source and the drain are formed by a second metal layer;
  • a common electrode formed of a transparent conductive layer on the substrate
  • a plurality of pixel electrodes are formed by a second metal layer on the gate insulating layer and connected to the drain of the thin film transistor.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer
  • the second metal layer is sequentially composed of a second molybdenum metal layer and a second aluminum metal.
  • the layer and the third molybdenum metal layer are combined to form.
  • the present invention performs a multi-stage adjustment mask process by sequentially depositing a transparent conductive layer and a first metal layer on a substrate, and further depositing a gate insulating layer and a semiconductor layer on the substrate to perform second light.
  • a third photomask process is performed to form a thin film transistor array substrate of the FFS liquid crystal display.
  • the present invention forms a thin film transistor array substrate of an FFS type liquid crystal display through a three-mask process, which simplifies the process, reduces the manufacturing difficulty and the manufacturing cost, and improves the output of the liquid crystal display.
  • FIG. 1 is a cross-sectional view of a display panel and a backlight module according to a preferred embodiment of the present invention
  • 2A-2E are schematic flow charts showing a preferred embodiment of fabricating a TFT array substrate in the present invention.
  • FIG. 1 shows a cross-sectional view of a display panel and a backlight module according to an embodiment of the invention.
  • the method of manufacturing the thin film transistor (TFT) array substrate of the present embodiment can be applied to the display panel 10 In the manufacturing process of (for example, a liquid crystal display panel), a protective layer of a transistor is fabricated.
  • the liquid crystal display panel 10 can be disposed on the backlight module 20, thereby forming a liquid crystal display device.
  • the display panel 10 can include a first substrate 11 , a second substrate 12 , a liquid crystal layer 13 , a first polarizer 14 , and a second polarizer 15 .
  • the substrate material of the first substrate 11 and the second substrate 12 may be a glass substrate or a flexible plastic substrate.
  • the first substrate 11 may be, for example, a thin film transistor (Thin Film Transistor (TFT) array substrate
  • the second substrate 12 may be, for example, a color filter (Color) Filter, CF) substrate.
  • TFT Thin Film Transistor
  • CF color filter
  • the color filter and the TFT matrix may also be disposed on the same substrate.
  • the liquid crystal layer 13 is formed between the first substrate 11 and the second substrate 12.
  • the first polarizer 14 is a side on which the first substrate 11 is disposed, and is opposite to the liquid crystal layer 13 (that is, the light incident side of the first substrate 11)
  • the second polarizer 15 is the side on which the second substrate 12 is disposed, and is opposite to the liquid crystal layer 13 (i.e., the light exiting side of the second substrate 12).
  • 2A-2E are schematic cross-sectional views showing a process of a thin film transistor array substrate of a display panel according to a preferred embodiment of the present invention.
  • a substrate 110 is provided on which a transparent conductive layer 120 and a first metal layer 130 are sequentially deposited.
  • the transparent conductive layer 120 is preferably formed using a transparent conductive metal such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
  • ITO indium tin oxide
  • TO tin oxide
  • IZO indium zinc oxide
  • ITZO indium tin zinc oxide
  • the first metal layer 130 is preferably composed of a combination of a first aluminum metal layer and a first molybdenum metal layer.
  • a first aluminum metal layer preferably composed of silver (Ag), copper (Cu), chromium (Cr), and tungsten (W) may also be used.
  • An alloy of tantalum (Ta), titanium (Ti), a metal nitride or any combination thereof may also be a multilayer structure having a heat resistant metal film and a low resistivity film.
  • the transparent conductive layer 120 and the first metal layer 130 shown in FIG. 2A are patterned by a multi-stage adjustment mask to form a gate electrode 140 and a common electrode 121.
  • the gate electrode 140 includes a transparent conductive layer 120 and a first metal layer 130.
  • the common electrode 121 is formed by a transparent conductive layer 120 on the substrate 110.
  • the transparent conductive layer 120 and the first metal layer 130 are preferably formed on the substrate 110 by a sputtering method, and then the lithography process and the etching process of the reticle are performed on the transparent conductive layer 120 by a multi-stage adjustment method.
  • the first metal layer 130 forms a gate electrode 140, and the transparent conductive layer 120 on the substrate 110 forms a common electrode 121.
  • the multi-stage adjustment mask adopts a multi-stage adjustment photomask
  • the multi-stage adjustment photomask can be, for example, a gray tone photomask (Gray Tone). Mask, GTM), Stacked Layer Mask (SLM) or Halftone Mask (Half Tone) Mask, HTM), etc.
  • the multi-segment adjustment photomask may include an exposed region, a partially exposed region, and an unexposed region, etc., such that the transparent conductive layer 120 and the first metal layer 130 form a gate 140 such that the substrate 110 is transparent.
  • the conductive layer 120 forms a common electrode 121.
  • the transparent conductive layer 120 and the first metal layer 130 In the process of patterning the transparent conductive layer 120 and the first metal layer 130 by using a multi-stage adjustment mask to form the gate electrode 140 and the common electrode 121, it is preferable to use a mixed solution of nitric acid, phosphoric acid, and acetic acid.
  • a metal layer 130 is subjected to wet etching, and the transparent conductive layer 120 is preferably wet-etched using oxalic acid to form the structure shown in FIG. 2B.
  • the transparent conductive layer 120 and the first layer may be used in other manners.
  • a metal layer 130 is subjected to wet etching, which is not enumerated here.
  • the gate insulating layer 150 and the semiconductor layer 160 are sequentially deposited on the substrate 110, and the semiconductor layer 160 is patterned by using the second mask to retain the semiconductor layer above the gate 140. 160, the structure shown in Fig. 2C is formed.
  • the present invention preferably deposits the gate insulating layer 150 and the semiconductor layer 160 using chemical vapor deposition, such as plasma enhanced chemical vapor deposition (Plasma Enhanced). Chemical Vapor Deposition, PECVD), of course, the gate insulating layer 150 and the semiconductor layer 160 may be deposited by other means, which are not enumerated here.
  • chemical vapor deposition such as plasma enhanced chemical vapor deposition (Plasma Enhanced).
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer 150 and the semiconductor layer 160 may be deposited by other means, which are not enumerated here.
  • the material of the gate insulating layer 150 is, for example, silicon nitride (SiNx) or silicon oxide (SiOx), and the material of the semiconductor layer 160 is preferably polysilicon (Poly-Silicon).
  • the semiconductor layer 160 may first deposit an amorphous silicon (a-Si) layer, and then rapidly thermally anneal the amorphous silicon layer (Rapid). A thermal annealing, RTA) step of recrystallizing the amorphous silicon layer into a polysilicon layer.
  • a second metal layer 170 is formed on the substrate 110.
  • the present invention preferably forms a second metal layer 170 by sputtering.
  • the second metal layer 170 is preferably formed by sequentially combining a second molybdenum metal layer, a second aluminum metal layer, and a third molybdenum metal layer.
  • a second molybdenum metal layer preferably formed by sequentially combining a second molybdenum metal layer, a second aluminum metal layer, and a third molybdenum metal layer.
  • other materials such as silver (Ag), copper (Cu), and chromium may also be used.
  • the alloy of Cr), tungsten (W), tantalum (Ta), titanium (Ti), metal nitride or any combination thereof may also be a multilayer structure having a heat resistant metal film and a low resistivity film.
  • the second metal layer 170 is patterned by using a third photomask, and a source 171 and a drain 172 are formed on the semiconductor layer 160 by the second metal layer 170, at the common electrode 121.
  • a pixel electrode 173 is formed on the corresponding gate insulating layer 150 by the second metal layer 170.
  • the pixel electrode 173 is connected to the drain 172, and the common electrode 121 is separated from the pixel electrode 173 by the gate insulating layer 150.
  • the second metal layer 170 is wet etched by a mixed solution of phosphoric acid and acetic acid.
  • a planarization layer (not shown) may be deposited on the pixel electrode 173, the source 171 constituting the thin film transistor, the drain 172, and the semiconductor layer 160. Achieve flatness and protect components.
  • the planarization layer is formed of a transparent insulating material, and may of course be other materials, which are not enumerated here.
  • the present invention also provides a thin film transistor array substrate including a substrate 110 and a common electrode 121 and a plurality of thin film transistors disposed on the substrate 110.
  • the thin film transistor includes a gate 140, a gate insulating layer 150, a semiconductor layer 160, a source 171, and a drain 172.
  • the gate 140, the gate insulating layer 150, the semiconductor layer 160, the source 171 and the drain 172 are sequentially formed on the substrate 110; the gate 140 includes a transparent conductive layer 120 and The first metal layer 130, the source electrode 171 and the drain electrode 172 are formed by the second metal layer 170 on the semiconductor layer 160.
  • the common electrode 121 is formed by the transparent conductive layer 120 on the substrate 110.
  • the thin film transistor array substrate further includes a plurality of pixel electrodes 173 formed by a second metal layer 170 on the gate insulating layer 150 corresponding to the common electrode 121, the pixel electrode 173 and the thin film transistor The drain 172 is connected.
  • the thin film transistor array substrate and the manufacturing method of the display panel of the present invention only require three photomasks (ie, a multi-stage adjustment mask, a second mask, and a third mask) to complete the thin film transistor array substrate of the FFS type liquid crystal display, thereby It can reduce the number of photomasks required for the process, thereby reducing process cost and time.
  • three photomasks ie, a multi-stage adjustment mask, a second mask, and a third mask

Abstract

一种薄膜晶体管阵列基板（11）及其制作方法，在基板（110）上沉积透明导电层（120）和第一金属层（130），利用一多段式调整光罩形成栅极（140）和共通电极（121）；在基板（110）上沉积栅绝缘层（150）和半导体层（160），利用第二光罩保留栅极（140）上方的半导体层（160）；在基板（110）上沉积第二金属层（170），利用第三光罩形成源极（171）、漏极（172）和像素电极（173）。从而，简化了工艺制程。

Description

一种薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及液晶生产技术领域，特别涉及一种薄膜晶体管阵列基板及其制作方法。
 背景技术
随着液晶显示器的不断推广和普及，对液晶显示器的显示性能提出了很高的要求。边界电场切换技术(Fringe Field Switching，FFS)由于具有高穿透性以及大视角的特征，被越来越多地应用在液晶显示领域。
在液晶显示器的薄膜晶体管(Thin Film Transistor，TFT) 阵列基板制程中，需使用多道光罩来进行光刻制程(Photo-lithography)，然而，光罩相当昂贵，光罩次数越多则薄膜晶体管制程所需的成本越高，且增加制程时间及复杂度。
因此，现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度。
故，有必要提供一种薄膜晶体管阵列基板及其制造方法，以解决现有技术所存在的问题。
 技术问题
本发明的一个目的在于提供一种薄膜晶体管阵列基板的制作方法，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
本发明的又一个目的在于提供一种薄膜晶体管阵列基板，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
 技术解决方案
本发明提供了一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：
提供基板；
在所述基板上通过溅射法依次沉积透明导电层和第一金属层，利用一多段式调整光罩对所述透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极包括透明导电层和第一金属层，所述共通电极由透明导电层形成；
在所述基板上继续沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
在所述基板上继续沉积第二金属层，利用第三光罩来图案化第二金属层，在半导体层上形成包括第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二金属层形成像素电极；
在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
在本发明的薄膜晶体管阵列基板的制作方法中，所述栅绝缘层和半导体层通过化学气相沉积法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第二金属层通过溅射法沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
在本发明的薄膜晶体管阵列基板的制作方法中，利用所述多段式调整光罩对所述透明导电层和第一金属层进行图案化形成栅极和共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述透明导电层进行湿法刻蚀。
在本发明的薄膜晶体管阵列基板的制作方法中，利用第三光罩在半导体层上形成包括所述第二金属层的源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀。
本发明的另一个目的在于提供一种薄膜晶体管阵列基板的制作方法，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
为解决上述问题，本发明提供了一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：
提供基板；
在所述基板上依次沉积透明导电层和第一金属层，利用一多段式调整光罩对所述透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极包括透明导电层和第一金属层，所述共通电极由透明导电层形成；
在所述基板上继续沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
在所述基板上继续沉积第二金属层，利用第三光罩来图案化第二金属层，在半导体层上形成包括第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二金属层形成像素电极。
在本发明的薄膜晶体管阵列基板的制作方法中，在形成所述源极、漏极和像素电极后，所述方法还包括以下步骤：
在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
在本发明的薄膜晶体管阵列基板的制作方法中，所述透明导电层和所述第一金属层通过溅射法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述栅绝缘层和所述半导体层通过化学气相沉积法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第二金属层通过溅射法沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
在本发明的薄膜晶体管阵列基板的制作方法中，利用所述多段式调整光罩对所述透明导电层和第一金属层进行图案化形成栅极和共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述透明导电层进行湿法刻蚀。
在本发明的薄膜晶体管阵列基板的制作方法中，利用所述第三光罩在半导体层上形成包括所述第二金属层的源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀。
本发明的又一个目的在于提供一种薄膜晶体管阵列基板，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
为解决上述问题，本发明提供了一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板；
多个薄膜晶体管，设置于所述基板上，其中每一所述薄膜晶体管包括栅极、栅绝缘层、半导体层、源极及漏极，所述栅极、所述栅绝缘层、所述半导体层、所述源极及漏极是依序形成于所述基板上；所述栅极包括透明导电层和第一金属层，所述源极及所述漏极由第二金属层形成；
共通电极，由所述基板上的透明导电层形成；
多个像素电极，由所述栅绝缘层上的第二金属层形成，并与所述薄膜晶体管的所述漏极连接。
在本发明的薄膜晶体管阵列基板中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
 有益效果
本发明相对于现有技术，通过基板上依次沉积透明导电层和第一金属层后进行一多段式调整光罩制程，在所述基板上继续沉积栅绝缘层和半导体层后进行第二光罩制程，在所述基板上继续沉积第二金属层后进行第三光罩制程形成FFS型液晶显示器的薄膜晶体管阵列基板。显然，本发明通过三道光罩制程形成FFS型液晶显示器的薄膜晶体管阵列基板，简化了工艺制程，降低了制作难度以及制作成本，提高了液晶显示器的产量。
 附图说明
图1为本发明的一较佳实施例的显示面板与背光模块的剖面示意图；
图2A-图2E为本发明中制作TFT阵列基板的较佳实施例的流程示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，其显示依照本发明的一实施例的显示面板与背光模块的剖面示意图。本实施例的薄膜晶体管(TFT)阵列基板的制造方法可应用于显示面板10 (例如液晶显示面板)的制造过程中，以制造晶体管的保护层。当应用本实施例的显示面板10来制造一液晶显示装置时，可设置液晶显示面板10于背光模块20上，因而形成液晶显示装置。此显示面板10可包括第一基板11、第二基板12、液晶层13、第一偏光片14及第二偏光片15。第一基板11和第二基板12的基板材料可为玻璃基板或可挠性塑料基板，在本实施例中，第一基板11可例如为薄膜晶体管(Thin Film Transistor，TFT)阵列基板，而第二基板12可例如为彩色滤光片(Color Filter，CF)基板。值得注意的是，在一些实施例中，彩色滤光片和TFT矩阵亦可配置在同一基板上。
如图1所示，液晶层13是形成于第一基板11与第二基板12之间。第一偏光片14是设置第一基板11的一侧，并相对于液晶层13 (即第一基板11的入光侧)，第二偏光片15是设置第二基板12的一侧，并相对于液晶层13 (即第二基板12的出光侧)。
图2A-图2E为本发明中较佳实施例的显示面板的薄膜晶体管阵列基板的制程剖面示意图。
请参阅图2A，提供基板110，在所述基板110上依次沉积透明导电层120和第一金属层130。
所述透明导电层120优选使用透明导电金属形成，该透明导电金属譬如铟锡氧化物（ITO）、锡氧化物（TO）、铟锌氧化物（IZO）以及铟锡锌氧化物（ITZO）。
所述第一金属层130优选由第一铝金属层和第一钼金属层组合构成，当然也可以使用其它材料，譬如银（Ag）、铜（Cu）、铬（Cr）、钨（W）、钽（Ta）、钛（Ti）、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构。
请参阅图2B，利用一多段式调整光罩对图2A所示的所述透明导电层120和第一金属层130进行图案化处理形成栅极140和共通电极121。其中，所述栅极140包括透明导电层120和第一金属层130，所述共通电极121由所述基板110上的透明导电层120形成。
在具体实施过程中，优选采用溅射法在基板110形成所述透明导电层120和第一金属层130，之后通过多段式调整光罩的光刻程序和蚀刻程序在所述透明导电层120和第一金属层130形成栅极140，在所述基板110上的透明导电层120形成共通电极121。
在具体实施过程中，所述多段式调整光罩采用一多段式调整光掩膜，所述多段式调整光掩膜可例如为灰阶色调光掩膜(Gray Tone Mask，GTM)、堆栈图层光掩膜(Stacked Layer Mask，SLM)或半色调光掩膜(Half Tone Mask，HTM)等。所述多段式调整光掩膜可包括曝光区域、部分曝光区域以及未曝光区域等，籍以使得所述透明导电层120和第一金属层130形成栅极140，使得所述基板110上的透明导电层120形成共通电极121。
其中，利用多段式调整光罩对所述透明导电层120和第一金属层130进行图案化形成栅极140和共通电极121的过程中，优选使用硝酸、磷酸以及醋酸的混合液对所述第一金属层130进行湿法刻蚀，优选使用草酸对所述透明导电层120进行湿法刻蚀，进而形成图2B所示的结构，当然可以使用其他的方式对所述透明导电层120和第一金属层130进行湿法刻蚀，此处不一一列举。
请继续参阅图2C，继续在所述基板110上依次沉积栅绝缘层150和半导体层160，利用第二光罩对所述半导体层160进行图案化，保留位于所述栅极140上方的半导体层160，形成图2C所示的结构。
本发明优选使用化学气相沉积法沉积所述栅绝缘层150和所述半导体层160，譬如等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition, PECVD)方式，当然还可以通过其它方式沉积所述栅绝缘层150和所述半导体层160，此处不一一列举。
所述栅绝缘层150的材料例如为氮化硅(SiNx)或氧化硅(SiOx)，所述半导体层160的材料优选为多晶硅(Poly-Silicon)。在本实施例中，所述半导体层160可先沉积一非晶硅(a-Si)层，接着，对该非晶硅层进行快速热退火(Rapid thermal annealing, RTA)步骤，藉以使该非晶硅层再结晶成一多晶硅层。
请参阅图2D， 继续在所述基板110上沉积形成第二金属层170。
本发明优选使用溅射法沉积形成第二金属层170。所述第二金属层170优选由第二钼金属层、第二铝金属层以及第三钼金属层依次组合形成，当然也可以使用其它材料，譬如银（Ag）、铜（Cu）、铬（Cr）、钨（W）、钽（Ta）、钛（Ti）、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构。
请参阅图2E，利用第三光罩对所述第二金属层170进行图案化，在半导体层160上由所述第二金属层170形成源极171和漏极172，在所述共通电极121对应的栅绝缘层150上由所述第二金属层170形成像素电极173。其中，所述像素电极173连接所述漏极172，所述共通电极121通过所述栅绝缘层150与所述像素电极173隔开。
利用第三光罩在半导体层160上由第二金属层170形成源极171和漏极172、以及在栅绝缘层150上由第二金属层170形成像素电极173的过程中，优选使用硝酸、磷酸以及醋酸的混合液对所述第二金属层170进行湿法刻蚀。
在一实施例中，在形成图2E所示结构后，可在像素电极173、构成薄膜晶体管的源极171、漏极172和半导体层160上沉积一平坦化层（图未示出），以达到平坦化及保护组件的功效。优选的，所述平坦化层由透明绝缘材质形成，当然也可以为其它材质，此处不一一列举。
本发明还提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括基板110以及设置在所述基板110上的共通电极121和多个薄膜晶体管。
所述薄膜晶体管包括栅极140、栅绝缘层150、半导体层160、源极171及漏极172。所述栅极140、所述栅绝缘层150、所述半导体层160、所述源极171及漏极172是依序形成于所述基板110上；所述栅极140包括透明导电层120和第一金属层130，所述源极171及所述漏极172是由半导体层160上的第二金属层170形成。
其中，所述共通电极121由所述基板110上的透明导电层120形成。所述薄膜晶体管阵列基板还包括多个像素电极173，所述像素电极173由所述共通电极121对应的栅绝缘层150上的第二金属层170形成，所述像素电极173与所述薄膜晶体管的所述漏极172连接。
本发明的薄膜晶体管阵列基板及显示面板的制造方法仅需三道光掩膜（即多段式调整光罩、第二光罩和第三光罩）来完成FFS型液晶显示器的薄膜晶体管阵列基板，因而可减少制程所需的光掩膜数，进而减少制程成本及时间。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (18)

  1. 一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：
    提供基板；
    在所述基板上通过溅射法依次沉积透明导电层和第一金属层，利用一多段式调整光罩对所述透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极包括透明导电层和第一金属层，所述共通电极由透明导电层形成；
    在所述基板上继续沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
    在所述基板上继续沉积第二金属层，利用第三光罩来图案化第二金属层，在半导体层上形成包括第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二金属层形成像素电极；
    在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
  2. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
  3. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述栅绝缘层和半导体层通过化学气相沉积法依次沉积形成。
  4. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述第二金属层通过溅射法沉积形成。
  5. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
  6. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，利用所述多段式调整光罩对所述透明导电层和第一金属层进行图案化形成栅极和共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述透明导电层进行湿法刻蚀。
  7. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，利用第三光罩在半导体层上形成包括所述第二金属层的源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀。
  8. 一种薄膜晶体管阵列基板的制作方法，其中，所述方法包括以下步骤：
    提供基板；
    在所述基板上依次沉积透明导电层和第一金属层，利用一多段式调整光罩对所述透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极包括透明导电层和第一金属层，所述共通电极由透明导电层形成；
    在所述基板上继续沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
    在所述基板上继续沉积第二金属层，利用第三光罩来图案化第二金属层，在半导体层上形成包括第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二金属层形成像素电极。
  9. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，在形成所述源极、漏极和像素电极后，所述方法还包括以下步骤：
    在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
  10. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
  11. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述透明导电层和第一金属层通过溅射法依次沉积形成。
  12. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述栅绝缘层和半导体层通过化学气相沉积法依次沉积形成。
  13. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述第二金属层通过溅射法沉积形成。
  14. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
  15. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，利用所述多段式调整光罩对所述透明导电层和第一金属层进行图案化形成栅极和共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述透明导电层进行湿法刻蚀。
  16. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，利用第三光罩在半导体层上形成包括所述第二金属层的源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀。
  17. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    基板；
    多个薄膜晶体管，设置于所述基板上，其中每一所述薄膜晶体管包括栅极、栅绝缘层、半导体层、源极及漏极，所述栅极、所述栅绝缘层、所述半导体层、所述源极及漏极是依序形成于所述基板上；所述栅极包括透明导电层和第一金属层，所述源极及所述漏极由第二金属层形成；
    共通电极，由所述基板上的透明导电层形成；
    多个像素电极，由所述共通电极对应的栅绝缘层上的第二金属层形成，并与所述薄膜晶体管的所述漏极连接。
  18. 根据权利要求17所述的薄膜晶体管阵列基板，其中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110246848A (zh) * 2019-05-05 2019-09-17 福建华佳彩有限公司 一种氧化物半导体tft阵列基板及其制作方法
CN111624826A (zh) * 2020-05-08 2020-09-04 福建华佳彩有限公司 一种lcd面板及其制备方法
CN111969015A (zh) * 2020-08-19 2020-11-20 福建华佳彩有限公司 一种阵列基板膜层结构及其制备方法
CN111969014A (zh) * 2020-08-19 2020-11-20 福建华佳彩有限公司 一种新型阵列基板膜层结构及其制备方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208506A (zh) * 2013-03-28 2013-07-17 京东方科技集团股份有限公司 阵列基板、显示装置及制作方法
CN103236440B (zh) 2013-04-12 2016-02-10 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法、显示装置
CN103646612B (zh) * 2013-12-18 2017-02-01 京东方科技集团股份有限公司 一种电极结构、阵列基板及显示装置
CN105679773B (zh) * 2016-01-29 2018-12-07 深圳市华星光电技术有限公司 阵列基板及阵列基板的制备方法
CN105487285B (zh) * 2016-02-01 2018-09-14 深圳市华星光电技术有限公司 阵列基板及阵列基板的制备方法
KR102503705B1 (ko) * 2016-05-19 2023-02-24 삼성디스플레이 주식회사 표시 기판
CN106024706B (zh) * 2016-06-22 2019-02-19 深圳市华星光电技术有限公司 阵列基板及其制作方法
CN106711159B (zh) * 2017-03-28 2019-09-03 上海天马微电子有限公司 阵列基板和阵列基板的制作方法
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CN107731882A (zh) * 2017-11-07 2018-02-23 深圳市华星光电半导体显示技术有限公司 一种有机薄膜晶体管阵列基板及其制备方法、显示装置
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CN109616443A (zh) * 2018-11-07 2019-04-12 深圳市华星光电半导体显示技术有限公司 阵列基板的制作方法及阵列基板
CN114935857A (zh) * 2022-04-21 2022-08-23 广州华星光电半导体显示技术有限公司 一种显示面板及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070109455A1 (en) * 2005-11-11 2007-05-17 Boe Hydis Technology Co., Ltd. Method for manufacturing array substrate of translucent LCD
KR20070080476A (ko) * 2006-02-07 2007-08-10 삼성전자주식회사 3 마스크 공정에 의한 액정표시장치의 제조방법
CN101995709A (zh) * 2009-08-27 2011-03-30 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板及其制造方法
CN102148195A (zh) * 2010-04-26 2011-08-10 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100325072B1 (ko) * 1998-10-28 2002-08-24 주식회사 현대 디스플레이 테크놀로지 고개구율및고투과율액정표시장치의제조방법
KR101167304B1 (ko) * 2004-12-31 2012-07-19 엘지디스플레이 주식회사 프린지 필드 스위칭 타입의 박막 트랜지스터 기판 및 그제조 방법
CN102315165B (zh) * 2010-10-14 2015-08-26 深超光电（深圳）有限公司 边缘电场型液晶显示器阵列基板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070109455A1 (en) * 2005-11-11 2007-05-17 Boe Hydis Technology Co., Ltd. Method for manufacturing array substrate of translucent LCD
KR20070080476A (ko) * 2006-02-07 2007-08-10 삼성전자주식회사 3 마스크 공정에 의한 액정표시장치의 제조방법
CN101995709A (zh) * 2009-08-27 2011-03-30 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板及其制造方法
CN102148195A (zh) * 2010-04-26 2011-08-10 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110246848A (zh) * 2019-05-05 2019-09-17 福建华佳彩有限公司 一种氧化物半导体tft阵列基板及其制作方法
CN110246848B (zh) * 2019-05-05 2024-04-12 福建华佳彩有限公司 一种氧化物半导体tft阵列基板及其制作方法
CN111624826A (zh) * 2020-05-08 2020-09-04 福建华佳彩有限公司 一种lcd面板及其制备方法
CN111969015A (zh) * 2020-08-19 2020-11-20 福建华佳彩有限公司 一种阵列基板膜层结构及其制备方法
CN111969014A (zh) * 2020-08-19 2020-11-20 福建华佳彩有限公司 一种新型阵列基板膜层结构及其制备方法

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