WO2017152450A1 - Ffs模式的阵列基板及制作方法 - Google Patents

Ffs模式的阵列基板及制作方法 Download PDF

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Publication number
WO2017152450A1
WO2017152450A1 PCT/CN2016/078754 CN2016078754W WO2017152450A1 WO 2017152450 A1 WO2017152450 A1 WO 2017152450A1 CN 2016078754 W CN2016078754 W CN 2016078754W WO 2017152450 A1 WO2017152450 A1 WO 2017152450A1
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Prior art keywords
layer
region
semiconductor layer
pixel electrode
insulating layer
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PCT/CN2016/078754
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English (en)
French (fr)
Inventor
葛世民
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深圳市华星光电技术有限公司
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Priority to US15/116,229 priority Critical patent/US9798202B2/en
Publication of WO2017152450A1 publication Critical patent/WO2017152450A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display, and in particular to an array substrate of an FFS mode and a method of fabricating the same.
  • the active matrix driven LCD display technology utilizes the bipolar polarization characteristics of the liquid crystal, and controls the arrangement direction of the liquid crystal molecules by applying an electric field, thereby realizing the switching control of the traveling direction of the backlight optical path.
  • the LCD display mode can be divided into TN series modes.
  • VA series mode refers to applying a longitudinal electric field to liquid crystal molecules
  • IPS series mode refers to applying a transverse electric field to liquid crystal molecules.
  • the IPS series mode for the application of the transverse electric field, it can be divided into the IPS mode and the FFS mode.
  • Each pixel unit of the FFS display mode includes two upper and lower electrodes, that is, a pixel electrode and a common electrode, and the common electrode of the lower layer is flattened on the entire surface of the open area.
  • the FFS display mode has a high transmittance, wide viewing angle and low color shift, and is a widely used LCD display technology.
  • etch stop layer (ESL) structure of the TFT structure is widely used, which can effectively reduce the influence of external environmental factors and etch damage of the source and drain electrodes on the back channel.
  • ESL etch stop layer
  • the conventional FFS display mode array substrate manufacturing method of the ESL structure requires more mask times, which increases the complexity of the process and the production cost.
  • An object of the present invention is to provide an FFS mode array substrate and a manufacturing method thereof.
  • the conventional FFS display mode array substrate manufacturing method for solving the ESL structure in the prior art requires more mask times, increases the complexity of the process, and Technical issues of production costs.
  • the embodiment of the invention provides a method for fabricating an array substrate of an FFS mode, which comprises the following steps:
  • a first insulating layer and a semiconductor layer on the glass substrate and the gate, the semiconductor layer being provided with a channel region, a common electrode region, and a third spacer region between the common electrode region and the channel region;
  • a second insulating layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulating layer, and a first via hole and a second via hole exposing the channel semiconductor layer are formed on the second insulating layer.
  • the method further includes the following steps:
  • a pixel electrode layer on the second insulating layer the pixel electrode layer being provided with a plurality of pixel electrode regions, and a first spacing region between adjacent two pixel electrode regions;
  • the first metal layer is provided with a source region, a drain region, and a second spacer region between the source region and the drain region;
  • a third insulating layer is deposited on the source, the drain, the pixel electrode, and the second insulating layer.
  • the channel semiconductor layer is provided with two doped regions respectively corresponding to the first via and the second via, and the trench is removed.
  • the step of the second photoresist layer on the semiconductor layer includes:
  • the second insulating layer and the third insulating layer each comprise silicon nitride and/or silicon dioxide.
  • the channel semiconductor layer comprises indium gallium zinc oxide.
  • the pixel electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the pixel electrode layer has a thickness of 10 nm to 100 nm.
  • the invention also provides a method for fabricating an array substrate of an FFS mode, comprising the following steps:
  • a first insulating layer and a semiconductor layer on the glass substrate and the gate, the semiconductor layer being provided with a channel region, a common electrode region, and a third spacer region between the common electrode region and the channel region;
  • a pixel electrode layer on the second insulating layer the pixel electrode layer being provided with a plurality of pixel electrode regions, and a first spacing region between adjacent two pixel electrode regions;
  • the first metal layer is provided with a source region, a drain region, and a second spacer region between the source region and the drain region;
  • the second insulating layer and the third insulating layer each comprise silicon nitride and/or silicon dioxide.
  • the invention also provides an array substrate of an FFS mode, comprising:
  • the gate is disposed on the glass substrate
  • a first insulating layer disposed on the glass substrate and the gate
  • the semiconductor layer disposed on the first insulating layer, the semiconductor layer including a channel region and a common electrode region, the channel semiconductor layer being formed in a channel region of the semiconductor layer, in the semiconductor layer Semiconductor doping of the common electrode region forms a common electrode layer;
  • a second insulating layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulating layer, and the first via hole and the second via hole exposing the channel semiconductor layer are formed on the second insulating layer.
  • the method further includes:
  • a pixel electrode layer deposited on the second insulating layer, wherein the pixel electrode layer is provided with a pixel electrode;
  • a source and a drain the source and the drain being disposed on the pixel electrode layer
  • a third insulating layer disposed on the source, the drain, the pixel electrode, and the second insulating layer.
  • the method further includes:
  • the channel semiconductor layer includes indium gallium zinc oxide.
  • the method further includes:
  • the pixel electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the pixel electrode layer has a thickness of 10 nm to 100 nm.
  • the present invention also provides an array substrate of an FFS mode, comprising:
  • the gate is disposed on the glass substrate
  • a first insulating layer disposed on the glass substrate and the gate
  • the semiconductor layer disposed on the first insulating layer, the semiconductor layer including a channel region and a common electrode region, the channel semiconductor layer being formed in a channel region of the semiconductor layer, in the semiconductor layer Semiconductor doping of the common electrode region forms a common electrode layer;
  • a pixel electrode layer deposited on the second insulating layer, wherein the pixel electrode layer is provided with a pixel electrode;
  • a source and a drain the source and the drain being disposed on the pixel electrode layer
  • a third insulating layer disposed on the source, the drain, the pixel electrode, and the second insulating layer;
  • the second insulating layer and the third insulating layer each comprise silicon nitride and/or silicon dioxide.
  • FIG. 1 is a schematic structural view of a preferred embodiment of an array substrate of an FFS mode according to the present invention
  • FIG. 2 is a flow chart of a preferred embodiment of a method for fabricating an array substrate of an FFS mode according to the present invention
  • 3A-3I are schematic diagrams showing specific fabrication in a preferred embodiment of a method for fabricating an FFS mode array substrate according to the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of an FFS mode array substrate according to the present invention.
  • An FFS mode array substrate of the preferred embodiment includes: a glass substrate 11, a gate electrode 12, a semiconductor layer (not labeled in FIG. 1), a first insulating layer 14, a second insulating layer 20, and a pixel electrode layer 30, The source 41, the drain 42 and the third insulating layer 50.
  • the glass substrate 11, the gate electrode 12, the semiconductor layer (not labeled in FIG. 1), and the first insulating layer 14 constitute a base layer.
  • the gate electrode 12 is disposed on the glass substrate 11.
  • the first insulating layer 14 is disposed on the glass substrate 11 and the gate electrode 12
  • the semiconductor layer is disposed on the first insulating layer 14 .
  • the semiconductor layer is provided with a channel region, a common electrode region, and a third spacer region (not labeled) between the channel region and the common electrode region, the channel region forming a channel of the thin film transistor
  • the semiconductor layer 13 is located above the gate electrode 12.
  • the semiconductor layer of the common electrode region is formed by doping to form a common electrode layer 15, and the semiconductor layer of the third spacer region is removed by a photolithography process.
  • the second insulating layer 20 is disposed on the first insulating layer 14 , the common electrode layer 15 , and the channel semiconductor layer 13 .
  • a first via hole and a second via hole through which the channel semiconductor layer 13 leaks are formed on the second insulating layer 20 by photolithography.
  • the pixel electrode layer 30 is disposed on the second insulating layer 20.
  • the pixel electrode layer 30 is provided with a contact portion 30a at the thin film transistor region and a plurality of pixel electrodes on a side of the thin film transistor region.
  • the contact portion 30a passes through The first via and the second via are in contact with the channel semiconductor layer 13.
  • the source 41 and the drain 42 are both disposed on the contact portion 30a of the pixel electrode layer 30, and are in contact with the channel semiconductor layer 13 through the contact portion 30a, respectively.
  • the third insulating layer 50 is disposed on the second insulating layer 20, the source 41, the drain 42 and the pixel electrode layer 30.
  • the semiconductor layer is made of indium gallium zinc oxide
  • the channel semiconductor layer 13 is made of indium gallium zinc oxide. Of course, it is not limited thereto.
  • the first insulating layer 14 is made of silicon nitride and/or silicon dioxide and is mainly used to insulate the gate electrode 12 from the common electrode layer 15.
  • the first insulating layer 14 has a thickness of 100 nm to 300 nm.
  • the second insulating layer 20 is made of silicon nitride and/or silicon dioxide and is mainly used to insulate the pixel electrode layer 30 from the common electrode layer 15.
  • the second insulating layer 20 has a thickness of 50 nm to 150 nm.
  • the third insulating layer 50 is made of silicon nitride. In the present embodiment, it is a flat layer, and is mainly used to protect the pixel electrode, the source 41, and the drain 42.
  • the pixel electrode layer 30 is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer having a thickness of 10 nm to 100 nm.
  • the channel semiconductor layer 13 is further provided with two doped regions corresponding to the first via holes and the second via holes, respectively, in the doped region of the channel semiconductor layer 13 The doping is performed to convert the semiconductor of the region into a conductor, thereby having the effect of lowering the impedance of the channel semiconductor layer 13.
  • the source electrode 41 and the drain electrode 42 are disposed on the pixel electrode layer 30, so that the source electrode 41, the drain electrode 42 and the pixel electrode can be simultaneously formed by a photomask during the fabrication process. Shorten the process and increase the efficiency of production efficiency.
  • the channel semiconductor layer 13 and the common electrode layer 15 in the same layer, it can be formed by a photomask and formed by doping the common electrode layer 15 in the common electrode region of the semiconductor layer, thereby further shortening Process flow and improved generation efficiency.
  • FIG. 2 is a flowchart of an FFS mode array substrate in a preferred embodiment of the present invention, the method comprising the following steps:
  • the base layer is provided with a gate electrode and a channel semiconductor layer;
  • the pixel electrode layer is provided with a plurality of pixel electrode regions, and a first spacing region between adjacent two pixel electrode regions;
  • S304 depositing a first metal layer on the pixel electrode layer, the first metal layer is provided with a source region, a drain region, and a second spacer region between the source region and the drain region;
  • step S301 it specifically includes the following sub-steps:
  • the second insulating layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulating layer.
  • the material of the gate electrode 13 is a stacked combination of one or more of molybdenum, titanium, aluminum, copper, which is formed by physical vapor deposition deposition. As shown in FIG. 4A, the process goes to step S32.
  • the first insulating layer 14 is formed by depositing silicon nitride and/or silicon dioxide by chemical vapor deposition, and is mainly used for insulating the gate electrode 12 from the common electrode layer 15.
  • the first insulating layer 14 has a thickness of 100 nm to 300 nm.
  • the semiconductor layer 1315 is formed by indium gallium zinc oxide and deposited by physical vapor deposition. It is divided into a channel region 1A, a common electrode region 1B, and a third spacer region 1C between the common electrode region 1B and the channel region 1A. As shown in FIG. 4B, the process goes to step S33.
  • step S33 the second photoresist layer 100 is processed by a halftone mask process or a gray tone mask process to make the light of the region of the second photoresist layer 100 facing the third spacer region. Block removal. As shown in FIG. 4C, the process goes to step S34.
  • the semiconductor layer 1315 may be etched by a dry method or a wet method.
  • the PLASMARATMENT process may be performed using hydrogen gas or helium gas. As shown in FIG. 4D, the process goes to step S36.
  • step S36 when the second photoresist layer 100 on the channel semiconductor layer 13 is removed, a method of oxidizing the photoresist may be employed. As shown in FIG. 4E, the process goes to step S302.
  • step S302 when a second insulating layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulating layer of the base layer, it is made of silicon nitride and/or silicon dioxide, which is mainly used for the pixel electrode. Layer 30 and common electrode layer 15 are insulated.
  • the second insulating layer 20 has a thickness of 50 nm to 150 nm.
  • the first via hole 20a and the via hole 20b expose the channel semiconductor layer 13, respectively. As shown in FIG. 4F, the process goes to step S303.
  • the pixel electrode layer 30 is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer having a thickness of 10 nm to 100 nm.
  • the first metal layer 40 is formed by physical vapor deposition. As shown in FIG. 4G, the process goes to step S305.
  • step S305 the second photoresist layer is processed to remove the photoresist on the second photoresist layer and the third spacer region facing the region by using a halftone mask process or a gray mask process.
  • step S306 when the first metal layer 40 and the pixel electrode layer 30 are etched, wet etching may be employed to form the source 41 and the drain respectively in the source region and the drain region of the first metal layer 40.
  • the pole 42 forms a pixel electrode in the pixel electrode region of the pixel electrode layer 30.
  • step S307 when the first photoresist layer is removed, the first metal layer 40 on the pixel electrode may be removed by oxidizing and then removing the first photoresist layer.
  • the conventional techniques in the art may be used, and details are not described herein.
  • a structure as shown in FIG. 4H is formed, and the process proceeds to step S308.
  • the third insulating layer 50 is made of silicon nitride, which is a flat layer in the embodiment, and is mainly used to protect the pixel electrode, the source 41, and the drain 42. As shown in Figure 4I.
  • the channel semiconductor layer 13 is provided with two doped regions respectively corresponding to the first via hole 20a and the second via hole 20b, and the step S36 includes:
  • the impedance of the channel semiconductor layer can be reduced by this step.
  • the source electrode 41 and the drain electrode 42 are disposed on the pixel electrode layer 30, so that the source electrode 41, the drain electrode 42 and the pixel electrode can be simultaneously formed by a photomask during the fabrication process. Shorten the process and increase the efficiency of production efficiency.
  • the channel semiconductor layer 13 and the common electrode layer 15 in the same layer, it can be formed by a photomask and formed by doping the common electrode layer 15 in the common electrode region of the semiconductor layer, thereby further shortening Process flow and improved generation efficiency.

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Abstract

一种FFS模式的阵列基板及制作方法，该FFS模式的阵列基板包括玻璃基板（11），栅极（13）设置于该玻璃基板（11）上；第一绝缘层（14）；半导体层（1315），半导体层（1315）包括沟道区域（1A）以及公共电极区域（1B），在半导体层（1315）的沟道区域（1A）形成沟道半导体层（13），在半导体层（1315）的公共电极区域（1B）的半导体掺杂形成公共电极层（15）；第二绝缘层（20），该第二绝缘层（20）上形成有第一过孔（20a）及第二过孔（20b）。

Description

FFS模式的阵列基板及制作方法 技术领域
本发明涉及显示领域，特别是涉及一种FFS模式的阵列基板及制作方法。
 背景技术
有源矩阵驱动的LCD显示技术利用了液晶的双极性偏振特点，通过施加电场控制液晶分子的排列方向，实现对背光源光路行进方向的开关控制。根据对液晶分子施加电场方向的不同，可以将LCD显示模式分为TN系列模式, VA系列模式及IPS系列模式。VA系列模式指对液晶分子施加纵向电场，而IPS系列模式指对液晶分子施加横向电场。而在IPS系列模式中，对于施加横向电场的不同，又可分为IPS模式和FFS模式等。其中FFS显示模式的每一个像素单元含有上下两层电极，即像素电极和公共电极，且下层的公共电极采用开口区整面平铺的方式。FFS显示模式具有高透过率，广视角以及较低的色偏等优点，是一种广泛应用的LCD显示技术。
为了提高氧化物TFT 的稳定性，刻蚀阻挡层(ESL)结构的TFT结构被广泛采用，该结构可以有效降低外界环境因素与源漏电极的刻蚀损伤对背沟道的影响。然而，ESL结构的传统FFS显示模式阵列基板制造方法需要更多的光罩次数，增加了工艺的复杂性以及生产成本。
 技术问题
本发明的目的在于提供一种FFS模式的阵列基板及其制作方法；以解决现有技术中ESL结构的传统FFS显示模式阵列基板制造方法需要更多的光罩次数，增加了工艺的复杂性以及生产成本的技术问题。
 技术解决方案
本发明实施例提供一种FFS模式的阵列基板的制作方法，其特征在于，包括以下步骤：
在玻璃基板上形成栅极；
在玻璃基板以及栅极上依次沉积第一绝缘层以及半导体层，该半导体层设置有沟道区域、公共电极区域以及位于公共电极区域与沟道区域之间的第三间隔区域；
在该半导体层上涂布第二光阻层，将该第二光阻层上与所述第三间隔区域正对区域的光阻去除；
对所述半导体层进行刻蚀，以在半导体层的沟道区域形成所述沟道半导体层，在该半导体层的公共电极区域形成待掺杂半导体层；
去除待掺杂半导体层上的第二光阻层，并对该待掺杂半导体层进行掺杂以形成公共电极层；
去除该沟道半导体层上的第二光阻层；
在沟道半导体层、公共电极层以及第一绝缘层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔。
在本发明所述的FFS模式的阵列基板的制作方法中，还包括以下步骤：
在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
去除第一光阻层，并除去位于像素电极上的第一金属层；
在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层。
在本发明所述的FFS模式的阵列基板的制作方法中，所述沟道半导体层设置有两个分别与所述第一过孔以及第二过孔对应的掺杂区域，所述去除该沟道半导体层上的第二光阻层的步骤包括：
将所述沟道半导体层的两个掺杂区域上的第二光阻层去除，并对该两个掺杂区域进行掺杂，以将该沟道半导体层位于该两个掺杂区域的半导体转换为导体，然后去除所述沟道半导体层上剩余的第二光阻层。
在本发明所述的FFS模式的阵列基板的制作方法中，所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
在本发明所述的FFS模式的阵列基板的制作方法中，所述沟道半导体层包括铟镓锌氧化物。
在本发明所述的FFS模式的阵列基板的制作方法中，所述像素电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，所述像素电极层的厚度为10纳米至100纳米。
本发明还提供了一种FFS模式的阵列基板的制作方法，包括以下步骤：
在玻璃基板上形成栅极；
在玻璃基板以及栅极上依次沉积第一绝缘层以及半导体层，该半导体层设置有沟道区域、公共电极区域以及位于公共电极区域与沟道区域之间的第三间隔区域；
在该半导体层上涂布第二光阻层，将该第二光阻层上与所述第三间隔区域正对区域的光阻去除；
对所述半导体层进行刻蚀，以在半导体层的沟道区域形成所述沟道半导体层，在该半导体层的公共电极区域形成待掺杂半导体层；
去除待掺杂半导体层上的第二光阻层，并对该待掺杂半导体层进行掺杂以形成公共电极层；
去除该沟道半导体层上的第二光阻层；
在沟道半导体层、公共电极层以及第一绝缘层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔；
在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
去除第一光阻层，并除去位于像素电极上的第一金属层；
在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层；
所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
本发明还提供了一种FFS模式的阵列基板，包括：
玻璃基板，所述栅极设置于该玻璃基板上；
第一绝缘层，其设置于该玻璃基板以及栅极上；
半导体层，其设置于所述第一绝缘层上，所述半导体层包括沟道区域以及公共电极区域，在所述半导体层的沟道区域形成所述沟道半导体层，在所述半导体层的公共电极区域的半导体掺杂形成公共电极层；
第二绝缘层，其沉积于该沟道半导体层、公共电极层以及第一绝缘层上，该第二绝缘层上形成有将该沟道半导体层露出的第一过孔以及第二过孔。
在本发明所述的FFS模式的阵列基板中，还包括：
像素电极层，其沉积于所述第二绝缘层上，所述像素电极层上设置有像素电极；
源极以及漏极，该源极以及漏极设置于所述像素电极层之上；
第三绝缘层，其设置于源极、漏极、像素电极以及第二绝缘层上。
在本发明所述的FFS模式的阵列基板中，还包括：
所述沟道半导体层包括铟镓锌氧化物。
在本发明所述的FFS模式的阵列基板中，还包括：
所述像素电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，所述像素电极层的厚度为10纳米至100纳米。
本发明还提供了一种FFS模式的阵列基板，其特征在于，包括：
玻璃基板，所述栅极设置于该玻璃基板上；
第一绝缘层，其设置于该玻璃基板以及栅极上；
半导体层，其设置于所述第一绝缘层上，所述半导体层包括沟道区域以及公共电极区域，在所述半导体层的沟道区域形成所述沟道半导体层，在所述半导体层的公共电极区域的半导体掺杂形成公共电极层；
第二绝缘层，其沉积于该沟道半导体层、公共电极层以及第一绝缘层上，该第二绝缘层上形成有将该沟道半导体层露出的第一过孔以及第二过孔；
像素电极层，其沉积于所述第二绝缘层上，所述像素电极层上设置有像素电极；
源极以及漏极，该源极以及漏极设置于所述像素电极层之上；
第三绝缘层，其设置于源极、漏极、像素电极以及第二绝缘层上；
所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
 有益效果
本实施例中，通过将通过将该沟道半导体层以及公共电极层设置在同一层，可以通过一道光罩形成，并通过在该半导体层的公共电极区域掺杂形成该公共电极层，具有缩短工艺流程，提高生产效率的有益效果。
 附图说明
图1为本发明的FFS模式的阵列基板的一优选实施例的结构示意图；
图2为本发明的FFS模式的阵列基板的制作方法的一优选实施例中的流程图；
图3A-图3I为本发明FFS模式的阵列基板的制作方法的一优选实施例中的具体制作示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的FFS模式的阵列基板的优选实施例的结构示意图。本优选实施例的一种FFS模式的阵列基板，包括：玻璃基板11、栅极12、半导体层（图1中未标号）、第一绝缘层14、第二绝缘层20、像素电极层30、源极41、漏极42以及第三绝缘层50。其中，该玻璃基板11、栅极12、半导体层（图1中未标号）以及第一绝缘层14组成基层。
具体地，该栅极12设置于该玻璃基板11上。该第一绝缘层14设置于玻璃基板11以及栅极12上，该半导体层设置于该第一绝缘层14上。在本实施例中，该半导体层设置有沟道区域、公共电极区域以及位于该沟道区域和公共电极区域之间的第三间隔区域（未标号），该沟道区域形成薄膜晶体管的沟道半导体层13，该沟道半导体层13位于栅极12上方。该公共电极区域的半导体层通过掺杂形成公共电极层15，该第三间隔区域的半导体层通过光刻工艺除去。
该第二绝缘层20设置于该第一绝缘层14、公共电极层15以及沟道半导体层13之上。该第二绝缘层20上通过光刻形成有将该沟道半导体层13漏出的第一过孔以及第二过孔。该像素电极层30设置于该第二绝缘层20之上，该像素电极层30设置有位于薄膜晶体管区域的接触部30a以及位于该薄膜晶体管区域一侧的多个像素电极，该接触部30a通过该第一过孔以及第二过孔与沟道半导体层13接触。该源极41以及漏极42均设置于该像素电极层30的接触部30a上，并分别通过接触部30a与沟道半导体层13接触。该第三绝缘层50设置于第二绝缘层20、源极41、漏极42以及像素电极层30之上。
其中，该半导体层采用铟镓锌氧化物，也既是沟道半导体层13采用铟镓锌氧化物，当然其并不限于此。
该第一绝缘层14采用氮化硅和/或二氧化硅制成，其主要用于将栅极12与公共电极层15绝缘开。该第一绝缘层14的厚度为100纳米至300纳米。
该第二绝缘层20采用氮化硅和/或二氧化硅制成，其主要用于将该像素电极层30和公共电极层15绝缘开。该第二绝缘层20的厚度为50纳米至150纳米。
该第三绝缘层50采用氮化硅制成，在本实施例中其为平坦层，主要用于保护该像素电极、源极41、漏极42。
该像素电极层30为氧化铟锡透明电极层或氧化铟锌透明电极层，其厚度为10纳米至100纳米。
进一步地，在本实施例中，该沟道半导体层13上还设置有两个分别与第一过孔以及第二过孔对应的掺杂区域，在该沟道半导体层13的掺杂区域进行掺杂从而将该区域的半导体转换为导体，从而具有降低沟道半导体层13的阻抗的作用。
本实施例中，通过将源极41和漏极42设置在像素电极层30之上，从而使得在制作过程中，可以通过一道光罩同时形成该源极41、漏极42以及像素电极，具有缩短工艺流程，提高生产效率的有益效果。
进一步地，通过将该沟道半导体层13以及公共电极层15设置在同一层，可以通过一道光罩形成，并通过在该半导体层的公共电极区域掺杂形成该公共电极层15，进一步缩短了工艺流程，并提高了生成效率。
请参照图2，图2是本发明一优选实施例中的FFS模式的阵列基板的流程图，该方法包括以下步骤：
S301，形成一基层，该基层设置有栅极以及沟道半导体层；
S302，在基层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔；
S303，在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
S304，在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
S305，在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
S306，对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
S307，去除第一光阻层，并除去位于像素电极上的第一金属层；
S308，在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层。
下面结合图3A-图3I对各个步骤进行详细说明。
在步骤S301中，其具体包括以下子步骤：
S31，在玻璃基板上形成栅极；
S32，在玻璃基板以及栅极上依次沉积第一绝缘层以及半导体层，该半导体层设置有沟道区域、公共电极区域以及位于公共电极区域与沟道区域之间的第三间隔区域；
S33，在该半导体层上涂布第二光阻层，将该第二光阻层上与所述第三间隔区域正对区域的光阻去除；
S34，对所述半导体层进行刻蚀，以在半导体层的沟道区域形成所述沟道半导体层，在该半导体层的公共电极区域形成待掺杂半导体层；
S35，去除待掺杂半导体层上的第二光阻层，并对该待掺杂半导体层进行掺杂以形成公共电极层；
S36，去除该沟道半导体层上的第二光阻层；
其中，所述第二绝缘层沉积于该沟道半导体层、公共电极层以及第一绝缘层上。
在该步骤S31中，该栅极13的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，其采用物理气相沉积法沉积形成。如图4A所示，转至步骤S32。
在步骤S32中，该第一绝缘层14采用氮化硅和/或二氧化硅并采用化学气相沉积法沉积形成制成，其主要用于将栅极12与公共电极层15绝缘开。该第一绝缘层14的厚度为100纳米至300纳米。该半导体层1315采用铟镓锌氧化物并采用物理气相沉积法沉积形成。其上分为沟道区域1A、公共电极区域1B以及位于公共电极区域1B与沟道区域1A之间的第三间隔区域1C。如图4B所示，转至步骤S33。
在步骤S33中，采用半色调掩膜工艺或灰色调掩膜工艺，对该第二光阻层100进行处理，使得将该第二光阻层100上与第三间隔区域正对的区域的光阻去除。如图4C所示，转至步骤S34。
在步骤S34中，对该半导体层1315进行刻蚀时可以采用干法也可采用湿法。在步骤S35中，对该待掺杂半导体层进行掺杂以形成公共电极层15时，可以采用氢气或者氦气进行PLASMATREATMENT工艺。如图4D所示，转至步骤S36。
在步骤S36中，在去除该该沟道半导体层13上的第二光阻层100时，可以将光阻氧化的方法。如图4E所示，转至步骤S302。
在步骤S302中，在基层的沟道半导体层、公共电极层以及第一绝缘层上沉积第二绝缘层时，采用氮化硅和/或二氧化硅制成，其主要用于将该像素电极层30和公共电极层15绝缘开。该第二绝缘层20的厚度为50纳米至150纳米。该第一过孔20a以及过孔20b分别将沟道半导体层13露出。如图4F所示，转至步骤S303。
在步骤S303中，该像素电极层30为氧化铟锡透明电极层或氧化铟锌透明电极层，其厚度为10纳米至100纳米。在步骤S304中，该第一金属层40采用物理气相沉淀形成。如图4G所示，转至步骤S305。
在步骤S305中，采用半色调掩膜工艺或灰色调掩膜工艺，对该第二光阻层进行处理将该第二光阻层上与该第三间隔区域正对区域的光阻去除。
在步骤S306中，对第一金属层40和像素电极层30进行刻蚀时，可以采用湿法刻蚀，以在第一金属层40的源极区域和漏极区域分别形成源极41和漏极42，在像素电极层30的像素电极区域形成像素电极。
在步骤S307中，去除第一光阻层时可以采用将其氧化然后去除的方式，去除该像素电极上的第一金属层40时，可以采用本领域的常规技术，不赘述。去除该第一金属层后，形成如图4H所示的结构，转至步骤S308。
在步骤S308中，该第三绝缘层50采用氮化硅制成，在本实施例中其为平坦层，主要用于保护该像素电极、源极41、漏极42。如图4I所示。
进一步地，该沟道半导体层13设置有两个分别与第一过孔20a以及第二过孔20b对应的掺杂区域，该步骤S36包括：
将沟道半导体层的两个掺杂区域上的第二光阻层去除，并对该两个掺杂区域进行掺杂，以将该沟道半导体层位于该两个掺杂区域的半导体转换为导体，然后去除沟道半导体层上剩余的第二光阻层。通过该步骤可以减小沟道半导体层的阻抗。
本实施例中，通过将源极41和漏极42设置在像素电极层30之上，从而使得在制作过程中，可以通过一道光罩同时形成该源极41、漏极42以及像素电极，具有缩短工艺流程，提高生产效率的有益效果。
进一步地，通过将该沟道半导体层13以及公共电极层15设置在同一层，可以通过一道光罩形成，并通过在该半导体层的公共电极区域掺杂形成该公共电极层15，进一步缩短了工艺流程，并提高了生成效率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种FFS模式的阵列基板的制作方法，其特征在于，包括以下步骤：
    在玻璃基板上形成栅极；
    在玻璃基板以及栅极上依次沉积第一绝缘层以及半导体层，该半导体层设置有沟道区域、公共电极区域以及位于公共电极区域与沟道区域之间的第三间隔区域；
    在该半导体层上涂布第二光阻层，将该第二光阻层上与所述第三间隔区域正对区域的光阻去除；
    对所述半导体层进行刻蚀，以在半导体层的沟道区域形成所述沟道半导体层，在该半导体层的公共电极区域形成待掺杂半导体层；
    去除待掺杂半导体层上的第二光阻层，并对该待掺杂半导体层进行掺杂以形成公共电极层；
    去除该沟道半导体层上的第二光阻层；
    在沟道半导体层、公共电极层以及第一绝缘层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔。
  2. 根据权利要求1所述的FFS模式的阵列基板的制作方法，其特征在于，还包括以下步骤：
    在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
    在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
    在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
    对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
    去除第一光阻层，并除去位于像素电极上的第一金属层；
    在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层。
  3. 根据权利要求2所述的FFS模式的阵列基板的制作方法，其特征在于，所述沟道半导体层设置有两个分别与所述第一过孔以及第二过孔对应的掺杂区域，所述去除该沟道半导体层上的第二光阻层的步骤包括：
    将所述沟道半导体层的两个掺杂区域上的第二光阻层去除，并对该两个掺杂区域进行掺杂，以将该沟道半导体层位于该两个掺杂区域的半导体转换为导体，然后去除所述沟道半导体层上剩余的第二光阻层。
  4. 根据权利要求1所述的FFS模式的阵列基板的制作方法，其特征在于，所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
  5. 根据权利要求1所述的FFS模式的阵列基板的制作方法，其特征在于，所述沟道半导体层包括铟镓锌氧化物。
  6. 根据权利要求1所述的FFS模式的阵列基板的制作方法，其特征在于，所述像素电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，所述像素电极层的厚度为10纳米至100纳米。
  7. 一种FFS模式的阵列基板的制作方法，其特征在于，包括以下步骤：
    在玻璃基板上形成栅极；
    在玻璃基板以及栅极上依次沉积第一绝缘层以及半导体层，该半导体层设置有沟道区域、公共电极区域以及位于公共电极区域与沟道区域之间的第三间隔区域；
    在该半导体层上涂布第二光阻层，将该第二光阻层上与所述第三间隔区域正对区域的光阻去除；
    对所述半导体层进行刻蚀，以在半导体层的沟道区域形成所述沟道半导体层，在该半导体层的公共电极区域形成待掺杂半导体层；
    去除待掺杂半导体层上的第二光阻层，并对该待掺杂半导体层进行掺杂以形成公共电极层；
    去除该沟道半导体层上的第二光阻层；
    在沟道半导体层、公共电极层以及第一绝缘层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔；
    在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
    在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
    在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
    对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
    去除第一光阻层，并除去位于像素电极上的第一金属层；
    在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层；
    所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
  8. 一种FFS模式的阵列基板，其特征在于，包括：
    玻璃基板，所述栅极设置于该玻璃基板上；
    第一绝缘层，其设置于该玻璃基板以及栅极上；
    半导体层，其设置于所述第一绝缘层上，所述半导体层包括沟道区域以及公共电极区域，在所述半导体层的沟道区域形成所述沟道半导体层，在所述半导体层的公共电极区域的半导体掺杂形成公共电极层；
    第二绝缘层，其沉积于该沟道半导体层、公共电极层以及第一绝缘层上，该第二绝缘层上形成有将该沟道半导体层露出的第一过孔以及第二过孔。
  9. 根据权利要求8所述的FFS模式的阵列基板，其特征在于，还包括：
    像素电极层，其沉积于所述第二绝缘层上，所述像素电极层上设置有像素电极；
    源极以及漏极，该源极以及漏极设置于所述像素电极层之上；
    第三绝缘层，其设置于源极、漏极、像素电极以及第二绝缘层上。
  10. 根据权利要求8所述的FFS模式的阵列基板，其特征在于，其特征在于，所述沟道半导体层包括铟镓锌氧化物。
  11. 根据权利要求8所述的FFS模式的阵列基板，其特征在于，其特征在于，所述像素电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，所述像素电极层的厚度为10纳米至100纳米。
  12. 一种FFS模式的阵列基板，其特征在于，包括：
    玻璃基板，所述栅极设置于该玻璃基板上；
    第一绝缘层，其设置于该玻璃基板以及栅极上；
    半导体层，其设置于所述第一绝缘层上，所述半导体层包括沟道区域以及公共电极区域，在所述半导体层的沟道区域形成所述沟道半导体层，在所述半导体层的公共电极区域的半导体掺杂形成公共电极层；
    第二绝缘层，其沉积于该沟道半导体层、公共电极层以及第一绝缘层上，该第二绝缘层上形成有将该沟道半导体层露出的第一过孔以及第二过孔；
    像素电极层，其沉积于所述第二绝缘层上，所述像素电极层上设置有像素电极；
    源极以及漏极，该源极以及漏极设置于所述像素电极层之上；
    第三绝缘层，其设置于源极、漏极、像素电极以及第二绝缘层上；
    所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
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