CN104882485A - 薄膜晶体管及其制造方法 - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 38
- 239000012212 insulator Substances 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 135
- 239000011229 interlayer Substances 0.000 abstract description 6
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 10
- 239000011651 chromium Substances 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052779 Neodymium Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 229910001092 metal group alloy Inorganic materials 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明涉及一种薄膜晶体管,包括:基板;半导体层,该半导体层包括沟道区,设置在该沟道区两侧的轻掺杂漏极区及设置在该轻掺杂漏极区外侧的重掺杂区;依次层叠设置在该沟道区上的第一间介电层及第二间介电层;贯穿该第一间介电层与该第二间介电层的连接孔,且该连接孔位于该第一间介电层的侧壁相对于该基板倾斜设置形成倾斜部。本案还涉及一种薄膜晶体管的制造方法。
Description
技术领域
本发明涉及一种薄膜晶体管及其制造方法。
背景技术
薄膜晶体管(Thin Film Transistor,TFT)已被广泛应用于显示领域作为开关组件使用。薄膜晶体管具有连接源极与漏极的沟道层,该沟道层采用非晶硅(a-Si)、低温多晶硅(Low Temperature Poly-Silicon,LTPS)或金属氧化物制成。而具有轻掺杂漏极(Lightly Doped Drain, LDD)结构的薄膜晶体管因可在偏压时降低漏极附近空乏层中电子和电洞的生成速率而进一步降低漏电流而得到广泛使用。然在植入离子形成LDD结构的过程中需要单独光罩制程,从而使制程复杂并增加制造成本。
发明内容
有鉴于此,有必要提供一种可减少薄膜晶体管制程的薄膜晶体管及其制造方法。
一种薄膜晶体管,包括:
基板;
半导体层,该半导体层包括沟道区,设置在该沟道区两侧的轻掺杂漏极区及设置在该轻掺杂漏极区外侧的重掺杂区;
依次层叠设置在该沟道区上的第一间介电层及第二间介电层;
贯穿该第一间介电层与该第二间介电层的连接孔,且该连接孔位于该第一间介电层的侧壁相对于该基板倾斜设置形成倾斜部。
优选的,该连接孔包括电性连接源极、漏极及半导体层的第一连接孔与第二连接孔,该源极填充该第一连接孔,该漏极填充该第二连接孔。
优选的,该第一连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置;该第二连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置。
优选的,该第一、第二连接孔的第一连接部在该基板上的投影长度大于该重掺杂区的长度且小于该第一重掺杂区与该第一轻掺杂漏极区长度之和。
优选的,该第一间介电层与第二间介电层的材料不同具有不同的蚀刻速率。
优选的,该轻掺杂漏极区与该重掺杂区经该倾斜部阻挡在在同一离子植入制程中形成。
一种薄膜晶体管的制造方法,包括:
形成沟道层;
形成覆盖该沟道层的第一介电层与第二介电层;
蚀刻该第一间介电层与该第二间介电层形成连接孔,且该连接孔位于该第一间介电层的侧壁与该沟道层倾斜形成倾斜部;
进行离子植入制程,以该倾斜部做阻挡形成轻掺杂区及设置在该轻掺杂区两侧的重掺杂区。
优选的,该连接孔包括电性连接源极、漏极及半导体层的第一连接孔与第二连接孔,该源极填充该第一连接孔,该漏极填充该第二连接孔;该第一连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置;该第二连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置。
优选的,该第一间介电层与第二间介电层的材料不同具有不同的蚀刻速率。
优选的,该轻掺杂漏极区与该重掺杂区经该倾斜部阻挡在在同一离子植入制程中形成。
相较于先前技术,本发明的薄膜晶体管及其制造方法在形成连接孔后再进行离子植入制程且以连接孔的倾斜部做阻挡在同一离子植入制程中形成轻掺杂漏极区与重掺杂区,从而使轻掺杂漏极区与重掺杂区在同一制程中形成以减少制程降低制造成本。
附图说明
图1是本发明第一实施方式的薄膜晶体管平面结构示意图。
图2是图1所示的薄膜晶体管沿II-II线的剖面结构示意图。
图3-图8是图1所示薄膜晶体管制造流程示意图。
图9是本发明第二实施方式的薄膜晶体管平面结构示意图。
图10是图9所示的薄膜晶体管沿X-X线的剖面结构示意图。
图11-图18是图10所示薄膜晶体管制造流程示意图。
主要元件符号说明
薄膜晶体管 | 10、20 |
基板 | 110、210 |
缓冲层 | 120 |
半导体层 | 130、250 |
栅极绝缘层 | 140、240 |
栅极 | 150、230 |
第一间介电层 | 160、260 |
第二间介电层 | 170、270 |
第一连接孔 | 180、280 |
第一连接部 | 1801、1821、2801、2821 |
第二连接部 | 1802、1822、2802、2822 |
第二连接孔 | 182、282 |
倾斜部 | 181、183、281、283 |
源极 | 190、290 |
漏极 | 192、292 |
未掺杂部 | 132、252 |
第一轻掺杂漏极区 | 133、253 |
第二轻掺杂漏极区 | 134、254 |
第一重掺杂区 | 135、255 |
第二重掺杂区 | 136、256 |
通孔 | H1、H2、H11、H22 |
光阻层 | 172 |
步骤 | S201~S211、S401~S411 |
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请一并参阅图1、图2,图1是本发明第一实施方式薄膜晶体管组件的平面结构示意图;图2是图1所示的薄膜晶体管组件沿II-II线的剖面结构示意图。该薄膜晶体管结构可应用于P型薄膜晶体管、N型薄膜晶体管及互补型金属薄膜晶体管(Complementary Metal Oxide Semiconductor, CMOS),且可应用于像素区域或外围驱动电路区域。在本实施方式中以N型顶栅型薄膜晶体管为例进行说明。
该薄膜晶体管10包括基板110、依次层叠设置在该基板110上的缓冲层120、半导体层130、栅极绝缘层140、栅极150、第一间介电层(inter layer dielectric,ILD)160、第二间介电层(ILD)170、源极190及漏极192。
该薄膜晶体管10还包括用于电性连接源极190、漏极192及半导体层130的第一连接孔180与第二连接孔182。第一连接孔180与第二连接孔182贯穿该栅极绝缘层140、第一间介电层160、第二间介电层170。该第一连接孔180与第二连接孔182位于该栅极绝缘层140及该第一间介电层160的侧壁与该基板110倾斜形成倾斜部181、183。源极290填充该第一连接孔180,漏极192填充该第二连接孔182。
在本实施方式中,该基板110可为玻璃基板或者石英基板,该第一金属层150、第二金属层190可为金属材料或金属合金,如钼(Mo)、铝(Al)、铬(Cr)、铜(Cu)、钕(Nd)等。该栅极绝缘层140为可以包括氮化硅(SiNx)或氧化硅(SiOx)。该第一间介电层160为氧化物材料、第二间介电层170为氮化物材料。该第一间介电层160与该第二间介电层170具有不同的蚀刻速率。该半导体层130为多晶硅(Poly-Si)层。
该半导体层130包括位于中部的沟道区132,设置该沟道区132两侧的第一轻掺杂漏极区(Lightly Doped Drain, LDD)133与第二轻掺杂漏极区134、设置该第一、第二轻掺杂漏极区133、134外侧的第一重掺杂区135、第二重掺杂区136。该第一重掺杂区135为源极区、该第二重掺杂区136为漏极区。该第一重掺杂区135用于连接源极190,该第二重掺杂区136用于连接漏极192。
请一并参阅图6,该第一连接孔180包括贯穿该第二间介电层170的第一连接部1801及贯穿该第一间介电层160与该栅极绝缘层140的第二连接部1802。该第一连接部1801的侧壁与该基板110垂直,该第二连接部1802的侧壁与该基板110倾斜设置。该第一连接部1801在该基板110上的投影大于该第一重掺杂区135且小于该第一重掺杂区135与该第一轻掺杂漏极区133之和。该第二连接部1802的底部设置在该第一重掺杂区135上。该第二连接孔182包括贯穿该第二间介电层170的第一连接部1821及贯穿该第一间介电层160与该栅极绝缘层140的第二连接部1822。该第一连接部182的侧壁与该基板110垂直,该第二连接部1822的侧壁与该基板110倾斜设置。该第一连接部1821在该基板110上的投影长度大于该第一重掺杂区135且小于该第一重掺杂区135与该第一轻掺杂漏极区133之和。该第二连接部1822的底部设置在该第一重掺杂区135上。
请一并参阅图3-图9,其中图3-图8为图1所示的薄膜晶体管10各制作步骤结构示意图。图9是图1所示薄膜晶体管10的制造流程图。
步骤S201,请参阅图3,提供一基板110,于基板110上沉积缓冲层120,及在该缓冲层120上形成半导体层130。在本实施方式中,该半导体层的制作方法可采用低温多晶硅(Low Temperature Poly-Silicon, LTPS)制程,先于基板上形成一非晶层(a-Si)层,然后利用热处理或准分子镭射退火(Excimer Laser Annealing, ELA)的方式 将非晶硅转换为多晶硅材质。
步骤S203,请参阅图4,在该半导体层130沉积栅极绝缘层140,并在该栅极绝缘层140上沉积第一金属层,图案化该第一金属层形成栅极150,并在该栅极150上依次沉积第一间介电层160与第二间介电层170。
步骤S205,请参阅图5,在该第二间介电层170上涂布光阻层172,并利用黄光制程图案化该光阻层172从而在该光阻层172上定义出通孔H1、H2。该通孔H1、H2为贯穿该光阻层172设置。
步骤S207,请参阅图6,以该图案化光阻层172作屏蔽蚀刻该第二间介电层170、第一间介电层160与该栅极绝缘层140,形成沿厚度方向贯穿该第一间介电层160、第二间介电层170及该栅极绝缘层140的第一连接孔180与第二连接孔182。该第一连接孔180包括贯穿该第二间介电层170的第一连接部1801及贯穿该第一间介电层160与该栅极绝缘层140的第二连接部1802。该第一连接部1801的侧壁与该基板110垂直,该第二连接部1802的侧壁与该基板110倾斜设置形成倾斜部181。该第二连接孔182包括贯穿该第二间介电层170的第一连接部1821及贯穿该第一间介电层160与该栅极绝缘层140的第二连接部1822。该第一连接部1821的侧壁与该基板110垂直,该第二连接部1822的侧壁与该基板110倾斜设置形成倾斜部183。该倾斜部181、183由于该第一间介电层160与第二间介电层170由不同材料制成而形成。在本实施方式中,可利用电浆蚀刻(Plasma Etching)、反应离子蚀刻(Reactive Ion Etching,RIE)、等离子蚀刻等蚀刻方法。
步骤S209,请参阅图7,进行一离子植入制程,利用通孔H1、H2及图案化光阻层172做掩膜,,于该半导体层130形成一未掺杂的沟道区132、及位于该沟道区132两侧的第一轻掺杂漏极区(LDD)133与第二轻掺杂漏极区134、位于该第一、第二轻掺杂漏极区133、134外侧的第一重掺杂区135、第二重掺杂区136。在本实施方式中,该第一、第二轻掺杂漏极区133、134为N-掺杂区,该第一、第二重掺杂区135、136为N+掺杂区。在其他实施方式中,该薄膜晶体管10为P型,则该第一、第二轻掺杂漏极区133、134为P-掺杂区,该第一、第二重掺杂区135、136为P+掺杂区。在本实施方式中,该第一、第二轻掺杂漏极区133、134的掺杂浓度为1x1012~1x1014atom/cm2,该第一重掺杂区135、第二重掺杂区136的掺杂浓度为1x1014~1x1016atom/cm2。该第一连接部1821在该基板110上的投影大于该第一重掺杂区135且小于该第一重掺杂区135与该第一轻掺杂漏极区133之和。该第二连接部1822的底部设置在该第一重掺杂区135上。
步骤S211,请参阅图8,移除剩余光阻层172,在第一连接孔180上形成源极190、第二连接孔182上形成漏极192,源极190与漏极192分别填充该第一连接孔182、第二连接孔184。该源极190、漏极192为金属材料或金属合金,如钼(Mo)、铝(Al)、铬(Cr)、铜(Cu)、钕(Nd)等。
请一并参阅图10、图11,图10是本发明第二实施方式薄膜晶体管组件的平面结构示意图;图11是图10所示的薄膜晶体管组件沿II-II线的剖面结构示意图。该薄膜晶体管结构可应用于P型薄膜晶体管、N型薄膜晶体管及互补型金属薄膜晶体管(Complementary Metal Oxide Semiconductor, CMOS),且可应用于像素区域或外围驱动电路区域。在本实施方式中以N型底栅型薄膜晶体管为例进行说明。
该薄膜晶体管20包括基板210、依次层叠设置在该基板210上的栅极230、栅极绝缘层240、半导体层250、第一间介电层(ILD)260、第二间介电层(ILD)270、源极290及漏极292。
该薄膜晶体管20还包括用于电性连接源极290、漏极292及半导体层250的第一连接孔280与第二连接孔282。该第一连接孔280与该第二连接孔282贯穿该第一间介电层260、第二间介电层270。该第一连接孔280与第二连接孔282位于该第一间介电层260的侧壁与该基板210倾斜形成倾斜部281、283。该源极290填充该第一连接孔280,该漏极292填充该第二连接孔282。
在本实施方式中,该基板210可为玻璃基板或者石英基板,该栅极230、源极290与漏极292可为金属材料或金属合金,如钼(Mo)、铝(Al)、铬(Cr)、铜(Cu)、钕(Nd)等。该栅极绝缘层240为可以包括氮化硅(SiNx)或氧化硅(SiOx)。该第一间介电层260为氧化物材料、第二间介电层270为氮化物材料。该第一间介电支260与该第二间介电层270具有不同的蚀刻速率。该半导体层250为多晶硅(Poly-Si)层。
该半导体层250包括位于中部的未掺杂部252为该薄膜晶体管20的沟道层,设置该未掺杂部252两侧的第一轻掺杂漏极区(LDD)253与第二轻掺杂漏极区254、设置该第一、第二轻掺杂漏极区253、254外侧的第一重掺杂区255、第二重掺杂区256。该第一重掺杂区255为源极区、该第二重掺杂区256为漏极区。
请一并参阅图15,该第一连接孔280包括贯穿该第二间介电层270的第一连接部2801及贯穿该第一间介电层260的第二连接部2802。该第一连接部2801的侧壁与该基板210垂直,该第二连接部2802的侧壁与该基板210倾斜设置形成该倾斜部281。该第一连接部2801在该基板210上的投影长度大于该第一重掺杂区235且小于该第一重掺杂区235与该第一轻掺杂漏极区233之和。该第二连接部2802的底部设置在该第一重掺杂区235上。该第二连接孔282包括贯穿该第二间介电层270的第一连接部2821及贯穿该第一间介电层260的第二连接部2822。该第一连接部2821的侧壁与该基板210垂直,该第二连接部2822的侧壁与该基板210倾斜设置形成倾斜部283。该第一连接部2821在该基板210上的投影长度大于该第一重掺杂区255且小于该第一重掺杂区255与该第一轻掺杂漏极区253之和。该第二连接部2822的底部设置在该第一重掺杂区255上。
请一并参阅图12-图18,其中图12-图17为图10所示的薄膜晶体管20各制作步骤结构示意图。图18是图10所示薄膜晶体管20的制造流程图。
步骤S401,请参阅图12,提供一基板210,于基板210上沉积第一金属层,图案化第一金属层形成栅极230,并在该栅极上沉积栅极绝缘层240。
步骤S403,请参阅图13,在该栅极绝缘层240对应该栅极位置形成半导体层250,并在该半导体层250上依次沉积第一间介电层260与第二间介电层270。在本实施方式中,该半导体层的制作方法可采用低温多晶硅(Low Temperature Poly-Silicon, LTPS)制程,先于基板上形成一非晶层(a-Si)层,然后利用热处理或准分子镭射退火(Excimer Laser Annealing, ELA)的方式将非晶硅转换为多晶硅材质。
步骤S405,请参阅图14,在该第二间介电层270上涂布光阻层272,并利用黄光制程图案化该光阻层272从而在该光阻层272上定义出通孔H11、H22。该通孔H11、H22为贯穿该光阻层272设置。
步骤S407,请参阅图15,以该图案化光阻层272作屏蔽蚀刻该第二间介电层270、第一间介电层260,形成沿厚度方向贯穿该第一间介电层260与第二间介电层270的第一连接孔280与第二连接孔282。该第一连接孔280包括贯穿该第二间介电层170的第一连接部2801及贯穿该第一间介电层260的第二连接部1802。该第一连接部2801的侧壁与该基板210垂直,该第二连接部2802的侧壁与该基板210倾斜设置形成倾斜部281。该第二连接孔282包括贯穿该第二间介电层270的第一连接部2821及贯穿该第一间介电层260的第二连接部2822。该第一连接部2821的侧壁与该基板210垂直,该第二连接部2822的侧壁与该基板210倾斜设置形成倾斜部183。由于该第一间介电层260与第二间介电层270由不同材料制成而具有不同的蚀刻速率,从而该第一连接孔280与第二连接孔282位于该第一间介电层260的侧壁与该基板210倾斜形成倾斜部281、283。在本实施方式中,可利用电浆蚀刻(Plasma Etching)、反应离子蚀刻(Reactive Ion Etching,RIE)、等离子蚀刻等蚀刻方法。
步骤S409,请参阅图16,进行一离子植入制程,利用该倾斜部281、283作屏蔽,于该半导体层250形成一未掺杂部252、及位于该未掺杂部252两侧的第一轻掺杂漏极区(LDD)253与第二轻掺杂漏极区254、位于该第一、第二轻掺杂漏极区253、254外侧的第一重掺杂区255、第二重掺杂区256。在本实施方式中,该第一、第二轻掺杂漏极区253、254为N-掺杂区,该第一、第二重掺杂区255、256为N+掺杂区。在其他实施方式中,该薄膜晶体管20为P型,则该第一、第二轻掺杂漏极区253、254为P-掺杂区,该第一、第二重掺杂区255、256为P+掺杂区。在本实施方式中,该第一、第二轻掺杂漏极区253、254的掺杂浓度为1x1012~1x1014atom/cm2,该第一重掺杂区255、第二重掺杂区256的掺杂浓度为1x1014~1x1016atom/cm2。
步骤S411,请参阅图17,移除剩余光阻层272,填充该第一连接孔282、第二连接孔284形成源极290与漏极292。该源极290、漏极292为金属材料或金属合金,如钼(Mo)、铝(Al)、铬(Cr)、铜(Cu)、钕(Nd)等。
该薄膜晶体管及其制造方法在蚀刻形成连接孔后再进行离子植入制程且以连接孔的倾斜部做阻挡在同一离子植入制程中形成轻掺杂漏极区与重掺杂区,从而使轻掺杂漏极区与重掺杂区在同一制程中形成以减少制程降低制造成本。
以上实施例仅用以说明本发明的技术方案而非限制,尽管参照较佳实施例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或等同替换,而不脱离本发明技术方案的精神和范围。
Claims (10)
1.一种薄膜晶体管,包括:
基板;
半导体层,该半导体层包括沟道区,设置在该沟道区两侧的轻掺杂漏极区及设置在该轻掺杂漏极区外侧的重掺杂区;
依次层叠设置在该沟道区上的第一间介电层及第二间介电层;
贯穿该第一间介电层与该第二间介电层的连接孔,且该连接孔位于该第一间介电层的侧壁相对于该基板倾斜设置形成倾斜部。
2.如权利要求1所述的薄膜晶体管,其特征在于,该连接孔包括电性连接源极、漏极及半导体层的第一连接孔与第二连接孔,该源极填充该第一连接孔,该漏极填充该第二连接孔。
3.如权利要求2所述的薄膜晶体管,其特征在于,该第一连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置;该第二连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置。
4.如权利要求3所述的薄膜晶体管,其特征在于,该第一、第二连接孔的第一连接部在该基板上的投影长度大于该重掺杂区的长度且小于该第一重掺杂区与该第一轻掺杂漏极区长度之和。
5.如权利要求1所述的薄膜晶体管,其特征在于,该第一间介电层与第二间介电层的材料不同具有不同的蚀刻速率。
6.如权利要求1-5任意一项所述的薄膜晶体管,其特征在于,该轻掺杂漏极区与该重掺杂区经该倾斜部阻挡在在同一离子植入制程中形成。
7.一种薄膜晶体管的制造方法,包括:
形成沟道区;
形成覆盖该沟道区的第一介电层与第二介电层;
蚀刻该第一间介电层与该第二间介电层形成连接孔,且该连接孔位于该第一间介电层的侧壁与该沟道层倾斜形成倾斜部;
进行离子植入制程,以该倾斜部做阻挡形成轻掺杂区及设置在该轻掺杂区两侧的重掺杂区。
8.如权利要求7所述的薄膜晶体管制造方法,其特征在于,该连接孔包括电性连接源极、漏极及半导体层的第一连接孔与第二连接孔,该源极填充该第一连接孔,该漏极填充该第二连接孔;该第一连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置;该第二连接孔包括贯穿该第二间介电层的第一连接部及贯穿该第一间介电层与该栅极绝缘层的第二连接部,该第一连接部的侧壁与该基板垂直,该第二连接部的侧壁与该基板倾斜设置。
9.如权利要求8所述的薄膜晶体管制造方法,其特征在于,该第一间介电层与第二间介电层的材料不同具有不同的蚀刻速率。
10.如权利要求7-9任意一项所述的薄膜晶体管制造方法,其特征在于,该轻掺杂漏极区与该重掺杂区经该倾斜部阻挡在在同一离子植入制程中形成。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017020358A1 (zh) * | 2015-08-04 | 2017-02-09 | 深圳市华星光电技术有限公司 | 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管 |
WO2017054258A1 (zh) * | 2015-09-30 | 2017-04-06 | 深圳市华星光电技术有限公司 | Tft阵列基板的制备方法、tft阵列基板及显示装置 |
EP3261125A1 (en) * | 2016-06-23 | 2017-12-27 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
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Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105097827A (zh) * | 2015-06-08 | 2015-11-25 | 深圳市华星光电技术有限公司 | Ltps阵列基板及其制造方法 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004172623A (ja) * | 2003-11-17 | 2004-06-17 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
CN1553751A (zh) * | 2003-09-30 | 2004-12-08 | �Ѵ���ɷ�����˾ | 电激发光显示装置 |
US20050272186A1 (en) * | 2004-06-08 | 2005-12-08 | Te-Ming Chu | Method for forming a lightly doped drain in a thin film transistor |
US20050287722A1 (en) * | 1995-11-19 | 2005-12-29 | Semiconductor Energy Laboratory Co., Ltd., A Japan Corporation | Method of fabricating semiconductor device |
US7064021B2 (en) * | 2003-07-02 | 2006-06-20 | Au Optronics Corp. | Method for fomring a self-aligned LTPS TFT |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10340909A (ja) * | 1997-06-06 | 1998-12-22 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
TWI348767B (en) | 2007-12-07 | 2011-09-11 | Chimei Innolux Corp | Thin film transistor and manufacture method thereof |
-
2015
- 2015-03-30 CN CN201510143210.0A patent/CN104882485A/zh active Pending
- 2015-04-08 TW TW104111218A patent/TWI604529B/zh active
- 2015-05-21 US US14/718,951 patent/US9653607B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050287722A1 (en) * | 1995-11-19 | 2005-12-29 | Semiconductor Energy Laboratory Co., Ltd., A Japan Corporation | Method of fabricating semiconductor device |
US7064021B2 (en) * | 2003-07-02 | 2006-06-20 | Au Optronics Corp. | Method for fomring a self-aligned LTPS TFT |
CN1553751A (zh) * | 2003-09-30 | 2004-12-08 | �Ѵ���ɷ�����˾ | 电激发光显示装置 |
JP2004172623A (ja) * | 2003-11-17 | 2004-06-17 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
US20050272186A1 (en) * | 2004-06-08 | 2005-12-08 | Te-Ming Chu | Method for forming a lightly doped drain in a thin film transistor |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017020358A1 (zh) * | 2015-08-04 | 2017-02-09 | 深圳市华星光电技术有限公司 | 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管 |
WO2017054258A1 (zh) * | 2015-09-30 | 2017-04-06 | 深圳市华星光电技术有限公司 | Tft阵列基板的制备方法、tft阵列基板及显示装置 |
EP3261125A1 (en) * | 2016-06-23 | 2017-12-27 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
US10217771B2 (en) | 2016-06-23 | 2019-02-26 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
US10396101B2 (en) | 2016-06-23 | 2019-08-27 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
WO2019071751A1 (zh) * | 2017-10-09 | 2019-04-18 | 深圳市华星光电半导体显示技术有限公司 | Tft基板及其制作方法与oled面板的制作方法 |
US10497620B2 (en) | 2017-10-09 | 2019-12-03 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | TFT substrate and manufacturing method thereof and manufacturing method of OLED panel |
CN107946196A (zh) * | 2017-11-28 | 2018-04-20 | 合肥鑫晟光电科技有限公司 | 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置 |
CN108807422A (zh) * | 2018-06-12 | 2018-11-13 | 武汉华星光电技术有限公司 | 阵列基板制作方法及阵列基板、显示面板 |
CN110767676A (zh) * | 2018-08-06 | 2020-02-07 | 昆山国显光电有限公司 | 透明显示面板、显示屏和显示终端 |
CN110767676B (zh) * | 2018-08-06 | 2022-04-15 | 昆山国显光电有限公司 | 透明显示面板、显示屏和显示终端 |
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