CN105097827A - Ltps阵列基板及其制造方法 - Google Patents
Ltps阵列基板及其制造方法 Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66742—Thin film unipolar transistors
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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Abstract
本发明提供一种LTPS阵列基板及其制造方法。该方法包括:在基体上形成薄膜晶体管的栅极;在包括栅极的基体上依次形成第一绝缘层、半导体层和正性光阻层;自基体背向栅极的一侧进行曝光以形成多晶硅层;在包括多晶硅层的基板上形成具有接触孔的第二绝缘层;在第二绝缘层上形成薄膜晶体管的源极和漏极,使得源极和漏极可通过接触孔与多晶硅层电连接。本发明能够减少LTPS工艺所使用的光罩的类型及数量,简化制程并降低生产成本。
Description
技术领域
本发明涉及显示技术领域,具体涉及一种LTPS(LowTemperaturePoly-silicon,低温多晶硅)阵列基板及其制造方法。
背景技术
采用LTPS工艺的液晶显示装置由于具有较高的电子迁移率,能够有效减小TFT(ThinFilmTransistor,薄膜晶体管)的面积以提升像素的开口率,并且在增强显示亮度的同时能够降低功耗及生产成本,目前已成为液晶显示领域的研究热点。但是LTPS工艺复杂,制备阵列基板(Array基板)所需的光罩(Mask)的类型及数量较多,导致制造流程繁多,无法降低生产成本。因此如何减少LTPS工艺所使用的光罩的类型及数量,实为目前企业需要努力的目标。
发明内容
鉴于此,本发明实施例提供一种LTPS阵列基板及其制造方法,能够减少LTPS工艺所使用的光罩的类型及数量。
本发明一实施例提供一种LTPS阵列基板的制造方法,包括:在基体上形成LTPS阵列基板的薄膜晶体管的栅极;在包括栅极的基体上依次形成第一绝缘层、半导体层和正性光阻层,其中第一绝缘层的上表面为一平面;自基体背向栅极的一侧进行曝光以形成多晶硅层;在包括多晶硅层的基板上形成第二绝缘层,并在第二绝缘层内形成暴露多晶硅层的两端的第一接触孔;在第二绝缘层上形成薄膜晶体管的源极和漏极,使得源极和漏极可通过第一接触孔与多晶硅层电连接。
其中,在包括栅极的基体上形成第一绝缘层之前,还在未被栅极覆盖的基体上形成缓冲层,且其上表面和栅极的上表面构成一平面。
其中,在未被栅极覆盖的基体上形成缓冲层的步骤包括:在包括栅极的基体上依次形成缓冲层、负性光阻层;自基体背向栅极的一侧进行曝光,以除去位于栅极正上方的负性光阻层;除去位于栅极正上方的缓冲层,且保留未被栅极覆盖的基体上的缓冲层。
其中,自基体背向栅极的一侧进行曝光以形成多晶硅层的步骤包括:自基体背向栅极的一侧进行曝光,以仅在对应于栅极的正上方的第一区域保留正性光阻层;向除第一区域之外的半导体层注入第一杂质离子;自基体背向栅极的一侧进行曝光,以在栅极的正上方形成第二区域的正性光阻层,第二区域小于第一区域;向除第二区域之外的半导体层注入第二杂质离子;除去第二区域的正性光阻层。
其中,第一杂质离子和第二杂质离子分别为N+、N-型杂质离子。
其中,自基体背向栅极的一侧进行曝光以形成多晶硅层的步骤包括:自基体背向栅极的一侧进行曝光,以仅在对应于栅极的正上方的第一区域保留正性光阻层;向除第一区域之外的半导体层注入P型杂质离子;自基体背向栅极的一侧进行曝光,以在栅极的正上方形成第二区域的正性光阻层,第二区域小于第一区域;
除去所述第二区域的所述正性光阻层。
其中,在第二绝缘层上形成源极和漏极之后,在由源极和漏极组成的源漏电极层上形成平坦钝化层,并在平坦钝化层内形成第二接触孔以暴露漏极的表面;在平坦钝化层上且第二接触孔远离薄膜晶体管的一侧形成LTPS阵列基板的公共电极层;在平坦钝化层和公共电极层上形成第三绝缘层,第三绝缘层未覆盖第二接触孔;在平坦钝化层上形成像素电极,并且像素电极可通过第二接触孔与漏极电连接。
本发明另一实施例提供一种LTPS阵列基板,包括:基体;栅极,位于基体上;依次形成于包括栅极的基体上的第一绝缘层、多晶硅层、第二绝缘层,第二绝缘层内形成有第一接触孔;源极和漏极,位于第二绝缘层上,且源极和漏极可通过第一接触孔与多晶硅层电连接;平坦钝化层,位于由源极和漏极组成的源漏电极层上,平坦钝化层内形成有暴露漏极的表面的第二接触孔;第三绝缘层,位于平坦钝化层上且未覆盖第二接触孔;像素电极,位于平坦钝化层上且像素电极可通过第二接触孔与漏极电连接。
其中,LTPS阵列基板还包括缓冲层,缓冲层位于未被栅极覆盖的基体上,且缓冲层的上表面和栅极的上表面构成一平面。
其中,LTPS阵列基板还包括公共电极层,公共电极层位于平坦钝化层上的第二接触孔远离薄膜晶体管的一侧。
本发明实施例的LTPS阵列基板及其制造方法,自基体背向栅极的一侧进行曝光,即利用不透光的栅极进行曝光以形成多晶硅层,在多晶硅层的制程中无需使用光罩,从而能够减少LTPS工艺所使用的光罩的类型及数量,简化制程并降低生产成本。
附图说明
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图;
图2是本发明的制造方法中形成栅极的示意图;
图3是本发明的制造方法中形成第一绝缘层、半导体层和正性光阻层的示意图;
图4是本发明的制造方法中形成多晶硅层的示意图;
图5是本发明的制造方法中形成第二绝缘层的示意图;
图6是本发明的制造方法中形成源极和漏极的示意图;
图7是本发明的制造方法中形成像素电极的的示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图。如图1所示,本实施例的制造方法包括以下步骤:
步骤11:在基体上形成LTPS阵列基板的薄膜晶体管的栅极。
如图2所示,基体21用于形成液晶显示面板的LTPS阵列基板,所述基体21可为玻璃基体、塑料基体或可挠式基体。
本实施例可以利用第一光罩对形成于基体21上的第一金属层进行曝光,并在曝光后进行显影、刻蚀等图案化制程以得到形成栅极22,其中可利用包含有磷酸、硝酸、醋酸以及去离子水的蚀刻液对第一金属层12进行蚀刻,当然也可以采用干法蚀刻。
当然,本实施例还可以通过其他方式得到栅极22,例如采用化学气相沉积(Chemicalvapordeposition,CVD)、等离子化学气相沉积(PlasmaEnhancedChemicalvapordeposition,PECVD)、溅射、真空蒸镀或低压化学气相沉积等方法直接在基体21上形成具有预定图案的栅极22。其中,第一金属层可由金属,例如铝、钼、钛、铬、铜,或金属氧化物,例如氧化钛,或金属的合金或其它导电材料构成。
步骤12:在包括栅极的基体上依次形成第一绝缘层、半导体层和正性光阻层,其中第一绝缘层的上表面为一平面。
结合图3所示,在形成第一绝缘层25、半导体层26和正性光阻层27之前,本实施例需要在未被栅极22覆盖的基体21上形成缓冲层(Bufferlayer)23,具体过程包括但不限于:
首先,在包括栅极22的基体21上依次形成缓冲层23、负性光阻层24。缓冲层23可以为氮化硅(SiNx)层、氧化硅(SiOx)层或者其他非导电材料的组合,缓冲层23可用于防止基体21内的杂质在后续工艺中向上扩散而影响之后形成的低温多晶硅层的品质,氮化硅层和氧化硅层可以采用化学气相沉积、等离子化学气相沉积形成、溅射、真空蒸镀或低压化学气相沉积等方法形成,但不限于此。
然后,自基体21背向栅极22的一侧进行曝光,位于栅极22正上方的负性光阻层24由于受到栅极22的遮挡而未曝光,因此可在显影时被灰化去除。
最后,剥离除去剩余的负性光阻层24,再通过刻蚀除去位于栅极22正上方的缓冲层23,从而保留未覆盖栅极22的缓冲层23。
步骤13:自基体背向栅极的一侧进行曝光以形成多晶硅层。
结合图4所示,首先,自基体21背向栅极22的一侧进行曝光,位于栅极22上方的第一区域Q1的正性光阻层27由于受到栅极22的遮挡而未曝光,因此可在显影时被保留,且未被栅极22遮挡而被曝光的正性光阻层27在显影时可被灰化去除,从而仅仅在对应于栅极22的正上方的第一区域Q1中保留有正性光阻层27。
然后,向除第一区域Q1之外的半导体层26注入第一杂质离子,即对半导体层26进行传统意义上的重掺杂处理。
接着,自基体21背向栅极22的一侧进行曝光,本次曝光的强度大于形成第一区域Q1的正性光阻层27的曝光的强度,因此位于第一区域Q1的两端的正性光阻层27被除去,从而在栅极22的正上方形成第二区域Q2的正性光阻层27,其中第二区域Q2小于第一区域Q1。
进一步,向除第二区域Q2之外的半导体层26注入第二杂质离子,即对半导体层26进行传统意义上的轻掺杂处理。本实施例的第一杂质离子可以为N+型杂质离子,对应地第二杂质离子为N-型杂质离子,但是当第一杂质离子为P+型杂质离子时无需掺杂第二杂质离子,即省略了轻掺杂处理的步骤。
最后,除去第二区域Q2的正性光阻层27,并利用第二光罩经过曝光、显影、刻蚀得到如图4所示具有预定图案的多晶硅层28。
步骤S14:在包括多晶硅层的基板上形成第二绝缘层,并在第二绝缘层内形成暴露多晶硅层的两端的第一接触孔。
第二绝缘层29覆盖于多晶硅层28和第一绝缘层25上。本实施例可以利用第三光罩经曝光、显影、刻蚀得到图5所示第一接触孔O1。
步骤S15:在第二绝缘层上形成薄膜晶体管的源极和漏极,使得源极和漏极可通过第一接触孔与多晶硅层电连接。
本实施例可以利用第四光罩经过曝光、显影、刻蚀得到如图6所示的薄膜晶体管的源极S和漏极D。
承上所述,本实施例自基体21背向栅极22的一侧进行曝光,即利用不透光的栅极22进行曝光以形成多晶硅层28,在多晶硅层28的制程中无需使用光罩,从而能够减少整个LTPS阵列面板所使用的光罩的类型及数量,简化制程并降低生产成本。
如图7所示,本发明实施例的制造方法还包括以下步骤:
在由源极S和漏极D组成的源漏电极层上形成平坦钝化层30,并在平坦钝化层30内形成第二接触孔O2以暴露漏极D的表面。本实施例可以利用第五光罩经曝光、显影、刻蚀得到第二接触孔O2。
在平坦钝化层30上且第二接触孔O2远离薄膜晶体管的一侧形成LTPS阵列基板的公共电极层31。本实施例可以利用第六光罩经曝光、显影、刻蚀得到具有预定图案的公共电极层31。
在平坦钝化层30和公共电极层31上形成第三绝缘层32,且第三绝缘层32未覆盖第二接触孔O2。本实施例可以利用第七光罩经曝光、显影、刻蚀得到具有预定图案的第三绝缘层32,还可以采用化学气相沉积、等离子化学气相沉积形成、溅射、真空蒸镀或低压化学气相沉积等方法直接形成具有预定图案的第三绝缘层32。
在平坦钝化层30上形成像素电极33,并且像素电极33可通过第二接触孔O2与漏极D电连接。本实施例可以利用第八光罩经曝光、显影、刻蚀得到具有预定图案的像素电极33。另外,薄膜晶体管的栅极22与形成于基体21(阵列基板)上的栅极线对应电连接,薄膜晶体管的源极S与形成于阵列基板上的数据线对应电连接,栅极线和数据线垂直交叉形成像素电极33所在的像素显示区域。
本发明实施例还提供一种具有图7所示LTPS阵列面板的液晶显示面板以及液晶显示器,与其具有相同的有益效果。
在此基础上,以上所述仅为本发明的实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,例如各实施例之间技术特征的相互结合,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。
Claims (10)
1.一种LTPS阵列基板的制造方法,其特征在于,包括:
在基体上形成所述LTPS阵列基板的薄膜晶体管的栅极;
在包括所述栅极的所述基体上依次形成第一绝缘层、半导体层和正性光阻层,其中所述第一绝缘层的上表面为一平面;
自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层;
在包括所述多晶硅层的所述基板上形成第二绝缘层,并在所述第二绝缘层内形成暴露所述多晶硅层的两端的第一接触孔;
在所述第二绝缘层上形成所述薄膜晶体管的源极和漏极,使得所述源极和所述漏极可通过所述第一接触孔与所述多晶硅层电连接。
2.根据权利要求1所述的方法,其特征在于,在包括所述栅极的所述基体上形成所述第一绝缘层之前,所述方法还包括:
在未被所述栅极覆盖的所述基体上形成缓冲层,且所述缓冲层的上表面和所述栅极的上表面构成一平面。
3.根据权利要求2所述的方法,其特征在于,在未被所述栅极覆盖的所述基体上形成所述缓冲层的步骤包括:
在包括所述栅极的所述基体上依次形成缓冲层、负性光阻层;
自所述基体背向所述栅极的一侧进行曝光,以除去位于所述栅极正上方的所述负性光阻层;
除去位于所述栅极正上方的所述缓冲层,且保留未被所述栅极覆盖的所述基体上的所述缓冲层。
4.根据权利要求1所述的方法,其特征在于,所述自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层的步骤包括:
自所述基体背向所述栅极的一侧进行曝光,以仅在对应于所述栅极的正上方的第一区域保留所述正性光阻层;
向除所述第一区域之外的所述半导体层注入第一杂质离子;
自所述基体背向所述栅极的一侧进行曝光,以在所述栅极的正上方形成第二区域的所述正性光阻层,所述第二区域小于所述第一区域;
向除所述第二区域之外的所述半导体层注入第二杂质离子;
除去所述第二区域的所述正性光阻层。
5.根据权利要求4所述的方法,其特征在于,所述第一杂质离子为N+型杂质离子,且所述第二杂质离子为N-型杂质离子。
6.根据权利要求4所述的方法,其特征在于,所述自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层的步骤包括:
自所述基体背向所述栅极的一侧进行曝光,以仅在对应于所述栅极的正上方的第一区域保留所述正性光阻层;
向除所述第一区域之外的所述半导体层注入P型杂质离子;
自所述基体背向所述栅极的一侧进行曝光,以在所述栅极的正上方形成第二区域的所述正性光阻层,所述第二区域小于所述第一区域;
除去所述第二区域的所述正性光阻层。
7.根据权利要求1所述的方法,其特征在于,所述在所述第二绝缘层上形成所述薄膜晶体管的源极和漏极的步骤之后包括:
在由所述源极和所述漏极组成的源漏电极层上形成平坦钝化层,并在所述平坦钝化层内形成第二接触孔以暴露所述漏极的表面;
在所述平坦钝化层上且所述第二接触孔远离所述薄膜晶体管的一侧形成所述LTPS阵列基板的公共电极层;
在所述平坦钝化层和所述公共电极层上形成第三绝缘层,所述第三绝缘层未覆盖所述第二接触孔;
在所述平坦钝化层上形成像素电极,并且所述像素电极可通过所述第二接触孔与所述漏极电连接。
8.一种LTPS阵列基板,其特征在于,所述LTPS阵列基板包括:
基体;
栅极,位于所述基体上;
依次形成于包括所述栅极的所述基体上的第一绝缘层、多晶硅层、第二绝缘层,所述第二绝缘层内形成有第一接触孔;
源极和漏极,位于所述第二绝缘层上,且所述源极和所述漏极可通过所述第一接触孔与所述多晶硅层电连接;
平坦钝化层,位于由所述源极和所述漏极组成的源漏电极层上,所述平坦钝化层内形成有暴露所述漏极的表面的第二接触孔;
第三绝缘层,位于所述平坦钝化层上且未覆盖所述第二接触孔;
像素电极,位于所述平坦钝化层上且所述像素电极可通过所述第二接触孔与所述漏极电连接。
9.根据权利要求8所述的LTPS阵列基板,其特征在于,所述LTPS阵列基板还包括缓冲层,所述缓冲层位于未被所述栅极覆盖的所述基体上,且所述缓冲层的上表面和所述栅极的上表面构成一平面。
10.根据权利要求8所述的LTPS阵列基板,其特征在于,所述LTPS阵列基板还包括公共电极层,所述公共电极层位于所述平坦钝化层上的所述第二接触孔远离所述薄膜晶体管的一侧。
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PCT/CN2015/081635 WO2016197400A1 (zh) | 2015-06-08 | 2015-06-17 | Ltps阵列基板及其制造方法 |
US15/863,988 US20180130830A1 (en) | 2015-06-08 | 2018-01-08 | Ltps array substrate and method for producing the same |
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