WO2016197400A1 - Ltps阵列基板及其制造方法 - Google Patents

Ltps阵列基板及其制造方法 Download PDF

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Publication number
WO2016197400A1
WO2016197400A1 PCT/CN2015/081635 CN2015081635W WO2016197400A1 WO 2016197400 A1 WO2016197400 A1 WO 2016197400A1 CN 2015081635 W CN2015081635 W CN 2015081635W WO 2016197400 A1 WO2016197400 A1 WO 2016197400A1
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Prior art keywords
layer
gate
substrate
forming
drain
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PCT/CN2015/081635
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English (en)
French (fr)
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王聪
杜鹏
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/762,458 priority Critical patent/US9893097B2/en
Publication of WO2016197400A1 publication Critical patent/WO2016197400A1/zh
Priority to US15/863,989 priority patent/US20180122840A1/en
Priority to US15/863,988 priority patent/US20180130830A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a LTPS (Low Temperature Poly-silicon) array substrate and a method of fabricating the same.
  • LTPS Low Temperature Poly-silicon
  • the liquid crystal display device adopting the LTPS process can effectively reduce the area of a TFT (Thin Film Transistor) to increase the aperture ratio of the pixel, and can enhance the display brightness while reducing power consumption and Production costs have become a research hotspot in the field of liquid crystal display.
  • TFT Thin Film Transistor
  • the LTPS process is complicated, and the types and the number of masks required for preparing an array substrate (Array substrate) are large, resulting in a large number of manufacturing processes and incapable of reducing production costs. Therefore, how to reduce the type and quantity of reticle used in the LTPS process is the goal that enterprises need to work hard at present.
  • embodiments of the present invention provide an LTPS array substrate and a method of fabricating the same, which can reduce the type and number of reticle used in the LTPS process.
  • An embodiment of the present invention provides a method for fabricating an LTPS array substrate, comprising: forming a gate of a thin film transistor of a LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive light sequentially on the substrate including the gate a resist layer, wherein an upper surface of the first insulating layer is a plane; and a side of the substrate facing away from the gate is exposed to retain a positive photoresist layer only in a first region directly above the gate; a semiconductor layer outside the first region is implanted with the first impurity ions; and a side of the substrate facing away from the gate is exposed to form a positive photoresist layer of the second region directly above the gate, the second region being smaller than the first region a region; implanting a second impurity ion to the semiconductor layer other than the second region; removing the positive photoresist layer of the second region to form a polysilicon layer; forming a second insulating layer on the substrate
  • the buffer layer is also formed on the substrate not covered by the gate, and the upper surface and the upper surface of the gate form a plane.
  • the step of forming a buffer layer on the substrate not covered by the gate includes: sequentially forming a buffer layer and a negative photoresist layer on the substrate including the gate; and exposing from the side of the substrate facing the gate to remove a negative photoresist layer directly above the gate; removing the buffer layer directly above the gate and leaving the buffer layer on the substrate not covered by the gate.
  • the first impurity ion and the second impurity ion are respectively N+ and N-type impurity ions.
  • Another embodiment of the present invention provides a method for fabricating an LTPS array substrate, comprising: forming a gate of a thin film transistor of an LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive layer sequentially on the substrate including the gate a photoresist layer, wherein an upper surface of the first insulating layer is a plane; a side of the substrate facing away from the gate is exposed to form a polysilicon layer; a second insulating layer is formed on the substrate including the polysilicon layer, and the second insulating layer is formed A first contact hole exposing both ends of the polysilicon layer is formed in the layer; a source and a drain of the thin film transistor are formed on the second insulating layer such that the source and the drain are electrically connected to the polysilicon layer through the first contact hole.
  • the buffer layer is also formed on the substrate not covered by the gate, and the upper surface and the upper surface of the gate form a plane.
  • the step of forming a buffer layer on the substrate not covered by the gate includes: sequentially forming a buffer layer and a negative photoresist layer on the substrate including the gate; and exposing from the side of the substrate facing the gate to remove a negative photoresist layer directly above the gate; removing the buffer layer directly above the gate and leaving the buffer layer on the substrate not covered by the gate.
  • the step of exposing from the side of the substrate facing the gate to form the polysilicon layer comprises: exposing from a side of the substrate facing away from the gate to remain positive only in the first region corresponding directly above the gate a photoresist layer; implanting a first impurity ion to a semiconductor layer other than the first region; and exposing from a side of the substrate facing away from the gate to form a positive photoresist layer of the second region directly above the gate electrode,
  • the second region is smaller than the first region; the second impurity ions are implanted into the semiconductor layer other than the second region; and the positive photoresist layer of the second region is removed.
  • the first impurity ion and the second impurity ion are respectively N+ and N-type impurity ions.
  • the step of exposing from the side of the substrate facing the gate to form the polysilicon layer comprises: exposing from a side of the substrate facing away from the gate to remain positive only in the first region corresponding directly above the gate a photoresist layer; implanting P-type impurity ions into a semiconductor layer other than the first region; and exposing from a side of the substrate facing away from the gate to form a positive photoresist layer of the second region directly above the gate electrode,
  • the second area is smaller than the first area;
  • the positive photoresist layer of the second region is removed.
  • a flat passivation layer is formed on the source/drain electrode layer composed of the source and the drain, and a second contact hole is formed in the flat passivation layer to be exposed a surface of the drain; a common electrode layer of the LTPS array substrate formed on the flat passivation layer and a side of the second contact hole away from the thin film transistor; a third insulating layer, a third insulation formed on the flat passivation layer and the common electrode layer The layer does not cover the second contact hole; the pixel electrode is formed on the flat passivation layer, and the pixel electrode is electrically connected to the drain through the second contact hole.
  • a further embodiment of the present invention provides an LTPS array substrate, comprising: a substrate; a gate on the substrate; a first insulating layer, a polysilicon layer, a second insulating layer, and a second insulating layer sequentially formed on the substrate including the gate a first contact hole is formed in the layer; a source and a drain are located on the second insulating layer, and the source and the drain are electrically connected to the polysilicon layer through the first contact hole; the flat passivation layer is located at the source and a second contact hole having a surface exposing the drain is formed in the flat passivation layer on the source/drain electrode layer composed of the drain; the third insulating layer is located on the flat passivation layer and does not cover the second contact hole; the pixel electrode, Located on the flat passivation layer and the pixel electrode can be electrically connected to the drain through the second contact hole.
  • the LTPS array substrate further includes a buffer layer on the substrate not covered by the gate, and the upper surface of the buffer layer and the upper surface of the gate form a plane.
  • the LTPS array substrate further includes a common electrode layer, and the common electrode layer is located on a side of the second contact hole on the flat passivation layer away from the thin film transistor.
  • the LTPS array substrate and the manufacturing method thereof are exposed from a side of the substrate facing away from the gate, that is, exposure is performed by using an opaque gate to form a polysilicon layer, and a mask is not required in the process of the polysilicon layer. This can reduce the type and number of reticle used in the LTPS process, simplify the process and reduce production costs.
  • FIG. 1 is a flow chart showing a method of fabricating an embodiment of an LTPS array substrate of the present invention
  • FIG. 2 is a schematic view showing the formation of a gate electrode in the manufacturing method of the present invention.
  • FIG. 3 is a schematic view showing formation of a first insulating layer, a semiconductor layer, and a positive photoresist layer in the manufacturing method of the present invention
  • FIG. 4 is a schematic view showing formation of a polysilicon layer in the manufacturing method of the present invention.
  • Figure 5 is a schematic view showing the formation of a second insulating layer in the manufacturing method of the present invention.
  • Figure 6 is a schematic view showing the formation of a source and a drain in the manufacturing method of the present invention.
  • Fig. 7 is a schematic view showing the formation of a pixel electrode in the manufacturing method of the present invention.
  • FIG. 1 is a flow chart showing a method of fabricating an embodiment of an LTPS array substrate of the present invention. As shown in FIG. 1, the manufacturing method of this embodiment includes the following steps:
  • Step 11 forming a gate of the thin film transistor of the LTPS array substrate on the substrate.
  • the substrate 21 is used to form an LTPS array substrate of a liquid crystal display panel, and the substrate 21 may be a glass substrate, a plastic substrate or a flexible substrate.
  • the first metal layer formed on the substrate 21 is exposed by the first mask, and after the exposure, a patterning process such as development, etching, or the like is performed to obtain the gate electrode 22, wherein the phosphoric acid is used.
  • the first metal layer 12 is etched by an etching solution of nitric acid, acetic acid, and deionized water, although dry etching may of course be employed.
  • the gate 22 can be obtained by other methods, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, or low pressure.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • a method of chemical vapor deposition or the like directly forms the gate electrode 22 having a predetermined pattern on the substrate 21.
  • the first metal layer may be composed of a metal such as aluminum, molybdenum, titanium, chromium, copper, or a metal oxide such as titanium oxide, or an alloy of metal or other conductive material.
  • Step 12 sequentially forming a first insulating layer, a semiconductor layer and a positive photoresist layer on the substrate including the gate, wherein the upper surface of the first insulating layer is a plane.
  • the first insulating layer 25, the semiconductor layer 26, and the positive photoresist layer 27 are formed.
  • the present embodiment needs to form a buffer layer 23 on the substrate 21 not covered by the gate 22.
  • the specific process includes but is not limited to:
  • the buffer layer 23 and the negative photoresist layer 24 are sequentially formed on the substrate 21 including the gate electrode 22.
  • the buffer layer 23 may be a combination of a silicon nitride (SiN x ) layer, a silicon oxide (SiO x ) layer, or other non-conductive material, and the buffer layer 23 may be used to prevent impurities in the substrate 21 from being diffused in a subsequent process to be formed after being affected.
  • the quality of the low temperature polysilicon layer, the silicon nitride layer and the silicon oxide layer may be formed by chemical vapor deposition, plasma chemical vapor deposition, sputtering, vacuum evaporation or low pressure chemical vapor deposition, but is not limited thereto.
  • the remaining negative photoresist layer 24 is stripped off, and the buffer layer 23 located directly above the gate electrode 22 is removed by etching, thereby leaving the buffer layer 23 not covering the gate electrode 22.
  • Step 13 Exposing from the side of the substrate facing away from the gate to form a polysilicon layer.
  • this exposure is formed larger than the intensity of the exposure intensity of Q 1 positive photoresist layer 27 of the first region, the first region located at both ends of a Q positive photoresist layer 27 is removed, thereby forming a second region Q 2 positive photoresist layer 27 is immediately above the gate electrode 22, wherein the second area smaller than the first area Q 2 Q 1.
  • the second impurity ions are implanted into the semiconductor layer 26 other than the second region Q 2 , that is, the semiconductor layer 26 is subjected to a light doping treatment in a conventional sense.
  • the first impurity ions of this embodiment may be N+ type impurity ions, and correspondingly, the second impurity ions are N-type impurity ions, but when the first impurity ions are P+ type impurity ions, it is not necessary to dope the second impurity ions, that is, The step of light doping treatment.
  • the positive photoresist layer 27 of the second region Q 2 is removed, and the polysilicon layer 28 having a predetermined pattern as shown in FIG. 4 is obtained by exposure, development, and etching using a second mask.
  • Step S14 forming a second insulating layer on the substrate including the polysilicon layer, and forming a first contact hole exposing both ends of the polysilicon layer in the second insulating layer.
  • the second insulating layer 29 covers the polysilicon layer 28 and the first insulating layer 25.
  • the first contact hole O 1 shown in FIG. 5 can be obtained by exposure, development, and etching using a third mask.
  • Step S15 forming a source and a drain of the thin film transistor on the second insulating layer, so that the source and the drain are electrically connected to the polysilicon layer through the first contact hole.
  • the source S and the drain D of the thin film transistor shown in FIG. 6 can be obtained by exposure, development, and etching using a fourth mask.
  • the present embodiment exposes the side of the substrate 21 facing away from the gate 22, that is, by using the opaque gate 22 to form the polysilicon layer 28, and the mask is not required in the process of the polysilicon layer 28. Therefore, the type and number of masks used in the entire LTPS array panel can be reduced, the process can be simplified, and the production cost can be reduced.
  • the manufacturing method of the embodiment of the present invention further includes the following steps:
  • a flat passivation layer 30 is formed on the source/drain electrode layer composed of the source S and the drain D, and a second contact hole O 2 is formed in the flat passivation layer 30 to expose the surface of the drain D.
  • the second contact hole O 2 can be obtained by exposure, development, and etching using the fifth mask.
  • a common electrode layer 31 of the LTPS array substrate is formed on the flat passivation layer 30 and on the side of the second contact hole O 2 away from the thin film transistor.
  • the sixth electrode mask can be exposed, developed, and etched to obtain a common electrode layer 31 having a predetermined pattern.
  • a third insulating layer 32 is formed on the flat passivation layer 30 and the common electrode layer 31, and the third insulating layer 32 does not cover the second contact hole O 2 .
  • the third insulating layer 32 having a predetermined pattern can be obtained by exposure, development, and etching using a seventh photomask, and can also be formed by chemical vapor deposition, plasma chemical vapor deposition, sputtering, vacuum evaporation, or low pressure chemical vapor phase.
  • a method of deposition or the like directly forms the third insulating layer 32 having a predetermined pattern.
  • the pixel electrode 33 is formed on a flat passivation layer 30, and the pixel electrode contact hole 33 may be a second O 2 is electrically connected to the drain D through.
  • the pixel electrode 33 having a predetermined pattern can be obtained by exposure, development, and etching using the eighth mask.
  • the gate electrode 22 of the thin film transistor is electrically connected to the gate line formed on the substrate 21 (array substrate), and the source S of the thin film transistor is electrically connected to the data line formed on the array substrate, and the gate line and the data are electrically connected.
  • the lines vertically intersect to form a pixel display area in which the pixel electrode 33 is located.
  • the embodiment of the invention further provides a liquid crystal display panel and a liquid crystal display having the LTPS array panel shown in FIG. 7, which have the same beneficial effects.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种LTPS阵列基板及其制造方法。方法包括：在基体（21）上形成薄膜晶体管的栅极（22）；在包括栅极（22）的基体（21）上依次形成第一绝缘层（25）、半导体层（26）和正性光阻层（27）；自基体（21）背向栅极（22）的一侧进行曝光以形成多晶硅层（28）；在包括多晶硅层（28）的基体（21）上形成具有接触孔（O 1）的第二绝缘层（29）；在第二绝缘层（29）上形成薄膜晶体管的源极（S）和漏极（D），使得源极（S）和漏极（D）可通过接触孔（O 1）与多晶硅层（28）电连接。能够减少LTPS工艺所使用的光罩的类型及数量，简化制程并降低生产成本。

Description

LTPS阵列基板及其制造方法 【技术领域】
本发明涉及显示技术领域，具体涉及一种LTPS(Low Temperature Poly-silicon，低温多晶硅)阵列基板及其制造方法。
【背景技术】
采用LTPS工艺的液晶显示装置由于具有较高的电子迁移率，能够有效减小TFT(Thin Film Transistor，薄膜晶体管)的面积以提升像素的开口率，并且在增强显示亮度的同时能够降低功耗及生产成本，目前已成为液晶显示领域的研究热点。但是LTPS工艺复杂，制备阵列基板(Array基板)所需的光罩(Mask)的类型及数量较多，导致制造流程繁多，无法降低生产成本。因此如何减少LTPS工艺所使用的光罩的类型及数量，实为目前企业需要努力的目标。
【发明内容】
鉴于此，本发明实施例提供一种LTPS阵列基板及其制造方法，能够减少LTPS工艺所使用的光罩的类型及数量。
本发明一实施例提供一种LTPS阵列基板的制造方法，包括：在基体上形成LTPS阵列基板的薄膜晶体管的栅极；在包括栅极的基体上依次形成第一绝缘层、半导体层和正性光阻层，其中第一绝缘层的上表面为一平面；自基体背向栅极的一侧进行曝光，以仅在对应于栅极的正上方的第一区域保留正性光阻层；向除第一区域之外的半导体层注入第一杂质离子；自基体背向栅极的一侧进行曝光，以在栅极的正上方形成第二区域的正性光阻层，第二区域小于第一区域；向除第二区域之外的半导体层注入第二杂质离子；除去第二区域的正性光阻层以形成多晶硅层；在包括多晶硅层的基板上形成第二绝缘层，并在第二绝缘层内形成暴露多晶硅层的两端的第一接触孔；在第二绝缘层上形成薄膜晶体管的源极和漏极，使得源极和漏极可通过第一接触孔与多晶硅层电连接；在由源极和漏极组成的源漏电极层上形成平坦钝化层，并在平坦钝化层内形成第二接触孔以暴露漏极的表面； 在平坦钝化层上且第二接触孔远离薄膜晶体管的一侧形成LTPS阵列基板的公共电极层；在平坦钝化层和公共电极层上形成第三绝缘层，第三绝缘层未覆盖第二接触孔；在平坦钝化层上形成像素电极，并且像素电极可通过第二接触孔与漏极电连接。
其中，在包括栅极的基体上形成第一绝缘层之前，还在未被栅极覆盖的基体上形成缓冲层，且其上表面和栅极的上表面构成一平面。
其中，在未被栅极覆盖的基体上形成缓冲层的步骤包括：在包括栅极的基体上依次形成缓冲层、负性光阻层；自基体背向栅极的一侧进行曝光，以除去位于栅极正上方的负性光阻层；除去位于栅极正上方的缓冲层，且保留未被栅极覆盖的基体上的缓冲层。
其中，第一杂质离子和第二杂质离子分别为N+、N-型杂质离子。
本发明另一实施例提供一种LTPS阵列基板的制造方法，包括：在基体上形成LTPS阵列基板的薄膜晶体管的栅极；在包括栅极的基体上依次形成第一绝缘层、半导体层和正性光阻层，其中第一绝缘层的上表面为一平面；自基体背向栅极的一侧进行曝光以形成多晶硅层；在包括多晶硅层的基板上形成第二绝缘层，并在第二绝缘层内形成暴露多晶硅层的两端的第一接触孔；在第二绝缘层上形成薄膜晶体管的源极和漏极，使得源极和漏极可通过第一接触孔与多晶硅层电连接。
其中，在包括栅极的基体上形成第一绝缘层之前，还在未被栅极覆盖的基体上形成缓冲层，且其上表面和栅极的上表面构成一平面。
其中，在未被栅极覆盖的基体上形成缓冲层的步骤包括：在包括栅极的基体上依次形成缓冲层、负性光阻层；自基体背向栅极的一侧进行曝光，以除去位于栅极正上方的负性光阻层；除去位于栅极正上方的缓冲层，且保留未被栅极覆盖的基体上的缓冲层。
其中，自基体背向栅极的一侧进行曝光以形成多晶硅层的步骤包括：自基体背向栅极的一侧进行曝光，以仅在对应于栅极的正上方的第一区域保留正性光阻层；向除第一区域之外的半导体层注入第一杂质离子；自基体背向栅极的一侧进行曝光，以在栅极的正上方形成第二区域的正性光阻层，第二区域小于第一区域；向除第二区域之外的半导体层注入第二杂质离子；除去第二区域的正性光阻层。
其中，第一杂质离子和第二杂质离子分别为N+、N-型杂质离子。
其中，自基体背向栅极的一侧进行曝光以形成多晶硅层的步骤包括：自基体背向栅极的一侧进行曝光，以仅在对应于栅极的正上方的第一区域保留正性光阻层；向除第一区域之外的半导体层注入P型杂质离子；自基体背向栅极的一侧进行曝光，以在栅极的正上方形成第二区域的正性光阻层，第二区域小于第一区域；
除去所述第二区域的所述正性光阻层。
其中，在第二绝缘层上形成源极和漏极之后，在由源极和漏极组成的源漏电极层上形成平坦钝化层，并在平坦钝化层内形成第二接触孔以暴露漏极的表面；在平坦钝化层上且第二接触孔远离薄膜晶体管的一侧形成LTPS阵列基板的公共电极层；在平坦钝化层和公共电极层上形成第三绝缘层，第三绝缘层未覆盖第二接触孔；在平坦钝化层上形成像素电极，并且像素电极可通过第二接触孔与漏极电连接。
本发明又一实施例提供一种LTPS阵列基板，包括：基体；栅极，位于基体上；依次形成于包括栅极的基体上的第一绝缘层、多晶硅层、第二绝缘层，第二绝缘层内形成有第一接触孔；源极和漏极，位于第二绝缘层上，且源极和漏极可通过第一接触孔与多晶硅层电连接；平坦钝化层，位于由源极和漏极组成的源漏电极层上，平坦钝化层内形成有暴露漏极的表面的第二接触孔；第三绝缘层，位于平坦钝化层上且未覆盖第二接触孔；像素电极，位于平坦钝化层上且像素电极可通过第二接触孔与漏极电连接。
其中，LTPS阵列基板还包括缓冲层，缓冲层位于未被栅极覆盖的基体上，且缓冲层的上表面和栅极的上表面构成一平面。
其中，LTPS阵列基板还包括公共电极层，公共电极层位于平坦钝化层上的第二接触孔远离薄膜晶体管的一侧。
本发明实施例的LTPS阵列基板及其制造方法，自基体背向栅极的一侧进行曝光，即利用不透光的栅极进行曝光以形成多晶硅层，在多晶硅层的制程中无需使用光罩，从而能够减少LTPS工艺所使用的光罩的类型及数量，简化制程并降低生产成本。
【附图说明】
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图；
图2是本发明的制造方法中形成栅极的示意图；
图3是本发明的制造方法中形成第一绝缘层、半导体层和正性光阻层的示意图；
图4是本发明的制造方法中形成多晶硅层的示意图；
图5是本发明的制造方法中形成第二绝缘层的示意图；
图6是本发明的制造方法中形成源极和漏极的示意图；
图7是本发明的制造方法中形成像素电极的示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图。如图1所示，本实施例的制造方法包括以下步骤：
步骤11：在基体上形成LTPS阵列基板的薄膜晶体管的栅极。
如图2所示，基体21用于形成液晶显示面板的LTPS阵列基板，所述基体21可为玻璃基体、塑料基体或可挠式基体。
本实施例可以利用第一光罩对形成于基体21上的第一金属层进行曝光，并在曝光后进行显影、刻蚀等图案化制程以得到形成栅极22，其中可利用包含有磷酸、硝酸、醋酸以及去离子水的蚀刻液对第一金属层12进行蚀刻，当然也可以采用干法蚀刻。
当然，本实施例还可以通过其他方式得到栅极22，例如采用化学气相沉积(Chemical vapor deposition，CVD)、等离子化学气相沉积(Plasma Enhanced Chemical vapor deposition，PECVD)、溅射、真空蒸镀或低压化学气相沉积等方法直接在基体21上形成具有预定图案的栅极22。其中，第一金属层可由金属，例如铝、钼、钛、铬、铜，或金属氧化物，例如氧化钛，或金属的合金或其它导电材料构成。
步骤12：在包括栅极的基体上依次形成第一绝缘层、半导体层和正性光阻层，其中第一绝缘层的上表面为一平面。
结合图3所示，在形成第一绝缘层25、半导体层26和正性光阻层27 之前，本实施例需要在未被栅极22覆盖的基体21上形成缓冲层(Buffer layer)23，具体过程包括但不限于：
首先，在包括栅极22的基体21上依次形成缓冲层23、负性光阻层24。缓冲层23可以为氮化硅(SiNx)层、氧化硅(SiOx)层或者其他非导电材料的组合，缓冲层23可用于防止基体21内的杂质在后续工艺中向上扩散而影响之后形成的低温多晶硅层的品质，氮化硅层和氧化硅层可以采用化学气相沉积、等离子化学气相沉积形成、溅射、真空蒸镀或低压化学气相沉积等方法形成，但不限于此。
然后，自基体21背向栅极22的一侧进行曝光，位于栅极22正上方的负性光阻层24由于受到栅极22的遮挡而未曝光，因此可在显影时被灰化去除。
最后，剥离除去剩余的负性光阻层24，再通过刻蚀除去位于栅极22正上方的缓冲层23，从而保留未覆盖栅极22的缓冲层23。
步骤13：自基体背向栅极的一侧进行曝光以形成多晶硅层。
结合图4所示，首先，自基体21背向栅极22的一侧进行曝光，位于栅极22上方的第一区域Q1的正性光阻层27由于受到栅极22的遮挡而未曝光，因此可在显影时被保留，且未被栅极22遮挡而被曝光的正性光阻层27在显影时可被灰化去除，从而仅仅在对应于栅极22的正上方的第一区域Q1中保留有正性光阻层27。
然后，向除第一区域Q1之外的半导体层26注入第一杂质离子，即对半导体层26进行传统意义上的重掺杂处理。
接着，自基体21背向栅极22的一侧进行曝光，本次曝光的强度大于形成第一区域Q1的正性光阻层27的曝光的强度，因此位于第一区域Q1的两端的正性光阻层27被除去，从而在栅极22的正上方形成第二区域Q2的正性光阻层27，其中第二区域Q2小于第一区域Q1。
进一步，向除第二区域Q2之外的半导体层26注入第二杂质离子，即对半导体层26进行传统意义上的轻掺杂处理。本实施例的第一杂质离子可以为N+型杂质离子，对应地第二杂质离子为N-型杂质离子，但是当第一杂质离子为P+型杂质离子时无需掺杂第二杂质离子，即省略了轻掺杂处理的步骤。
最后，除去第二区域Q2的正性光阻层27，并利用第二光罩经过曝光、显影、刻蚀得到如图4所示具有预定图案的多晶硅层28。
步骤S14：在包括多晶硅层的基板上形成第二绝缘层，并在第二绝缘层内形成暴露多晶硅层的两端的第一接触孔。
第二绝缘层29覆盖于多晶硅层28和第一绝缘层25上。本实施例可以利用第三光罩经曝光、显影、刻蚀得到图5所示第一接触孔O1。
步骤S15：在第二绝缘层上形成薄膜晶体管的源极和漏极，使得源极和漏极可通过第一接触孔与多晶硅层电连接。
本实施例可以利用第四光罩经过曝光、显影、刻蚀得到如图6所示的薄膜晶体管的源极S和漏极D。
承上所述，本实施例自基体21背向栅极22的一侧进行曝光，即利用不透光的栅极22进行曝光以形成多晶硅层28，在多晶硅层28的制程中无需使用光罩，从而能够减少整个LTPS阵列面板所使用的光罩的类型及数量，简化制程并降低生产成本。
如图7所示，本发明实施例的制造方法还包括以下步骤：
在由源极S和漏极D组成的源漏电极层上形成平坦钝化层30，并在平坦钝化层30内形成第二接触孔O2以暴露漏极D的表面。本实施例可以利用第五光罩经曝光、显影、刻蚀得到第二接触孔O2。
在平坦钝化层30上且第二接触孔O2远离薄膜晶体管的一侧形成LTPS阵列基板的公共电极层31。本实施例可以利用第六光罩经曝光、显影、刻蚀得到具有预定图案的公共电极层31。
在平坦钝化层30和公共电极层31上形成第三绝缘层32，且第三绝缘层32未覆盖第二接触孔O2。本实施例可以利用第七光罩经曝光、显影、刻蚀得到具有预定图案的第三绝缘层32，还可以采用化学气相沉积、等离子化学气相沉积形成、溅射、真空蒸镀或低压化学气相沉积等方法直接形成具有预定图案的第三绝缘层32。
在平坦钝化层30上形成像素电极33，并且像素电极33可通过第二接触孔O2与漏极D电连接。本实施例可以利用第八光罩经曝光、显影、刻蚀得到具有预定图案的像素电极33。另外，薄膜晶体管的栅极22与形成于基体21(阵列基板)上的栅极线对应电连接，薄膜晶体管的源极S与形成于 阵列基板上的数据线对应电连接，栅极线和数据线垂直交叉形成像素电极33所在的像素显示区域。
本发明实施例还提供一种具有图7所示LTPS阵列面板的液晶显示面板以及液晶显示器，与其具有相同的有益效果。
在此基础上，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种LTPS阵列基板的制造方法，其中，包括：
    在基体上形成所述LTPS阵列基板的薄膜晶体管的栅极；
    在包括所述栅极的所述基体上依次形成第一绝缘层、半导体层和正性光阻层，其中所述第一绝缘层的上表面为一平面；
    自所述基体背向所述栅极的一侧进行曝光，以仅在对应于所述栅极的正上方的第一区域保留所述正性光阻层；
    向除所述第一区域之外的所述半导体层注入第一杂质离子；
    自所述基体背向所述栅极的一侧进行曝光，以在所述栅极的正上方形成第二区域的所述正性光阻层，所述第二区域小于所述第一区域；
    向除所述第二区域之外的所述半导体层注入第二杂质离子；
    除去所述第二区域的所述正性光阻层以形成多晶硅层；
    在包括所述多晶硅层的所述基板上形成第二绝缘层，并在所述第二绝缘层内形成暴露所述多晶硅层的两端的第一接触孔；
    在所述第二绝缘层上形成所述薄膜晶体管的源极和漏极，使得所述源极和所述漏极可通过所述第一接触孔与所述多晶硅层电连接；
    在由所述源极和所述漏极组成的源漏电极层上形成平坦钝化层，并在所述平坦钝化层内形成第二接触孔以暴露所述漏极的表面；
    在所述平坦钝化层上且所述第二接触孔远离所述薄膜晶体管的一侧形成所述LTPS阵列基板的公共电极层；
    在所述平坦钝化层和所述公共电极层上形成第三绝缘层，所述第三绝缘层未覆盖所述第二接触孔；
    在所述平坦钝化层上形成像素电极，并且所述像素电极可通过所述第二接触孔与所述漏极电连接。
  2. 根据权利要求1所述的方法，其中，在包括所述栅极的所述基体上形成所述第一绝缘层之前，所述方法还包括：
    在未被所述栅极覆盖的所述基体上形成缓冲层，且所述缓冲层的上表面和所述栅极的上表面构成一平面。
  3. 根据权利要求2所述的方法，其中，在未被所述栅极覆盖的所述基 体上形成所述缓冲层的步骤包括：
    在包括所述栅极的所述基体上依次形成缓冲层、负性光阻层；
    自所述基体背向所述栅极的一侧进行曝光，以除去位于所述栅极正上方的所述负性光阻层；
    除去位于所述栅极正上方的所述缓冲层，且保留未被所述栅极覆盖的所述基体上的所述缓冲层。
  4. 根据权利要求1所述的方法，其中，所述第一杂质离子为N+型杂质离子，且所述第二杂质离子为N-型杂质离子。
  5. 一种LTPS阵列基板的制造方法，其中，包括：
    在基体上形成所述LTPS阵列基板的薄膜晶体管的栅极；
    在包括所述栅极的所述基体上依次形成第一绝缘层、半导体层和正性光阻层，其中所述第一绝缘层的上表面为一平面；
    自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层；
    在包括所述多晶硅层的所述基板上形成第二绝缘层，并在所述第二绝缘层内形成暴露所述多晶硅层的两端的第一接触孔；
    在所述第二绝缘层上形成所述薄膜晶体管的源极和漏极，使得所述源极和所述漏极可通过所述第一接触孔与所述多晶硅层电连接。
  6. 根据权利要求5所述的方法，其中，在包括所述栅极的所述基体上形成所述第一绝缘层之前，所述方法还包括：
    在未被所述栅极覆盖的所述基体上形成缓冲层，且所述缓冲层的上表面和所述栅极的上表面构成一平面。
  7. 根据权利要求6所述的方法，其中，在未被所述栅极覆盖的所述基体上形成所述缓冲层的步骤包括：
    在包括所述栅极的所述基体上依次形成缓冲层、负性光阻层；
    自所述基体背向所述栅极的一侧进行曝光，以除去位于所述栅极正上方的所述负性光阻层；
    除去位于所述栅极正上方的所述缓冲层，且保留未被所述栅极覆盖的所述基体上的所述缓冲层。
  8. 根据权利要求5所述的方法，其中，所述自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层的步骤包括：
    自所述基体背向所述栅极的一侧进行曝光，以仅在对应于所述栅极的正上方的第一区域保留所述正性光阻层；
    向除所述第一区域之外的所述半导体层注入第一杂质离子；
    自所述基体背向所述栅极的一侧进行曝光，以在所述栅极的正上方形成第二区域的所述正性光阻层，所述第二区域小于所述第一区域；
    向除所述第二区域之外的所述半导体层注入第二杂质离子；
    除去所述第二区域的所述正性光阻层。
  9. 根据权利要求8所述的方法，其中，所述第一杂质离子为N+型杂质离子，且所述第二杂质离子为N-型杂质离子。
  10. 根据权利要求5所述的方法，其中，所述自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层的步骤包括：
    自所述基体背向所述栅极的一侧进行曝光，以仅在对应于所述栅极的正上方的第一区域保留所述正性光阻层；
    向除所述第一区域之外的所述半导体层注入P型杂质离子；
    自所述基体背向所述栅极的一侧进行曝光，以在所述栅极的正上方形成第二区域的所述正性光阻层，所述第二区域小于所述第一区域；
    除去所述第二区域的所述正性光阻层。
  11. 根据权利要求5所述的方法，其中，所述在所述第二绝缘层上形成所述薄膜晶体管的源极和漏极的步骤之后包括：
    在由所述源极和所述漏极组成的源漏电极层上形成平坦钝化层，并在所述平坦钝化层内形成第二接触孔以暴露所述漏极的表面；
    在所述平坦钝化层上且所述第二接触孔远离所述薄膜晶体管的一侧形成所述LTPS阵列基板的公共电极层；
    在所述平坦钝化层和所述公共电极层上形成第三绝缘层，所述第三绝缘层未覆盖所述第二接触孔；
    在所述平坦钝化层上形成像素电极，并且所述像素电极可通过所述第二接触孔与所述漏极电连接。
  12. 一种LTPS阵列基板，其中，所述LTPS阵列基板包括：
    基体；
    栅极，位于所述基体上；
    依次形成于包括所述栅极的所述基体上的第一绝缘层、多晶硅层、第二绝缘层，所述第二绝缘层内形成有第一接触孔；
    源极和漏极，位于所述第二绝缘层上，且所述源极和所述漏极可通过所述第一接触孔与所述多晶硅层电连接；
    平坦钝化层，位于由所述源极和所述漏极组成的源漏电极层上，所述平坦钝化层内形成有暴露所述漏极的表面的第二接触孔；
    第三绝缘层，位于所述平坦钝化层上且未覆盖所述第二接触孔；
    像素电极，位于所述平坦钝化层上且所述像素电极可通过所述第二接触孔与所述漏极电连接。
  13. 根据权利要求12所述的LTPS阵列基板，其中，所述LTPS阵列基板还包括缓冲层，所述缓冲层位于未被所述栅极覆盖的所述基体上，且所述缓冲层的上表面和所述栅极的上表面构成一平面。
  14. 根据权利要求12所述的LTPS阵列基板，其中，所述LTPS阵列基板还包括公共电极层，所述公共电极层位于所述平坦钝化层上的所述第二接触孔远离所述薄膜晶体管的一侧。
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