WO2017148007A1 - 金属氧化物薄膜晶体管及其制备方法 - Google Patents

金属氧化物薄膜晶体管及其制备方法 Download PDF

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Publication number
WO2017148007A1
WO2017148007A1 PCT/CN2016/082315 CN2016082315W WO2017148007A1 WO 2017148007 A1 WO2017148007 A1 WO 2017148007A1 CN 2016082315 W CN2016082315 W CN 2016082315W WO 2017148007 A1 WO2017148007 A1 WO 2017148007A1
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layer
gate
gate insulating
oxide
metal
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PCT/CN2016/082315
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English (en)
French (fr)
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谢应涛
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武汉华星光电技术有限公司
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Priority to US15/115,488 priority Critical patent/US20180114854A1/en
Publication of WO2017148007A1 publication Critical patent/WO2017148007A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the invention relates to the field of wafer manufacturing and display technology, in particular to a metal oxide thin film transistor and a preparation method thereof.
  • a thin film transistor liquid crystal flat panel display is a type of active matrix liquid crystal display device. Each liquid crystal pixel on the display screen is driven by a thin film transistor integrated behind the pixel, and a thin film transistor (TFT, Thin Film Transistor) The responsiveness of the display and the trueness of the color have an important influence and are an important part of this type of display.
  • TFT Thin Film Transistor
  • Common thin film transistors are mainly amorphous silicon thin film transistors (a-Si TFTs), low temperature polysilicon thin film transistors (LTPS TFTs), metal oxide thin film transistors, and the like.
  • TFT technology using metal oxide as a channel layer material is currently a research hotspot in the field of panel technology, especially using TFT technology of Indium Gallium Zinc Oxide, which can be used for display screens.
  • Power consumption is close to OLED, the thickness is only 25% higher than OLED, and the resolution can reach full HD (f ⁇ ll HD, 1920*1080P) or even ultra high definition ( ⁇ ltraDefinition, resolution 4k*2k) level, but the cost is relatively lower .
  • Common techniques for the preparation of metal oxide thin film transistors include back channel etch (BCE) technology, etch stopper layer (ESL) technology, and self-aligned top gate structure (self-aligned). Top gate).
  • BCE back channel etch
  • ESL etch stopper layer
  • Top gate self-aligned top gate structure
  • an object of the present invention is to provide a metal oxide thin film crystal
  • the tube and the preparation method thereof are optimized and improved by the preparation method of the metal oxide thin film transistor, thereby achieving the purpose of simplifying the process flow and reducing the production cost.
  • the present invention includes three aspects.
  • the present invention provides a method of fabricating a metal oxide thin film transistor, comprising the steps of:
  • S2 sequentially forming a buffer layer, an oxide film layer, a gate insulating layer and a first metal layer on the substrate;
  • S3 patterning the first metal layer, the gate insulating layer, and the oxide film layer by using a photomask, patterning the first metal layer to form a gate, and making the gate
  • the insulating layer is patterned to pattern the oxide film layer to form an oxide active layer.
  • the method further includes the following steps, S4: forming a photoresist layer on the first metal layer, The photoresist layer is exposed to obtain a patterned photoresist layer.
  • the step S4 is specifically: depositing the photoresist layer on the first metal layer by spin coating or printing, and obtaining a patterned photoresist layer through an exposure machine.
  • the patterned photoresist layer is post-baked.
  • step S3 patterning the first metal layer is performed by patterning the photoresist layer, and engraving the first metal layer Etching, patterning the first metal layer to form the gate.
  • the etching of the first metal layer is performed by wet etching.
  • the gate size is smaller than the photoresist
  • the pattern size of the gate is smaller than the pattern size of the photoresist layer by 1 ⁇ m or less.
  • step S3 patterning the gate insulating layer is performed by tying the patterned photoresist layer to the gate insulating layer Etching is performed to obtain the patterned gate insulating layer.
  • the etching of the gate insulating layer is performed by dry etching.
  • step S3 patterning the oxide film layer is blocked by the patterned photoresist layer, and the oxide film is masked The layer is etched to pattern the oxide film layer to form the oxide active layer.
  • the etching is performed by wet etching or dry etching.
  • the oxide film layer is an IGZO film layer.
  • IGZO refers to Indium Gallium Zinc Oxide, which is indium gallium zinc oxide.
  • the material selected for the buffer layer is SiOx.
  • the step S5 is specifically: using a plasma treatment technique, the photoresist layer is removed by ashing with O 2 .
  • the method further includes the following steps, S6: patterning the gate insulating layer, The buffer layer is etched. The etching of the patterned gate insulating layer and the buffer layer is performed by dry etching.
  • the buffer layer is etched by using the oxide active layer as a protective layer, and the buffer layer is divided into first in the oxide active layer protection region.
  • the buffer layer and the exposed second buffer layer outside the gate protection region of the oxide active layer etch away all or part of the second buffer layer, leaving the first buffer layer.
  • the thickness of the first buffer layer is L
  • the thickness of the portion where the second buffer layer is etched is d
  • the method further includes the step of: S7: exposing the oxide active layer outside the gate protection region Performing a plasma treatment to change the oxide active layer exposed outside the gate protection region into a conductor to form a source contact region and a drain contact region to interconnect with a subsequently formed source and drain.
  • S7 exposing the oxide active layer outside the gate protection region Performing a plasma treatment to change the oxide active layer exposed outside the gate protection region into a conductor to form a source contact region and a drain contact region to interconnect with a subsequently formed source and drain.
  • the plasma treatment is performed using CF 4 , NH 3 , H 2 or Ar.
  • the method further includes the following steps, S8: forming an interconnect layer (ILD) on the gate.
  • ILD interconnect layer
  • the interconnection layer is formed by depositing on the gate by a chemical vapor deposition process, and the material selected for the interconnection layer is one or a combination of SiOx and SiNx.
  • the method further includes the following steps, S9: forming a region corresponding to the source contact region in the interconnect layer to expose a portion of the source contact region a source contact hole; a region corresponding to the drain contact region in the interconnect layer forms a drain contact hole exposing a portion of the drain contact region.
  • the source contact hole and the drain contact hole are formed by a photolithography process.
  • a second metal layer is deposited in the source contact hole and the drain contact hole, and photolithography is performed on the second metal layer to obtain a source and a drain, respectively;
  • a source contact hole is in contact with the source contact region; and the drain is in contact with the drain contact region through the drain contact hole.
  • the present invention also provides a metal oxide thin film transistor obtained by the above preparation method, comprising a substrate and a buffer layer, an oxide active layer, a gate insulating layer and a gate which are sequentially disposed on the substrate
  • the gate electrode, the gate insulating layer, and the oxide active layer are respectively patterned by patterning a first metal layer, a gate insulating layer, and an oxide film layer formed on the substrate. of.
  • the pattern size of the gate electrode is smaller than the pattern size of the photoresist layer.
  • the gate insulating layer is patterned by using a patterned photoresist layer as an occlusion, and the gate insulating layer is etched to obtain a patterned device.
  • a gate insulating layer is described. The etching of the gate insulating layer is performed by dry etching.
  • oxide Active Layer-Etching Further, patterning the oxide film layer is blocked by a patterned photoresist layer, and the oxide film layer is etched to cause the oxidation The film layer is patterned to form the oxide active layer. Wherein the etching of the oxide film layer is performed by wet etching Etching or dry etching.
  • the oxide active layer is an IGZO film layer.
  • IGZO refers to Indium Gallium Zinc Oxide, which is indium gallium zinc oxide.
  • the material selected for the buffer layer is SiOx.
  • the patterned gate insulating layer and the buffer layer are etched.
  • the etching of the patterned gate insulating layer and the buffer layer is performed by dry etching.
  • the buffer layer is etched by using the oxide active layer as a protective layer, and the buffer layer is divided into first in the oxide active layer protection region.
  • the buffer layer and the exposed second buffer layer outside the gate protection region of the oxide active layer etch away all or part of the second buffer layer, leaving the first buffer layer.
  • the thickness of the first buffer layer is L
  • the difference in thickness of the portion where the second buffer layer is etched is d
  • a source contact region and a drain contact region are further provided, and the source contact region and the drain contact region are exposed
  • the oxide active layer outside the gate protection region is subjected to plasma treatment to form the oxide active layer exposed outside the gate protection region into a conductor.
  • the plasma treatment is performed using CF 4 , NH 3 , H 2 or Ar.
  • an interconnection layer is further provided on the gate electrode.
  • the interconnection layer is formed by depositing on the gate by a chemical vapor deposition process, and the material selected for the interconnection layer is one or a combination of SiOx and SiNx.
  • a source contact hole formed in a portion of the interconnect layer corresponding to the source contact region to expose a portion of the source contact region; a region corresponding to the drain contact region in the interconnect layer a drain contact hole that exposes a portion of the drain contact region.
  • the source contact hole and the drain contact hole are formed by a photolithography process.
  • a second metal layer is deposited in the source contact hole and the drain contact hole, and photolithography is performed on the second metal layer to obtain a source and a drain, respectively;
  • a source contact hole is in contact with the source contact region; and the drain is in contact with the drain contact region through the drain contact hole.
  • the present invention also provides the use of the above metal oxide thin film transistor for preparing an LCD, OLED display panel.
  • the oxide film layer is patterned by the first photomask to form an oxide active layer.
  • the first metal layer is patterned by a second photomask to form a gate electrode, and the process requires two photomasks.
  • a film layer structure such as an oxide film layer and a first metal layer is sequentially formed, and then a patterning process on the oxide film layer and the first metal layer can be completed using only one photomask, so that The oxide active layer and the gate are respectively formed, thereby reducing a mask, thereby simplifying the process process, saving process time, and effectively reducing the production cost.
  • the process characteristics of the wet etching and the dry etching are fully utilized, and different etching processes are respectively applied to the oxide active layer, the gate electrode and the gate insulating layer, thereby realizing the use of one light.
  • the lithography process of the mask completes the patterning process of the oxide active layer and the gate, respectively.
  • the gate can be directly used as a protective layer to insulate the gate which is not in the protective region.
  • the layer and buffer layer portions are etched.
  • the process can etch away the excess structure of the gate insulating layer, expose a portion of the active layer, and subsequently form a source-drain contact region; without affecting the performance of other structures, only a part of the buffer layer is etched away.
  • the structure is such that the buffer layer forms a certain step. This approach saves process and reduces production costs.
  • 1 to 8 are process flows of a method of fabricating a metal oxide thin film transistor according to an embodiment of the present invention.
  • the embodiment provides a method for manufacturing a metal oxide thin film transistor, comprising the following steps:
  • a substrate 1 is provided.
  • a SiOx film layer is formed on the substrate 1 by a chemical vapor deposition process, and the SiOx film layer is a buffer layer 2; a IGZO oxide film layer 31 is deposited on the buffer layer 2 by a physical deposition process; A vapor deposition process is performed on the IGZO oxide film layer 31 to form a gate insulating layer 4; a first metal layer 51 is deposited on the gate insulating layer 4 by a physical deposition process. That is, a buffer layer, an oxide film layer, a gate insulating layer and a first metal layer are sequentially formed on the substrate by a chemical or physical vapor deposition process, and after forming the film layer, the film layers are further photolithographically engraved and engraved. Eclipse process.
  • a photoresist layer 100 is deposited on the first metal layer 51 by spin coating or printing, and exposed by an exposure machine to form a photoresist pattern into a desired pattern.
  • the pattern required here refers to a pattern required to form a pattern for subsequently processing a film layer such as a first metal layer and an IGZO film layer on the photoresist layer.
  • the patterned photoresist layer 100 is also subjected to a post-baking operation to make it more robust to prevent the photoresist from being deformed in subsequent processes.
  • the first metal layer 51 is etched by a wet etching process to control the time of the wet etching to form a patterned first metal layer, that is, the gate electrode 52. Since the wet etching has the characteristics of isotropic, it is easy to over-etch the gate under the photoresist, so that the size of the gate pattern after the wet etching is smaller than the pattern size of the photoresist.
  • the gate insulating layer 4 and the IGZO film layer 31 are respectively etched by a dry etching process to form a patterned gate insulating layer 4 and a patterned IGZO film layer, and the patterned IGZO layer is formed.
  • the film layer is the oxide active layer 32. It should be noted that the purpose of dry etching the gate insulating layer in this step is to form a gate insulating layer having a certain pattern.
  • the photoresist layer 100 is ashed and removed by O 2 using a plasma processing technique.
  • the gate insulating layer 4 is dry etched by using the gate electrode 52 as a protective layer.
  • the gate insulating layer 4 under the gate electrode 52 can be roughly divided into a first gate insulating layer 41 in the gate protection region and an exposed second gate insulating layer 42 outside the gate protection region.
  • the gate insulating layer 4 is dry etched, since the first gate insulating layer 41 is in the protective region of the gate electrode 52, it is not etched away; in contrast, since the second gate insulating layer 42 is at Protection of the gate 52 Outside of the area, the portion of the film is exposed to the outside and is thus etched away during the etching process.
  • the purpose of dry etching the gate insulating layer in this step is to remove excess gate insulating layer and expose part of the oxide active layer 32, the partially exposed oxide active layer. 32 will be used to form the source contact region and the drain contact region in subsequent steps.
  • the buffer layer 2 is dry etched with the oxide active layer 32 as a protective layer.
  • the buffer layer 2 under the oxide active layer may be roughly divided into a first buffer layer 21 in the oxide active layer protection region and an exposed second buffer outside the oxide active layer protection region. Layer 22.
  • the first buffer layer 21 is in the protective region of the oxide active layer 32, it is not etched away; in contrast, since the second buffer layer 22 is in the oxide layer Outside of the protected area of the source layer 32, the portion of the film layer is exposed to the outside, so that a portion of the second buffer layer 22 is etched away during the etching process.
  • the thickness of the first buffer layer is L
  • the method further includes the following steps: after dry etching the gate insulating layer 4 and the buffer layer 2, for being exposed outside the gate protection region
  • the oxide active layer is subjected to plasma treatment of CF 4 , NH 3 , H 2 or Ar to form a source contact region 61 on the left side of the exposed oxide active layer and a drain contact region 62 on the right side;
  • An interconnect layer 7 made of SiOx is formed on the gate 52 by a chemical vapor deposition process, and the interconnect layer 7 has a gate 52, a first gate insulating layer 41, an oxide active layer 32, a source contact region 61, a drain contact region 62 and a portion of the buffer layer 2 are encapsulated therein;
  • a source contact hole 71 exposing a portion of the source contact region 61 is formed in a region corresponding to the source contact region 61 in the interconnect layer by a photolithography process, corresponding to The region of the drain contact region 62 forms a drain contact
  • an organic photoresist film may be deposited on the interconnect layer by spin coating or printing to form a planarization layer (not shown), and the planarization layer is post-baked;
  • An ITO film layer may be deposited, and the ITO film layer is etched by a photolithography process to obtain a patterned ITO film layer, and the ITO film layer is brought into contact with the drain.
  • the source contact region, the drain contact region, the interconnect layer, the source contact hole, the drain contact hole, and the source are sequentially formed.
  • the techniques of the film structure such as the drain, the planarization layer, and the ITO film layer are prior art in the art, and these layers and layers are The technical solutions in the foregoing embodiments may be used in the manufacturing process, and other technical solutions in the prior art may also be used, and details are not described herein again.
  • a film layer structure such as an oxide film layer and a first metal layer is deposited on the substrate in turn, and then combined with wet etching and dry etching, respectively, the oxide film layer is separately formed.
  • the film layer structure such as the first metal layer is patterned to obtain an oxide active layer and a gate correspondingly. This operation only needs to use a photomask to lithography and etch the first metal layer after forming the first metal layer to realize the purpose of patterning the gate electrode, and subsequently performing the oxide film layer.
  • the same mask can be used for etching to achieve the purpose of patterning. Therefore, compared with the existing related processes, the preparation method of the embodiment can save a mask, save process time and reduce production cost.
  • This embodiment further provides a metal oxide thin film transistor obtained by the above preparation method, as shown in FIG. 8, comprising:
  • the material having a step formed on the substrate 1 is a buffer layer 2 of SiOx;
  • a patterned oxide active layer 32 formed on the buffer layer 2 the oxide active layer being an IGZO film layer, and the patterning is obtained by etching the IGZO film layer by a dry etching process;
  • the oxide is formed on the left side of the active layer 32 of the source contact region 61, the drain contact region on the right side 62, respectively, both using plasma processing using CF4, NH3, H 2 or Ar active oxide layer processing Forming an oxide active layer to improve conductivity;
  • the material formed on the gate is an interconnect layer 7 of SiOx, which interconnects gate 52, gate insulating layer 4, oxide active layer 32, source contact region 61, drain contact region 62, and partial buffer
  • the layer 2 is coated therein; a region corresponding to the source contact region 61 in the interconnection layer is formed with a source contact hole 71 exposing a portion of the source contact region 61, and a region corresponding to the drain contact region 62 by a photolithography process.
  • a drain contact hole 72 exposing a portion of the drain contact region 62 is formed by a photolithography process; a source electrode 81 and a drain electrode 82 are formed in the source contact hole 71 and the drain contact hole 72, respectively; the source 81 passes through the source The contact hole 71 is in contact with the source contact region 61, and the drain 82 is in contact with the drain contact region 62 through the drain contact hole 72.
  • the step difference of the buffer layer 2 is obtained by a dry etching process.
  • the buffer layer 2 under the oxide active layer can be roughly divided into the first buffer layer 21 in the oxide active layer protection region and is oxidized.
  • the buffer layer 2 is dry etched, since the first buffer layer 21 is in the protective region of the oxide active layer 32, it is not etched away; in contrast, since the second buffer layer 22 is in the oxide layer Outside of the protected area of the source layer 32, the portion of the film layer is exposed to the outside, so that a portion of the second buffer layer 22 is etched away during the etching process.
  • the thickness of the first buffer layer is L
  • the gate insulating layer 4 is obtained by two dry etching processes.
  • the first dry etching is to pattern the gate insulating layer
  • the second dry etching is to form the gate insulating layer.
  • the excess is etched away.
  • the gate insulating layer 4 under the gate electrode may be roughly divided into the first gate insulating layer 41 and the gate insulating region.
  • the gate insulating layer 4 When the gate insulating layer 4 is dry etched, since the first gate insulating layer 41 is in the protective region of the gate electrode 52, it is not etched away; in contrast, since the second gate insulating layer 42 is at Outside of the protected area of the gate 52, the portion of the film is exposed to the outside and is thus etched away during the etching process.
  • the metal oxide thin film transistor of this embodiment may further deposit an organic photoresist film on the interconnect layer by spin coating or printing to form a planarization layer (not shown), and post-baking the planarization layer;
  • the ITO film layer is deposited, and the ITO film layer is etched by photolithography to obtain a patterned ITO film layer, and the ITO film layer is in contact with the drain.
  • the source contact region, the drain contact region, the interconnection layer, the source contact hole, the drain contact hole, the source, the drain, the planarization layer, the pixel electrode, and the like in the above metal oxide thin film transistor The layer structures are all prior art in the prior art. These film layers may adopt the technical solutions in the above embodiments, and may also adopt other technical solutions in the prior art, which will not be described in detail herein.
  • the metal oxide thin film transistor may further include other conventional functional structures, which will not be repeatedly described in the present invention.

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Abstract

一种金属氧化物薄膜晶体管及其制造方法，该制备方法包括以下步骤：提供一基板（1）；在基板（1）上依次形成缓冲层（2）、氧化物膜层（31）、栅极绝缘层（4）和第一金属层（51）；采用一道光罩分别对第一金属层（51）、栅极绝缘层（4）、氧化物膜层（31）进行图形化处理，形成栅极（52）、图形化的栅极绝缘层（4）、氧化物有源层（32）。在该制造方法中，对于氧化物有源层和栅极等膜层结构，采用先沉积、后分别刻蚀的方法，仅需使用一道光罩，即可完成对氧化物有源层和栅极等膜层结构的图形化处理过程。由于能够减少使用光罩的数量，因此能够简化工艺制程、节省工艺时间，有效降低生产成本。

Description

金属氧化物薄膜晶体管及其制备方法 技术领域
本发明涉及晶圆制造领域及显示技术领域，具体是一种金属氧化物薄膜晶体管及其制备方法。
背景技术
薄膜晶体管液晶平板显示器是一类有源矩阵液晶显示设备，该类显示屏上的每个液晶像素点都是由集成在像素点后面的薄膜晶体管来驱动，薄膜晶体管(TFT，Thin Film Transistor)对于显示器的响应度及色彩真实度等具有重要影响，是该类显示器中的重要组成部分。常见的薄膜晶体管主要有非晶硅薄膜晶体管(a-Si TFT)、低温多晶硅薄膜晶体管(LTPS TFT)、金属氧化物薄膜晶体管等。其中，采用金属氧化物作为沟道层材料的TFT技术是目前在面板技术领域的研究热点，尤其采用铟镓锌氧化物(IGZO，Indium Gallium Zinc Oxide)的TFT技术，使用该技术可以使显示屏功耗接近OLED，厚度仅比OLED高出25％，且分辨率可以达到全高清(fμll HD，1920*1080P)乃至超高清(ΜltraDefinition，分辨率4k*2k)级别程度，而成本却相对更低。
目前对于金属氧化物薄膜晶体管的制备常用技术包括背沟道刻蚀(back channel etch，BCE)技术、刻蚀阻挡层(etch stopper layer，ESL)技术和自对准的顶栅结构(self-aligned top gate)。在上述制造技术中，较常见的是采用五道掩膜的光刻工艺，最少也需要使用四道掩膜才能完成薄膜晶体管的制作。然而，由于光刻工艺的成本较高，若能减少上述阵列基板制作过程中所使用的掩膜数量，就能够达到简化工艺制程、降低生产成本的目的。
基于上述分析可知，实有必要对于现有的金属氧化物薄膜晶体管的工艺流程进行改进优化。
发明内容
为克服现有技术的不足，本发明的目的在于提供一种金属氧化物薄膜晶体 管及其制备方法，通过对金属氧化物薄膜晶体管的制备方法进行优化和改进，来实现简化工艺流程、降低生产成本的目的。
本发明包括三个方面，第一个方面，本发明提供一种金属氧化物薄膜晶体管的制备方法，包括以下步骤：
S1：提供一基板；
S2：在所述基板上依次形成缓冲层、氧化物膜层、栅极绝缘层和第一金属层；
S3：采用一道光罩对所述第一金属层、所述栅极绝缘层、所述氧化物膜层进行图形化处理，使所述第一金属层图形化形成栅极、使所述栅极绝缘层图形化、使所述氧化物膜层图形化形成氧化物有源层。
【光阻】进一步地，在本发明所述的制备方法中，在所述S2步骤之后、所述S3步骤之前还包括以下步骤，S4：在所述第一金属层上形成光阻层，对所述光阻层进行曝光得到图形化的光阻层。
【光阻-具体】进一步地，所述S4步骤具体为，利用旋涂或打印的方法在所述第一金属层上沉积形成所述光阻层，通过曝光机得到图形化的光阻层之后，对图形化的所述光阻层进行后烘。
【栅极-刻蚀】进一步地，在所述S3步骤中，对所述第一金属层进行图形化处理是以图形化的所述光阻层为遮挡，对所述第一金属层进行刻蚀，使所述第一金属层图形化，形成所述栅极。其中，对所述第一金属层进行刻蚀是采用湿法刻蚀。
【栅极尺寸小于光阻】进一步地，所述栅极的图形尺寸小于所述光阻层的图形尺寸1μm以下。
【栅极绝缘层-刻蚀】进一步地，在所述S3步骤中，对所述栅极绝缘层进行图形化处理是以图形化的所述光阻层为遮挡，对所述栅极绝缘层进行刻蚀，得到图形化的所述栅极绝缘层。其中，对所述栅极绝缘层进行刻蚀是采用干法刻蚀。
【氧化物有源层-刻蚀】进一步地，在所述S3步骤中，对所述氧化物膜层进行图形化处理是以图形化的所述光阻层为遮挡，对所述氧化物膜层进行刻蚀，使所述氧化物膜层图形化，形成所述氧化物有源层。其中，对所述氧化物膜层 进行刻蚀是采用湿法刻蚀或干法刻蚀。
【氧化物有源层-材料】进一步地，所述氧化物膜层为IGZO膜层。其中IGZO是指Indium Gallium Zinc Oxide，即铟镓锌氧化物。
【缓冲层-材料】进一步地，所述缓冲层所选用的材料为SiOx。
【去光阻】进一步地，在本发明所述的制备方法中，在所述S3步骤之后，还包括以下步骤，S5：去除图形化的所述光阻层。
【去光阻-具体】进一步地，所述S5步骤具体为，采用等离子处理技术，利用O2将光阻层灰化去除。
【重要从权：GI、buffer-干刻】进一步地，在本发明所述的制备方法中，在所述S5步骤之后，还包括以下步骤，S6：对图形化的所述栅极绝缘层、所述缓冲层进行刻蚀。其中，对图形化的所述栅极绝缘层、所述缓冲层进行刻蚀是采用干法刻蚀。
【GI干刻-具体】进一步地，对所述栅极绝缘层进行刻蚀是以所述栅极为保护层，将所述栅极绝缘层划分为处于栅极保护区域内的第一栅极绝缘层和处于栅极保护区域外的、暴露的第二栅极绝缘层，将所述第二栅极绝缘层刻蚀掉，保留所述第一栅极绝缘层。
【buffer干刻-具体】进一步地，对所述缓冲层进行刻蚀是以所述氧化物有源层为保护层，将所述缓冲层划分为处于氧化物有源层保护区域内的第一缓冲层和处于氧化物有源层栅极保护区域外的、暴露的第二缓冲层，将所述第二缓冲层的全部或者部分刻蚀掉，保留所述第一缓冲层。
【buffer厚度差】进一步地，设所述第一缓冲层的厚度为L，设所述第二缓冲层被刻蚀掉的部分的厚度为d，则0＜d/L≤1。其中，0＜d/L≤1是指该数值范围内的任一点值，例如d/L＝0.2、d/L＝0.4、d/L＝0.5、d/L＝0.6、d/L＝0.8。
【S/D】进一步地，在本发明的所述制备方法中，在所述S6步骤之后还包括以下步骤，S7：对暴露在所述栅极保护区域之外的所述氧化物有源层进行等离子处理，使暴露在所述栅极保护区域之外的所述氧化物有源层变为导体形成源极接触区和漏极接触区，以便与后续形成的源极、漏极互联，其优点在于能降低接触电阻。
更进一步地，所述等离子处理采用CF4、NH3、H2或Ar进行处理。
【ILD】进一步地，在本发明的所述制备方法中，还包括以下步骤，S8：在所述栅极上形成互联层(interlayer dielectric，ILD)。
更进一步地，利用化学气相沉积工艺在栅极上沉积形成所述互联层，所述互联层选用的材料为SiOx、SiNx中的一种或两种组合。
【接触孔】进一步地，在本发明的所述制备方法中，还包括以下步骤，S9：在所述互联层中对应于所述源极接触区的区域形成使部分所述源极接触区暴露的源极接触孔；在所述互联层中对应于所述漏极接触区的区域形成使部分所述漏极接触区暴露的漏极接触孔。
更进一步地，所述源极接触孔和所述漏极接触孔是采用光刻工艺制得的。
进一步地，在所述源极接触孔、所述漏极接触孔中沉积第二金属层，对所述第二金属层进行光刻，分别得到源极和漏极；所述源极通过所述源极接触孔与所述源极接触区相接触；所述漏极通过所述漏极接触孔与所述漏极接触区相接触。
第二个方面，本发明还提供一种采用上述制备方法制得的金属氧化物薄膜晶体管，包括基板和依次设置在所述基板上的缓冲层、氧化物有源层、栅极绝缘层以及栅极；其中，所述栅极、所述栅极绝缘层、所述氧化物有源层是分别对形成于基板上的第一金属层、栅极绝缘层、氧化物膜层进行图形化处理得到的。
【栅极-刻蚀】进一步地，对所述第一金属层进行图形化处理是以图形化的光阻层为遮挡，对所述第一金属层进行刻蚀，使所述第一金属层图形化，形成所述栅极。其中，对所述第一金属层进行刻蚀是采用湿法刻蚀。
【栅极尺寸小于光阻】进一步地，所述栅极的图形尺寸小于所述光阻层的图形尺寸。
【栅极绝缘层-刻蚀】进一步地，对所述栅极绝缘层进行图形化处理是以图形化的光阻层为遮挡，对所述栅极绝缘层进行刻蚀，得到图形化的所述栅极绝缘层。其中，对所述栅极绝缘层进行刻蚀是采用干法刻蚀。
【氧化物有源层-刻蚀】进一步地，对所述氧化物膜层进行图形化处理是以图形化的光阻层为遮挡，对所述氧化物膜层进行刻蚀，使所述氧化物膜层图形化，形成所述氧化物有源层。其中，对所述氧化物膜层进行刻蚀是采用湿法刻 蚀或干法刻蚀。
【氧化物有源层-材料】进一步地，所述氧化物有源层为IGZO膜层。其中IGZO是指Indium Gallium Zinc Oxide，即铟镓锌氧化物。
【缓冲层-材料】进一步地，所述缓冲层所选用的材料为SiOx。
【干刻-具体】进一步地，在本发明的所述金属氧化物薄膜晶体管中，对图形化的所述栅极绝缘层、所述缓冲层进行刻蚀。其中，对图形化的所述栅极绝缘层、所述缓冲层进行刻蚀是采用干法刻蚀。
【GI干刻-具体】进一步地，对所述栅极绝缘层进行刻蚀是以所述栅极为保护层，将所述栅极绝缘层划分为处于栅极保护区域内的第一栅极绝缘层和处于栅极保护区域外的、暴露的第二栅极绝缘层，将所述第二栅极绝缘层刻蚀掉，保留所述第一栅极绝缘层。
【buffer干刻-具体】进一步地，对所述缓冲层进行刻蚀是以所述氧化物有源层为保护层，将所述缓冲层划分为处于氧化物有源层保护区域内的第一缓冲层和处于氧化物有源层栅极保护区域外的、暴露的第二缓冲层，将所述第二缓冲层的全部或者部分刻蚀掉，保留所述第一缓冲层。
【buffer厚度差】进一步地，设所述第一缓冲层的厚度为L，设所述第二缓冲层被刻蚀掉的部分的厚度差为d，则0＜d/L≤1。其中，0＜d/L≤1是指该数值范围内的任一点值，例如d/L＝0.2、d/L＝0.4、d/L＝0.5、d/L＝0.6、d/L＝0.8。
【S/D】进一步地，在本发明的所述金属氧化物薄膜晶体管中，还设有源极接触区和漏极接触区，所述源极接触区和所述漏极接触区是对暴露在所述栅极保护区域之外的所述氧化物有源层进行等离子处理，使暴露在所述栅极保护区域之外的所述氧化物有源层变为导体形成的。
更进一步地，所述等离子处理采用CF4、NH3、H2或Ar进行处理。
【ILD】进一步地，在本发明的所述金属氧化物薄膜晶体管中，在所述栅极上还设有互联层。
更进一步地，所述互联层是利用化学气相沉积工艺在栅极上沉积形成的，所述互联层选用的材料为SiOx、SiNx中的一种或两种组合。
【接触孔】进一步地，在本发明的所述金属氧化物薄膜晶体管中，还包括 在所述互联层中对应于所述源极接触区的区域形成的使部分所述源极接触区暴露的源极接触孔；在所述互联层中对应于所述漏极接触区的区域形成的使部分所述漏极接触区暴露的漏极接触孔。
更进一步地，所述源极接触孔和所述漏极接触孔是采用光刻工艺制得的。
进一步地，在所述源极接触孔、所述漏极接触孔中沉积第二金属层，对所述第二金属层进行光刻，分别得到源极和漏极；所述源极通过所述源极接触孔与所述源极接触区相接触；所述漏极通过所述漏极接触孔与所述漏极接触区相接触。
第三个方面，本发明还提供一种上述金属氧化物薄膜晶体管的用途，所述金属氧化物薄膜晶体管用于制备LCD、OLED显示面板。
与现有技术相比，本发明的有益效果如下：
以往传统的薄膜晶体管制备方法中，在形成氧化物膜层后，即利用第一道光罩对氧化物膜层进行图形化处理，使其形成氧化物有源层。之后，在形成第一金属层后，再利用第二道光罩对第一金属层进行图形化处理，使其形成栅极，该过程需利用两道光罩。但是在本发明中，首先依次形成了氧化物膜层和第一金属层等膜层结构，然后仅使用一道光罩即能够完成对氧化物膜层和第一金属层的图形化处理，使二者分别形成氧化物有源层和栅极，因此减少了一道光罩，从而简化工艺制程、节省工艺时间，有效降低了生产成本。此外，本发明中充分利用了湿法刻蚀和干法刻蚀的工艺特点，分别对氧化物有源层、栅极和栅极绝缘层采用了不同的刻蚀工艺，因此能够实现利用一道光罩的光刻工艺分别完成对氧化物有源层和栅极的图形化处理。
另外，由于本发明是先在基板上形成各膜层、后对各膜层进行图形化处理，因此在图形化处理之后，能够直接以栅极为保护层，对未处于保护区域内的栅极绝缘层和缓冲层部分进行刻蚀。该过程既可以刻蚀掉栅极绝缘层的多余结构，露出有源层的部分区域，使其后续可形成源漏极接触区；又不影响其它结构的性能，仅会刻蚀掉部分缓冲层的结构，使缓冲层形成一定阶梯差。这种做法能够节约制程，降低生产成本。
附图说明
图1至图8是本发明实施例金属氧化物薄膜晶体管的制造方法的工艺流程。
具体实施方式
实施例
本实施例提供一种金属氧化物薄膜晶体管的制造方法，包括以下步骤：
如图1所示，提供一基板1。
如图2所示，采用化学气相沉积工艺在基板1上沉积形成SiOx膜层，该SiOx膜层为缓冲层2；采用物理沉积工艺在缓冲层2上沉积形成IGZO氧化物膜层31；采用化学气相沉积工艺在IGZO氧化物膜层31上沉积形成栅极绝缘层4；采用物理沉积工艺在栅极绝缘层4上沉积形成第一金属层51。即：利用化学或物理气相沉积工艺在基板上依次形成缓冲层、氧化物膜层、栅极绝缘层和第一金属层，在形成上述膜层之后，再继续对各膜层进行光刻、刻蚀工艺处理。
如图3所示，通过旋涂或打印方法在第一金属层51上沉积形成光阻层100，并通过曝光机曝光，使光阻层形成所需图形。此处所需图形是指在光阻层上形成对后续处理第一金属层和IGZO膜层等膜层的图形化时所需要的图形。对图形化的光阻层100还要进行后烘操作，使其更坚固，以防止光阻在后续工艺中变形。
如图4所示，采用湿法刻蚀工艺对第一金属层51进行刻蚀，控制湿法刻蚀的时间，形成图形化的第一金属层，即为栅极52。由于湿法刻蚀具有各项同性的特点，易于对位于光阻下的栅极形成过刻蚀，从而使湿法刻蚀后的栅极图形尺寸小于光阻的图形尺寸。
如图5所示，采用干法刻蚀工艺分别对栅极绝缘层4、IGZO膜层31进行刻蚀，形成图形化的栅极绝缘层4和图形化的IGZO膜层，该图形化的IGZO膜层即为氧化物有源层32。值得注意的是，在本步骤中对栅极绝缘层进行干法刻蚀的目的在于：形成具有一定图形的栅极绝缘层。
如图6所示，采用等离子处理技术，利用O2将光阻层100灰化、除去。
结合图6、图7所示，以栅极52为保护层，对栅极绝缘层4进行干法刻蚀。具体为：位于栅极52下方的栅极绝缘层4可大致划分为处于栅极保护区域内的第一栅极绝缘层41和处于栅极保护区域外的、暴露的第二栅极绝缘层42。对栅极绝缘层4进行干法刻蚀时，由于第一栅极绝缘层41处于栅极52的保护区域中，因而不被刻蚀掉；与之相反，由于第二栅极绝缘层42处于栅极52的保护 区域之外，该部分膜层是暴露在外面的，因而在刻蚀过程中被刻蚀掉。值得注意的是，在本步骤中对栅极绝缘层进行干法刻蚀的目的在于：除去多余的栅极绝缘层，使部分氧化物有源层32暴露，该部分暴露的氧化物有源层32将在后续步骤中用于形成源极接触区和漏极接触区。
类似地，以氧化物有源层32为保护层，对缓冲层2进行干法刻蚀。具体为：位于氧化物有源层下方的缓冲层2可大致划分为处于氧化物有源层保护区域内的第一缓冲层21和处于氧化物有源层保护区域外的、暴露的第二缓冲层22。对缓冲层2进行干法刻蚀时，由于第一缓冲层21处于氧化物有源层32的保护区域中，因而不被刻蚀掉；与之相反，由于第二缓冲层22处于氧化物有源层32的保护区域之外，该部分膜层是暴露在外面的，因而在刻蚀过程中有部分第二缓冲层22被刻蚀掉。该第一缓冲层的厚度为L，第二缓冲层的被刻蚀掉的部分的厚度为d，d/L＝0.5。
如图8所示，在本实施例的制备方法中，还包括以下步骤：在对栅极绝缘层4和缓冲层2进行干法刻蚀之后，对于处于栅极保护区域之外的、暴露在外的氧化物有源层进行CF4、NH3、H2或Ar的等离子处理，使暴露在外的氧化物有源层的左侧形成源极接触区61、右侧形成漏极接触区62；在栅极52上基于化学气相沉积工艺沉积形成以SiOx为材料的互联层7，该互联层7将栅极52、第一栅极绝缘层41、氧化物有源层32、源极接触区61、漏极接触区62以及部分缓冲层2包覆在其中；采用光刻工艺在互联层中对应于源极接触区61的区域形成使部分源极接触区61暴露的源极接触孔71、对应于漏极接触区62的区域形成使部分漏极接触区62暴露的漏极接触孔72；在源极接触孔71、漏极接触孔72中及互联层上沉积形成第二金属层，并对第二金属层进行光刻，分别形成源极81和漏极82；源极81通过源极接触孔71与源极接触区61相接触，漏极82通过漏极接触孔72与漏极接触区62相接触。
进一步地，本实施例中还可以在互联层上采用旋涂或打印的方法沉积有机光阻膜，形成平坦化层(图未示)，并对该平坦化层进行后烘；本实施例还可以沉积ITO膜层，并采用光刻工艺对ITO膜层进行刻蚀得到图形化的ITO膜层，并将ITO膜层与漏极相接触。
可以理解的是，在对栅极绝缘层和缓冲层进行干法刻蚀之后，再依次形成源极接触区、漏极接触区、互联层、源极接触孔、漏极接触孔、源极、漏极、平坦化层、ITO膜层等膜层结构的技术为本领域的现有技术，这些膜层以及膜层 的制作技术可以采用上述实施例中的技术方案，也可以采用其它现有技术中的技术方案，在此不再一一详述。
在本实施例中，首先在基板上依次先沉积形成氧化物膜层和第一金属层等膜层结构，然后再结合湿法刻蚀和干法刻蚀的工艺特点，分别对氧化物膜层和第一金属层等膜层结构进行图形化处理，相应得到氧化物有源层和栅极。这种操作只需要在形成了第一金属层之后，使用一道光罩对第一金属层进行光刻、刻蚀的工艺，来实现其图形化形成栅极的目的，后续对氧化物膜层进行图形化处理时，仍以同样的光罩进行刻蚀即能够达到图形化的目的。因此与现有的相关工艺比较，本实施例的制备方法可节省一道光罩，节省工艺制程时间、降低生产成本。
本实施例还提供一种采用上述制备方法制得的金属氧化物薄膜晶体管，如图8所示，包括：
基板1；
形成于基板1上的具有阶梯差的材料为SiOx的缓冲层2；
形成于缓冲层2上的图形化的氧化物有源层32，该氧化物有源层为IGZO膜层，图形化是通过干法刻蚀工艺对IGZO膜层进行刻蚀得到的；
形成于氧化物有源层32左侧的源极接触区61、右侧的漏极接触区62，二者分别是采用等离子处理技术利用CF4、NH3、H2或Ar处理氧化物有源层后，使氧化物有源层的导电性提高从而形成的；
形成于氧化物有源层32上方的图形化的栅极绝缘层4；
形成于栅极绝缘层4上的图形化的栅极52，该图形是通过湿法刻蚀工艺对第一金属层进行刻蚀后得到的；
形成于栅极上的材料为SiOx的互联层7，该互联层7将栅极52、栅极绝缘层4、氧化物有源层32、源极接触区61、漏极接触区62以及部分缓冲层2包覆在其中；在互联层中对应于源极接触区61的区域通过光刻工艺形成有使部分源极接触区61暴露的源极接触孔71、对应于漏极接触区62的区域通过光刻工艺形成有使部分漏极接触区62暴露的漏极接触孔72；在源极接触孔71、漏极接触孔72中分别形成有源极81和漏极82；源极81通过源极接触孔71与源极接触区61相接触，漏极82通过漏极接触孔72与漏极接触区62相接触。
其中，缓冲层2的阶梯差是利用干法刻蚀工艺得到的。如图6所示，对缓冲层2进行干法刻蚀之前，位于氧化物有源层下方的缓冲层2可大致划分为处于氧化物有源层保护区域内的第一缓冲层21和处于氧化物有源层保护区域外的、暴露的第二缓冲层22。对缓冲层2进行干法刻蚀时，由于第一缓冲层21处于氧化物有源层32的保护区域中，因而不被刻蚀掉；与之相反，由于第二缓冲层22处于氧化物有源层32的保护区域之外，该部分膜层是暴露在外面的，因而在刻蚀过程中有部分第二缓冲层22被刻蚀掉。该第一缓冲层的厚度为L，第二缓冲层的被刻蚀掉的部分的厚度为d，d/L＝0.5。
其中，栅极绝缘层4是经过两次干法刻蚀得到的，第一次干法刻蚀是把栅极绝缘层进行图形化处理，第二次干法刻蚀是将栅极绝缘层的多余部分刻蚀掉。具体地，在进行第二次干法刻蚀时，如图6所示，位于栅极下方的栅极绝缘层4可大致划分为处于栅极保护区域内的第一栅极绝缘层41和处于栅极保护区域外的、暴露的第二栅极绝缘层42。对栅极绝缘层4进行干法刻蚀时，由于第一栅极绝缘层41处于栅极52的保护区域中，因而不被刻蚀掉；与之相反，由于第二栅极绝缘层42处于栅极52的保护区域之外，该部分膜层是暴露在外面的，因而在刻蚀过程中被刻蚀掉。
本实施例的金属氧化物薄膜晶体管还可以在互联层上采用旋涂或打印的方法沉积有机光阻膜，形成平坦化层(图未示)，并对该平坦化层进行后烘；还可以沉积ITO膜层，并采用光刻工艺对ITO膜层进行刻蚀得到图形化的ITO膜层，并将ITO膜层与漏极相接触。
可以理解的是，上述金属氧化物薄膜晶体管中的源极接触区、漏极接触区、互联层、源极接触孔、漏极接触孔、源极、漏极、平坦化层、像素电极等膜层结构均为本领域的现有技术，这些膜层可以采用上述实施例中的技术方案，也可以采用其它现有技术中的技术方案，在此不再一一详述。
以上仅对金属氧化物薄膜晶体管的主体结构进行了说明，该金属氧化物薄膜晶体管还可以包括其它常规的功能结构，在本发明中不再一一赘述。
以上所述为本发明的具体实施方式，其目的是为了清楚说明本发明而作的举例，并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (10)

  1. 一种金属氧化物薄膜晶体管的制备方法，其中，所述制备方法包括以下步骤：
    S1：提供一基板；
    S2：在所述基板上依次形成缓冲层、氧化物膜层、栅极绝缘层和第一金属层；
    S3：采用一道光罩分别对所述第一金属层、所述栅极绝缘层、所述氧化物膜层进行图形化处理，使所述第一金属层图形化形成栅极、使所述栅极绝缘层图形化、使所述氧化物膜层图形化形成氧化物有源层。
  2. 如权利要求1所述的制备方法，其中：在所述S2步骤之后、所述S3步骤之前还包括以下步骤，S4：在所述第一金属层上形成光阻层，对所述光阻层进行曝光得到图形化的光阻层。
  3. 如权利要求2所述的制备方法，其中：在所述S3步骤中，对所述第一金属层进行图形化处理是以图形化的所述光阻层为遮挡，对所述第一金属层进行刻蚀，使所述第一金属层图形化，形成所述栅极，其宽度小于其上光阻的宽度1μm以上；对所述氧化物膜层进行图形化处理是以图形化的所述光阻层为遮挡，对所述栅绝缘层和氧化物膜层进行连续刻蚀，使所述氧化物膜层图形化，形成所述氧化物有源层。
  4. 如权利要求2所述的制备方法，其中：在所述S3步骤之后，还包括以下步骤，S5：去除图形化的所述光阻层。
  5. 如权利要求2所述的制备方法，其中：在所述S5步骤之后，还包括以下步骤，S6：对图形化的所述栅极绝缘层、所述缓冲层进行刻蚀。
  6. 如权利要求2所述的制备方法，其中：对所述栅极绝缘层进行刻蚀是以所述栅极为保护层，将所述栅极绝缘层划分为处于栅极保护区域内的第一栅极绝缘层和处于栅极保护区域外的、暴露的第二栅极绝缘层，将所述第二栅极绝缘层刻蚀掉，保留所述第一栅极绝缘层。
  7. 如权利要求6所述的制备方法，其中：对所述缓冲层进行刻蚀是以所述氧化物有源层为保护层，将所述缓冲层划分为处于氧化物有源层保护区域内的第一缓冲层和处于氧化物有源层栅极保护区域外的、暴露的第二缓冲层，将所述第二缓冲层的全部或者部分刻蚀掉，保留所述第一缓冲层。
  8. 如权利要求6所述的制备方法，其中：设所述第一缓冲层的厚度为L，设所述第二缓冲层被刻蚀掉的部分的厚度为d，0＜d/L≤1。
  9. 一种金属氧化物薄膜晶体管，其中：所述金属氧化物薄膜晶体管是采用如权利要求1所述的制备方法制得的。
  10. 一种如权利要求1所述的制备方法制得的金属氧化物薄膜晶体管的用途，其中：金属氧化物薄膜晶体管用于制备LCD、OLED显示面板。
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CN103928406A (zh) * 2014-04-01 2014-07-16 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板、显示装置
CN104681627A (zh) * 2015-03-10 2015-06-03 京东方科技集团股份有限公司 阵列基板、薄膜晶体管及制作方法、显示装置

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