CN107464836B - 一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管 - Google Patents

一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管 Download PDF

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CN107464836B
CN107464836B CN201710592932.3A CN201710592932A CN107464836B CN 107464836 B CN107464836 B CN 107464836B CN 201710592932 A CN201710592932 A CN 201710592932A CN 107464836 B CN107464836 B CN 107464836B
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photoresist pattern
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film transistor
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CN107464836A (zh
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宋利旺
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Abstract

本发明提供一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管，通过形成第一光阻图案，该第一光阻图案包括第一遮挡部以及第二遮挡部，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，从而使得栅极图形与导电沟道的沟道区尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。

Description

一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
技术领域
本发明涉及显示技术领域，尤其涉及一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管。
背景技术
薄膜晶体管按照结构不同可以分为底栅型薄膜晶体管和顶栅型薄膜晶体管，其中，顶栅型薄膜晶体管可以显著减小源漏极和栅极之间形成的寄生电容，从而提高薄膜晶体管的开态电流，进而提高器件的工作速度，有利于器件尺寸的缩小，所以近年来成为行业研究的热点。
但是，在现有的顶栅型薄膜晶体管的制作方法中，形成栅极图形的步骤具体为：形成一栅极金属层，并对栅极金属层进行蚀刻。然而，在对栅极金属层进行蚀刻的过程中容易导致金属过蚀刻，从而使得栅极图形的宽度小于导电沟道的沟道区的宽度，进而使得栅极并不能够完全控制导电沟道，使得源漏电极间电流减小，薄膜晶体管器件性能下降。
故，有必要提供一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管，以解决现有技术所存在的问题。
发明内容
本发明的目的在于提供一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管，以提高栅极对导电沟道的控制力，进而提高器件的性能。
本发明提供一种顶栅型薄膜晶体管的制作方法，其包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程；
所述在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体为：
在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部在所述基板上的投影与所述沟道区在所述基板上的投影重合，所述第一遮挡部的厚度大于所述第二遮挡部的厚度；
以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道。
本发明的顶栅型薄膜晶体管的制作方法中，所述栅极图形在所述基板上的投影与所述沟道区在所述基板上的投影重合。
本发明的顶栅型薄膜晶体管的制作方法中，所述对所述光阻层进行图案化处理，以形成第一光阻图案的步骤包括：
采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成所述第一光阻图案。
本发明的顶栅型薄膜晶体管的制作方法中，可使用氧气对所述第一光阻图案的第二遮挡部进行灰化处理。
本发明的顶栅型薄膜晶体管的制作方法中，所述有源层的材料为铟镓锌氧化物或非晶硅。
本发明的顶栅型薄膜晶体管的制作方法中，所述制作方法还包括：形成层间绝缘层、源极、及漏极的过程；
所述形成层间绝缘层、源极、及漏极的过程具体为：
剥离所述第二光阻图案；
在所述栅极图形、源极接触区和漏极接触区上形成层间绝缘层和贯穿所述层间绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述源极接触区和漏极接触区；
在所述层间绝缘层上形成源极与漏极，所述源极与漏极分别通过所述第一过孔和第二过孔与所述源极接触区和漏极接触区接触。
本发明的顶栅型薄膜晶体管的制作方法中，所述剥离所述第二光阻图案的步骤具体为：将所述第二光阻图案浸泡在剥离液中。
本发明的顶栅型薄膜晶体管的制作方法中，所述栅极绝缘层的材料分别包括氧化硅与氮化硅中的一种或多种。
本发明的顶栅型薄膜晶体管的制作方法中，可使用等离子气体对所述有源层进行导体化。
依据本发明的上述目的，还提供一种薄膜晶体管，采用以上所述的方法制成。
本发明的顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管，通过形成第一光阻图案，该第一光阻图案包括第一遮挡部以及第二遮挡部，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，从而使得栅极图形与导电沟道的沟道区尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法的流程图；
图2A-2F为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中在基板上形成导电沟道、栅极绝缘层和栅极图形的过程示意图；
图3A-3C为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中形成层间绝缘层、源极、及漏及的过程示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明优选实施例提供一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管，通过形成第一光阻图案并以第一光阻图案作为罩幕对栅极金属层进行蚀刻，以及形成第二光阻图案并以第二光阻图案作为罩幕对栅极绝缘层进行蚀刻，从而使得栅极图形、栅极绝缘层、及导电沟道的沟道区在基板上的投影重合，提高了栅极对导电沟道的控制力。
参阅图1,图1为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法的流程图。如图1所示，本发明优选实施例提供了一种顶栅型薄膜晶体管的制作方法，该方法旨在提高栅极对导电沟道的控制力，其具体是通过精密控制形成的栅极图形与导电沟道的沟道区的尺寸吻合而实现。
下面将结合具体实施例对该顶栅型薄膜晶体管的制作方法作详细描述，该方法包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程，进一步的，在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体包括以下步骤：
步骤S101，在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
步骤S102，在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
步骤S103，对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部的投影与所述沟道区重合，所述第一遮挡区的厚度大于所述第二遮挡区的厚度；
步骤S104，以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
步骤S105，对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
步骤S106，以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
步骤S107，对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道。
需要说明的是，本发明的顶栅型薄膜晶体管的制作方法，为了抑制形成栅极图形时金属过蚀刻，造成栅极与导电沟道的沟道区尺寸不吻合，其通过形成第一光阻图案，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，形成一尺寸与导电沟道的沟道区吻合的栅极，进而提高栅极对导电沟道的控制力，提高器件的性能。
下面结合图2A-2F来详细说明制作顶栅型薄膜晶体管的过程。图2A-2F为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中在基板上形成导电沟道、栅极绝缘层和栅极图形的过程示意图。
在步骤S101中，如图2A所示，在基板201上形成有源层202，该有源层202包括源区2021、漏区2022、及沟道区2023，其中，该有缘层202的材料为铟镓锌氧化物或非晶硅。更具体的，本优选实施例通过在基板201上沉积有缘源层202，然后通过图形化工艺定义出本优选实施例的顶栅型薄膜晶体管的源区2021、漏区2022、及沟道区2023。需要指出的是，该图形化工艺至少包括光刻胶涂覆或滴注、曝光、显影、光刻刻蚀等步骤，这些步骤均属于本领域常用手段，在此不做赘述。
在步骤S102中，如图2B所示，在该有源层202上依次形成栅极绝缘层203、栅极金属层204、及光阻层205。优选的，该栅极绝缘层203的材料包括氧化硅与氮化硅中的一种或多种。需要指出的是，步骤S102仅仅只是在有源层202上沉积栅极绝缘层203、栅极金属层204、及光阻层205，而形成栅极绝缘层203、栅极金属层204、及光阻层205可通过本领域技术人员熟知的沉积方式进行，在此不做赘述。
在步骤S103中，结合图2B、2C所示，对光阻层205进行图案化处理，以形成第一光阻图案2051，其中，第一光阻图案2051包括第一遮挡部20511以及设置在第一遮挡部20511两侧的第二遮挡部20512，且第一遮挡部20511在基板201上的投影与沟道区2023在基板201上的投影重合，第一遮挡部20511的厚度大于第二遮挡部201512的厚度。
更具体的，在步骤S103中，对光阻层205进行图案化处理，以形成第一光阻图案2051的步骤包括：采用半色调掩膜对该光阻层205进行曝光，并用显影夜对曝光后的光阻层205进行显影，从而形成第一光阻图案2051。
在步骤S104中，结合图2C、2D所示，以第一光阻图案2051作为罩幕，对栅极金属层204进行蚀刻，以形成栅极图形2041。需要指出的是，在步骤S104中，可通过本领域技术人员熟知的蚀刻方式对栅极金属层204进行蚀刻，在此不做赘述，而本发明强调的是，形成的栅极图形2041与沟道区2023吻合，即栅极图形2041在基板201上的投影与沟道区2023在基板201上的投影重合。
在步骤S105中，如图2E所示，对第一光阻图案2051的第二遮挡部20512进行灰化处理，以去除第一光阻图案2051的第二遮挡部20512，形成第二光阻图案2052。具体的，在步骤103中通过形成第一光阻图案2051的第二遮挡部20512，以使得形成的栅极图形2041不会受金属过蚀刻的影响而出现尺寸与沟道区2023不吻合的现象，但在步骤S105中，为使栅极绝缘层203的尺寸与栅极图形2041的尺寸一致，需去除第一光阻图案2051的第二遮挡部20512。
优选的，可使用氧气对第一光阻图案2051的第二遮挡部20512进行灰化处理。
在步骤S106中，结合图2E、2F所示，以第二光阻图案2052作为罩幕，对栅极绝缘层203进行蚀刻，以裸露出源区2021和漏区2022。
在步骤S107中，如图2F所示，对有源层进行导体化，以在源区2021上形成源极接触区、及在漏区2022上形成漏极接触区，其中，该源极接触区、漏极接触区、及沟道区2023形成导电沟道。优选的，可使用等离子气体对所述有源层进行导体化。
更进一步的，参阅图3A-3C，图3A-3C为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中形成层间绝缘层、源极、及漏及的过程示意图。本优选实施例提供的顶栅型薄膜晶体管的制作方法，还包括：形成层间绝缘层、源极、及漏极的过程，该形成层间绝缘层、源极、及漏极的过程具体为：
首先，结合图2F、3A所示，剥离第二光阻图案2052；
随后，如图3B所示，在栅极图形2041、源极接触区和漏极接触区上形成层间绝缘层206和贯穿层间绝缘层206的第一过孔2061和第二过孔2062，第一过孔2061和第二过孔2062分别暴露出源极接触区和漏极接触区；
最后，结合图3B、3C所示，在层间绝缘层206上形成源极2071与漏极2072，源极2071与漏极2072分别通过第一过孔2061和第二过孔2062与源极接触区和漏极接触区接触。
优选的，可通过将第二光阻图案浸泡在剥离液中，以剥离第二光阻图案。
本优选实施例的顶栅型薄膜晶体管的制作方法，通过形成第一光阻图案，该第一光阻图案包括第一遮挡部以及第二遮挡部，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，从而使得栅极图形与导电沟道的沟道区尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。
本发明还提供一种顶栅型薄膜晶体管，其采用以上所述的顶栅型薄膜晶体管的制作方法制成，其结构特征在于：栅极图形与导电沟道的沟道区尺寸吻合，具体可参照上述顶栅型薄膜晶体管的制作方法的优选实施例制成的顶栅型薄膜晶体管，在此不做赘述。
本发明的顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管，通过形成第一光阻图案，该第一光阻图案包括第一遮挡部以及第二遮挡部，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，从而使得栅极图形与导电沟道的沟道区尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。
综上，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (8)

1.一种顶栅型薄膜晶体管的制作方法，其特征在于，包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程；
所述在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体为：
在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部在所述基板上的投影与所述沟道区在所述基板上的投影重合，所述第一遮挡部的厚度大于所述第二遮挡部的厚度；
以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道；
所述栅极图形在所述基板上的投影与所述沟道区在所述基板上的投影重合。
2.根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其特征在于，所述对所述光阻层进行图案化处理，以形成第一光阻图案的步骤包括：
采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成所述第一光阻图案。
3.根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其特征在于，可使用氧气对所述第一光阻图案的第二遮挡部进行灰化处理。
4.根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其特征在于，所述有源层的材料为铟镓锌氧化物或非晶硅。
5.根据权利要求1所述顶栅型薄膜晶体管的制作方法，其特征在于，所述制作方法还包括：形成层间绝缘层、源极、及漏极的过程；
所述形成层间绝缘层、源极、及漏极的过程具体为：
剥离所述第二光阻图案；
在所述栅极图形、源极接触区和漏极接触区上形成层间绝缘层和贯穿所述层间绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述源极接触区和漏极接触区；
在所述层间绝缘层上形成源极与漏极，所述源极与漏极分别通过所述第一过孔和第二过孔与所述源极接触区和漏极接触区接触。
6.根据权利要求5所述的顶栅型薄膜晶体管的制作方法，其特征在于，所述剥离所述第二光阻图案的步骤具体为：将所述第二光阻图案浸泡在剥离液中。
7.根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其特征在于，所述栅极绝缘层的材料分别包括氧化硅与氮化硅中的一种或多种。
8.根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其特征在于，可使用等离子气体对所述有源层进行导体化。
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KR101143005B1 (ko) * 2004-12-14 2012-05-08 삼성전자주식회사 마스크 및 이를 이용한 반도체 소자의 제조 방법 및 박막트랜지스터 표시판의 제조 방법
KR101206038B1 (ko) * 2006-12-18 2012-11-28 삼성전자주식회사 박막 트랜지스터의 제조방법
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KR20130111872A (ko) * 2012-04-02 2013-10-11 삼성디스플레이 주식회사 박막 트랜지스터, 이를 포함하는 박막 트랜지스터 표시판 및 그 제조 방법
CN102723269B (zh) * 2012-06-21 2015-04-01 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
KR102039424B1 (ko) * 2012-06-22 2019-11-01 엘지디스플레이 주식회사 산화물 박막 트랜지스터의 제조방법
KR101454190B1 (ko) * 2012-12-07 2014-11-03 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
CN103227148B (zh) * 2013-04-02 2015-12-23 京东方科技集团股份有限公司 一种阵列基板制备方法及阵列基板和显示装置
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KR102458907B1 (ko) * 2015-12-29 2022-10-25 엘지디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN105762195B (zh) * 2016-03-04 2019-07-26 武汉华星光电技术有限公司 金属氧化物薄膜晶体管及其制备方法

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