WO2019015054A1 - 一种顶栅型薄膜晶体管的制作方法 - Google Patents

一种顶栅型薄膜晶体管的制作方法 Download PDF

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Publication number
WO2019015054A1
WO2019015054A1 PCT/CN2017/101162 CN2017101162W WO2019015054A1 WO 2019015054 A1 WO2019015054 A1 WO 2019015054A1 CN 2017101162 W CN2017101162 W CN 2017101162W WO 2019015054 A1 WO2019015054 A1 WO 2019015054A1
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Prior art keywords
gate
photoresist pattern
thin film
film transistor
drain
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PCT/CN2017/101162
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English (en)
French (fr)
Inventor
宋利旺
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to JP2020500627A priority Critical patent/JP2020526043A/ja
Priority to US15/742,153 priority patent/US10204942B1/en
Priority to KR1020207004739A priority patent/KR102228288B1/ko
Priority to EP17918145.8A priority patent/EP3657547A4/en
Publication of WO2019015054A1 publication Critical patent/WO2019015054A1/zh

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a top gate thin film transistor.
  • the thin film transistor can be divided into a bottom gate type thin film transistor and a top gate type thin film transistor according to different structures, wherein the top gate type thin film transistor can significantly reduce the parasitic capacitance formed between the source drain and the gate, thereby improving the opening of the thin film transistor.
  • the state current which in turn increases the operating speed of the device, is conducive to the reduction of device size, so it has become a hot spot in the industry in recent years.
  • the step of forming a gate pattern is specifically: forming a gate metal layer and etching the gate metal layer.
  • the metal is over-etched, so that the width of the gate pattern is smaller than the width of the channel region of the conductive channel, so that the gate does not completely control the conductive channel. The current between the source and drain electrodes is reduced, and the performance of the thin film transistor device is degraded.
  • the present invention provides a method of fabricating a top gate thin film transistor including a process of forming a conductive channel, a gate insulating layer, and a gate pattern on a substrate;
  • the process of forming a conductive channel, a gate insulating layer and a gate pattern on a substrate is specifically:
  • the active layer including a source region, a drain region, and a channel region
  • the first photoresist pattern includes a first shielding portion and a second shielding portion disposed on opposite sides of the first shielding portion, And the projection of the first shielding portion on the substrate coincides with the projection of the channel region on the substrate, and the thickness of the first shielding portion is greater than the thickness of the second shielding portion;
  • a projection of the gate pattern on the substrate coincides with a projection of the channel region on the substrate; a second occlusion portion of the first photoresist pattern may be ashed using oxygen.
  • the step of patterning the photoresist layer to form the first photoresist pattern comprises:
  • the photoresist layer is exposed using a halftone mask, and the exposed photoresist layer is developed with a developer to form the first photoresist pattern.
  • the material of the active layer is indium gallium zinc oxide or amorphous silicon.
  • the manufacturing method further includes: a process of forming an interlayer insulating layer, a source, and a drain;
  • the process of forming the interlayer insulating layer, the source, and the drain is specifically as follows:
  • a source and a drain are formed on the interlayer insulating layer, and the source and the drain are in contact with the source contact region and the drain contact region through the first via and the second via, respectively.
  • the step of stripping the second photoresist pattern is specifically: immersing the second photoresist pattern in a stripping solution.
  • the material of the gate insulating layer includes one or more of silicon oxide and silicon nitride, respectively.
  • the active layer can be electrically conductive using a plasma gas.
  • the present invention also provides a method of fabricating a top gate thin film transistor, comprising the steps of forming a conductive channel, a gate insulating layer, and a gate pattern on a substrate;
  • the process of forming a conductive channel, a gate insulating layer and a gate pattern on a substrate is specifically:
  • the active layer including a source region, a drain region, and a channel region
  • the first photoresist pattern includes a first shielding portion and a second shielding portion disposed on opposite sides of the first shielding portion, And the projection of the first shielding portion on the substrate coincides with the projection of the channel region on the substrate, and the thickness of the first shielding portion is greater than the thickness of the second shielding portion;
  • the projection of the gate pattern on the substrate coincides with the projection of the channel region on the substrate.
  • the step of patterning the photoresist layer to form the first photoresist pattern comprises:
  • the photoresist layer is exposed using a halftone mask, and the exposed photoresist layer is developed with a developer to form the first photoresist pattern.
  • the second shielding portion of the first photoresist pattern may be subjected to ashing treatment using oxygen.
  • the material of the active layer is indium gallium zinc oxide or amorphous silicon.
  • the manufacturing method further includes: a process of forming an interlayer insulating layer, a source, and a drain;
  • the process of forming the interlayer insulating layer, the source, and the drain is specifically as follows:
  • a source and a drain are formed on the interlayer insulating layer, and the source and the drain are in contact with the source contact region and the drain contact region through the first via and the second via, respectively.
  • the step of stripping the second photoresist pattern is specifically: immersing the second photoresist pattern in a stripping solution.
  • the material of the gate insulating layer includes one or more of silicon oxide and silicon nitride, respectively.
  • the active layer can be electrically conductive using a plasma gas.
  • the first photoresist pattern includes a first shielding portion and a second shielding portion, and the first photoresist pattern is used as a mask to the gate.
  • the electrode metal layer is etched such that the gate pattern conforms to the channel region size of the conductive channel, thereby improving the control force of the gate on the conductive channel, thereby improving the performance of the device.
  • FIG. 1 is a flow chart of a method for fabricating a top gate thin film transistor according to a preferred embodiment of the present invention
  • 2A-2F are schematic diagrams showing processes of forming a conductive channel, a gate insulating layer, and a gate pattern on a substrate in a method of fabricating a top-gate thin film transistor according to a preferred embodiment of the present invention
  • 3A-3C are schematic diagrams showing processes of forming an interlayer insulating layer, a source, and a drain in a method of fabricating a top-gate thin film transistor according to a preferred embodiment of the present invention.
  • a preferred embodiment of the present invention provides a method for fabricating a top gate thin film transistor and a top gate thin film transistor, which is formed by forming a first photoresist pattern and etching the gate metal layer with the first photoresist pattern as a mask.
  • the second photoresist pattern etches the gate insulating layer with the second photoresist pattern as a mask, so that the projections of the gate pattern, the gate insulating layer, and the channel region of the conductive channel on the substrate coincide
  • the gate has a control force on the conductive channel.
  • FIG. 1 is a flow chart of a method for fabricating a top gate thin film transistor according to a preferred embodiment of the present invention.
  • a preferred embodiment of the present invention provides a method for fabricating a top gate thin film transistor, which is intended to improve the control force of a gate on a conductive channel, which is specifically a gate pattern formed by precise control. This is achieved by matching the size of the channel region of the conductive channel.
  • the method for fabricating the top gate thin film transistor will be described in detail below in conjunction with a specific embodiment, the method comprising the steps of forming a conductive channel, a gate insulating layer and a gate pattern on a substrate, and further, forming a conductive layer on the substrate.
  • the process of the channel, the gate insulating layer and the gate pattern specifically includes the following steps:
  • Step S101 forming an active layer on the substrate, the active layer including a source region, a drain region, and a channel region;
  • Step S102 sequentially forming a gate insulating layer, a gate metal layer, and a photoresist layer on the active layer;
  • Step S103 performing patterning processing on the photoresist layer to form a first photoresist pattern, wherein the first photoresist pattern includes a first shielding portion and a second portion disposed on two sides of the first shielding portion a shielding portion, and a projection of the first shielding portion coincides with the channel region, wherein a thickness of the first shielding region is greater than a thickness of the second shielding region;
  • Step S104 using the first photoresist pattern as a mask, etching the gate metal layer to form a gate pattern
  • Step S105 performing ashing treatment on the second shielding portion of the first photoresist pattern to remove the second shielding portion of the first photoresist pattern to form a second photoresist pattern;
  • Step S106 using the second photoresist pattern as a mask, etching the gate insulating layer to expose the source region and the drain region;
  • Step S107 conducting the active layer to form a source contact region on the source region and forming a drain contact region on the drain region, wherein the source contact region and the drain The contact region and the channel region form a conductive channel.
  • the size of the channel region of the gate and the conductive channel does not match, and the first photoresist is formed by the first photoresist. Patterning, and etching the gate metal layer with the first photoresist pattern as a mask to form a gate having a size matching the channel region of the conductive channel, thereby improving the control force of the gate on the conductive channel and improving The performance of the device.
  • FIGS. 2A-2F are schematic diagrams showing processes of forming a conductive channel, a gate insulating layer, and a gate pattern on a substrate in a method of fabricating a top-gate thin film transistor according to a preferred embodiment of the present invention.
  • an active layer 202 is formed on the substrate 201.
  • the active layer 202 includes a source region 2021, a drain region 2022, and a channel region 2023, wherein the material of the edge layer 202 is Indium gallium zinc oxide or amorphous silicon. More specifically, the preferred embodiment defines a source region 2021, a drain region 2022, and a channel region 2023 of the top gate thin film transistor of the preferred embodiment by depositing a source layer 202 on the substrate 201 and then performing a patterning process. .
  • the patterning process includes at least steps of photoresist coating or dripping, exposure, development, photolithography etching, etc., and these steps are all commonly used in the art, and are not described herein.
  • a gate insulating layer 203, a gate metal layer 204, and a photoresist layer 205 are sequentially formed on the active layer 202.
  • the material of the gate insulating layer 203 comprises one or more of silicon oxide and silicon nitride. It should be noted that step S102 only deposits the gate insulating layer 203, the gate metal layer 204, and the photoresist layer 205 on the active layer 202 to form the gate insulating layer 203, the gate metal layer 204, and the light.
  • the resist layer 205 can be performed by a deposition method well known to those skilled in the art, and will not be described herein.
  • the photoresist layer 205 is patterned to form a first photoresist pattern 2051, wherein the first photoresist pattern 2051 includes a first shielding portion 20511 and is disposed at the first a second shielding portion 20512 on both sides of the shielding portion 20511, and the projection of the first shielding portion 20511 on the substrate 201 coincides with the projection of the channel region 2023 on the substrate 201, and the thickness of the first shielding portion 20511 is greater than the second shielding portion.
  • step S103 the step of patterning the photoresist layer 205 to form the first photoresist pattern 2051 includes: exposing the photoresist layer 205 with a halftone mask, and using the development night to expose The subsequent photoresist layer 205 is developed to form a first photoresist pattern 2051.
  • step S104 the gate metal layer 204 is etched using the first photoresist pattern 2051 as a mask to form a gate pattern 2041.
  • the gate metal layer 204 can be etched by an etching method well known to those skilled in the art, which will not be described herein.
  • the present invention emphasizes that the gate pattern 2041 and the trench are formed.
  • the track region 2023 coincides, that is, the projection of the gate pattern 2041 on the substrate 201 coincides with the projection of the channel region 2023 on the substrate 201.
  • step S105 the second shielding portion 20512 of the first photoresist pattern 2051 is subjected to ashing processing to remove the second shielding portion 20512 of the first photoresist pattern 2051 to form a second photoresist pattern. 2052.
  • the second shielding portion 20512 of the first photoresist pattern 2051 is formed such that the formed gate pattern 2041 is not affected by the metal overetching, and the size does not coincide with the channel region 2023.
  • the second blocking portion 20512 of the first photoresist pattern 2051 needs to be removed.
  • the second shielding portion 20512 of the first photoresist pattern 2051 can be ashed using oxygen.
  • step S106 as shown in FIGS. 2E and 2F, the gate insulating layer 203 is etched with the second photoresist pattern 2052 as a mask to expose the source region 2021 and the drain region 2022.
  • the active layer is conductorized to form a source contact region on the source region 2021 and a drain contact region on the drain region 2022, wherein the source contact region
  • the drain contact region and the channel region 2023 form a conductive channel.
  • the active layer can be conductorized using a plasma gas.
  • FIGS. 3A-3C are schematic diagrams showing the process of forming an interlayer insulating layer, a source, and a drain in a method of fabricating a top-gate thin film transistor according to a preferred embodiment of the present invention.
  • the method for fabricating the top-gate thin film transistor provided by the preferred embodiment further includes a process of forming an interlayer insulating layer, a source, and a drain, and the process of forming the interlayer insulating layer, the source, and the drain is specifically :
  • the second photoresist pattern 2052 is peeled off
  • an interlayer insulating layer 206 and a first via 2061 and a second via 2062 extending through the interlayer insulating layer 206 are formed on the gate pattern 2041, the source contact region and the drain contact region,
  • the first via 2061 and the second via 2062 expose a source contact region and a drain contact region, respectively;
  • a source electrode 2071 and a drain electrode 2072 are formed on the interlayer insulating layer 206.
  • the source electrode 2071 and the drain electrode 2072 are in contact with the source via the first via hole 2061 and the second via hole 2062, respectively.
  • the region is in contact with the drain contact region.
  • the second photoresist pattern may be peeled off by immersing the second photoresist pattern in the stripping solution.
  • the first photoresist pattern includes a first shielding portion and a second shielding portion, and the first photoresist pattern is used as a mask
  • the gate metal layer is etched such that the gate pattern conforms to the channel region size of the conductive channel, thereby improving the control force of the gate on the conductive channel, thereby improving the performance of the device.
  • the present invention also provides a top-gate thin film transistor which is fabricated by the above-described fabrication method of a top-gate thin film transistor, and is characterized in that the gate pattern is in accordance with the channel region size of the conductive channel, specifically A top gate type thin film transistor which is formed by referring to a preferred embodiment of the above-described method for fabricating a top gate type thin film transistor will not be described herein.
  • the first photoresist pattern includes a first shielding portion and a second shielding portion, and the first photoresist pattern is used as a mask to the gate.
  • the electrode metal layer is etched such that the gate pattern conforms to the channel region size of the conductive channel, thereby improving the control force of the gate on the conductive channel, thereby improving the performance of the device.

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Abstract

一种顶栅型薄膜晶体管的制作方法，通过形成第一光阻图案（2051），第一光阻图案（2051）包括第一遮挡部（20511）以及第二遮挡部（20512），并以该第一光阻图案（2051）作为罩幕对栅极金属层（204）进行蚀刻，从而使得栅极图形（2041）与导电沟道的沟道区（2023）尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。

Description

一种顶栅型薄膜晶体管的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种顶栅型薄膜晶体管的制作方法。
 背景技术
薄膜晶体管按照结构不同可以分为底栅型薄膜晶体管和顶栅型薄膜晶体管，其中，顶栅型薄膜晶体管可以显著减小源漏极和栅极之间形成的寄生电容，从而提高薄膜晶体管的开态电流，进而提高器件的工作速度，有利于器件尺寸的缩小，所以近年来成为行业研究的热点。
但是，在现有的顶栅型薄膜晶体管的制作方法中，形成栅极图形的步骤具体为：形成一栅极金属层，并对栅极金属层进行蚀刻。然而，在对栅极金属层进行蚀刻的过程中容易导致金属过蚀刻，从而使得栅极图形的宽度小于导电沟道的沟道区的宽度，进而使得栅极并不能够完全控制导电沟道，使得源漏电极间电流减小，薄膜晶体管器件性能下降。
故，有必要提供一种顶栅型薄膜晶体管的制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种顶栅型薄膜晶体管的制作方法，以提高栅极对导电沟道的控制力，进而提高器件的性能。
 技术解决方案
本发明提供一种顶栅型薄膜晶体管的制作方法，其包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程；
所述在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体为：
在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部在所述基板上的投影与所述沟道区在所述基板上的投影重合，所述第一遮挡部的厚度大于所述第二遮挡部的厚度；
以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道；
所述栅极图形在所述基板上的投影与所述沟道区在所述基板上的投影重合；可使用氧气对所述第一光阻图案的第二遮挡部进行灰化处理。
在本发明的顶栅型薄膜晶体管的制作方法中，所述对所述光阻层进行图案化处理，以形成第一光阻图案的步骤包括：
采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成所述第一光阻图案。
在本发明的顶栅型薄膜晶体管的制作方法中，所述有源层的材料为铟镓锌氧化物或非晶硅。
在本发明的顶栅型薄膜晶体管的制作方法中，所述制作方法还包括：形成层间绝缘层、源极、及漏极的过程；
所述形成层间绝缘层、源极、及漏极的过程具体为：
剥离所述第二光阻图案；
在所述栅极图形、源极接触区和漏极接触区上形成层间绝缘层和贯穿所述层间绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述源极接触区和漏极接触区；
在所述层间绝缘层上形成源极与漏极，所述源极与漏极分别通过所述第一过孔和第二过孔与所述源极接触区和漏极接触区接触。
在本发明的顶栅型薄膜晶体管的制作方法中，所述剥离所述第二光阻图案的步骤具体为：将所述第二光阻图案浸泡在剥离液中。
在本发明的顶栅型薄膜晶体管的制作方法中，所述栅极绝缘层的材料分别包括氧化硅与氮化硅中的一种或多种。
在本发明的顶栅型薄膜晶体管的制作方法中，可使用等离子气体对所述有源层进行导体化。
本发明还提供一种顶栅型薄膜晶体管的制作方法，其包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程；
所述在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体为：
在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部在所述基板上的投影与所述沟道区在所述基板上的投影重合，所述第一遮挡部的厚度大于所述第二遮挡部的厚度；
以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道。
本发明的顶栅型薄膜晶体管的制作方法中，所述栅极图形在所述基板上的投影与所述沟道区在所述基板上的投影重合。
本发明的顶栅型薄膜晶体管的制作方法中，所述对所述光阻层进行图案化处理，以形成第一光阻图案的步骤包括：
采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成所述第一光阻图案。
本发明的顶栅型薄膜晶体管的制作方法中，可使用氧气对所述第一光阻图案的第二遮挡部进行灰化处理。
本发明的顶栅型薄膜晶体管的制作方法中，所述有源层的材料为铟镓锌氧化物或非晶硅。
本发明的顶栅型薄膜晶体管的制作方法中，所述制作方法还包括：形成层间绝缘层、源极、及漏极的过程；
所述形成层间绝缘层、源极、及漏极的过程具体为：
剥离所述第二光阻图案；
在所述栅极图形、源极接触区和漏极接触区上形成层间绝缘层和贯穿所述层间绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述源极接触区和漏极接触区；
在所述层间绝缘层上形成源极与漏极，所述源极与漏极分别通过所述第一过孔和第二过孔与所述源极接触区和漏极接触区接触。
本发明的顶栅型薄膜晶体管的制作方法中，所述剥离所述第二光阻图案的步骤具体为：将所述第二光阻图案浸泡在剥离液中。
本发明的顶栅型薄膜晶体管的制作方法中，所述栅极绝缘层的材料分别包括氧化硅与氮化硅中的一种或多种。
本发明的顶栅型薄膜晶体管的制作方法中，可使用等离子气体对所述有源层进行导体化。
 有益效果
本发明的顶栅型薄膜晶体管的制作方法，通过形成第一光阻图案，该第一光阻图案包括第一遮挡部以及第二遮挡部，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，从而使得栅极图形与导电沟道的沟道区尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法的流程图；
图2A-2F为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中在基板上形成导电沟道、栅极绝缘层和栅极图形的过程示意图；
图3A-3C为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中形成层间绝缘层、源极、及漏及的过程示意图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明优选实施例提供一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管，通过形成第一光阻图案并以第一光阻图案作为罩幕对栅极金属层进行蚀刻，以及形成第二光阻图案并以第二光阻图案作为罩幕对栅极绝缘层进行蚀刻，从而使得栅极图形、栅极绝缘层、及导电沟道的沟道区在基板上的投影重合，提高了栅极对导电沟道的控制力。
参阅图1,图1为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法的流程图。如图1所示，本发明优选实施例提供了一种顶栅型薄膜晶体管的制作方法，该方法旨在提高栅极对导电沟道的控制力，其具体是通过精密控制形成的栅极图形与导电沟道的沟道区的尺寸吻合而实现。
下面将结合具体实施例对该顶栅型薄膜晶体管的制作方法作详细描述，该方法包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程，进一步的，在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体包括以下步骤：
步骤S101，在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
步骤S102，在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
步骤S103，对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部的投影与所述沟道区重合，所述第一遮挡区的厚度大于所述第二遮挡区的厚度；
步骤S104，以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
步骤S105，对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
步骤S106，以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
步骤S107，对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道。
需要说明的是，本发明的顶栅型薄膜晶体管的制作方法，为了抑制形成栅极图形时金属过蚀刻，造成栅极与导电沟道的沟道区尺寸不吻合，其通过形成第一光阻图案，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，形成一尺寸与导电沟道的沟道区吻合的栅极，进而提高栅极对导电沟道的控制力，提高器件的性能。
下面结合图2A-2F来详细说明制作顶栅型薄膜晶体管的过程。图2A-2F为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中在基板上形成导电沟道、栅极绝缘层和栅极图形的过程示意图。
在步骤S101中，如图2A所示，在基板201上形成有源层202，该有源层202包括源区2021、漏区2022、及沟道区2023，其中，该有缘层202的材料为铟镓锌氧化物或非晶硅。更具体的，本优选实施例通过在基板201上沉积有缘源层202，然后通过图形化工艺定义出本优选实施例的顶栅型薄膜晶体管的源区2021、漏区2022、及沟道区2023。需要指出的是，该图形化工艺至少包括光刻胶涂覆或滴注、曝光、显影、光刻刻蚀等步骤，这些步骤均属于本领域常用手段，在此不做赘述。
在步骤S102中，如图2B所示，在该有源层202上依次形成栅极绝缘层203、栅极金属层204、及光阻层205。优选的，该栅极绝缘层203的材料包括氧化硅与氮化硅中的一种或多种。需要指出的是，步骤S102仅仅只是在有源层202上沉积栅极绝缘层203、栅极金属层204、及光阻层205，而形成栅极绝缘层203、栅极金属层204、及光阻层205可通过本领域技术人员熟知的沉积方式进行，在此不做赘述。
在步骤S103中，结合图2B、2C所示，对光阻层205进行图案化处理，以形成第一光阻图案2051，其中，第一光阻图案2051包括第一遮挡部20511以及设置在第一遮挡部20511两侧的第二遮挡部20512，且第一遮挡部20511在基板201上的投影与沟道区2023在基板201上的投影重合，第一遮挡部20511的厚度大于第二遮挡部201512的厚度。
更具体的，在步骤S103中，对光阻层205进行图案化处理，以形成第一光阻图案2051的步骤包括：采用半色调掩膜对该光阻层205进行曝光，并用显影夜对曝光后的光阻层205进行显影，从而形成第一光阻图案2051。
在步骤S104中，结合图2C、2D所示，以第一光阻图案2051作为罩幕，对栅极金属层204进行蚀刻，以形成栅极图形2041。需要指出的是，在步骤S104中，可通过本领域技术人员熟知的蚀刻方式对栅极金属层204进行蚀刻，在此不做赘述，而本发明强调的是，形成的栅极图形2041与沟道区2023吻合，即栅极图形2041在基板201上的投影与沟道区2023在基板201上的投影重合。
在步骤S105中，如图2E所示，对第一光阻图案2051的第二遮挡部20512进行灰化处理，以去除第一光阻图案2051的第二遮挡部20512，形成第二光阻图案2052。具体的，在步骤103中通过形成第一光阻图案2051的第二遮挡部20512，以使得形成的栅极图形2041不会受金属过蚀刻的影响而出现尺寸与沟道区2023不吻合的现象，但在步骤S105中，为使栅极绝缘层203的尺寸与栅极图形2041的尺寸一致，需去除第一光阻图案2051的第二遮挡部20512。
优选的，可使用氧气对第一光阻图案2051的第二遮挡部20512进行灰化处理。
在步骤S106中，结合图2E、2F所示，以第二光阻图案2052作为罩幕，对栅极绝缘层203进行蚀刻，以裸露出源区2021和漏区2022。
在步骤S107中，如图2F所示，对有源层进行导体化，以在源区2021上形成源极接触区、及在漏区2022上形成漏极接触区，其中，该源极接触区、漏极接触区、及沟道区2023形成导电沟道。优选的，可使用等离子气体对所述有源层进行导体化。
更进一步的，参阅图3A-3C，图3A-3C为本发明优选实施例提供的顶栅型薄膜晶体管的制作方法中形成层间绝缘层、源极、及漏及的过程示意图。本优选实施例提供的顶栅型薄膜晶体管的制作方法，还包括：形成层间绝缘层、源极、及漏极的过程，该形成层间绝缘层、源极、及漏极的过程具体为：
首先，结合图2F、3A所示，剥离第二光阻图案2052；
随后，如图3B所示，在栅极图形2041、源极接触区和漏极接触区上形成层间绝缘层206和贯穿层间绝缘层206的第一过孔2061和第二过孔2062，第一过孔2061和第二过孔2062分别暴露出源极接触区和漏极接触区；
最后，结合图3B、3C所示，在层间绝缘层206上形成源极2071与漏极2072，源极2071与漏极2072分别通过第一过孔2061和第二过孔2062与源极接触区和漏极接触区接触。
优选的，可通过将第二光阻图案浸泡在剥离液中，以剥离第二光阻图案。
本优选实施例的顶栅型薄膜晶体管的制作方法，通过形成第一光阻图案，该第一光阻图案包括第一遮挡部以及第二遮挡部，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，从而使得栅极图形与导电沟道的沟道区尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。
本发明还提供一种顶栅型薄膜晶体管，其采用以上所述的顶栅型薄膜晶体管的制作方法制成，其结构特征在于：栅极图形与导电沟道的沟道区尺寸吻合，具体可参照上述顶栅型薄膜晶体管的制作方法的优选实施例制成的顶栅型薄膜晶体管，在此不做赘述。
本发明的顶栅型薄膜晶体管的制作方法，通过形成第一光阻图案，该第一光阻图案包括第一遮挡部以及第二遮挡部，并以该第一光阻图案作为罩幕对栅极金属层进行蚀刻，从而使得栅极图形与导电沟道的沟道区尺寸吻合，提高栅极对导电沟道的控制力，进而提高器件的性能。
综上，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种顶栅型薄膜晶体管的制作方法，其包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程；
    所述在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体为：
    在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
    在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
    对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部在所述基板上的投影与所述沟道区在所述基板上的投影重合，所述第一遮挡部的厚度大于所述第二遮挡部的厚度；
    以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
    对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
    以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
    对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道；
    所述栅极图形在所述基板上的投影与所述沟道区在所述基板上的投影重合；可使用氧气对所述第一光阻图案的第二遮挡部进行灰化处理。
  2. 根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其中所述对所述光阻层进行图案化处理，以形成第一光阻图案的步骤包括：
    采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成所述第一光阻图案。
  3. 根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其中所述有源层的材料为铟镓锌氧化物或非晶硅。
  4. 根据权利要求1所述顶栅型薄膜晶体管的制作方法，其中所述制作方法还包括：形成层间绝缘层、源极、及漏极的过程；
    所述形成层间绝缘层、源极、及漏极的过程具体为：
    剥离所述第二光阻图案；
    在所述栅极图形、源极接触区和漏极接触区上形成层间绝缘层和贯穿所述层间绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述源极接触区和漏极接触区；
    在所述层间绝缘层上形成源极与漏极，所述源极与漏极分别通过所述第一过孔和第二过孔与所述源极接触区和漏极接触区接触。
  5. 根据权利要求4所述的顶栅型薄膜晶体管的制作方法，其中所述剥离所述第二光阻图案的步骤具体为：将所述第二光阻图案浸泡在剥离液中。
  6. 根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其中所述栅极绝缘层的材料分别包括氧化硅与氮化硅中的一种或多种。
  7. 根据权利要求1所述的顶栅型薄膜晶体管的制作方法，其中可使用等离子气体对所述有源层进行导体化。
  8. 一种顶栅型薄膜晶体管的制作方法，其包括在基板上形成导电沟道、栅极绝缘层和栅极图形的过程；
    所述在基板上形成导电沟道、栅极绝缘层和栅极图形的过程具体为：
    在基板上形成有源层，所述有源层包括源区、漏区、及沟道区；
    在所述有源层上依次形成栅极绝缘层、栅极金属层、及光阻层；
    对所述光阻层进行图案化处理，以形成第一光阻图案，其中，所述第一光阻图案包括第一遮挡部以及设置在所述第一遮挡部两侧的第二遮挡部，且所述第一遮挡部在所述基板上的投影与所述沟道区在所述基板上的投影重合，所述第一遮挡部的厚度大于所述第二遮挡部的厚度；
    以所述第一光阻图案作为罩幕，对所述栅极金属层进行蚀刻，以形成栅极图形；
    对所述第一光阻图案的第二遮挡部进行灰化处理，以去除所述第一光阻图案的第二遮挡部，形成第二光阻图案；
    以所述第二光阻图案作为罩幕，对所述栅极绝缘层进行蚀刻，以裸露出所述源区和漏区；
    对所述有源层进行导体化，以在所述源区上形成源极接触区、及在所述漏区上形成漏极接触区，其中，所述源极接触区、漏极接触区、及沟道区形成导电沟道。
  9. 根据权利要求8所述的顶栅型薄膜晶体管的制作方法，其中所述栅极图形在所述基板上的投影与所述沟道区在所述基板上的投影重合。
  10. 根据权利要求8所述的顶栅型薄膜晶体管的制作方法，其中所述对所述光阻层进行图案化处理，以形成第一光阻图案的步骤包括：
    采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成所述第一光阻图案。
  11. 根据权利要求9所述的顶栅型薄膜晶体管的制作方法，其中所述对所述光阻层进行图案化处理，以形成第一光阻图案的步骤包括：
    采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成所述第一光阻图案。
  12. 根据权利要求8所述的顶栅型薄膜晶体管的制作方法，其中可使用氧气对所述第一光阻图案的第二遮挡部进行灰化处理。
  13. 根据权利要求8所述的顶栅型薄膜晶体管的制作方法，其中所述有源层的材料为铟镓锌氧化物或非晶硅。
  14. 根据权利要求8所述顶栅型薄膜晶体管的制作方法，其特中所述制作方法还包括：形成层间绝缘层、源极、及漏极的过程；
    所述形成层间绝缘层、源极、及漏极的过程具体为：
    剥离所述第二光阻图案；
    在所述栅极图形、源极接触区和漏极接触区上形成层间绝缘层和贯穿所述层间绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述源极接触区和漏极接触区；
    在所述层间绝缘层上形成源极与漏极，所述源极与漏极分别通过所述第一过孔和第二过孔与所述源极接触区和漏极接触区接触。
  15. 根据权利要求14所述的顶栅型薄膜晶体管的制作方法，其中所述剥离所述第二光阻图案的步骤具体为：将所述第二光阻图案浸泡在剥离液中。
  16. 根据权利要求8所述的顶栅型薄膜晶体管的制作方法，其中所述栅极绝缘层的材料分别包括氧化硅与氮化硅中的一种或多种。
  17. 根据权利要求8所述的顶栅型薄膜晶体管的制作方法，其中可使用等离子气体对所述有源层进行导体化。
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