WO2017197679A1 - 一种薄膜晶体管的制作方法 - Google Patents

一种薄膜晶体管的制作方法 Download PDF

Info

Publication number
WO2017197679A1
WO2017197679A1 PCT/CN2016/085495 CN2016085495W WO2017197679A1 WO 2017197679 A1 WO2017197679 A1 WO 2017197679A1 CN 2016085495 W CN2016085495 W CN 2016085495W WO 2017197679 A1 WO2017197679 A1 WO 2017197679A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist pattern
etching
metal layer
thin film
film transistor
Prior art date
Application number
PCT/CN2016/085495
Other languages
English (en)
French (fr)
Inventor
叶江波
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/128,112 priority Critical patent/US9960255B2/en
Publication of WO2017197679A1 publication Critical patent/WO2017197679A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a method for fabricating a thin film transistor.
  • Low-temperature polysilicon panel fabrication technology is a new generation of thin-film transistor liquid crystal display manufacturing technology.
  • the so-called low-temperature polysilicon technology mainly uses laser annealing process to a-
  • the thin film of Si is converted into a polysilicon thin film layer, and the polycrystalline silicon thin film layer is used to form a thin film transistor for driving data lines and scanning lines of the liquid crystal display panel.
  • the thin film transistor of polycrystalline silicon has a magnetic moving speed of 100 times that of the same amorphous silicon component, so that liquid crystal can be realized.
  • the display panel features fast screen response, high brightness display and high resolution.
  • FIG. 1A to FIG. 1F are process flow diagrams of a method for fabricating a thin film transistor of the prior art
  • a first photoresist pattern 101 is first formed on a semiconductor substrate 102, and then the semiconductor substrate 102 is subjected to a first ion implantation step using the first photoresist pattern 101 as a mask.
  • the coverage region ions of the first photoresist pattern 101 cannot be implanted, thereby forming the preliminary source region 104 and the preliminary drain region 103.
  • the first photoresist pattern 101 is removed, the gate insulating layer 105 and the gate metal layer 106 are sequentially deposited on the semiconductor substrate 102, and the second light is formed on the gate metal layer 106. Resistance pattern 107.
  • the gate metal layer 106 is etched, specifically, the portion of the gate metal layer 106 that is not blocked by the first photoresist pattern is etched away, as the etching time is lengthened, The sidewalls of the gate metal layer 106 are also gradually etched away to form a new gate metal layer 106a.
  • the second photoresist pattern 107 is removed.
  • a second ion implantation step is performed on the semiconductor substrate 102 to form a source/drain, wherein the source/drain includes a heavily doped drain region 103 and 104 and a Lightly doped drain regions 109 and 108.
  • the invention provides a method for fabricating a thin film transistor, which can effectively solve the complicated preparation process of the existing thin film transistor manufacturing method, has a long production cycle, and has a great influence on ion uniformity, thereby affecting the heavily doped drain region and Technical problem of electron mobility of lightly doped drain regions.
  • the present invention provides a method for fabricating a thin film transistor, including:
  • Forming a first photoresist pattern on the gate metal layer comprising: coating a photoresist on the gate metal layer, exposing the photoresist by using a mask, and developing a first photoresist pattern after development Etching the gate metal layer not covered by the first photoresist pattern to form a gate electrode, wherein a width of the gate electrode is smaller than a width of the first photoresist pattern;
  • Etching the gate metal layer not covered by the first photoresist pattern comprises: first etching the gate metal layer to form a preliminary gate electrode; and performing a second etching on the preliminary gate electrode, A gate electrode is formed.
  • the rate of the first etch is greater than the rate of the second etch.
  • the first etching uses sulfur fluoride and oxygen.
  • the second etching uses chlorine gas and oxygen gas.
  • the first photoresist pattern is etched using oxygen.
  • the invention also provides a method for fabricating a thin film transistor, comprising:
  • Forming a first photoresist pattern on the gate metal layer comprising: coating a photoresist on the gate metal layer, exposing the photoresist by using a mask, and developing a first photoresist pattern after development .
  • Etching the gate metal layer not covered by the first photoresist pattern comprises: first etching the gate metal layer to form a preliminary gate electrode; and performing a second etching on the preliminary gate electrode, A gate electrode is formed.
  • the rate of the first etch is greater than the rate of the second etch.
  • the first etching uses sulfur fluoride and oxygen.
  • the second etching uses chlorine gas and oxygen gas.
  • the first photoresist pattern is etched using oxygen.
  • the width of the lightly doped drain region and the second photoresist pattern are equal to a smaller value of the width of the gate electrode.
  • the gate insulating layer is a silicon nitride layer or a silicon oxide layer, or a mixture of a silicon nitride layer and a silicon oxide layer.
  • the silicon nitride layer is over the silicon oxide layer.
  • the invention also provides a method for fabricating a thin film transistor, comprising:
  • a gate insulating layer and a gate metal layer sequentially on a semiconductor substrate, the gate insulating layer being a silicon nitride layer or a silicon oxide layer, or a mixture of a silicon nitride layer and a silicon oxide layer;
  • Forming a first photoresist pattern on the gate metal layer comprising: coating a photoresist on the gate metal layer, exposing the photoresist by using a mask, and developing a first photoresist pattern after development .
  • Etching the gate metal layer not covered by the first photoresist pattern comprises: first etching the gate metal layer to form a preliminary gate electrode; and performing a second etching on the preliminary gate electrode, A gate electrode is formed.
  • the silicon nitride layer is located above the silicon oxide layer.
  • the method for fabricating the thin film transistor provided by the invention forms a light-resist pattern to form a lightly doped drain region, which simplifies the process preparation process, thereby shortening the production cycle, and by performing sidewalls on the photoresist pattern Etching, to avoid secondary etching of the gate metal layer, has less influence on the implanted ion uniformity, and thus does not affect the electron mobility of the heavily doped drain region and the lightly doped drain region.
  • FIGS. 1A to 1F are process flow diagrams of a prior art thin film transistor fabrication method
  • 2A to 2F are flowcharts showing an improved process of a method for fabricating a thin film transistor
  • 3A to 3E are process flowcharts of a method of fabricating a thin film transistor of the present invention.
  • FIG. 4 is a schematic flow chart of a method of fabricating a thin film transistor of the present invention.
  • the preparation process for the thin film transistor is complicated, resulting in a long production cycle, which is disadvantageous for production, and the following improvements are made.
  • a gate insulating layer 202 and a gate metal layer 203 are sequentially deposited on the semiconductor substrate 201, and a first photoresist pattern 204 is formed on the gate metal layer 203;
  • the gate metal layer 203 is etched to form a new gate metal layer 203a.
  • the gate metal layer 203 is first quickly etched using sulfur fluoride and oxygen, and then chlorine gas is used.
  • the electrode metal layer 203 is slowly etched with oxygen, and the gate insulating layer 202 is easily etched away during the etching process.
  • the semiconductor substrate 201 is subjected to a first ion implantation step to form a preliminary source region 205 and a preliminary drain region 206.
  • the gate metal layer 203a is re-etched. Specifically, the gate metal layer 203a is first quickly etched using sulfur fluoride and oxygen, and the gate metal is further treated with chlorine gas and oxygen. The layer 203a is slowly etched, and as time elapses, the sidewalls of the first photoresist pattern 204 are also etched away by a small portion to form a new first photoresist pattern 204a and a new gate metal layer 203b.
  • the semiconductor substrate 201 is subjected to a second ion implantation step to form a source/drain, wherein the source/drain includes a heavily doped drain region 205 and 206 and a Lightly doped drain regions 207 and 208.
  • the thin film transistor is fabricated by forming a photoresist pattern to form a lightly doped drain region, which simplifies the preparation process, but performs two main etchings, which tend to cause uniformity of the gate insulating layer during the etching process.
  • Insufficient property resulting in insufficient ion uniformity when implanting ions onto the semiconductor substrate; also when the gate metal layer is re-etched, the surface uniformity of the gate insulating layer is easily caused during the etching process, resulting in Secondary implantation of ions onto the semiconductor substrate results in insufficient ion uniformity.
  • the two ions are insufficient in uniformity, which in turn affects the electron mobility of the heavily doped drain region and the lightly doped drain region.
  • FIG. 4 is a schematic flow chart of a method for fabricating a thin film transistor according to the present invention, the method including steps 401 to 405:
  • Step 401 sequentially depositing a gate insulating layer 302 and a gate metal layer 303 on a semiconductor substrate 301;
  • Step 402 forming a first photoresist pattern 304 on the gate metal layer 303, etching the gate metal layer 303 not covered by the first photoresist pattern 304 to form a gate electrode, wherein the gate The width 303a of the electrode is smaller than the width of the first photoresist pattern 304;
  • Step 403 using the first photoresist pattern 304 as a mask, performing a first ion implantation on the semiconductor substrate 301 to form a preliminary source region 306 and a preliminary drain region 305;
  • Step 404 etching sidewalls of the first photoresist pattern 304 to form a second photoresist pattern 304a, wherein a width of the second photoresist pattern 304a is smaller than a width of the first photoresist pattern 304 ;
  • Step 405 using the second photoresist pattern 304a as a mask, performing a second ion implantation on the semiconductor substrate 301 to form a source/drain, wherein the source/drain includes a heavily doped drain.
  • a semiconductor substrate is first provided.
  • a buffer layer is deposited on a substrate, an amorphous silicon layer is deposited on the buffer layer, and a polysilicon layer is formed through a process to form a layer.
  • the substrate cleaning is first performed by an initial cleaning process.
  • plasma enhanced chemical vapor deposition may be employed.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a buffer layer is deposited on the substrate, and pre-cleaning is performed before the buffer layer is deposited. After the buffer layer is prepared, it can be annealed to optimize the quality of the buffer layer.
  • PECVD can be used.
  • the amorphous silicon layer is deposited on the buffer layer, and the amorphous silicon layer is dehydrogenated by a high temperature oven to prevent hydrogen explosion during the crystallization process and to reduce the density of defect states inside the film after crystallization.
  • low temperature polysilicon is performed.
  • LTPS Low Temperature Poly-silicon
  • the general method used is laser annealing
  • the amorphous silicon layer is crystallized by a crystallization means such as (ELA), a metal induced crystallization process (MIC) or a solid phase crystallization process (SPC) to obtain a polysilicon layer 303.
  • Pair of polysilicon layers 303 The surface is treated so that the surface roughness of the polysilicon layer 303 can be lowered, and wrinkles or tip bumps due to crystallization can be removed to make the polysilicon layer 303 Better contact with the back film layer to improve the performance of the entire device.
  • the gate insulating layer 302 in the embodiment of the present invention includes a silicon nitride layer or a silicon oxide layer, or a mixture of a silicon nitride layer and a silicon oxide layer, because the silicon oxide layer can better match the polysilicon layer.
  • the surface is bonded, and the silicon nitride layer is on the silicon oxide layer.
  • a first photoresist pattern 304 is formed on the gate metal layer 303. Specifically, a photoresist is coated on the gate metal layer 303, and the photoresist is exposed by using a mask. After the development, the first photoresist pattern 304 is formed.
  • the gate metal layer 303 not covered by the first photoresist pattern 304 is etched to form a gate electrode.
  • the gate metal layer 303 is first etched to form a preliminary gate electrode, wherein the gate metal layer is etched using a dry etching technique, preferably by using sulfur fluoride and oxygen, due to fluorination
  • the etching rate of sulfur and oxygen is faster, and the gate metal layer can be quickly etched, thereby effectively shortening the preparation time; the preliminary etching of the preliminary gate electrode is performed to form the gate electrode 303a, wherein dry etching is used.
  • the preliminary gate electrode is re-etched, preferably by etching with chlorine gas and oxygen gas. Since the etching rate of chlorine gas and oxygen gas is slow, the surface integrity of the gate insulating layer 302 can be better maintained during the etching process, thereby not It will have an impact on the uniformity of subsequent ion implantation.
  • the first etching is to etch the gate metal layer 303 not covered by the first photoresist pattern 304
  • the second etching is to etch the side of the preliminary gate electrode covered by the first photoresist pattern 304, wherein The width of the gate electrode 303a is smaller than the width of the first photoresist pattern 304.
  • step 403 the semiconductor substrate 301 is subjected to a first ion implantation using the first photoresist pattern 304 as a mask to form a preliminary source region 306 and a preliminary drain.
  • Polar region 305 the semiconductor substrate 301 is subjected to a first ion implantation using the first photoresist pattern 304 as a mask to form a preliminary source region 306 and a preliminary drain.
  • the region of the semiconductor substrate 301 covered by the first photoresist pattern 304 cannot implant ions, and the gate metal layer is etched, a bare gate insulating layer 302 is formed on each side, and the ion energy transmission grating
  • the insulating layer 302 is implanted on the semiconductor substrate 301, and the surface of the gate insulating layer 302 can be made relatively complete by the first etching and the second etching, thereby making the preliminary source region 306 and ion implantation
  • the ion uniformity of the preliminary drain region 305 is good.
  • these regions are also not implanted with ions, and the regions pass through the second After the second etch, portions of the gate metal layer 303 have been etched away, with only the exposed gate insulating layer 302 creating conditions for subsequent formation of lightly doped drain regions.
  • step 404 the sidewall of the first photoresist pattern 304 is etched as shown in FIG. 3D to form a second photoresist pattern 304a.
  • the first photoresist pattern 304 is etched using oxygen.
  • the oxygen is sensitive to the first photoresist pattern 304, the etching only affects the second photoresist pattern 304, and this The sub-etching does not affect the surface uniformity of the gate insulating layer 302, and the subsequent ion implantation is uniform on the semiconductor substrate 301, so that the electron mobility of the doped drain region and the lightly doped drain region is improved. it is good.
  • a condition for forming a lightly doped drain region is formed, that is, a sidewall of the first photoresist pattern 304 that can block ions from being implanted onto the semiconductor substrate.
  • the width of the lightly doped drain structure and the smaller of the second photoresist pattern 304a and the width of the gate electrode 303a are equal.
  • step 405 the semiconductor substrate 301 is subjected to a second ion implantation using the second photoresist pattern 304a as a mask to form a source/drain, wherein the source The / drain includes a heavily doped drain region 305 and 306 and a lightly doped drain region 307 and 308.
  • the method for fabricating the thin film transistor provided by the invention forms a light-resist pattern to form a lightly doped drain region, which simplifies the process preparation process, thereby shortening the production cycle, and by performing sidewalls on the photoresist pattern Etching, to avoid secondary etching of the gate metal layer, has less influence on the implanted ion uniformity, and thus does not affect the electron mobility of the heavily doped drain region and the lightly doped drain region.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供一种薄膜晶体管的制作方法，包括：在一半导体衬底（301）上依序沉积栅绝缘层（302）和栅金属层（303）；蚀刻未被第一光阻图案（304）遮盖住的栅金属层（303）；对半导体衬底（301）进行第一次离子植入；对第一光阻图案（304）的侧壁进行蚀刻；对半导体衬底（301）进行第二次离子植入，以形成源/漏极，其中源/漏极包括一重掺杂漏极区（305，306）和一轻掺杂漏极区（307，308）。

Description

一种薄膜晶体管的制作方法 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种薄膜晶体管的制作方法。
 背景技术
低温多晶硅面板制作技术是新一代薄膜晶体管液晶显示器制造技术，所谓低温多晶硅技术主要是通过镭射退火制程将a- Si的薄膜转变为多晶硅薄膜层，多晶硅薄膜层用于形成驱动液晶显示面板的数据线和扫描线的薄膜晶体管，多晶硅的薄膜晶体管的电子移动速度为同类非晶硅元件的百倍，因此可实现液晶显示面板的快速画面反应、高亮度显示和高解析度等特点。
如图1A至图1F所示，为现有技术的薄膜晶体管的制作方法的工艺流程图；
如图1A所示，首先在半导体衬底102上形成第一光阻图案101，接着，以所述第一光阻图案101作为掩膜对所述半导体衬底102进行第一次离子植入步骤，如图1B所示，第一光阻图案101的覆盖区域离子无法植入，进而形成预备源极区域104和预备漏极区域103。
然后，如图1C所示，去除第一光阻图案101，在所述半导体衬底102上依序沉积栅绝缘层105和栅金属层106，并在所述栅金属层106上形成第二光阻图案107。
接下来，如图1D所示，对所述栅金属层106进行蚀刻，具体地，未被第一光阻图案遮挡的所述栅极金属层106部分被蚀刻掉，随着蚀刻时间的加长，所述栅极金属层106的侧壁也逐渐被蚀刻掉一小部分，形成新的栅极金属层106a。接着，如图1E所示，去除所述第二光阻图案107。
最后，如图1F所示，对所述半导体衬底102进行第二次离子植入步骤，进而形成源/漏极，其中所述源/漏极包括一重掺杂漏极区103及104和一轻掺杂漏极区109及108。
上述薄膜晶体管的制作方法，通过形成两个光阻图案，进而形成轻掺杂漏极区，制备过程较复杂，从而致使生产周期长，不利于生产。因此，有必要提供一种薄膜晶体管的制作方法，使得工艺制备过程简化，并且对植入的离子均一性影响较小，进而不会影响重掺杂漏极区和轻掺杂漏极区的电子迁移率。
 技术问题
本发明提供一种薄膜晶体管的制作方法，可以有效的解决现有的薄膜晶体管制作方法中工艺制备过程复杂，生产周期长，并且对离子均一性影响较大，进而影响重掺杂漏极区和轻掺杂漏极区的电子迁移率的技术问题。
 技术解决方案
为了解决上述技术问题，本发明提供一种薄膜晶体管的制作方法，包括：
在一半导体衬底上依序沉积栅绝缘层和栅金属层；
形成第一光阻图案于所述栅金属层上，包括：在所述栅金属层上涂覆光刻胶，利用掩膜板对所述光刻胶进行曝光，显影后形成第一光阻图案；蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，以形成栅电极，其中，所述栅电极的宽度小于所述第一光阻图案的宽度；
以所述第一光阻图案作为掩膜，对所述半导体衬底进行第一次离子植入，以形成预备源/漏极；
使用氧气对所述第一光阻图案的侧壁进行蚀刻，以形成第二光阻图案，其中，所述第二光阻图案的宽度小于所述第一光阻图案的宽度；
以所述第二光阻图案作为掩膜，对所述半导体衬底进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区和一轻掺杂漏极区。
蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，包括：对所述栅金属层进行第一次蚀刻，形成初步栅电极；对所述初步栅电极进行第二次蚀刻，形成栅电极。
所述第一次蚀刻的速率大于所述第二次蚀刻的速率。
所述第一次蚀刻使用氟化硫和氧气。
所述第二次蚀刻使用氯气和氧气。
使用氧气对所述第一光阻图案进行蚀刻。
本发明还提供一种薄膜晶体管的制作方法，包括：
在一半导体衬底上依序沉积栅绝缘层和栅金属层；
形成第一光阻图案于所述栅金属层上，蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，以形成栅电极，其中，所述栅电极的宽度小于所述第一光阻图案的宽度；
以所述第一光阻图案作为掩膜，对所述半导体衬底进行第一次离子植入，以形成预备源/漏极；
对所述第一光阻图案的侧壁进行蚀刻，以形成第二光阻图案，其中，所述第二光阻图案的宽度小于所述第一光阻图案的宽度；
以所述第二光阻图案作为掩膜，对所述半导体衬底进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区和一轻掺杂漏极区。
形成第一光阻图案于所述栅金属层上，包括：在所述栅金属层上涂覆光刻胶，利用掩膜板对所述光刻胶进行曝光，显影后形成第一光阻图案。
蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，包括：对所述栅金属层进行第一次蚀刻，形成初步栅电极；对所述初步栅电极进行第二次蚀刻，形成栅电极。
所述第一次蚀刻的速率大于所述第二次蚀刻的速率。
所述第一次蚀刻使用氟化硫和氧气。
所述第二次蚀刻使用氯气和氧气。
使用氧气对所述第一光阻图案进行蚀刻。
所述轻掺杂漏极区的宽度和所述第二光阻图案与所述栅电极的宽度之中的较小值相等。
所述栅绝缘层采用氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
所述氮化硅层在所述氧化硅层上面。
本发明还提供一种薄膜晶体管的制作方法，包括：
在一半导体衬底上依序沉积栅绝缘层和栅金属层,所述栅绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合；
形成第一光阻图案于所述栅金属层上，蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，以形成栅电极，其中，所述栅电极的宽度小于所述第一光阻图案的宽度；
以所述第一光阻图案作为掩膜，对所述半导体衬底进行第一次离子植入，以形成预备源/漏极；
使用氧气对所述第一光阻图案的侧壁进行蚀刻，以形成第二光阻图案，其中，所述第二光阻图案的宽度小于所述第一光阻图案的宽度；
以所述第二光阻图案作为掩膜，对所述半导体衬底进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区和一轻掺杂漏极区,所述轻掺杂漏极区的宽度和所述第二光阻图案与所述栅电极的宽度之中的较小值相等。。
形成第一光阻图案于所述栅金属层上，包括：在所述栅金属层上涂覆光刻胶，利用掩膜板对所述光刻胶进行曝光，显影后形成第一光阻图案。
蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，包括：对所述栅金属层进行第一次蚀刻，形成初步栅电极；对所述初步栅电极进行第二次蚀刻，形成栅电极。
所述氮化硅层位于所述氧化硅层上面。
 有益效果
本发明提供的薄膜晶体管的制作方法，通过形成一个光阻图案，进而形成轻掺杂漏极区，简化了工艺制备过程，从而缩短了生产周期，并且通过对所述光阻图案的侧壁进行蚀刻，避免对栅金属层进行二次蚀刻，从而对植入的离子均一性影响较小，进而不会对重掺杂漏极区和轻掺杂漏极区的电子迁移率造成影响。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A至图1F，为现有技术薄膜晶体管制作方法的工艺流程图；
图2A至图2F，为薄膜晶体管制作方法的改进工艺流程图；
图3A至图3E，为本发明薄膜晶体管制作方法的工艺流程图；
图4为本发明薄膜晶体管制作方法的流程示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
下面结合附图详细本发明实施例的实现过程。
针对薄膜晶体管的制备过程较复杂，从而致使生产周期长，不利于生产，进行以下改进。
如图2A至图2F所示，为薄膜晶体管制作方法的改进工艺流程图；
如图2A所示，首先在半导体衬底201上依序沉积栅绝缘层202和栅金属层203，在所述栅金属层203上形成第一光阻图案204；
然后，如图2B所示，对所述栅金属层203进行蚀刻，形成新的栅金属层203a，具体地，先使用氟化硫和氧气对所述栅金属层203进行快蚀刻，再使用氯气和氧气对所述极金属层203进行慢蚀刻，蚀刻过程中，极易导致栅绝缘层202部分被蚀刻掉。
接下来，如图2C所示，对所述半导体衬底201进行第一次离子植入步骤，以形成预备源极区域205和预备漏极区域206。接着，如图2D所示，对所述栅金属层203a进行再蚀刻，具体地，先使用氟化硫和氧气对所述栅金属层203a进行快蚀刻，再使用氯气和氧气对所述栅金属层203a进行慢蚀刻，随着时间的加长，致使第一光阻图案204侧壁也被蚀刻掉一小部分，以形成新的第一光阻图案204a和新的栅极金属层203b。
然后，如图2E所示，去除第一光阻图案204a。最后，如图2F所示，对所述半导体衬底201进行第二次离子植入步骤，进而形成源/漏极，其中所述源/漏极包括一重掺杂漏极区205及206和一轻掺杂漏极区207及208。
上述薄膜晶体管的制作方法，只通过形成一个光阻图案，进而形成轻掺杂漏极区，简化了制备流程，但是却进行了两次的主蚀刻，由于蚀刻过程中易造成栅绝缘层表面均一性不足，致使植入离子到半导体衬底上时致使离子均一性不足；同样在对所述栅金属层进行再蚀刻时，由于蚀刻过程中易造成所述栅绝缘层表面均一性不足，致使第二次植入离子到半导体衬底上时致使离子均一性不足。而两次的离子均一性不足，进而会影响重掺杂漏极区和轻掺杂漏极区的电子迁移率。
图4为本发明薄膜晶体管制作方法的流程示意图，该方法包括步骤401至步骤405：
步骤401，在一半导体衬底301上依序沉积栅绝缘层302和栅金属层303；
步骤402，形成第一光阻图案304于所述栅金属层303上，蚀刻未被所述第一光阻图案304遮盖住的所述栅金属层303，以形成栅电极，其中，所述栅电极的宽度303a小于所述第一光阻图案304的宽度；
步骤403，以所述第一光阻图案304作为掩膜，对所述半导体衬底301进行第一次离子植入，，以形成预备源极区域306和预备漏极区域305；
步骤404，对所述第一光阻图案304的侧壁进行蚀刻，以形成第二光阻图案304a，其中，所述第二光阻图案304a的宽度小于所述第一光阻图案304的宽度；
步骤405，以所述第二光阻图案304a作为掩膜，对所述半导体衬底301进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区305及306和一轻掺杂漏极区307及308。
在步骤401之前，需先提供一半导体衬底，本实施例，通过在一基板上沉积缓冲层，在所述缓冲层上沉积非晶硅层，并经过工艺处理形成多晶硅层，进而制成形成轻掺杂漏极结构所需的半导体衬底。
具体地，先通过初始清洁工艺实现对基板清洗。为了防止基板中的有害物质如碱金属离子对多晶硅层的性能造成不良影响，可以采用等离子体增强化学气相沉积法 (Plasma Enhanced Chemical Vapor Deposition,PECVD) 在基板沉积缓冲层，且沉积缓冲层前要进行预清洗。缓冲层制备完后可以进行退火处理，以优化缓冲层的质量。
在步骤401中，可以采用 PECVD 法在缓冲层上沉积非晶硅层，采用高温烤箱对非晶硅层进行脱氢工艺处理，以防止在晶化过程中的氢爆现象以及降低晶化后薄膜内部的缺陷态密度。脱氢工艺完成后，进行低温多晶硅 (Low Temperature Poly-silicon，LTPS)技术工艺过程，对非晶硅层进行多晶化处理。一般采用的方法为激光退火工艺 (ELA)、金属诱导结晶工艺 (MIC)、固相结晶工艺 (SPC) 等结晶化手段对非晶硅层进行结晶化处理，得到多晶硅层 303。对多晶硅层 303 的表面进行处理，这样可以降低多晶硅层 303 的表面粗糙度，去除由于结晶化而带来的褶皱或者尖端凸起等，以使多晶硅层 303 能更好的与后面的薄膜层相接触，提高整个器件的性能。
如图3A所示，本发明实施例中的栅绝缘层302包括氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合，，由于氧化硅层能更好的与多晶硅层表面贴合，所述氮化硅层在所述氧化硅层上面。
在步骤402中，形成第一光阻图案304于所述栅金属层303上，具体地，在所述栅金属层303上涂覆光刻胶，利用掩膜板对所述光刻胶进行曝光，显影后形成第一光阻图案304。
在步骤402中，如图3B所示，蚀刻未被所述第一光阻图案304遮盖住的所述栅金属层303，以形成栅电极。具体地，对所述栅金属层303进行第一次蚀刻，形成初步栅电极，其中使用干蚀刻技术对所述栅金属层进行蚀刻，优选地，采用氟化硫和氧气进行蚀刻，由于氟化硫和氧气的蚀刻速率较快，能快速对所述栅金属层进行蚀刻，从而能有效缩短制备时间；对所述初步栅电极进行第二次蚀刻，形成栅电极303a，其中使用干蚀刻技术对所述初步栅电极进行再蚀刻，优选地，采用氯气和氧气进行蚀刻，由于氯气和氧气的蚀刻速率较慢，在蚀刻过程中，能较好的保持栅绝缘层302表面的完整性，从而不会对后续离子植入的均一性产生影响。
第一次蚀刻是对未被第一光阻图案304遮盖住的栅金属层303进行蚀刻，第二次蚀刻是对被第一光阻图案304遮盖住的初步栅电极侧边进行蚀刻，其中，所述栅电极303a的宽度小于所述第一光阻图案304的宽度。
在步骤403中，如图3C所示，以所述第一光阻图案304作为掩膜，对所述半导体衬底301进行第一次离子植入，，以形成预备源极区域306和预备漏极区域305。具体地，由于被第一光阻图案304覆盖住的半导体衬底301区域无法植入离子，并且所述栅金属层经蚀刻后，两边各形成一裸露的栅绝缘层302，离子能透过栅绝缘层302植入到半导体衬底301上，并且可以通过所述第一次蚀刻和所述第二次蚀刻，使得栅绝缘层302表面较完整，进而离子植入后使得预备源极区域306和预备漏极区域305的离子均一性较好。
其中，在所述半导体衬底上靠近预备源极区域306和预备漏极区域305，由于被第一光阻图案304遮挡住，这些区域也未植入离子，并且这些区域上方通过所述第二次蚀刻后，所述栅金属层303部分已被蚀刻掉，只有裸露的栅绝缘层302，为后续形成轻掺杂漏区创造条件。
在步骤404中，如图3D所示对所述第一光阻图案304的侧壁进行蚀刻，以形成第二光阻图案304a。具体地，使用氧气对所述第一光阻图案304进行蚀刻，蚀刻过程中，由于氧气对第一光阻图案304较敏感，故此次蚀刻几乎只对第二光阻图案304造成影响，而这次蚀刻不会对栅绝缘层302表面均一性造成影响，进而后续离子植入到半导体衬底301上均一性较好，进而使得掺杂漏极区和轻掺杂漏极区的电子迁移率较好。
通过对所述第一光阻图案304的侧壁进行蚀刻，进而为形成轻掺杂漏极区构创造条件，即将能阻挡离子植入到半导体衬底上的第一光阻图案304的侧壁剔除，所述轻掺杂漏极结构的宽度和所述第二光阻图案304a与所述栅电极303a的宽度之中的较小值相等。
在步骤405中，如图3E所示，以所述第二光阻图案304a作为掩膜，对所述半导体衬底301进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区305及306和一轻掺杂漏极区307及308。
本发明提供的薄膜晶体管的制作方法，通过形成一个光阻图案，进而形成轻掺杂漏极区，简化了工艺制备过程，从而缩短了生产周期，并且通过对所述光阻图案的侧壁进行蚀刻，避免对栅金属层进行二次蚀刻，从而对植入的离子均一性影响较小，进而不会对重掺杂漏极区和轻掺杂漏极区的电子迁移率造成影响。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (20)

  1. 一种薄膜晶体管的制作方法，其包括：
    在一半导体衬底上依序沉积栅绝缘层和栅金属层；
    形成第一光阻图案于所述栅金属层上，包括：在所述栅金属层上涂覆光刻胶，利用掩膜板对所述光刻胶进行曝光，显影后形成第一光阻图案；蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，以形成栅电极，其中，所述栅电极的宽度小于所述第一光阻图案的宽度；
    以所述第一光阻图案作为掩膜，对所述半导体衬底进行第一次离子植入，以形成预备源/漏极；
    对所述第一光阻图案的侧壁进行蚀刻，以形成第二光阻图案，其中，所述第二光阻图案的宽度小于所述第一光阻图案的宽度；
    以所述第二光阻图案作为掩膜，对所述半导体衬底进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区和一轻掺杂漏极区,所述轻掺杂漏极区的宽度和所述第二光阻图案与所述栅电极的宽度之中的较小值相等。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，包括：对所述栅金属层进行第一次蚀刻，形成初步栅电极；对所述初步栅电极进行第二次蚀刻，形成栅电极。
  3. 根据权利要求2所述的薄膜晶体管的制作方法，其中所述第一次蚀刻的速率大于所述第二次蚀刻的速率。
  4. 根据权利要求3所述的薄膜晶体管的制作方法，其中所述第一次蚀刻使用氟化硫和氧气。
  5. 根据权利要求3所述的薄膜晶体管的制作方法，其中所述第二次蚀刻使用氯气和氧气。
  6. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，使用氧气对所述第一光阻图案进行蚀刻。
  7. 一种薄膜晶体管的制作方法，其包括：
    在一半导体衬底上依序沉积栅绝缘层和栅金属层；
    形成第一光阻图案于所述栅金属层上，蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，以形成栅电极，其中，所述栅电极的宽度小于所述第一光阻图案的宽度；
    以所述第一光阻图案作为掩膜，对所述半导体衬底进行第一次离子植入，以形成预备源/漏极；
    对所述第一光阻图案的侧壁进行蚀刻，以形成第二光阻图案，其中，所述第二光阻图案的宽度小于所述第一光阻图案的宽度；
    以所述第二光阻图案作为掩膜，对所述半导体衬底进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区和一轻掺杂漏极区。
  8. 根据权利要求7所述的薄膜晶体管的制作方法，其中形成第一光阻图案于所述栅金属层上，包括：在所述栅金属层上涂覆光刻胶，利用掩膜板对所述光刻胶进行曝光，显影后形成第一光阻图案。
  9. 根据权利要求8所述的薄膜晶体管的制作方法，其中蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，包括：对所述栅金属层进行第一次蚀刻，形成初步栅电极；对所述初步栅电极进行第二次蚀刻，形成栅电极。
  10. 根据权利要求9所述的薄膜晶体管的制作方法，其中所述第一次蚀刻的速率大于所述第二次蚀刻的速率。
  11. 根据权利要求10所述的薄膜晶体管的制作方法，其中所述第一次蚀刻使用氟化硫和氧气。
  12. 根据权利要求10所述的薄膜晶体管的制作方法，其中所述第二次蚀刻使用氯气和氧气。
  13. 根据权利要求7所述的薄膜晶体管的制作方法，其特征在于，使用氧气对所述第一光阻图案进行蚀刻。
  14. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述轻掺杂漏极区的宽度和所述第二光阻图案与所述栅电极的宽度之中的较小值相等。
  15. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述栅绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
  16. 根据权利要求15所述的薄膜晶体管的制作方法，其中所述氮化硅层位于所述氧化硅层上面。
  17. 一种薄膜晶体管的制作方法，其包括：
    在一半导体衬底上依序沉积栅绝缘层和栅金属层,所述栅绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合；
    形成第一光阻图案于所述栅金属层上，蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，以形成栅电极，其中，所述栅电极的宽度小于所述第一光阻图案的宽度；
    以所述第一光阻图案作为掩膜，对所述半导体衬底进行第一次离子植入，以形成预备源/漏极；
    使用氧气对所述第一光阻图案的侧壁进行蚀刻，以形成第二光阻图案，其中，所述第二光阻图案的宽度小于所述第一光阻图案的宽度；
    以所述第二光阻图案作为掩膜，对所述半导体衬底进行第二次离子植入，以形成源/漏极，其中所述源/漏极包括一重掺杂漏极区和一轻掺杂漏极区。
  18. 根据权利要求17所述的薄膜晶体管的制作方法，其中形成第一光阻图案于所述栅金属层上，包括：在所述栅金属层上涂覆光刻胶，利用掩膜板对所述光刻胶进行曝光，显影后形成第一光阻图案。
  19. 根据权利要求18所述的薄膜晶体管的制作方法，其中蚀刻未被所述第一光阻图案遮盖住的所述栅金属层，包括：对所述栅金属层进行第一次蚀刻，形成初步栅电极；对所述初步栅电极进行第二次蚀刻，形成栅电极。
  20. 根据权利要求17所述的薄膜晶体管的制作方法，其中所述氮化硅层位于所述氧化硅层上面。
PCT/CN2016/085495 2016-05-17 2016-06-12 一种薄膜晶体管的制作方法 WO2017197679A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/128,112 US9960255B2 (en) 2016-05-17 2016-06-12 Method for manufacturing thin film transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610325163.6A CN105762081A (zh) 2016-05-17 2016-05-17 一种薄膜晶体管的制作方法
CN201610325163.6 2016-05-17

Publications (1)

Publication Number Publication Date
WO2017197679A1 true WO2017197679A1 (zh) 2017-11-23

Family

ID=56324031

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/085495 WO2017197679A1 (zh) 2016-05-17 2016-06-12 一种薄膜晶体管的制作方法

Country Status (3)

Country Link
US (1) US9960255B2 (zh)
CN (1) CN105762081A (zh)
WO (1) WO2017197679A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109616479A (zh) * 2018-12-18 2019-04-12 武汉华星光电半导体显示技术有限公司 Ltps tft基板的制作方法
CN110349858A (zh) * 2019-06-20 2019-10-18 深圳市华星光电技术有限公司 阵列基板的制备方法和制备系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104064472A (zh) * 2014-06-13 2014-09-24 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置
CN104538455A (zh) * 2014-12-31 2015-04-22 上海天马有机发光显示技术有限公司 一种轻掺杂漏极区的制作方法、薄膜晶体管及阵列基板
US20150206905A1 (en) * 2013-03-05 2015-07-23 Boe Technology Group Co., Ltd. Polysilicon thin film transistor and manufacturing method thereof, array substrate

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4149904A (en) * 1977-10-21 1979-04-17 Ncr Corporation Method for forming ion-implanted self-aligned gate structure by controlled ion scattering
US4599118A (en) * 1981-12-30 1986-07-08 Mostek Corporation Method of making MOSFET by multiple implantations followed by a diffusion step
JP3474604B2 (ja) * 1993-05-25 2003-12-08 三菱電機株式会社 薄膜トランジスタおよびその製法
US5650343A (en) * 1995-06-07 1997-07-22 Advanced Micro Devices, Inc. Self-aligned implant energy modulation for shallow source drain extension formation
US5929496A (en) * 1997-12-18 1999-07-27 Gardner; Mark I. Method and structure for channel length reduction in insulated gate field effect transistors
TW565939B (en) * 2000-04-07 2003-12-11 Koninkl Philips Electronics Nv Electronic device manufacture
CN101236904A (zh) * 2008-02-29 2008-08-06 上海广电光电子有限公司 具有轻掺杂漏极区的多晶硅薄膜晶体管的制造方法
CN103794566A (zh) * 2014-01-17 2014-05-14 深圳市华星光电技术有限公司 一种显示面板制作方法
CN105428244A (zh) * 2016-01-14 2016-03-23 信利（惠州）智能显示有限公司 薄膜晶体管及制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150206905A1 (en) * 2013-03-05 2015-07-23 Boe Technology Group Co., Ltd. Polysilicon thin film transistor and manufacturing method thereof, array substrate
CN104064472A (zh) * 2014-06-13 2014-09-24 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置
CN104538455A (zh) * 2014-12-31 2015-04-22 上海天马有机发光显示技术有限公司 一种轻掺杂漏极区的制作方法、薄膜晶体管及阵列基板

Also Published As

Publication number Publication date
CN105762081A (zh) 2016-07-13
US9960255B2 (en) 2018-05-01
US20180083123A1 (en) 2018-03-22

Similar Documents

Publication Publication Date Title
JPH0350740A (ja) Ｍｉｓ型半導体装置の製造方法
WO2018120309A1 (zh) Oled显示装置的阵列基板及其制作方法
WO2015090016A1 (zh) 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置
WO2017215109A1 (zh) 双栅电极氧化物薄膜晶体管及其制备方法
WO2017054191A1 (zh) 一种tft阵列基板及其制作方法
WO2017054250A1 (zh) 一种tft阵列基板及其制作方法
WO2017035851A1 (zh) Tft、阵列基板及tft的制备方法
WO2016119280A1 (zh) 氧化物薄膜晶体管及其制作方法
WO2017054258A1 (zh) Tft阵列基板的制备方法、tft阵列基板及显示装置
WO2017140015A1 (zh) 双栅极tft阵列基板及制作方法
WO2017054259A1 (zh) 液晶显示面板、阵列基板及其制造方法
WO2018032558A1 (zh) 一种阵列基板及其制作方法
WO2017197679A1 (zh) 一种薄膜晶体管的制作方法
KR20210075164A (ko) 트랜지스터 제조 방법 및 게이트 올 어라운드 디바이스 구조
WO2013013586A1 (zh) 薄膜晶体管、其制造方法及包括该薄膜晶体管的阵列基板
WO2016090690A1 (zh) 一种ltps像素单元及其制造方法
WO2017206269A1 (zh) 阵列基板及其制备方法
WO2019071675A1 (zh) 一种薄膜晶体管及其制作方法
WO2017152450A1 (zh) Ffs模式的阵列基板及制作方法
WO2016106923A1 (zh) 一种ltps tft像素单元及其制造方法
WO2020113595A1 (zh) 主动开关及其制作方法、显示装置
WO2019029009A1 (zh) 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板
WO2015154327A1 (zh) 薄膜晶体管的制程方法
WO2019015055A1 (zh) Amoled 器件的阵列基板的制作方法
WO2020107753A1 (zh) 薄膜晶体管、薄膜晶体管制备方法及制备系统

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15128112

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16902061

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16902061

Country of ref document: EP

Kind code of ref document: A1