WO2020107753A1 - 薄膜晶体管、薄膜晶体管制备方法及制备系统 - Google Patents

薄膜晶体管、薄膜晶体管制备方法及制备系统 Download PDF

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WO2020107753A1
WO2020107753A1 PCT/CN2019/079275 CN2019079275W WO2020107753A1 WO 2020107753 A1 WO2020107753 A1 WO 2020107753A1 CN 2019079275 W CN2019079275 W CN 2019079275W WO 2020107753 A1 WO2020107753 A1 WO 2020107753A1
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active layer
layer
film transistor
thin film
photoresist
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PCT/CN2019/079275
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English (en)
French (fr)
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聂晓辉
张嘉伟
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武汉华星光电技术有限公司
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Priority to US16/467,046 priority Critical patent/US10916641B2/en
Publication of WO2020107753A1 publication Critical patent/WO2020107753A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species

Definitions

  • the present application relates to the field of display technology, in particular to a thin film transistor, a thin film transistor preparation method and a preparation system.
  • the top gate structure is usually used in the device design, and the self-alignment feature is used Lightly doped drain (Lightly DopedDrain (LDD) structure to reduce channel leakage current.
  • LDD Lightly DopedDrain
  • the LTPS-TFT is formed by dry etching to form a silicon island pattern
  • the gate insulating layer 200 is formed on the silicon island 100 using a chemical vapor deposition process
  • the silicon island 100 The gate insulating layer 201 formed on the side area is thinner, the gate insulating layer 202 formed on the top surface area of the silicon island 100 is thicker, and the thin film transistor (Thin-film transistor (TFT) operation, the area where the gate insulating layer 202 is located is unintentionally turned on in advance to form a weak channel current, causing a Hump effect, resulting in a decrease in the electrical reliability of the device.
  • TFT thin film transistor
  • the present application provides a thin film transistor and a preparation method thereof, so as to alleviate the technical problem that the existing silicon island boundary gate insulating layer is thin and causes the Hump effect.
  • the present application provides a method for preparing a thin film transistor, which includes:
  • Step S1 Provide a glass substrate on which a buffer layer and a polysilicon active layer are deposited in sequence;
  • Step S2 coating a photoresist on the active layer, so that the part of the active layer that is not covered by the photoresist is etched away;
  • Step S3 Doping and modifying the side of the active layer to make it a high resistance region
  • Step S4 After the doping modification on the side of the active layer is completed, strip the photoresist on the top surface of the active layer after modification;
  • Step S5 a gate insulating layer is prepared on the active layer.
  • doping and modifying the side of the active layer to make it into a high resistance region includes: doping and modifying the side of the active layer using directional ion implantation technology to make it become High resistance area.
  • the thin film transistor is an N-type thin film transistor, and the ion doped on the side of the active layer in step S3 is a group V compound.
  • the ion doped on the side of the active layer in step S3 is phosphorus trihydride (PH 3 ).
  • the thin film transistor is a P-type thin film transistor, and the ion doped on the side of the active layer in the step S3 is a group III compound.
  • the ion doped on the side of the active layer in step S3 is boron trifluoride (BF 3 ).
  • the ion implantation energy in the step of doping and modifying the side of the active layer by using the directional ion implantation technology is 10-15 keV.
  • step S2 specifically includes the following steps:
  • Step S21 coating a photoresist layer on the surface of the active layer away from the substrate, the photoresist layer completely covering the active layer;
  • Step S22 Expose the photoresist layer with a half-tone mask, and develop the exposed photoresist layer with a developing solution to form a photoresist pattern;
  • Step S23 using the photoresist pattern as a mask layer, dry etching the active layer to remove a portion of the active layer not covered by the photoresist pattern.
  • a thin film transistor which includes:
  • a buffer layer prepared on the substrate
  • An active layer prepared on the buffer layer, and the side of the active layer is a high resistance region
  • the gate insulating layer is prepared on the surface of the active layer.
  • the thin film transistor of the present application is manufactured by using the above thin film transistor manufacturing method.
  • the present application also provides a thin film transistor manufacturing system, which includes:
  • the buffer layer preparation device is used for depositing and forming a buffer layer on a glass substrate
  • An active layer preparation device for depositing and forming a polysilicon active layer on the buffer layer
  • a silicon island pattern forming device for coating a photoresist on the active layer, and etching away portions of the active layer not covered by the photoresist to form a silicon island pattern;
  • a photoresist removing device used for stripping the photoresist on the top surface of the active layer after the doping modification on the side of the active layer;
  • a gate preparation device is used to prepare a gate insulating layer on the active layer.
  • the doping device includes an ion implantation portion, and the ion implantation portion is used for doping and modifying the side of the active layer by directional ion implantation technology to modify It becomes a high resistance area.
  • the thin-film transistor is an N-type thin-film transistor, and the ions doped in the ion implantation portion are group V compounds.
  • the ion doped in the ion implantation portion is phosphorus trihydride (PH 3 ).
  • the thin film transistor is a P-type thin film transistor, and the ions doped in the ion implantation portion are group III compounds.
  • the ion doped in the ion implantation portion is boron trifluoride (BF 3 ).
  • the ion implantation energy doped by the ion implantation portion is 10-15 keV.
  • the silicon island pattern forming device includes:
  • a photoresist coating member for coating a photoresist layer on the surface of the active layer away from the substrate, the photoresist layer completely covering the active layer;
  • a photoresist pattern forming member for exposing the photoresist layer with a halftone mask, and developing the exposed photoresist layer with a developing solution to form a photoresist pattern;
  • An etching member is used to use the photoresist pattern as a mask layer to dry etch the active layer to remove a portion of the active layer not covered by the photoresist pattern.
  • the active layer preparation device is used to deposit and form an amorphous silicon active layer on the buffer layer, and perform an excimer laser on the amorphous silicon active layer Annealing converts amorphous silicon to polycrystalline silicon.
  • the gate preparation device is used to prepare a gate insulating layer on the active layer by a chemical deposition method.
  • the present application provides a thin film transistor, a thin film transistor preparation method, and a preparation system.
  • the thin film transistor includes a substrate, a buffer layer, an active layer, and a gate insulating layer. After the active layer is formed with a silicon island pattern, ion implantation is used Doping technology doped and modified the side regions of the active layer without photoresist protection to change its surface layer into a high-resistance region, and then used a chemical deposition process to prepare a gate insulating layer, which was formed by dry etching.
  • the side of the active layer has a certain inclination angle, so the gate insulating layer deposited thereon is thinner than other positions, and the side region of the active layer is made into a high-resistance structure to avoid the gate insulating layer.
  • the thin edge causes unintentional opening during operation to form a weak channel current, improve the boundary effect, and improve the electrical reliability of the thin film transistor.
  • FIG. 1 is a schematic structural diagram of a conventional low-temperature polysilicon thin film transistor
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of this application;
  • FIG. 3 is a schematic structural diagram of different stages in the preparation process of a thin film transistor provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present application.
  • the present application is directed to the thinning of the boundary gate insulating layer of the silicon island of the existing thin film transistor, which leads to the Hump effect; this embodiment can alleviate this defect.
  • a specific embodiment of the present application provides a method for manufacturing a thin film transistor, the method includes the following steps;
  • Step S1 Provide a glass substrate on which a buffer layer and a polysilicon active layer are deposited in sequence;
  • Step S2 coating a photoresist on the active layer, so that the part of the active layer that is not covered by the photoresist is etched away;
  • Step S3 Doping and modifying the side of the active layer to make it a high resistance region
  • Step S4 After the doping modification on the side of the active layer is completed, strip the photoresist on the top surface of the active layer after modification;
  • Step S5 a gate insulating layer is prepared on the active layer.
  • the thin film transistor may be a top-gate low-temperature polysilicon thin film transistor.
  • a substrate 10 is first provided, a buffer layer 20 is prepared on the substrate 10, an amorphous silicon film layer is prepared on the buffer layer 20, and the low-temperature crystallization process The amorphous silicon film layer is converted into a polysilicon active layer 30.
  • the substrate 10 is mostly made of glass. In order to prevent harmful substances in the substrate 10 from adversely affecting the performance of the active layer 30, it is necessary to first use a chemical vapor deposition or sputtering method to form a layer of buffer on the substrate 10
  • the layer 20 is used to block impurities contained in the glass from diffusing into the active layer 30.
  • pre-cleaning of the substrate 10 is required to improve the cleanliness of the substrate 10.
  • the material of the buffer layer 20 may be oxide, nitride, or oxynitride.
  • the buffer layer 20 may be a single-layer, double-layer, or multi-layer structure.
  • the buffer layer 31 may be SiNx, SiOx or Si(ON)x.
  • the conversion of amorphous silicon into polycrystalline silicon in the active layer 30 can be obtained by excimer laser annealing.
  • the commonly used excimer lasers include xenon chloride (XeCl) laser, ArF laser, KrF laser, and XeF laser. These excimer lasers generate laser beams in the ultraviolet band through the ultraviolet band.
  • the short pulse laser beam irradiates the amorphous silicon in the active layer 30, and the amorphous silicon will quickly absorb the laser energy to melt and recrystallize.
  • the buffer layer 20 can reduce the thermal diffusion between the polycrystalline silicon active layer 30 and the substrate 10, and reduce the temperature rise during annealing to the substrate 10 effects.
  • a photoresist layer 40 with a uniform thickness is coated on the surface of the active layer 30 away from the substrate 10, and the photoresist layer 40 completely covers the active layer 30.
  • the photoresist layer 40 may be a photoresist.
  • the photoresist layer 40 is exposed using a halftone mask, the photoresist layer 41 in the exposed portion is dissolved with a developer, and then deionized water is used The dissolved photoresist layer 41 is washed away, thereby forming a photoresist pattern 42.
  • the active layer 30 includes a first region 31 blocked by the photoresist pattern 42 and a second region 32 not blocked by the photoresist pattern , A dry etching process is used to etch away the first region 31 on the active layer 30, leaving the second region 32.
  • the side surface 321 of the second region 32 has a certain inclination angle, and the side surface 321 is doped and modified by directional ion implantation technology to make its surface layer 3211 Become a high resistance area.
  • intrinsic polysilicon does not have conductivity, it can be made into a semiconductor with a specific conductivity type by specific ion doping.
  • Existing low-temperature polysilicon thin film transistors can be divided into N-type thin film transistors and P according to the type of channel carriers.
  • the doping substance corresponding to the N-type thin-film transistor is a group III compound, such as BF 3
  • the doping substance corresponding to the P-type thin-film transistor is a group V compound, such as PH 3 .
  • the low-temperature polysilicon thin-film transistor is an N-type thin-film transistor
  • the surface layer 3211 of the second region 32 needs to be doped and modified with PH 3 or other group V compounds to form a high-resistance region
  • the low-temperature polysilicon The thin film transistor is a P-type thin film transistor, and the surface layer 3211 of the second region 32 needs to be doped and modified with BH 3 or other group III compounds to form a high resistance region.
  • N-type ions such as phosphorus ions and phosphorus trihydride and P-type ions such as boron ions and boron trifluoride have a potential energy difference relative to the polysilicon substrate, they will need to overcome their N-type ions and P-type ions in polysilicon when transferring electrons
  • the difference in potential barrier established between the substrates greatly increases the difficulty of electron conduction, thereby achieving the purpose of increasing the resistance value of the surface layer 3211.
  • the method used for doping is directional ion implantation, and the ion implantation energy is 10-15 keV.
  • the photoresist pattern 42 is peeled off.
  • a gate insulating layer 50 is prepared on the second region 32.
  • the cleaning process of the interface is helpful to reduce the interface energy and improve the performance of the TFT, so the second region 32 is The gate insulating layer 50 is deposited after the interface is cleaned.
  • the preparation method further includes sequentially forming a gate layer, an interlayer insulating layer, and a source-drain layer on the gate insulating layer 50 from bottom to top.
  • the thickness of the gate insulating layer 50 prepared later is not uniform, and is on the top surface of the second region 32
  • the gate insulating layer 50 is thicker, and the gate insulating layer 50 is thinner on the side of the second region 32, after the voltage is applied to the gate, the thinner side region of the gate insulating layer 50 is turned on first , The thicker top surface area of the gate insulating layer 50 is turned on, so that the channels under the gate insulating layer 50 are not reversed at the same time, which may cause different slopes of the Id-Vg characteristic curve of the device , Resulting in an inflection point of the characteristic curve, the so-called hump effect (hump effect), thereby reducing the stability of the device operating characteristics.
  • the surface layer 3211 of the second region 32 is changed into a high resistance region, and then the gate insulating layer 50 is prepared in sequence. After the voltage is applied to the gate, the top surface and the side surface The gate insulating layer 50 is turned on at the same time, and the channel under the gate insulating layer 50 is inverted simultaneously, which improves the boundary effect and improves the electrical reliability of the device.
  • an embodiment of the present application further provides a thin film transistor, including a substrate 10, a buffer layer 20 provided on the substrate 10, a polysilicon active layer 30 provided on the buffer layer 20, and a cover
  • the source electrode 80 and the drain electrode 90 provided on the interlayer insulating layer 70, the source electrode 80 and the drain electrode 90 are connected to the active layer 30 through via holes of the gate insulating layer 50 and the interlayer insulating layer 70, respectively .
  • a buffer layer 20 and an amorphous silicon active layer 30 are sequentially deposited on the substrate 10, the amorphous silicon is converted into polycrystalline silicon through a low-temperature crystallization process, and a photoresist 40 is coated on the active layer 30 (in the figure (Not marked), the photoresist 40 is exposed and developed through a yellow light process, and then the part of the active layer 30 that is not protected by the photoresist 40 is etched away using an etching process, using ion implantation Doping technique is used to modify the side 301 of the active layer 30 to make the surface 3011 into a high resistance region.
  • the photoresist 40 on the top surface of the active layer 30 is peeled off, and then A gate insulating layer 50, a gate 60, an interlayer insulating layer 70, and a source 80 and a drain 90 are sequentially prepared on the active layer 30 to form the thin film transistor.
  • the side surface 321 of the second region 32 has a certain inclination angle, and the thickness of the gate insulating layer 50 prepared later is not uniform.
  • the gate insulating layer 50 on the top surface of the second region 32 is thicker, and the gate insulating layer 50 is thinner on the side surface of the second region 32.
  • the side surface 301 of the active layer 30 is doped by ion implantation doping technology Doping modification to make the surface 3011 into a high-resistance region, and then preparing the gate insulating layer 50 in sequence, after the voltage is applied to the gate 60, the gates on the top surface and the side surfaces are insulated
  • the layers 50 are turned on at the same time, and the channels under the gate insulating layer 50 are simultaneously inverted, which improves the boundary effect and improves the electrical reliability of the device.
  • the present application also provides a thin film transistor preparation system, which includes: a buffer layer preparation device for depositing and forming a buffer layer on a glass substrate; an active layer preparation device for depositing and forming a polysilicon active on the buffer layer A layer; a silicon island patterning device for coating a photoresist on the active layer, and etching away portions of the active layer that are not covered by the photoresist to form a silicon island pattern; doping Device for doping and modifying the side of the active layer to make it into a high-resistance region; photoresist removing device for modifying the doping and modification of the side of the active layer The photoresist stripping of the top surface of the active layer; a grid preparation device for preparing a gate insulating layer on the active layer.
  • the doping device includes an ion implantation portion, and the ion implantation portion is used for doping modification of the side of the active layer by directional ion implantation technology to make it into a high resistance region.
  • the thin film transistor is an N-type thin film transistor, and the ions doped in the ion implantation part are group V compounds.
  • the ion doped by the ion implantation portion is phosphorus trihydride (PH 3 ).
  • the thin film transistor is a P-type thin film transistor, and the ions doped in the ion implantation portion are group III compounds.
  • the ion doped by the ion implantation portion is boron trifluoride (BF 3 ).
  • the ion implantation energy of the ion implantation portion is 10-15 keV.
  • the silicon island pattern forming device includes: a photoresist coating member for coating a photoresist layer on a surface of the active layer away from the substrate, the photoresist layer completely covering the photoresist layer The active layer; a photoresist pattern forming member for exposing the photoresist layer with a halftone mask, and developing the exposed photoresist layer with a developing solution to form a photoresist pattern; an etching member, Use the photoresist pattern as a mask layer to dry etch the active layer to remove a portion of the active layer not covered by the photoresist pattern.
  • the active layer preparation device is used to deposit and form an amorphous silicon active layer on the buffer layer, and perform excimer laser annealing on the amorphous silicon active layer to Crystalline silicon is converted into polycrystalline silicon.
  • the gate preparation device is used to prepare a gate insulating layer by chemical deposition on the active layer.
  • Embodiments of the present application provide a thin film transistor, a thin film transistor manufacturing method, and a manufacturing system.
  • the thin film transistor includes a substrate, a buffer layer, an active layer, and a gate insulating layer. After forming a silicon island pattern in the active layer, ions are used Implantation doping technology doped and modified the side region of the active layer without photoresist protection, and changed its surface layer into a high-resistance region, and then used a chemical deposition process to prepare the gate insulating layer, which was formed by dry etching.
  • the side of the active layer has a certain inclination angle, so the gate insulating layer deposited thereon is thinner than other positions, and the side region of the active layer is made into a high-resistance structure to avoid the gate
  • the thin edge of the insulating layer causes the edge to unintentionally turn on during operation to form a weak channel current, improve the boundary effect, and improve the electrical reliability of the thin film transistor.

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Abstract

一种薄膜晶体管、薄膜晶体管制备方法及制备系统，所述薄膜晶体管包括基板（10），缓冲层（20），有源层（30）和栅极绝缘层（50），对所述有源层（30）侧面区域掺杂改性，将其表层变为高电阻区域，再利用化学沉积工艺制备栅极绝缘层（50），避免了因所述栅极绝缘层（50）偏薄导致的工作时边缘非故意开启形成弱沟道电流，提高了所述薄膜晶体管电学可靠性。

Description

薄膜晶体管、薄膜晶体管制备方法及制备系统 技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管、薄膜晶体管制备方法及制备系统。
 背景技术
现有的低温多晶硅薄膜晶体管（Low Temperature Poly Silicon-Thin-film transistor，LTPS-TFT）中，为避免漏电流较大引起的显示不良，通常器件设计时使用顶栅结构，利用自对准特点制作轻掺杂漏(Lightly DopedDrain，LDD)结构以降低沟道漏电流。如图1所示，在实际生产中，由于LTPS-TFT是通过干法刻蚀形成硅岛图案，因此利用化学气相沉积工艺在硅岛100上形成栅极绝缘层200时，所述硅岛100侧面区域形成的栅极绝缘层201较薄，所述硅岛100顶面区域形成的栅极绝缘层202较厚，薄膜晶体管（Thin-film transistor，TFT）工作时，所述栅极绝缘层202所在区域提前非故意开启形成弱沟道电流，引起驼峰（Hump）效应，导致器件电学可靠性下降。
因此，提供一种可以缓解硅岛边界栅极绝缘层偏薄而导致Hump效应的技术，是本领域技术人员亟待解决的技术问题。
 技术问题
本申请提供一种薄膜晶体管及其制备方法，以缓解现有硅岛边界栅极绝缘层偏薄而导致Hump效应的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种薄膜晶体管的制备方法，其包括：
步骤S1、提供一玻璃基板，在所述基板上依次沉积形成缓冲层和多晶硅有源层；
步骤S2、在所述有源层上涂布光阻，以使得所述有源层上未被所述光阻覆盖的部分刻蚀掉；
步骤S3、对所述有源层侧面掺杂改性，使其成为高电阻区域；
步骤S4、在所述有源层侧面掺杂改性完成后，将掺杂改性后的有源层顶面的光阻剥离；
步骤S5、在所述有源层上制备栅极绝缘层。
在本申请的制备方法中，对所述有源层侧面掺杂改性，使其成为高电阻区域，包括：利用定向离子植入技术对所述有源层侧面掺杂改性，使其成为高电阻区域。
在本申请的制备方法中，所述薄膜晶体管为N型薄膜晶体管，所述步骤S3中所述有源层侧面掺杂的离子为V族化合物。
在本申请的制备方法中，所述步骤S3中所述有源层侧面掺杂的离子为三氢化磷（PH 3）。
在本申请的制备方法中，所述薄膜晶体管为P型薄膜晶体管，所述步骤S3中所述有源层侧面掺杂的离子为III族化合物。
在本申请的制备方法中，所述步骤S3中所述有源层侧面掺杂的离子为三氟化硼（BF 3）。
在本申请的制备方法中，所述利用定向离子植入技术对所述有源层侧面掺杂改性的步骤中离子植入能量为10-15keV。
在本申请的制备方法中，所述步骤S2具体包括如下步骤：
步骤S21、在所述有源层远离所述基板的表面涂布光阻层，所述光阻层完全覆盖所述有源层；
步骤S22、采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成光阻图案；
步骤S23、以所述光阻图案作为掩膜层，对所述有源层进行干法刻蚀，将未被所述光阻图案覆盖的部分有源层移除。
同时，本申请提供一种薄膜晶体管，其包括：
基板；
缓冲层，制备于所述基板上；
有源层，制备于所述缓冲层上，所述有源层侧面为高电阻区域；
栅极绝缘层，制备于所述有源层表面。
本申请的薄膜晶体管采用上述的薄膜晶体管的制备方法制备。
本申请还提供一种薄膜晶体管的制备系统，其包括：
缓冲层制备装置，用于在玻璃基板上沉积形成缓冲层；
有源层制备装置，用于在所述缓冲层上沉积形成多晶硅有源层；
硅岛图案形成装置，用于在所述有源层上涂布光阻，并将所述有源层上未被所述光阻覆盖的部分刻蚀掉，形成硅岛图案；
掺杂装置，用于对所述有源层侧面掺杂改性，使其成为高电阻区域；
光阻去除装置，用于在所述有源层侧面掺杂改性完成后，将掺杂改性后的有源层顶面的光阻剥离；
栅极制备装置，用于在所述有源层上制备栅极绝缘层。
在本申请的薄膜晶体管的制备系统中，所述掺杂装置包括离子植入部，所述离子植入部用于对所述有源层侧面进行定向离子植入技术来掺杂改性，使其成为高电阻区域。
在本申请的薄膜晶体管的制备系统中，所述薄膜晶体管为N型薄膜晶体管，所述离子植入部掺杂的离子为V族化合物。
在本申请的薄膜晶体管的制备系统中，所述离子植入部掺杂的离子为三氢化磷（PH 3）。
在本申请的薄膜晶体管的制备系统中，所述薄膜晶体管为P型薄膜晶体管，所述离子植入部掺杂的离子为III族化合物。
在本申请的薄膜晶体管的制备系统中，所述离子植入部掺杂的离子为三氟化硼（BF 3）。
在本申请的薄膜晶体管的制备系统中，所述离子植入部掺杂的离子植入能量为10-15keV。
在本申请的薄膜晶体管的制备系统中，所述硅岛图案形成装置包括：
光阻涂布构件，用于在所述有源层远离所述基板的表面涂布光阻层，所述光阻层完全覆盖所述有源层；
光阻图案形成构件，用于采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成光阻图案；
刻蚀构件，用于以所述光阻图案作为掩膜层，对所述有源层进行干法刻蚀，将未被所述光阻图案覆盖的部分有源层移除。
在本申请的薄膜晶体管的制备系统中，所述有源层制备装置，用于在所述缓冲层上沉积形成非晶硅有源层，并对所述非晶硅有源层进行准分子激光退火，将非晶硅转化为多晶硅。
在本申请的薄膜晶体管的制备系统中，所述栅极制备装置用于在所述有源层上用化学沉积法制备栅极绝缘层。
 有益效果
本申请提供一种薄膜晶体管、薄膜晶体管制备方法及制备系统，所述薄膜晶体管包括基板，缓冲层，有源层和栅极绝缘层，所述有源层形成硅岛图案后，利用离子植入掺杂技术对无光阻保护的所述有源层侧面区域掺杂改性，将其表层变为高电阻区域，再利用化学沉积工艺制备栅极绝缘层，由于干法刻蚀形成的所述有源层侧面具有一定倾斜角度，因此在其上沉积的所述栅极绝缘层较其他位置偏薄，将所述有源层侧面区域制作成高电阻结构，避免了因所述栅极绝缘层偏薄导致的工作时边缘非故意开启形成弱沟道电流，改善边界效应，提高了所述薄膜晶体管电学可靠性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有低温多晶硅薄膜晶体管的结构示意图；
图2为本申请实施例提供的薄膜晶体管的制备方法流程图；
图3为本申请实施例提供的薄膜晶体管的制备过程中的不同阶段的结构示意图；
图4为本申请实施例提供的薄膜晶体管的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有薄膜晶体管硅岛边界栅绝缘层偏薄而导致Hump效应；本实施例能够缓解该缺陷。
如图2所示，本申请具体实施例提供了一种薄膜晶体管的制备方法，所述方法包括以下步骤；
步骤S1、提供一玻璃基板，在所述基板上依次沉积形成缓冲层和多晶硅有源层；
步骤S2、在所述有源层上涂布光阻，以使得所述有源层上未被所述光阻覆盖的部分刻蚀掉；
步骤S3、对所述有源层侧面掺杂改性，使其成为高电阻区域；
步骤S4、在所述有源层侧面掺杂改性完成后，将掺杂改性后的有源层顶面的光阻剥离；
步骤S5、在所述有源层上制备栅极绝缘层。
下面结合附图详细介绍本申请具体实施例提供的薄膜晶体管的制备过程。
优选地，该薄膜晶体管可以为顶栅型低温多晶硅薄膜晶体管。
如图3中的a所示，先提供一基板10，在所述基板10上制备一层缓冲层20，在所述缓冲层20上制备一非晶硅膜层，通过低温结晶工艺将所述非晶硅膜层转化为多晶硅有源层30。
所述基板10多采用玻璃材质，为了防止所述基板10中有害物质对所述有源层30的性能产生不良影响，需要先采用化学气相沉积或者溅射等方法在基板10上形成一层缓冲层20，用于阻挡玻璃中所含的杂质扩散进入所述有源层30。此外，在沉积所述缓冲层20之前需要进行所述基板10的预清洗，提高所述基板10的清洁度。
所述缓冲层20材料可选用氧化物、氮化物或者氮氧化物等，所述缓冲层20可以为单层、双层或者多层结构。具体地，所述缓冲层31可以是SiNx，SiOx 或Si(ON)x。
所述有源层30中非晶硅转化为多晶硅可以通过准分子激光退火的方法得到。采用准分子激光退火晶化法时，一般用的准分子激光有氯化氙(XeCl)激光、ArF激光、KrF激光和XeF激光等，这类准分子激光器产生紫外波段的激光束，通过紫外波段的短脉冲激光束照射所述有源层30中的非晶硅，非晶硅会快速吸收激光能量而融化和再结晶。
在利用准分子激光退火将非晶硅转变为多晶硅以形成有源层30时，所述缓冲层20可以减小多晶硅有源层30和基板10之间的热扩散，降低退火时温度上升对基板10的影响。
当然，本申请中低温结晶工艺还可以采用其他方法，例如金属诱导横向晶化法、固相晶化、准分子激光晶化和快速热退火法等。
如图3中的b所示，在所述有源层30远离所述基板10的表面涂布厚度均匀的光阻层40，所述光阻层40完全覆盖所述有源层30。具体地，所述光阻层40可以为光刻胶。
如图3中的c、图3中的d所示，采用半色调掩膜对所述光阻层40进行曝光，用显影剂将曝光部分的光阻层41溶解掉，然后用去离子水将溶解的光阻层41冲走,从而形成光阻图案42。
如图3中的e、图3中的f所示，所述有源层30包括被所述光阻图案42遮挡的第一区域31，和未被所述光阻图案遮挡的第二区域32，采用干法刻蚀工艺将所述有源层30上的所述第一区域31刻蚀掉，留下所述第二区域32。
如图3中的g所示，由于使用干法刻蚀，所述第二区域32的侧面321具有一定倾斜角度，利用定向离子植入技术对所述侧面321掺杂改性，使其表层3211成为高电阻区域。
由于本征多晶硅不具备导电能力，通过特定离子掺杂可以使其成为具有特定导电类型的半导体，现有的低温多晶硅薄膜晶体管根据沟道载流子的类型不同可以分为N型薄膜晶体管和P型薄膜晶体管，所述N型薄膜晶体管对应的掺杂物质为III族化合物，比如BF 3，所述P型薄膜晶体管对应的掺杂物质为V族化合物，比如PH 3。
因此，如果所述低温多晶硅薄膜晶体管为N型薄膜晶体管，需使用PH 3或其他V族化合物对所述第二区域32的所述表层3211掺杂改性形成高电阻区域，如果所述低温多晶硅薄膜晶体管为P型薄膜晶体管，需使用BH 3或其他III族化合物对所述第二区域32的所述表层3211掺杂改性形成高电阻区域。由于磷离子、三氢化磷等N型离子与硼离子、三氟化硼等P型离子相对于多晶硅基底具有电位能差异，将使得电子传递时，需要克服其N型离子、P型离子在多晶硅基底间所建立的势垒差，使得电子传导时的困难度大为增加，从而达到增加所述表层3211电阻值的目的。
具体地，掺杂使用的方法为定向离子植入，离子植入能量为10-15keV。
如图3中的h所示，离子植入完成后将所述光阻图案42剥离。
如图3中的i所示，在所述第二区域32上制备栅极绝缘层50。
由于所述第二区域32与所述栅极绝缘层50之间的界面将形成TFT沟道通路，界面的清洁处理有利于降低界面能从而提高TFT的性能，因此对所述第二区域32进行界面清理后再沉积所述栅极绝缘层50。
该制备方法还包括在所述栅极绝缘层50上自下而上依次形成栅极层、层间绝缘层、以及源漏极层。
根据上述结构，由于干法刻蚀后，所述第二区域32的侧面321具有一定倾斜角度，后序制备的所述栅极绝缘层50的厚度不均匀，在所述第二区域32顶面所述栅极绝缘层50较厚，在所述第二区域32侧面所述栅极绝缘层50较薄，则在栅极施加电压之后，所述栅极绝缘层50较薄的侧面区域先导通，所述栅极绝缘层50较厚的顶面区域后导通，使位于所述栅极绝缘层50下方的沟道不是同时反型，则引起器件的Id - Vg特性曲线存在斜率不同的情况，导致该特性曲线存在拐点，即所谓的hump效应（驼峰效应），从而降低了器件工作特性稳定性。
通过上述设计，将所述第二区域32表层3211变为高电阻区域，后序再制备所述栅极绝缘层50，则在栅极施加电压后，所述顶面和所述侧面上的所述栅极绝缘层50同时导通，位于所述栅极绝缘层50下方的沟道同时反型，改善了边界效应，提高器件电学可靠性。
如图4所示，本申请实施例还提供一种薄膜晶体管，包括基板10、设于所述基板10上的缓冲层20、设于所述缓冲层20上的多晶硅有源层30、覆盖所述多晶硅有源层30的栅极绝缘层50、设于所述栅极绝缘层50上的栅极60、在所述栅极绝缘层50上覆盖所述栅极60的层间绝缘层70及设于所述层间绝缘层70上的源极80和漏极90，源极80和漏极90分别通过栅极绝缘层50和层间绝缘层70的过孔连接到所述有源层30。
在所述基板10上依次沉积缓冲层20和非晶硅有源层30，通过低温结晶工艺将所述非晶硅转化成多晶硅，在所述有源层30上涂布光阻40（图中未标出），通过黄光工艺对所述光阻40进行曝光、显影，然后采用刻蚀工艺将所述有源层30上未被所述光阻40保护的部分刻蚀掉，利用离子植入掺杂技术对所述有源层30侧面301掺杂改性，使其表面3011成为高电阻区域，离子植入完成后将所述有源层30顶面的所述光阻40剥离，然后依次在所述有源层30上制备栅极绝缘层50、栅极60、层间绝缘层70、以及源极80和漏极90，形成所述薄膜晶体管。
具体的，在上述的薄膜晶体管中，由于干法刻蚀后，所述第二区域32的侧面321具有一定倾斜角度，后序制备的所述栅极绝缘层50的厚度不均匀，在所述第二区域32顶面所述栅极绝缘层50较厚，在所述第二区域32侧面所述栅极绝缘层50较薄，利用离子植入掺杂技术对所述有源层30侧面301掺杂改性，使其表面3011成为高电阻区域，后序再制备所述栅极绝缘层50，则在栅极60施加电压后，所述顶面和所述侧面上的所述栅极绝缘层50同时导通，位于所述栅极绝缘层50下方的沟道同时反型，改善了边界效应，提高器件电学可靠性。
本申请还提供一种薄膜晶体管的制备系统，其包括：缓冲层制备装置，用于在玻璃基板上沉积形成缓冲层；有源层制备装置，用于在所述缓冲层上沉积形成多晶硅有源层；硅岛图案形成装置，用于在所述有源层上涂布光阻，并将所述有源层上未被所述光阻覆盖的部分刻蚀掉，形成硅岛图案；掺杂装置，用于对所述有源层侧面掺杂改性，使其成为高电阻区域；光阻去除装置，用于在所述有源层侧面掺杂改性完成后，将掺杂改性后的有源层顶面的光阻剥离；栅极制备装置，用于在所述有源层上制备栅极绝缘层。
在一种实施例中，所述掺杂装置包括离子植入部，所述离子植入部用于对所述有源层侧面进行定向离子植入技术来掺杂改性，使其成为高电阻区域。
在一种实施例中，所述薄膜晶体管为N型薄膜晶体管，所述离子植入部掺杂的离子为V族化合物。
在一种实施例中，所述离子植入部掺杂的离子为三氢化磷（PH 3）。
在一种实施例中，所述薄膜晶体管为P型薄膜晶体管，所述离子植入部掺杂的离子为III族化合物。
在一种实施例中，所述离子植入部掺杂的离子为三氟化硼（BF 3）。
在一种实施例中，所述离子植入部掺杂的离子植入能量为10-15keV。
在一种实施例中，所述硅岛图案形成装置包括：光阻涂布构件，用于在所述有源层远离所述基板的表面涂布光阻层，所述光阻层完全覆盖所述有源层；光阻图案形成构件，用于采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成光阻图案；刻蚀构件，用于以所述光阻图案作为掩膜层，对所述有源层进行干法刻蚀，将未被所述光阻图案覆盖的部分有源层移除。
在一种实施例中，所述有源层制备装置，用于在所述缓冲层上沉积形成非晶硅有源层，并对所述非晶硅有源层进行准分子激光退火，将非晶硅转化为多晶硅。
在一种实施例中，所述栅极制备装置，用于在所述有源层上用化学沉积法制备栅极绝缘层。
根据上述实施例可知：
本申请实施例提供一种薄膜晶体管、薄膜晶体管制备方法及制备系统，所述薄膜晶体管包括基板，缓冲层，有源层和栅极绝缘层，所述有源层形成硅岛图案后，利用离子植入掺杂技术对无光阻保护的所述有源层侧面区域掺杂改性，将其表层变为高电阻区域，再利用化学沉积工艺制备栅极绝缘层，由于干法刻蚀形成的所述有源层侧面具有一定倾斜角度，因此在其上沉积的所述栅极绝缘层较其他位置偏薄，将所述有源层侧面区域制作成高电阻结构，避免了因所述栅极绝缘层偏薄导致的工作时边缘非故意开启形成弱沟道电流，改善边界效应，提高了所述薄膜晶体管电学可靠性。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管的制备方法，其包括以下步骤：
    步骤S1、提供一玻璃基板，在所述基板上依次沉积形成缓冲层和多晶硅有源层；
    步骤S2、在所述有源层上涂布光阻，以使得所述有源层上未被所述光阻覆盖的部分刻蚀掉；
    步骤S3、对所述有源层侧面掺杂改性，使其成为高电阻区域；
    步骤S4、在所述有源层侧面掺杂改性完成后，将掺杂改性后的有源层顶面的光阻剥离；
    步骤S5、在所述有源层上制备栅极绝缘层。
  2. 根据权利要求1所述的制备方法，其中，对所述有源层侧面掺杂改性，使其成为高电阻区域，包括：利用定向离子植入技术对所述有源层侧面掺杂改性，使其成为高电阻区域。
  3. 根据权利要求2所述的制备方法，其中，所述薄膜晶体管为N型薄膜晶体管，所述步骤S3中所述有源层侧面掺杂的离子为V族化合物。
  4. 根据权利要求3所述的制备方法，其中，所述步骤S3中所述有源层侧面掺杂的离子为三氢化磷（PH 3）。
  5. 根据权利要求2所述的制备方法，其中，所述薄膜晶体管为P型薄膜晶体管，所述步骤S3中所述有源层侧面掺杂的离子为III族化合物。
  6. 根据权利要求5所述的制备方法，其中，所述步骤S3中所述有源层侧面掺杂的离子为三氟化硼（BF 3）。
  7. 根据权利要求2所述的制备方法，其中，所述利用定向离子植入技术对所述有源层侧面掺杂改性的步骤中离子植入能量为10-15keV。
  8. 根据权利要求1所述的制备方法，其中，所述步骤S2具体包括如下步骤：
    步骤S21、在所述有源层远离所述基板的表面涂布光阻层，所述光阻层完全覆盖所述有源层；
    步骤S22、采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成光阻图案；
    步骤S23、以所述光阻图案作为掩膜层，对所述有源层进行干法刻蚀，将未被所述光阻图案覆盖的部分有源层移除。
  9. 一种薄膜晶体管，其包括：
    基板；
    缓冲层，制备于所述基板上；
    有源层，制备于所述缓冲层上，所述有源层侧面为高电阻区域；
    栅极绝缘层，制备于所述有源层表面。
  10. 根据权利要求9所述的薄膜晶体管，其中，采用权利要求1所述的薄膜晶体管的制备方法制备。
  11. 一种薄膜晶体管的制备系统，其包括：
    缓冲层制备装置，用于在玻璃基板上沉积形成缓冲层；
    有源层制备装置，用于在所述缓冲层上沉积形成多晶硅有源层；
    硅岛图案形成装置，用于在所述有源层上涂布光阻，并将所述有源层上未被所述光阻覆盖的部分刻蚀掉，形成硅岛图案；
    掺杂装置，用于对所述有源层侧面掺杂改性，使其成为高电阻区域；
    光阻去除装置，用于在所述有源层侧面掺杂改性完成后，将掺杂改性后的有源层顶面的光阻剥离；
    栅极制备装置，用于在所述有源层上制备栅极绝缘层。
  12. 根据权利要求11所述的薄膜晶体管的制备系统，其中，所述掺杂装置包括离子植入部，所述离子植入部用于对所述有源层侧面进行定向离子植入技术来掺杂改性，使其成为高电阻区域。
  13. 根据权利要求12所述的薄膜晶体管的制备系统，其中，所述薄膜晶体管为N型薄膜晶体管，所述离子植入部掺杂的离子为V族化合物。
  14. 根据权利要求13所述的薄膜晶体管的制备系统，其中，所述离子植入部掺杂的离子为三氢化磷（PH 3）。
  15. 根据权利要求12所述的薄膜晶体管的制备系统，其中，所述薄膜晶体管为P型薄膜晶体管，所述离子植入部掺杂的离子为III族化合物。
  16. 根据权利要求15所述的薄膜晶体管的制备系统，其中，所述离子植入部掺杂的离子为三氟化硼（BF 3）。
  17. 根据权利要求12所述的薄膜晶体管的制备系统，其中，所述离子植入部掺杂的离子植入能量为10-15keV。
  18. 根据权利要求11所述的薄膜晶体管的制备系统，其中，所述硅岛图案形成装置包括：
    光阻涂布构件，用于在所述有源层远离所述基板的表面涂布光阻层，所述光阻层完全覆盖所述有源层；
    光阻图案形成构件，用于采用半色调掩膜对所述光阻层进行曝光，并用显影液对曝光后的光阻层进行显影，以形成光阻图案；
    刻蚀构件，用于以所述光阻图案作为掩膜层，对所述有源层进行干法刻蚀，将未被所述光阻图案覆盖的部分有源层移除。
  19. 根据权利要求11所述的薄膜晶体管的制备系统，其中，所述有源层制备装置，用于在所述缓冲层上沉积形成非晶硅有源层，并对所述非晶硅有源层进行准分子激光退火，将非晶硅转化为多晶硅。
  20. 根据权利要求11所述的薄膜晶体管的制备系统，其中，所述栅极制备装置用于在所述有源层上用化学沉积法制备栅极绝缘层。
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