CN105514116B - Tft背板结构及其制作方法 - Google Patents
Tft背板结构及其制作方法 Download PDFInfo
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- CN105514116B CN105514116B CN201510882240.3A CN201510882240A CN105514116B CN 105514116 B CN105514116 B CN 105514116B CN 201510882240 A CN201510882240 A CN 201510882240A CN 105514116 B CN105514116 B CN 105514116B
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- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 392
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 106
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 52
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 47
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 47
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 44
- 238000003860 storage Methods 0.000 claims abstract description 44
- 239000002356 single layer Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 73
- 229920005591 polysilicon Polymers 0.000 claims description 68
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 239000011229 interlayer Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 14
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910003978 SiClx Inorganic materials 0.000 claims description 6
- -1 phosphonium ion Chemical class 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- SHPBBNULESVQRH-UHFFFAOYSA-N [O-2].[O-2].[Ti+4].[Zr+4] Chemical compound [O-2].[O-2].[Ti+4].[Zr+4] SHPBBNULESVQRH-UHFFFAOYSA-N 0.000 claims description 5
- 229910052593 corundum Inorganic materials 0.000 claims description 5
- 239000004408 titanium dioxide Substances 0.000 claims description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 5
- 241000790917 Dioxys <bee> Species 0.000 claims description 4
- 238000002425 crystallisation Methods 0.000 claims description 4
- 230000008025 crystallization Effects 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- 239000007790 solid phase Substances 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 16
- 229910004205 SiNX Inorganic materials 0.000 description 14
- 238000010276 construction Methods 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910001415 sodium ion Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- NPYPAHLBTDXSSS-UHFFFAOYSA-N Potassium ion Chemical compound [K+] NPYPAHLBTDXSSS-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- RQMMPEWEOUNPCT-UHFFFAOYSA-N [O-2].[O-2].[Ti+4].[Hf+4] Chemical compound [O-2].[O-2].[Ti+4].[Hf+4] RQMMPEWEOUNPCT-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
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Abstract
本发明提供一种TFT背板结构及其制作方法。该TFT背板结构通过设置栅极绝缘层(4)对应于TFT(T)所在的区域为三层结构,自下至上依次为介电层(41)、氮化硅层(42)、与二氧化硅层(43),能够增强TFT的可靠性;设置栅极绝缘层(4)对应于存储电容(C)所在的区域为双层结构,自下至上依次为介电层(41)、与至少部分氮化硅层(42),或者所述栅极绝缘层(4)对应于存储电容(C)所在的区域为单层结构,仅包括介电层(41),能够增大介电常数,减小存储电容(C)两电极板之间的距离,从而能够在保证存储电容性能的前提下,减少电容面积,提高开口率。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种TFT背板结构及其制作方法。
背景技术
在显示技术领域,液晶显示器(Liquid Crystal Display,LCD)与有机发光二极管显示器(Organic Light Emitting Diode,OLED)等平板显示技术已经逐步取代CRT显示器。其中,OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽,可实现柔性显示与大面积全色显示等诸多优点,被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)。低温多晶硅(Low Temperature Poly-Silicon,LTPS)薄膜晶体管(Thin Film Transistor,TFT)在高分辨AMOLED技术中得到了业界的重视,有很大的应用价值和潜力。与非晶硅(a-Si)相比,LTPSTFT具有较高的载流子迁移率,器件反应速度快,稳定性好,可以满足高分辨率AMOLED显示器的要求。
现有技术中常见的适用于AMOLED的低温多晶硅TFT背板中的栅极绝缘层(GateInsulation,GI)通常采用二氧化硅/氮化硅(SiO2/SiNx)的双层结构,其中SiO2层接触多晶硅有源层,SiNx层接触栅极(Gate)。SiNx层相比SiO2层,有较好的阻挡钠离子(Na+)、钾离子(K+)等可移动离子的能力,并且介电常数更大,相同的绝缘能力下可以比SiO2层做得更薄,且SiNx层氢(H)含量较多,可以对多晶硅中的悬空键起到钝化作用。但是SiNx层与多晶硅有源层的接触由于应力原因,界面性质不好,所以通常需要先沉积一层SiO2层,再加一层SiNx层构成栅极绝缘层。
SiNx层越厚,阻挡可移动离子以及钝化的效果越好,但随之而来的是TFT器件的可靠性下降,这是因为栅极不断地将载流子注入SiNx层,从而会破坏SiNx层,使得SiNx层的品质变差,导致TFT器件的可靠性降低,所以一般情况下,SiNx层都不会做的太厚;另外,在蚀刻制作栅极的过程中往往会对SiNx层造成过蚀刻。若为了保护SiNx层而单纯在SiNx层上叠加保护层则会使得存储电容区对应的栅极绝缘层的厚度同时增大,造成电容存储性能下降,只能以增大电容面积、牺牲开口率的方式来保证电容的存储性能。
发明内容
本发明的目的在于提供一种TFT背板结构,既能够增强TFT的可靠性,又能够在保证存储电容性能的前提下,减少电容面积,提高开口率。
本发明的另一目的在于提供一种TFT背板的制作方法,通过该方法制作的TFT背板既具有较强的可靠性,又能够在保证存储电容性能的前提下,减少电容面积,提高开口率。
为实现上述目的,本发明首先提供一种TFT背板结构,包括基板、覆盖所述基板的缓冲层、设于所述缓冲层上相互间隔开的多晶硅有源层与多晶硅电极板、覆盖所述多晶硅有源层、多晶硅电极板、与缓冲层的栅极绝缘层、于所述多晶硅有源层上方设于栅极绝缘层上的栅极、于所述多晶硅电极板上方设于栅极绝缘层上的金属电极板、覆盖所述栅极、金属电极板、与栅极绝缘层的层间绝缘层、及设于所述层间绝缘层上的源极与漏极;
所述多晶硅有源层、栅极、源极、与漏极构成TFT,所述多晶硅电极板与金属电极板构成存储电容;
所述栅极绝缘层对应于TFT所在的区域为三层结构,自下至上依次为介电层、氮化硅层、与二氧化硅层;所述栅极绝缘层对应于存储电容所在的区域为双层结构,自下至上依次为介电层、与至少部分氮化硅层;或者所述栅极绝缘层对应于存储电容所在的区域为单层结构,仅包括介电层。
所述多晶硅有源层的两侧均植入掺杂离子,分别构成源极接触区与漏极接触区,所述源极接触区与漏极接触区之间构成沟道区;所述源极与漏极分别经由贯穿层间绝缘层和栅极绝缘层的第一过孔与第二过孔接触所述源极接触区与漏极接触区。
所述TFT背板结构还包括覆盖所述源极、漏极、与层间绝缘层的平坦层、设于所述平坦层上的像素电极、设于所述像素电极与平坦层上的像素定义层、及设于所述像素定义层上的光阻间隔物;
所述像素电极经由贯穿所述平坦层的第三过孔接触所述漏极。
所述介电层为二氧化硅层。
所述介电层为三氧化二铝层、二氧化钛层、二氧化锆层、或二氧化铪层。
本发明还提供一种TFT背板的制作方法,包括如下步骤:
步骤1、提供一经过清洗和预烘烤的基板;
步骤2、在所述基板上依次沉积形成缓冲层、与非晶硅层;
步骤3、通过准分子激光退火制程或固相晶化制程使非晶硅层结晶转变为多晶硅层,并对多晶硅层进行图案化处理,定义出多晶硅有源层、与多晶硅电极板;
步骤4、于所述缓冲层、多晶硅有源层、与多晶硅电极板上自下至上依次沉积介电层、氮化硅层、与二氧化硅层,形成栅极绝缘层;
步骤5、通过光刻制程对欲形成存储电容所在区域对应的栅极绝缘层进行蚀刻,蚀刻掉该区域内全部的二氧化硅层以及部分氮化硅层或者蚀刻掉该区域内全部的二氧化硅层以及全部的氮化硅层;
步骤6、于所述栅极绝缘层上沉积并图案化第一金属层,形成栅极、与金属电极板,所述栅极位于所述多晶硅有源层上方,所述金属电极板位于多晶硅电极板上方;
所述多晶硅电极板与金属电极板构成存储电容;
步骤7、以栅极、与金属电极板为遮蔽层对多晶硅有源层的两侧植入掺杂离子,分别形源极接触区与漏极接触区,所述源极接触区与漏极接触区之间构成沟道区;
步骤8、于所述栅极绝缘层、栅极、与金属电极板上沉积并图案化层间绝缘层,形成分别暴露出所述源极接触区与漏极接触区部分表面的第一过孔与第二过孔;
步骤9、于所述层间绝缘层上沉积并图案化第二金属层,形成源极与漏极,所述源极与漏极分别经由第一过孔与第二过孔接触所述源极接触区与漏极接触区;
所述多晶硅有源层、栅极、源极、与漏极构成TFT。
所述TFT背板的制作方法还包括步骤10、于所述层间绝缘层、源极、与漏极上由下至上依次制作平坦层、像素电极、像素定义层、及光阻间隔物;
所述像素电极经由贯穿所述平坦层的第三过孔接触所述漏极。
所述步骤4中沉积的介电层为二氧化硅层。
所述步骤4中沉积的介电层为三氧化二铝层、二氧化钛层、二氧化锆层、或二氧化铪层。
所述步骤7中植入的掺杂离子为磷离子、或硼离子。
本发明的有益效果:本发明提供的一种TFT背板结构,通过设置栅极绝缘层对应于TFT所在的区域为三层结构,自下至上依次为介电层、氮化硅层、与二氧化硅层,由所述二氧化硅层来阻止栅极向氮化硅层注入载流子,保护氮化硅层不受破坏,并且所述二氧化硅层还可以防止对氮化硅层造成过蚀刻,从而能够增强TFT的可靠性;设置栅极绝缘层对应于存储电容所在的区域为双层结构,自下至上依次为介电层、与至少部分氮化硅层,或者所述栅极绝缘层对应于存储电容所在的区域为单层结构,仅包括介电层,能够增大介电常数,减小存储电容两电极板之间的距离,从而能够在保证存储电容性能的前提下,减少电容面积,提高开口率。本发明提供的一种TFT背板的制作方法,通过光刻制程对欲形成存储电容所在区域对应的栅极绝缘层进行蚀刻,蚀刻掉该区域内全部的二氧化硅层以及部分氮化硅层,或者蚀刻掉该区域内全部的二氧化硅层以及全部的氮化硅层,使得由该方法制作的TFT背板中栅极绝缘层对应于TFT所在的区域为三层结构,而栅极绝缘层对应于存储电容所在的区域为双层结构或单层结构,从而使得TFT背板既具有较强的可靠性,又能够在保证存储电容性能的前提下,减少电容面积,提高开口率。
附图说明
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图中,
图1为本发明的TFT背板结构第一实施例的剖面示意图;
图2为本发明的TFT背板结构第二实施例的剖面示意图;
图3为本发明的TFT背板的制作方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
本发明首先提供一种TFT背板结构。请参阅图1,为本发明的TFT背板结构的第一实施例,包括基板1、覆盖所述基板1的缓冲层2、设于所述缓冲层2上相互间隔开的多晶硅有源层31与多晶硅电极板32、覆盖所述多晶硅有源层31、多晶硅电极板32、与缓冲层2的栅极绝缘层4、于所述多晶硅有源层31上方设于栅极绝缘层4上的栅极51、于所述多晶硅电极板32上方设于栅极绝缘层4上的金属电极板52、覆盖所述栅极51、金属电极板52、与栅极绝缘层4的层间绝缘层6、及设于所述层间绝缘层6上的源极71与漏极72,还包括覆盖所述源极71、漏极72、与层间绝缘层6的平坦层8、设于所述平坦层8上的像素电极9、设于所述像素电极9与平坦层8上的像素定义层10、及设于所述像素定义层10上的光阻间隔物11。
所述多晶硅有源层31的两侧均植入掺杂离子,分别构成源极接触区311与漏极接触区312,所述源极接触区311与漏极接触区312之间构成沟道区313。所述源极71与漏极72分别经由贯穿层间绝缘层6和栅极绝缘层4的第一过孔641与第二过孔642接触所述源极接触区311与漏极接触区312。所述像素电极9经由贯穿所述平坦层8的第三过孔81接触所述漏极72。
所述多晶硅有源层31、栅极51、源极71、与漏极72构成TFT T,所述多晶硅电极板32与金属电极板52构成存储电容C。
重点需要说明的是,在该第一实施例中,所述栅极绝缘层4对应于TFT所在的区域为三层结构,自下至上依次为由介电层41、氮化硅(SiNx)层42、与二氧化硅(Si02)层43;所述栅极绝缘层4对应于存储电容C所在的区域为双层结构,自下至上依次为介电层41、与至少部分氮化硅层42。进一步地,在该第一实施例中,所述介电层41为二氧化硅层。这样设置的益处在于:对应于TFT所在的区域,位于所述栅极绝缘层4最上层的二氧化硅层43能够有效阻止栅极51向氮化硅层42注入载流子,保护氮化硅层42不受破坏,而二氧化硅层43的可靠性优于氮化硅层42,受载流子的影响较小,栅极绝缘层4的品质得以保证,并且所述二氧化硅层43还可以防止在蚀刻栅极51时对氮化硅层42造成过蚀刻,从而能够增强TFT的可靠性;对应于存储电容C所在的区域,栅极绝缘层4的厚度得以减薄,二氧化硅成分减少,增大了介电常数,减小了存储电容C的多晶硅电极板32与金属电极板52之间的距离,从而能够在保证存储电容性能(主要是电容存储容量)的前提下,减少电容C的面积,提高开口率。
具体地,所述基板1优选为玻璃基板。
所述缓冲层2的厚度为可为单层氮化硅层、单层氧化硅(SiOx)层、或氮化硅层与氧化硅层的叠加。
所述多晶硅有源层31与多晶硅电极板32的厚度均为
所述由二氧化硅层充当的介电层41的厚度为氮化硅层42的厚度为二氧化硅层43的厚度为
所述栅极51与金属电极板52均为钼/铝/钼(Mo/Al/Mo)层叠结构,或钼/铝(Mo/Al)层叠结构,厚度均为
所述多晶硅有源层31的两侧均植入的掺杂离子为磷离子(P+)、或硼离子(B+),相应的,所述TFT T为N型TFT、或P型TFT。
所述层间绝缘层6的厚度为可为单层氮化硅层、单层氧化硅层、或氮化硅层与氧化硅层的叠加。
所述源极71与漏极72均为Mo/Al/Mo层叠结构,或Mo/Al层叠结构,厚度均为
所述像素电极9的材料为氧化铟锡(Indium Tin Oxid,ITO)。
请参阅图2,为本发明的TFT背板结构的第二实施例,其与上述第一实施例的区别在于:所述栅极绝缘层4对应于TFT T所在的区域为三层结构,自下至上依次为介电层41、氮化硅层42、与二氧化硅层43;所述栅极绝缘层4对应于存储电容C所在的区域为单层结构,仅包括介电层41。进一步地,在该第二实施例中,所述介电层41为三氧化二铝(Al3O2)层、二氧化钛(TiO2)层、二氧化锆(ZrO2)层、或二氧化铪(HfO2)层等高介电常数层。该实施例二采用高介电常数层来取代二氧化硅层充当介电层41,相比于实施例一能够进一步减薄所述栅极绝缘层4对应于存储电容C所在的区域的厚度,仅保留高介电常数层充当的介电层41,从而能够进一步减少电容C的面积,提高开口率。
请参阅图3,结合图1或图2,本发明还提供一种TFT背板的制作方法,包括如下步骤:
步骤1、提供一经过清洗和预烘烤的基板1。
所述基板1优选为玻璃基板。
步骤2、在所述基板1上依次沉积形成缓冲层2、与非晶硅层。
具体地,所述缓冲层2的厚度为可为单层氮化硅层、单层氧化硅层、或氮化硅层与氧化硅层的叠加。
所述非晶硅层的厚度均为
步骤3、通过准分子激光退火(Excimer Laser Annealing,ELA)制程或固相晶化(Solid Phase Crystallization,SPC)制程使非晶硅层结晶转变为多晶硅层,并对多晶硅层进行图案化处理,定义出相互间隔开的多晶硅有源层31、与多晶硅电极板32。
步骤4、于所述缓冲层2、多晶硅有源层31、与多晶硅电极板32上自下至上依次沉积介电层41、氮化硅层42、与二氧化硅层43,形成栅极绝缘层4。
具体地,所述介电层41的厚度为氮化硅层42的厚度为二氧化硅层43的厚度为
可选地,如图1所示,所述介电层41为二氧化硅层。
可选地,如图2所示,所述介电层41为三氧化二铝层、二氧化钛层、二氧化锆层、或二氧化铪层等高介电常数层。
步骤5、通过光刻制程对欲形成存储电容所在区域对应的栅极绝缘层4进行蚀刻,如图1所示,蚀刻掉该区域内全部的二氧化硅层43以及部分氮化硅层42,或者如图2所示,蚀刻掉该区域内全部的二氧化硅层43以及全部的氮化硅层42。
通过该步骤5对欲形成存储电容所在区域对应的栅极绝缘层4的厚度进行了减薄。
步骤6、于所述栅极绝缘层4上沉积并图案化第一金属层,形成栅极51、与金属电极板52,所述栅极51位于所述多晶硅有源层31上方,所述金属电极板52位于多晶硅电极板32上方。
所述多晶硅电极板32与金属电极板52构成存储电容C。
具体地,所述第一金属层为Mo/Al/Mo层叠结构,或Mo/Al层叠结构,厚度为
步骤7、以栅极51、与金属电极板52为遮蔽层对多晶硅有源层31的两侧植入掺杂离子,分别形源极接触区311与漏极接触区312,所述源极接触区311与漏极接触区312之间构成沟道区313。
具体地,该步骤7可选择磷化氢(PH3)气源植入P+离子,或选择乙硼烷(B2H6)气源植入B+离子。
步骤8、于所述栅极绝缘层4、栅极51、与金属电极板52上沉积并图案化层间绝缘层6,形成分别暴露出所述源极接触区311与漏极接触区312部分表面的第一过孔641与第二过孔642。
具体地,所述层间绝缘层6的厚度为可为单层氮化硅层、单层氧化硅层、或氮化硅层与氧化硅层的叠加。
步骤9、于所述层间绝缘层6上沉积并图案化第二金属层,形成源极71与漏极72,所述源极71与漏极72分别经由第一过孔641与第二过孔642接触所述源极接触区311与漏极接触区312。
所述多晶硅有源层31、栅极51、源极71、与漏极72构成TFT T。若上述步骤7植入的是P+离子,则所述TFT T为N型TFT;若上述步骤7植入的是B+离子,则所述TFT T为P型TFT。
具体地,所述第二金属层为Mo/Al/Mo层叠结构,或Mo/Al层叠结构,厚度为
以及步骤10、于所述层间绝缘层6、源极71、与漏极72上由下至上依次制作平坦层8、像素电极9、像素定义层10、及光阻间隔物11。
具体地,所述像素电极9经由贯穿所述平坦层8的第三过孔81接触所述漏极72。所述像素电极9的材料为ITO。
由上述方法制作的TFT背板的结构如图1或图2所示,对应于TFT所在的区域,所述栅极绝缘层4为三层结构,自下至上依次为由介电层41、氮化硅层42、与二氧化硅层43,位于所述栅极绝缘层4最上层的二氧化硅层43能够有效阻止栅极51向氮化硅层42注入载流子,保护氮化硅层42不受破坏,而二氧化硅层43的可靠性优于氮化硅层42,受载流子的影响较小,栅极绝缘层4的品质得以保证,并且所述二氧化硅层43还可以防止在蚀刻栅极51时对氮化硅层42造成过蚀刻,从而能够增强TFT的可靠性。对应于存储电容C所在的区域,所述栅极绝缘层4为双层结构,自下至上依次为由二氧化硅层充当的介电层41、与至少部分氮化硅层42;或者所述栅极绝缘层4为单层结构,仅包括由Al3O2层、TiO2层、ZrO2层、或HfO2层等高介电常数层充当的介电层41,栅极绝缘层4的厚度得以减薄,二氧化硅成分减少,增大了介电常数,减小了存储电容C的多晶硅电极板32与金属电极板52之间的距离,从而能够在保证存储电容性能(主要是电容存储容量)的前提下,减少电容C的面积,提高开口率。
综上所述,本发明的TFT背板结构,通过设置栅极绝缘层对应于TFT所在的区域为三层结构,自下至上依次为介电层、氮化硅层、与二氧化硅层,由所述二氧化硅层来阻止栅极向氮化硅层注入载流子,保护氮化硅层不受破坏,并且所述二氧化硅层还可以防止对氮化硅层造成过蚀刻,从而能够增强TFT的可靠性;设置栅极绝缘层对应于存储电容所在的区域为双层结构,自下至上依次为介电层、与至少部分氮化硅层,或者所述栅极绝缘层对应于存储电容所在的区域为单层结构,仅包括介电层,能够增大介电常数,减小存储电容两电极板之间的距离,从而能够在保证存储电容性能的前提下,减少电容面积,提高开口率。本发明的TFT背板的制作方法,通过光刻制程对欲形成存储电容所在区域对应的栅极绝缘层进行蚀刻,蚀刻掉该区域内全部的二氧化硅层以及部分氮化硅层,或者蚀刻掉该区域内全部的二氧化硅层以及全部的氮化硅层,使得由该方法制作的TFT背板中栅极绝缘层对应于TFT所在的区域为三层结构,而栅极绝缘层对应于存储电容所在的区域为双层结构或单层结构,从而使得TFT背板既具有较强的可靠性,又能够在保证存储电容性能的前提下,减少电容面积,提高开口率。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (6)
1.一种TFT背板结构,其特征在于,包括基板(1)、覆盖所述基板(1)的缓冲层(2)、设于所述缓冲层(2)上相互间隔开的多晶硅有源层(31)与多晶硅电极板(32)、覆盖所述多晶硅有源层(31)、多晶硅电极板(32)、与缓冲层(2)的栅极绝缘层(4)、于所述多晶硅有源层(31)上方设于栅极绝缘层(4)上的栅极(51)、于所述多晶硅电极板(32)上方设于栅极绝缘层(4)上的金属电极板(52)、覆盖所述栅极(51)、金属电极板(52)、与栅极绝缘层(4)的层间绝缘层(6)、及设于所述层间绝缘层(6)上的源极(71)与漏极(72);
所述多晶硅有源层(31)、栅极(51)、源极(71)、与漏极(72)构成TFT(T),所述多晶硅电极板(32)与金属电极板(52)构成存储电容(C);
所述栅极绝缘层(4)对应于TFT(T)所在的区域为三层结构,自下至上依次为第一二氧化硅层、氮化硅层(42)、与第二二氧化硅层(43),所述栅极绝缘层(4)对应于存储电容(C)所在的区域为双层结构,自下至上依次为第一二氧化硅层与至少部分氮化硅层(42);或者所述栅极绝缘层(4)对应于TFT(T)所在的区域为三层结构,自下至上依次为介电层(41)、氮化硅层(42)与第二二氧化硅层(43),所述栅极绝缘层(4)对应于存储电容(C)所在的区域为单层结构,仅包括介电层(41),所述介电层(41)为三氧化二铝层、二氧化钛层、二氧化锆层或二氧化铪层。
2.如权利要求1所述的TFT背板结构,其特征在于,所述多晶硅有源层(31)的两侧均植入掺杂离子,分别构成源极接触区(311)与漏极接触区(312),所述源极接触区(311)与漏极接触区(312)之间构成沟道区(313);所述源极(71)与漏极(72)分别经由贯穿层间绝缘层(6)和栅极绝缘层(4)的第一过孔(641)与第二过孔(642)接触所述源极接触区(311)与漏极接触区(312)。
3.如权利要求1或2所述的TFT背板结构,其特征在于,还包括覆盖所述源极(71)、漏极(72)、与层间绝缘层(6)的平坦层(8)、设于所述平坦层(8)上的像素电极(9)、设于所述像素电极(9)与平坦层(8)上的像素定义层(10)、及设于所述像素定义层(10)上的光阻间隔物(11);
所述像素电极(9)经由贯穿所述平坦层(8)的第三过孔(81)接触所述漏极(72)。
4.一种TFT背板的制作方法,其特征在于,包括如下步骤:
步骤1、提供一经过清洗和预烘烤的基板(1);
步骤2、在所述基板(1)上依次沉积形成缓冲层(2)、与非晶硅层;
步骤3、通过准分子激光退火制程或固相晶化制程使非晶硅层结晶转变为多晶硅层,并对多晶硅层进行图案化处理,定义出多晶硅有源层(31)、与多晶硅电极板(32);
步骤4、于所述缓冲层(2)、多晶硅有源层(31)、与多晶硅电极板(32)上自下至上依次沉积第一二氧化硅层、氮化硅层(42)、与第二二氧化硅层(43),形成栅极绝缘层(4);或者于所述缓冲层(2)、多晶硅有源层(31)、与多晶硅电极板(32)上自下至上依次沉积介电层(41)、氮化硅层(42)、与第二二氧化硅层(43),形成栅极绝缘层(4),所述介电层(41)为三氧化二铝层、二氧化钛层、二氧化锆层或二氧化铪层;
步骤5、通过光刻制程对欲形成存储电容所在区域对应的栅极绝缘层(4)进行蚀刻,将该区域内自下至上依次沉积的第一二氧化硅层、氮化硅层(42)与第二二氧化硅层(43)中的全部的第二二氧化硅层(43)以及部分氮化硅层(42)蚀刻掉,或者将该区域内自下至上依次沉积的介电层(41)、氮化硅层(42)与第二二氧化硅层(43)中的全部的第二二氧化硅层(43)以及全部的氮化硅层(42)蚀刻掉;
步骤6、于所述栅极绝缘层(4)上沉积并图案化第一金属层,形成栅极(51)、与金属电极板(52),所述栅极(51)位于所述多晶硅有源层(31)上方,所述金属电极板(52)位于多晶硅电极板(32)上方;
所述多晶硅电极板(32)与金属电极板(52)构成存储电容(C);
步骤7、以栅极(51)、与金属电极板(52)为遮蔽层对多晶硅有源层(31)的两侧植入掺杂离子,分别形源极接触区(311)与漏极接触区(312),所述源极接触区(311)与漏极接触区(312)之间构成沟道区(313);
步骤8、于所述栅极绝缘层(4)、栅极(51)、与金属电极板(52)上沉积并图案化层间绝缘层(6),形成分别暴露出所述源极接触区(311)与漏极接触区(312)部分表面的第一过孔(641)与第二过孔(642);
步骤9、于所述层间绝缘层(6)上沉积并图案化第二金属层,形成源极(71)与漏极(72),所述源极(71)与漏极(72)分别经由第一过孔(641)与第二过孔(642)接触所述源极接触区(311)与漏极接触区(312);
所述多晶硅有源层(31)、栅极(51)、源极(71)、与漏极(72)构成TFT(T)。
5.如权利要求4所述的TFT背板的制作方法,其特征在于,还包括步骤10、于所述层间绝缘层(6)、源极(71)、与漏极(72)上由下至上依次制作平坦层(8)、像素电极(9)、像素定义层(10)、及光阻间隔物(11);
所述像素电极(9)经由贯穿所述平坦层(8)的第三过孔(81)接触所述漏极(72)。
6.如权利要求4所述的TFT背板的制作方法,其特征在于,所述步骤7中植入的掺杂离子为磷离子、或硼离子。
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Publication number | Publication date |
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US10269973B2 (en) | 2019-04-23 |
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