CN104681628A - 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置 - Google Patents

多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置 Download PDF

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CN104681628A
CN104681628A CN201510116969.XA CN201510116969A CN104681628A CN 104681628 A CN104681628 A CN 104681628A CN 201510116969 A CN201510116969 A CN 201510116969A CN 104681628 A CN104681628 A CN 104681628A
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grid
active layer
insulating barrier
polycrystalline sitft
array base
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刘政
陆小勇
李小龙
詹裕程
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BOE Technology Group Co Ltd
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Priority to CN201510116969.XA priority Critical patent/CN104681628A/zh
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Priority to PCT/CN2016/074211 priority patent/WO2016145967A1/zh
Priority to US15/122,066 priority patent/US9673333B2/en
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Abstract

本发明提供一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置，其中制作多晶硅薄膜晶体管的方法包括：形成多晶硅有源层；在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内；以所述第一栅极为掩膜，对所述有源层进行第一次离子注入，在所述有源层的两侧分别形成两个轻掺杂区；在所述第一栅极绝缘层和所述第一栅极上依次形成第二栅极绝缘层和第二栅极，所述第二栅极两端边缘的投影分别位于所述第一栅极的投影和所述有源层的两端边缘之间；以所述第二栅极为掩膜，对所述有源层进行第二次离子注入，从而在所述有源层的两个轻掺杂区的外侧部分形成两个源漏注入区。

Description

多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置。
背景技术
相对于非晶硅阵列基板，低温多晶硅阵列基板拥有高迁移率(可达非晶硅的数百倍)的优点，其薄膜晶体管尺寸可以做得很小，并且反应速度快，是近年来越来越被看好的一种显示面板的阵列基板，在高分辨率、高画质的有机电致发光显示和液晶显示面板上被越来越多的采用。
但是，低温多晶硅薄膜晶体管的构成一般较为复杂，工艺过程繁多，在大规模量产或一般研发中耗时长，难于监控，成本较高且稳定性差。例如，如图1所示，对于现有技术中利用双层栅极金属形成低温多晶硅晶体管阵列基板的存储电容结构来说，非常容易存在漏电流高、可靠性低等技术问题。在图1中，1为衬底，2为有源层，3为第一栅极绝缘层，4为第一栅极，5为第二栅极绝缘层，6为存储电容底电极，7为存储电容顶电极，其分别形成了左侧的多晶硅薄膜晶体管和右侧的存储电容。
发明内容
本发明提供一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置，以解决现有技术中所制造的低温多晶硅薄膜晶体管漏电流高、可靠性低的技术问题。
为解决上述技术问题，本发明提供一种制作多晶硅薄膜晶体管的方法，包括：
形成多晶硅有源层；
在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内；
以所述第一栅极为掩膜，对所述有源层进行第一次离子注入，在所述有源层的两侧分别形成两个轻掺杂区；
在所述第一栅极绝缘层和所述第一栅极上依次形成第二栅极绝缘层和第二栅极，所述第二栅极两端边缘的投影分别位于所述第一栅极的投影和所述有源层的两端边缘之间；
以所述第二栅极为掩膜，对所述有源层进行第二次离子注入，从而在所述有源层的两个轻掺杂区的外侧部分形成两个源漏注入区。
进一步地，
所述第一次离子注入的剂量比所述第二次离子注入的剂量低。
进一步地，
所述第一次离子注入的剂量为1x1012～1x1014atoms/cm3；
和/或，所述第二次离子注入的剂量为1x1014～1x1018atoms/cm3。
另一方面，本发明还提供一种制作阵列基板的方法，包括：
提供衬底；
在所述衬底上形成如上任一项所述的多晶硅薄膜晶体管。
进一步地，所述方法还包括：
在形成所述多晶硅薄膜晶体管第一栅极的同时，在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极；
在形成所述多晶硅薄膜晶体管第二栅极的同时，在与所述存储电容底电极对应的所述第二栅极绝缘层的上方形成存储电容顶电极。
进一步地，在所述提供衬底和形成所述多晶硅有源层之间还包括：
在所述衬底上形成缓冲层。
再一方面，本发明还提供一种多晶硅薄膜晶体管，包括：
多晶硅有源层，所述有源层包括中间区，分别位于所述中间区两侧的两个轻掺杂区，及分别位于所述两个轻掺杂区外侧的两个源漏注入区；
形成于所述有源层上的第一栅极绝缘层和第一栅极，所述第一栅极的两端边缘的投影分别与所述中间区的两端边缘重合；
形成于所述第一栅极绝缘层和所述第一栅极上的第二栅极绝缘层和第二栅极，所述第二栅极的两端边缘的投影分别与所述两个轻掺杂区的外侧端边缘重合。
进一步地，所述有源层的厚度为
进一步地，所述第一栅极绝缘层和/或第二栅极绝缘层为氧化硅、氮化硅或者二者的叠层，厚度为
进一步地，所述第一栅极和/或第二栅极包括金属和/或金属合金，厚度为
另一方面，本发明还提供一种阵列基板，包括：
衬底；
形成在所述衬底上的如上所述的多晶硅薄膜晶体管。
进一步地，所述阵列基板还包括：
存储电容，包括形成在第一栅极绝缘层上的存储电容底电极和形成在所述第二栅极绝缘层上的存储电容顶电极。
进一步地，在所述衬底和所述多晶硅有源层之间还包括：缓冲层。
再一方面，本发明还提供一种显示装置，包括如上任一项所述的阵列基板。
可见，在本发明提供的一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置中，能够利用现有技术中的双层栅极金属形成掩膜进行离子注入工艺，在不增加掩膜板的情况下，在形成存储电容的同时在薄膜晶体管中形成漏极轻掺杂(LDD)区域，从而起到降低薄膜晶体管漏电流，提高其稳定性的作用。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中薄膜晶体管的结构示意图；
图2是本发明实施例制作多晶硅薄膜晶体管的方法流程图；
图3是本发明实施例制作阵列基板的方法流程图；
图4是本发明实施例1阵列基板的制作方法流程图；
图5是本发明实施例1的有源层制作示意图；
图6是本发明实施例1的第一栅极绝缘层、第一栅极和存储电容底电极制作示意图；
图7是本发明实施例1的第一次离子注入示意图；
图8是本发明实施例1的第二栅极绝缘层、第二栅极和存储电容顶电极示意图；
图9是本发明实施例1的第二次离子注入示意图；
图10是本发明实施例的阵列基板结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
注意，在对本发明中，“第一”和“第二”等术语仅用于区分不同实体或步骤，并不意味着重要程度的不同。“形成”各层如本领域所公知的，一般表示溅射、沉积各层材料，需要时再对材料进行刻蚀等构图工艺。本发明的方法中的步骤先后顺序并不完全以描述的顺序为准，基于本领域的知识，有些步骤可以调换顺序或同时进行。
参见图2，本发明实施例首先提供一种制作多晶硅薄膜晶体管的方法，包括：
步骤201：形成多晶硅有源层；
步骤202：在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内；
步骤203：以所述第一栅极为掩膜，对所述有源层进行第一次离子注入，在所述有源层的两侧分别形成两个轻掺杂区；
步骤204：在所述第一栅极绝缘层和所述第一栅极上依次形成第二栅极绝缘层和第二栅极，所述第二栅极两端边缘的投影分别位于所述第一栅极的投影和所述有源层的两端边缘之间；
步骤205：以所述第二栅极为掩膜，对所述有源层进行第二次离子注入，从而在所述有源层的两个轻掺杂区的外侧部分形成两个源漏注入区。
其中，由于第一次离子注入和第二次离子注入时分别间隔一层栅极绝缘层和两层栅极绝缘层，因此第一次离子注入的剂量可以比所述第二次离子注入的剂量低。可选地，第一次离子注入的剂量利用为1x1012～1x1014atoms/cm3；第二次离子注入的剂量可以为1x1014～1x1018atoms/cm3。
参见图3，本发明实施例还提供一种制作阵列基板的方法，包括：
步骤301：提供衬底；
步骤302：在所述衬底上形成如上任一项所述的多晶硅薄膜晶体管。
其中，方法还可以包括存储电容区域的制作步骤：
在形成所述多晶硅薄膜晶体管第一栅极的同时，在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极；
在形成所述多晶硅薄膜晶体管第二栅极的同时，在与所述存储电容底电极对应的所述第二栅极绝缘层的上方形成存储电容顶电极。
其中，为了防止衬底中的金属离子杂质扩散至有源层中影响TFT工作特性，可以在所述衬底上形成缓冲层，缓冲层可以包括氧化硅、氮化硅或二者的叠层。
实施例1：
本发明实施例1提供一种阵列基板的制作方法，参见图4，具体步骤可以包括：
步骤401：提供衬底，在衬底上形成多晶硅有源层。
参见图5，本步骤中，衬底1可以是预先清洗的玻璃等透明衬底，其上可包含采用氧化硅、氮化硅或者二者叠层形成的缓冲层，以防止透明基板中的金属离子杂质扩散至有源层中而影响TFT工作特性。在衬底1上形成的多晶硅有源层2可为PECVD、LPCVD或者溅射方法在600℃以下沉积形成非晶硅层，并通过准分子激光晶化、金属诱导晶化、固相晶化等方法将非晶硅层转变而成的多晶硅层。需要说明的是，采用不同的晶化方法，其具体的工艺过程及阵列基板的结构会有所不同，在制备过程中需要根据情况增加热处理脱氢、沉积诱导金属、热处理晶化、准分子激光照射晶化、源漏区的掺杂(P型或者N型掺杂)及掺杂杂质的激活等工艺，但最终均可实现本发明所需的技术效果。有源层2的厚度可以为优选厚度可以为
步骤402：在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内，并在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极。
参见图6，本步骤中，在有源层2上首先形成第一栅极绝缘层3，然后在第一栅极绝缘层3上分别形成第一栅极4和存储电容底电极6，其中第一栅极4的投影位于有源层2两端边缘内。
步骤403：以第一栅极为掩膜，对有源层进行第一次离子注入，在有源层的两侧分别形成两个轻掺杂区。
如图7所示，以第一栅极4作为掩膜进行离子注入，以在有源层2的两侧分别形成两个轻掺杂区8。
步骤404：在第一栅极绝缘层和第一栅极上依次形成第二栅极绝缘层和第二栅极，并在与存储电容底电极对应的第二栅极绝缘层的上方形成存储电容顶电极，第二栅极两端边缘的投影分别位于第一栅极的投影和有源层的两端边缘之间。
参见图8，本步骤中，在第一栅极绝缘层3、第一栅极4和存储电容底电极6上形成第二栅极绝缘层5，然后形成第二栅极9和存储电容顶电极7，其中第二栅极9两端边缘的投影分别位于第一栅极4的投影和有源层2的两端边缘之间。
步骤405：以第二栅极为掩膜，对有源层进行第二次离子注入，在有源层的两个轻掺杂区的外侧部分形成两个源漏注入区。
参见图9，在本步骤中，以第二栅极9为掩膜，对有源层2进行第二次离子注入，从而在有源层2的两个轻掺杂区8的外侧部分分别形成两个源漏注入区10。
其中，第一和第二栅极绝缘层3和5可采用单层的氧化硅、氮化硅或者二者的叠层，可使用采用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积，厚度为可根据具体的设计需要选择合适的厚度，优选厚度为第一和第二栅极4和9以及第一和存储电容顶电极6和7可为单层、两层或两层以上结构，由金属、金属合金如钼、铝、钼钨等构成，厚度在范围内，优选厚度为用以形成图9中左侧的薄膜晶体管栅极和离子注入掩模，以及右侧存储电容的上下电极。
第一次和第二次离子注入工艺可采用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子注入或者固态扩散式注入等方法。本发明实施例采用主流的离子云式注入方法，可根据设计需要采用含硼如B2H6/H2或者含磷如PH3/H2的混合气体进行注入，离子注入能量可为10～200keV，优选能量在40～100keV。由于中间分别隔着一层栅极绝缘层和两层栅极绝缘层，因此对第一次离子注入可采用较小的注入能量，对第二次离子注入可采用较高的注入能量。注入剂量可在1x1011～1x1020atoms/cm3范围内。其中第一次离子注入为LDD注入，需要轻剂量注入，建议剂量为1x1012～1x1014atoms/cm3，第二次离子注入为源漏注入，需要重剂量注入，建议剂量为1x1014～1x1018atoms/cm3。
另外，在形成上述结构之后，还需要在第二栅极9之上分别形成源漏极，并将源漏极通过过孔分别与源漏注入区10连接。
实施例2：
参见图10，本发明实施例还提供一种多晶硅薄膜晶体管，其包括：
多晶硅有源层2，所述有源层包括中间区，分别位于所述中间区两侧的两个轻掺杂区8，及分别位于所述两个轻掺杂区8外侧的两个源漏注入区10；
形成于所述有源层2上的第一栅极绝缘层3和第一栅极4，所述第一栅极4的两端边缘的投影分别与所述中间区的两端边缘重合；
形成于所述第一栅极绝缘层3和所述第一栅极4上的第二栅极绝缘层5和第二栅极9，所述第二栅极9的两端边缘的投影分别与所述两个轻掺杂区8的外侧端边缘重合。
其中，有源层2的厚度可以为优选厚度为
其中，第一栅极绝缘层3和/或第二栅极绝缘层5可以为单层的氧化硅、氮化硅或者二者的叠层，其厚度可以为优选厚度为
其中，第一栅极4和/或第二栅极9可以由金属、金属合金如钼、铝、钼钨等构成，厚度为优选厚度为 通过选用上述材质和尺寸，多晶硅薄膜晶体管能达到优良的性能。
实施例3：
参见图10，本发明实施例3还提供一种阵列基板，包括：
衬底1；
形成在所述衬底1上的如本发明实施例2所述的多晶硅薄膜晶体管。
其中，阵列基板还可以包括：存储电容，包括形成在第一栅极绝缘层3上的存储电容底电极6和形成在所述第二栅极绝缘层5上的存储电容顶电极7。
其中，在所述衬底1和所述多晶硅有源层2之间还可以包括：缓冲层。
实施例4：
本发明实施例4还提供一种显示装置，包括如上任一项所述的阵列基板。
显示装置可以为显示面板、显示器、电视机、平板电脑、手机、导航仪等具有显示功能的设备，本发明对此不做限定。
可见，在本发明实施例提供的一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置中，通过调整离子注入工艺的流程和栅极结构，以第一栅极和第二栅极作为离子注入掩模同时形成带有LDD区域的高性能薄膜晶体管和存储电容，不需要专门的形成LDD区域的掩膜。在工艺复杂度保持不变的情况下，薄膜晶体管由于存在轻掺杂的高电阻LDD区，降低了薄膜晶体管的漏电流并提高了其工作稳定性。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (14)

1.一种制作多晶硅薄膜晶体管的方法，其特征在于，包括：
形成多晶硅有源层；
在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内；
以所述第一栅极为掩膜，对所述有源层进行第一次离子注入，在所述有源层的两侧分别形成两个轻掺杂区；
在所述第一栅极绝缘层和所述第一栅极上依次形成第二栅极绝缘层和第二栅极，所述第二栅极两端边缘的投影分别位于所述第一栅极的投影和所述有源层的两端边缘之间；
以所述第二栅极为掩膜，对所述有源层进行第二次离子注入，从而在所述有源层的两个轻掺杂区的外侧部分形成两个源漏注入区。
2.根据权利要求1所述的制作多晶硅薄膜晶体管的方法，其特征在于：
所述第一次离子注入的剂量比所述第二次离子注入的剂量低。
3.根据权利要求1或2所述的制作多晶硅薄膜晶体管的方法，其特征在于：
所述第一次离子注入的剂量为1x1012～1x1014atoms/cm3；
和/或，所述第二次离子注入的剂量为1x1014～1x1018atoms/cm3。
4.一种制作阵列基板的方法，其特征在于，包括：
提供衬底；
在所述衬底上形成如权利要求1～3中任一项所述的多晶硅薄膜晶体管。
5.根据权利要求4所述的制作阵列基板的方法，其特征在于，所述方法还包括：
在形成所述多晶硅薄膜晶体管第一栅极的同时，在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极；
在形成所述多晶硅薄膜晶体管第二栅极的同时，在与所述存储电容底电极对应的所述第二栅极绝缘层的上方形成存储电容顶电极。
6.根据权利要求4或5所述的制作阵列基板的方法，其特征在于，在所述提供衬底和形成所述多晶硅有源层之间还包括：
在所述衬底上形成缓冲层。
7.一种多晶硅薄膜晶体管，其特征在于，包括：
多晶硅有源层，所述有源层包括中间区，分别位于所述中间区两侧的两个轻掺杂区，及分别位于所述两个轻掺杂区外侧的两个源漏注入区；
形成于所述有源层上的第一栅极绝缘层和第一栅极，所述第一栅极的两端边缘的投影分别与所述中间区的两端边缘重合；
形成于所述第一栅极绝缘层和所述第一栅极上的第二栅极绝缘层和第二栅极，所述第二栅极的两端边缘的投影分别与所述两个轻掺杂区的外侧端边缘重合。
8.根据权利要求7所述的多晶硅薄膜晶体管，其特征在于：
所述有源层的厚度为
9.根据权利要求7所述的多晶硅薄膜晶体管，其特征在于：
所述第一栅极绝缘层和/或第二栅极绝缘层为氧化硅、氮化硅或者二者的叠层，厚度为
10.根据权利要求7至9中任一项所述的多晶硅薄膜晶体管，其特征在于：
所述第一栅极和/或第二栅极包括金属和/或金属合金，厚度为
11.一种阵列基板，其特征在于，包括：
衬底；
形成在所述衬底上的如权利要求7至10中任一项所述的多晶硅薄膜晶体管。
12.根据权利要求11所述的阵列基板，其特征在于，所述阵列基板还包括：
存储电容，包括形成在第一栅极绝缘层上的存储电容底电极和形成在所述第二栅极绝缘层上的存储电容顶电极。
13.根据权利要求11或12所述的阵列基板，其特征在于，在所述衬底和所述多晶硅有源层之间还包括：缓冲层。
14.一种显示装置，其特征在于，包括如权利要求11-13中任一项所述的阵列基板。
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