WO2018227991A1 - 薄膜晶体管及制备方法、显示基板及制备方法、显示装置 - Google Patents

薄膜晶体管及制备方法、显示基板及制备方法、显示装置 Download PDF

Info

Publication number
WO2018227991A1
WO2018227991A1 PCT/CN2018/076636 CN2018076636W WO2018227991A1 WO 2018227991 A1 WO2018227991 A1 WO 2018227991A1 CN 2018076636 W CN2018076636 W CN 2018076636W WO 2018227991 A1 WO2018227991 A1 WO 2018227991A1
Authority
WO
WIPO (PCT)
Prior art keywords
projection
metal layer
doping
gate
thin film
Prior art date
Application number
PCT/CN2018/076636
Other languages
English (en)
French (fr)
Inventor
冯佑雄
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2018227991A1 publication Critical patent/WO2018227991A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors

Definitions

  • Embodiments of the present disclosure relate to a thin film transistor, a method of fabricating the same, a display substrate, a method of fabricating the same, and a display device.
  • the display substrate includes a plurality of pixel units arranged in a matrix, each of the pixel units including a display electrode and a thin film transistor that drives the display electrodes.
  • the thin film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode, and the active layer includes a channel region and source and drain regions respectively located on both sides of the channel region.
  • the thin film transistor can function, for example, as a switch. The thin film transistor is turned on, and the external data signal can be transmitted to the pixel electrode in the display substrate through the thin film transistor; the thin film transistor is turned off, and the external data signal cannot be transmitted to the pixel electrode in the display substrate.
  • a method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a gate over the active layer, the gate is insulated from the active layer; and the active is performed by using a gate as a mask
  • the layer is doped for the first time; a metal layer is formed over the gate, the metal layer is insulated from the gate and has a protrusion, and the orthographic projection of the gate on the substrate is a first projection And an orthographic projection of the metal layer on the substrate is a second projection, the second projection protruding from the first projection at a region corresponding to the protrusion of the metal layer;
  • the active layer is doped a second time using the metal layer as a mask.
  • the first projection coincides with the second projection except for a region corresponding to the protrusion of the metal layer.
  • the first projection is located inside the second projection.
  • the projection of the active layer on the base substrate is a third projection, except for the portion of the active layer to be doped by the second doping, the second projection and The third projections coincide.
  • the second projection and the third projection are both S-shaped.
  • an interlayer insulating layer is provided between the gate electrode and the metal layer, and the method further includes forming a via hole penetrating the metal layer and the interlayer insulating layer to expose the gate Part of the pole.
  • the doping type of the first doping is the same as the type of the second doping;
  • the active layer includes a channel region, a first doping region, and a second doping region, the a doped region is located between the channel region and the second doped region; and the channel region is undoped in both the first doping and the second doping,
  • the first doped region is doped in the first doping
  • the second doped region is doped in both the first doping and the second doping.
  • the preparation method further includes forming a source electrode and a drain electrode, the source electrode being connected to the second doping region.
  • the thin film transistor is used to display a substrate, and the metal layer is connected to the source electrode.
  • the doping concentration of the first doping is less than the doping concentration of the second doping.
  • a method of preparing a display substrate comprises: fabricating a thin film transistor according to the preparation method as described above; and fabricating a light emitting diode, wherein a drain electrode of the thin film transistor is connected to a light emitting diode, a source electrode of the thin film transistor, and the metal The layer is connected to the power cord.
  • an interlayer insulating layer is provided between the gate electrode and the metal layer, and the gate electrode, the interlayer insulating layer, and the metal layer constitute a capacitor.
  • a thin film transistor includes: an active layer formed on a base substrate; a gate formed over the active layer, the gate being insulated from the active layer; and a metal layer formed over the gate
  • the metal layer is insulated from the gate and has a protrusion, an orthographic projection of the gate on the substrate is a first projection, and an orthographic projection of the metal layer on the substrate is And a second projection that protrudes from the first projection at a region corresponding to the protrusion of the metal layer.
  • the active layer includes a first doped region and a second doped region, and the doping concentration of the first doped region is less than a doping concentration of the second doped region.
  • a display substrate includes: a thin film transistor as described above, and a light emitting diode.
  • the drain electrode of the thin film transistor is connected to a light emitting diode, and a source electrode of the thin film transistor and the metal layer are connected to a power supply line.
  • an interlayer insulating layer is provided between the gate electrode and the metal layer, and the gate electrode, the interlayer insulating layer, and the metal layer constitute a capacitor.
  • a display device includes the display substrate as described above.
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure
  • FIGS. 2a-2f are schematic cross-sectional views showing a method of fabricating a thin film transistor according to an embodiment of the present disclosure
  • 3a is a schematic plan view 1 after forming a metal layer in a method of fabricating a thin film transistor according to an embodiment of the present disclosure
  • 3b is a plan view 2 after forming a metal layer in a method of fabricating a thin film transistor according to an embodiment of the present disclosure
  • 3c is a plan view 3 after forming a metal layer in a method of fabricating a thin film transistor according to an embodiment of the present disclosure
  • 3d is a plan view schematically showing a via hole formed in a method of fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional view of a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of a display substrate in accordance with an embodiment of the present disclosure.
  • FIG. 6 is a plan view of a display substrate in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of a display substrate in accordance with an embodiment of the present disclosure.
  • FIG. 8 is another schematic cross-sectional view of a display substrate in accordance with an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • the source region and the drain region of the thin film transistor may be disposed as a heavily doped region, between the source region and the channel region, and between the drain region and the channel region. Lightly doped area.
  • the current process for making lightly doped regions is too complicated, and some producers do not even make lightly doped regions in order to save costs.
  • Embodiments of the present disclosure provide a thin film transistor, a method of fabricating the same, a display substrate, a method of fabricating the same, and a display device.
  • a thin film transistor and a method of fabricating the same, a display substrate, a method of fabricating the same, and a display device according to the disclosed embodiments will be described in detail with reference to the accompanying drawings. It should be noted that, for the sake of clarity, the dimensions of some layers or regions in the drawings may be enlarged or reduced and not drawn to actual scale.
  • Embodiments of the present disclosure provide a method of fabricating a thin film transistor. As shown in FIG. 1, the method includes: forming an active layer 103 on a base substrate 101; forming a gate 105 over the active layer 103, the gate 105 is insulated from the active layer 103; and using the gate 105 as a mask
  • the active layer 103 is doped for the first time; a metal layer 107 is formed over the gate electrode 105, and the metal layer 107 is insulated from the gate electrode 105 and has a protrusion 1071 whose orthographic projection on the substrate substrate 101 is a first projection, the orthographic projection of the metal layer 107 on the substrate 101 is a second projection, the second projection protruding from the first projection at a region corresponding to the protrusion 1071 of the metal layer 107; The metal layer 107 is doped for the second time with the active layer 103 as a mask.
  • the second projection protrudes from the first projection at a region corresponding to the protruding portion 1071 of the metal layer 107”. It may be understood that the second projection corresponding to the metal layer 107 includes the metal layer 107.
  • the structure and shape of the protruding portion 1071 of the metal layer 107 are not specifically limited in the embodiment of the present disclosure, as long as the second projection protrudes from the first portion at a region corresponding to the protruding portion 1071 of the metal layer 107. Just a projection.
  • the method for fabricating the thin film transistor provided by the embodiment of the present disclosure includes the following steps, for example.
  • an active layer 103 is formed on the base substrate 101.
  • the base substrate 101 may be made of a material such as glass or plastic.
  • the active layer 103 may be made of an amorphous semiconductor such as amorphous silicon, a crystalline semiconductor such as polysilicon, a metal oxide semiconductor such as indium gallium tin oxide.
  • a semiconductor thin film may be first formed on the base substrate 101, and then the semiconductor thin film is patterned to form the active layer 103.
  • step S101 includes, for example, forming an amorphous silicon film on the base substrate 101; performing excimer laser annealing to change the amorphous silicon film into a polysilicon film; and patterning the polysilicon film to form an active layer 103.
  • the buffer layer 102 may be formed on the base substrate 101 before the active layer 103 is formed to prevent impurities in the base substrate 101 from diffusing into the active layer 103.
  • the buffer layer 102 may be made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.
  • a gate electrode 105 is formed over the active layer 103.
  • a gate insulating film 1041 is formed on the active layer 103 by a method such as chemical vapor deposition, and then a gate metal film 1051 is formed on the gate insulating film 1041 by sputtering or the like; then the gate insulating film 1041 and the gate metal are formed.
  • the film 1051 is patterned to form a gate insulating layer 104 and a gate electrode 105, and the active layer 103 and the gate electrode 105 are insulated from each other by the gate insulating layer 104.
  • the gate insulating film 1041 may be made of an inorganic material such as silicon oxide, silicon nitride or silicon oxynitride, and the gate metal film 1051 may be a metal such as Mo, Al or Cu or an alloy thereof.
  • the active layer 103 is doped for the first time with the gate electrode 105 as a mask.
  • the active layer 103 is doped for the first time using the gate electrode 105 as a mask.
  • the first doping is P-type doping (for example, doping with trivalent boron, indium, gallium, etc. when the active layer 103 is formed of amorphous or polycrystalline silicon) or N-type doping (for example)
  • the active layer 103 is formed of amorphous silicon or polycrystalline silicon, it may be doped with pentavalent phosphorus, arsenic or the like.
  • the first doping is performed by ion implantation.
  • the gate electrode 105 covers the channel region of the active layer 103 (described later) while the active layer Portions of 103 other than the channel region are not covered by the gate electrode 105, and portions of the active layer 103 not covered by the gate electrode 105 are doped.
  • a metal layer 107 is formed over the gate electrode 105, the metal layer 107 having a protrusion 1071.
  • an interlayer gate insulating layer 106 is formed on the gate electrode 105 by a method such as chemical vapor deposition, a metal film (not shown) is formed on the interlayer insulating layer 106 by sputtering or the like, and then the metal film is patterned.
  • the metal layer 107 having the protrusions 1071 is formed.
  • the metal layer 107 and the gate electrode 105 are insulated from each other by the interlayer insulating layer 106.
  • the metal layer 107 extends to have the protrusions 1071 such that the orthographic projection of the protrusions 1071 of the metal layer 107 on the base substrate 101 protrudes from the first projection.
  • the interlayer insulating layer 106 may be made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the metal layer 107 may be a metal such as Mo, Al, or Cu or an alloy thereof.
  • the gate electrode 105 and the metal layer 107 may be formed of the same material.
  • the metal layer 107 extends to have the protrusions 1071 in a direction parallel to the base substrate 101; however, the embodiment of the present disclosure is not limited thereto, for example, the metal layer 107 may also be along the lining.
  • the base substrate 101 extends in an oblique direction to have a protruding portion 1071 as long as the orthographic projection of the protruding portion 1071 of the metal layer 107 on the base substrate 101 protrudes from the first projection corresponding to the gate electrode 105.
  • the shape of the metal layer 107 may be arbitrary.
  • a thin film transistor prepared according to the method of the embodiments of the present disclosure may be used for a display substrate; in this case, the gate electrode 105, the interlayer insulating layer 106, and the metal layer 107 may together constitute a capacitor.
  • the gate electrode 105, the interlayer insulating layer 106, and the metal layer 107 may together constitute a storage capacitor in the display substrate.
  • the orthographic projection of the gate 105 on the substrate 101 is a first projection
  • the orthographic projection of the metal layer 107 on the substrate 101 is a second projection (linear shading), except for metal.
  • the first projection outside the area corresponding to the protrusion 1071 of the layer 107 (the portion indicated by the arrow) completely coincides with the second projection; in this case, the overlapping area between the gate 105 and the metal layer 107 can be maximized, Thereby increasing the storage capacitance.
  • the orthographic projection of the gate 105 on the substrate 101 is a first projection
  • the orthographic projection of the metal layer 107 on the substrate 101 is a second projection
  • the first projection is located at the second projection.
  • the inner side in this case, not only the overlapping area between the gate electrode 105 and the metal layer 107 can be maximized, but also the metal layer 107 can be formed into a regular shape (for example, a regular rectangle) to make the metal layer 107 Making it easier.
  • a regular shape for example, a regular rectangle
  • the first projection is located inside the second projection” means that the first projection does not have a portion beyond the second projection.
  • the metal layer 107 may have other shapes.
  • the orthographic projection of the metal layer 107 on the substrate 101 is a second projection (linear hatched portion), and the projection of the active layer 103 on the substrate 101 is a third projection (pointed)
  • the shaded portion) the second projection and the third projection have substantially the same shape, for example, both S-shaped; in this case, the design parameters of the mask for fabricating the metal layer 107 and the design parameters of the mask for fabricating the active layer 103 Generally the same or proportional, can reduce the difficulty of the process.
  • the second projection and the third projection coincide except for the region of the active layer 103 to be doped by the second doping; in this case, the mask of the metal layer 107 is formed and the active layer 103 is formed.
  • the reticle is more similar and can further reduce the process difficulty.
  • the active layer 103 and the metal layer 107 are both S-shaped, and the projection of the active layer 103 and the projection of the metal layer 107 coincide except for the positions where the both ends of the active layer 103 are located.
  • the active layer 103 is doped a second time using the metal layer 107 as a mask.
  • the active layer 103 is doped a second time using the metal layer 107 as a mask.
  • the second doping may be P-type doping (for example, doping with trivalent boron, indium, gallium, or the like when the active layer 103 is formed using amorphous silicon or polycrystalline silicon) or N-type doping (for example, when the active layer 103 is formed of amorphous silicon or polycrystalline silicon, doping may be performed using pentavalent phosphorus, arsenic or the like.
  • the second doping is performed by ion implantation.
  • the metal layer 107 covers the channel region (described later) and the active layer of the active layer 103.
  • a portion of the region 103 that has undergone the first doping, another portion of the active layer 103 that has undergone the first doping is not covered by the metal layer 107, and a portion of the active layer 103 that is not covered by the metal layer 107 is Doping.
  • the doping type of the first doping may be the same as the type of the second doping, for example, P-doping or N-doping.
  • the first doping region 1 and the second doping region 2 may be formed in the active layer 103 by the first doping and the second doping described above; the first doping region 1 only undergoes The first doping and the second doping region 2 undergo both the first doping and the second doping, so the doping concentration of the first doping region 1 is smaller than that of the second doping region 2 Miscellaneous concentration.
  • the active layer 103 further has a channel region 3 which is undoped in both the first and second doping described above, the channel region 3 corresponds to the gate electrode 105, and the first doping region 1 is located in the channel region 3 Between the second doped region 2.
  • a first doping region 1 having a low doping concentration is formed between the channel region 3 and the second doping region 2 having a high doping concentration; the first doping region 1 having a low doping concentration may A part of the voltage applied to the channel region 3 is shared, so that the leakage current of the thin film transistor prepared according to the method of the embodiment of the present disclosure is reduced as compared with the thin film transistor having the first doped region 1 having the low doping concentration. small.
  • the doping concentration of the first doping is less than the doping concentration of the second doping, thereby making the doping concentration of the first doping region 1 further smaller than the doping concentration of the second doping region 2, The leakage current of the thin film transistor is further reduced.
  • the doping concentration of the first doping is about 1/10 of the doping concentration of the second doping, however, the embodiment of the present disclosure is not limited thereto.
  • a first doped region 1 and a second doped region 2 are formed on both sides of the channel region 3, and a second doped region 2 is used as a source (described later).
  • the source region is connected, and the other second doping region 2 serves to connect the drain region to the drain (described later).
  • the first doping is performed using the gate as a mask and the second doping is performed using the metal layer having the protrusion as a mask, so that the trench can be easily used in the trench
  • a first doped region having a low doping concentration is formed between the track region and the second doped region having a high doping concentration, thereby reducing the process difficulty while reducing the leakage current of the thin film transistor.
  • a gate electrode, a metal layer, and an interlayer insulating layer between the gate electrode and the metal layer may together constitute a storage capacitor of the display substrate, the storage capacitor being disposed on the thin film Directly above the active layer of the transistor, the storage capacitor does not occupy extra space, thereby increasing the aperture ratio of the display substrate.
  • the gate electrode and the metal layer can double as the two plates of the storage capacitor of the display substrate, so that the storage capacitor is not separately fabricated when the thin film transistor is used for the display substrate. Simplified the production process.
  • a method of fabricating a thin film transistor according to an embodiment of the present disclosure may also be as follows.
  • a passivation layer 109 is formed on the metal layer 107 after the second doping, and then a patterning process is performed to form source and drain vias 113 through the passivation layer 109 and the interlayer insulating layer 106.
  • the source drain via 113 exposes the second doped region 2 of the active layer 103.
  • the passivation layer 109 may be an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.
  • two source and drain vias 113 are formed to expose the two second doping regions 2 of the active layer 103.
  • a via 108 may also be formed through the passivation layer 109, the metal layer 107, and the interlayer insulating layer 106 to expose a portion of the gate 105 to facilitate implementation of the gate 105 and other The connection of the parts.
  • source and drain vias 113 and the vias 108 may be simultaneously formed by the same patterning process, or the source and drain vias 113 and the vias 108 may be separately formed by two patterning processes.
  • the source electrode 111 and the drain electrode 110 are formed.
  • a source and drain metal film (not shown) is formed after the source and drain vias 113 are formed, and a source and drain metal film is patterned to form the source and drain electrodes 111 and 110.
  • the source/drain film may be a single layer or a multilayer material of a metal such as Ti or Al or an alloy thereof, such as a Ti/Al/Ti three-layer material.
  • the source electrode 111 is connected to the second doping region 2 on the side of the channel region 3 of the active layer 103 through the via 113
  • the drain electrode 110 is connected to the channel region 3 located in the active layer 103 through the via 113.
  • the second doping region 2 on the other side.
  • a thin film transistor fabricated according to a method of an embodiment of the present disclosure may be used for an organic light emitting display substrate including a plurality of pixel units, each of which includes, for example, a switching transistor, a driving transistor, a storage capacitor, and a light emitting a diode; in this case, a thin film transistor fabricated according to the method of the embodiment of the present disclosure can be used as a driving thin film transistor in an organic light emitting display substrate, the metal layer 107 and the source 111 of which are connected to each other and connected to a power supply line ( As will be described later, the drain 110 is connected to the organic light emitting diode, and the gate electrode 105, the interlayer insulating layer 106 and the metal layer 107 together constitute a storage capacitor.
  • the thin film transistor includes an active layer 103 formed on a base substrate 101, a gate 105 formed over the active layer 103, and a gate 105 insulated from the active layer 103; a metal layer 107, Above the gate electrode 105, the metal layer 107 is insulated from the gate electrode 105 and has a protrusion 1071.
  • the orthographic projection of the gate electrode 105 on the substrate substrate 101 is a first projection, and the metal layer 107 is on the substrate substrate 101.
  • the orthographic projection is a second projection, the second projection protruding from the first projection at a region corresponding to the protruding portion 1071 of the metal layer 107;
  • the active layer 103 includes a first doping region 1 and a second doping region 2.
  • the doping concentration of the first doping region 1 is smaller than the doping concentration of the second doping region 2.
  • the gate electrode 105 is insulated from the active layer 103 by the gate insulating layer 104, and the metal layer 107 is insulated from the gate electrode 105 by the interlayer insulating layer 106.
  • the active layer 103 also has a channel region 3, and the first doping region 1 is located between the channel region 3 and the second doping region 2.
  • the thin film transistor further includes a source electrode 111 and a drain electrode 110, the source electrode 111 is connected to the second doping region 2 on the side of the channel region 3 of the active layer 103, and the drain electrode 110 is connected to The second doping region 2 is located on the other side of the channel region 3 of the active layer 103.
  • the thin film transistor further includes a via 113, the source 111 is connected to the second doping region 2 through the via 113, and the drain 110 is connected to the second doping region 2 through the via 113.
  • the thin film transistor further includes a via 108 that exposes a portion of the gate 105 to facilitate connection of the gate 105 with other components.
  • the shape of the metal layer 107 may be arbitrary, as described in detail above.
  • a thin film transistor according to an embodiment of the present disclosure may be used for a display substrate; in this case, the gate electrode 105, the interlayer insulating layer 106, and the metal layer 107 may together constitute a storage capacitor in the display substrate, and the metal layer 107 and the source 111 are mutually connected to each other Connected and connected together to a power line (described later), the drain 110 is connected to an organic light emitting diode.
  • a thin film transistor according to an embodiment of the present disclosure is prepared using the above-described method of preparing a thin film transistor according to an embodiment of the present disclosure.
  • a method of preparing a display substrate includes: fabricating a thin film transistor using the preparation method as described above; and fabricating a light emitting diode.
  • a drain electrode of the thin film transistor is connected to a light emitting diode, and a source electrode of the thin film transistor and the metal layer are connected to a power supply line.
  • a display substrate is also provided.
  • the display substrate includes: a thin film transistor as described above, and a light emitting diode.
  • a drain electrode of the thin film transistor is connected to a light emitting diode, and a source electrode of the thin film transistor and the metal layer are connected to a power supply line.
  • a display substrate according to an embodiment of the present disclosure is prepared by the method of producing a display substrate according to an embodiment of the present disclosure as described above.
  • FIG. 5 is a schematic cross-sectional view of a display substrate in accordance with an embodiment of the present disclosure
  • FIG. 6 is a plan view of a display substrate in accordance with an embodiment of the present disclosure
  • FIG. 7 is a circuit diagram of a display substrate in accordance with an embodiment of the present disclosure.
  • the display substrate includes a plurality of pixel units, each of which includes, for example, a driving transistor T1, a switching transistor T2, a storage capacitor C, and a light emitting diode (LED), which is implemented according to the present disclosure.
  • the thin film transistor of the example is used as the driving transistor T1; the gate of the switching transistor T2 is connected to the scan line 121, the source is connected to the data line 122, the drain is connected to the gate 105 of the driving transistor T1; the source 111 of the driving transistor T1 is The metal layer 107 is connected to the power supply line 112, the drain 110 is connected to the light emitting diode, and the gate 105 and the metal layer 107 are used as the two plates of the storage capacitor C.
  • FIG. 5 is a schematic cross-sectional view showing only a part of the switching transistor T2.
  • the active layer, the gate insulating layer 204, the gate 205, the source and the drain of the switching transistor T2 can be respectively driven and driven, for example.
  • the active layer 103, the gate insulating layer 104, the gate electrode 105, the source electrode 111, and the drain electrode 110 of the body museum T1 are simultaneously formed and disposed in the same layer and in the same material.
  • the switching transistor T2 does not have a metal layer corresponding to the metal layer 107 of the driving transistor T1.
  • the light emitting diode includes a lower electrode 115, an upper electrode 118, and a light emitting layer 117 disposed between the lower electrode 115 and the upper electrode 118.
  • Reference numeral 116 denotes a pixel defining layer for separating a plurality of pixel cells.
  • the drain electrode 110 of the driving transistor T1 is connected to the lower electrode 115 of the light emitting diode through a via hole provided in the planarization layer 114.
  • the gate 105 of the driving transistor T2 is connected to the trace 112' through the via 108 and is finally connected to the drain of the switching transistor T2.
  • the display substrate according to an embodiment of the present disclosure is a flexible substrate.
  • the method of manufacturing the display substrate according to the embodiment of the present disclosure further includes: forming a flexible buffer layer 102 on the base substrate 101 before forming the thin film transistor and the light emitting diode, as shown in FIG. 8; After the thin film transistor and the light emitting diode are formed, the base substrate 101 is peeled off from the flexible buffer layer 102.
  • the flexible buffer layer 102 includes an organic buffer layer 1021 and an inorganic buffer layer 1022.
  • the organic buffer layer 1021 is in direct contact with the base substrate 101 to facilitate subsequent stripping of the substrate 101; the inorganic buffer layer 1022 is in direct contact with the thin film transistor to prevent impurities from diffusing into the thin film transistor.
  • the flexible buffer layer 102 includes a plurality of organic buffer layers 1021 and a plurality of inorganic buffer layers 1022 that are alternately disposed.
  • the display device 1 includes the display substrate 10 as described above.
  • the display device can be, for example, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • a first doping is performed using a gate as a mask and a metal layer having a protrusion is used as a mask
  • the second doping is such that a first doping region having a low doping concentration can be easily formed between the channel region and the second doping region having a high doping concentration, thereby reducing leakage current of the thin film transistor. Reduced process difficulty.
  • a gate electrode, a metal layer, and an interlayer insulating layer between the gate electrode and the metal layer may be configured together.
  • the storage capacitor of the substrate is disposed, and the storage capacitor is disposed directly above the active layer of the thin film transistor, so that the storage capacitor does not occupy extra space, thereby increasing the aperture ratio of the display substrate.
  • the gate and the metal layer can double as the two plates of the storage capacitor of the display substrate, thereby eliminating the need for another Making storage capacitors simplifies the manufacturing process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种薄膜晶体管及其制备方法、显示基板及其制备方法、以及显示装置。该薄膜晶体管的制备方法包括：在衬底基板(101)上形成有源层(103)；在有源层(103)上方形成栅极(105)，以栅极(105)为掩模对有源层(103)进行第一次掺杂；在栅极(105)上方形成金属层(107)，金属层(107)与栅极(105)绝缘并具有突出部(1071)，以金属层(107)为掩模对有源层(103)进行第二次掺杂。在减小薄膜晶体管的漏电流的同时降低了工艺难度。

Description

薄膜晶体管及制备方法、显示基板及制备方法、显示装置
本申请要求于2017年6月16日递交的中国专利申请第201710456964.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种薄膜晶体管及其制备方法、显示基板及其制备方法、以及显示装置。
背景技术
通常，显示基板包括排列成矩阵的多个像素单元，每个像素单元包括显示电极和对显示电极进行驱动的薄膜晶体管。薄膜晶体管包括栅极、有源层、源电极和漏电极，有源层包括沟道区和分别位于沟道区两侧的源极区和漏极区。在显示基板中，薄膜晶体管例如可以起到开关的作用。薄膜晶体管导通，外部数据信号可以通过薄膜晶体管传输至显示基板中的像素电极；薄膜晶体管截止，外部数据信号无法传输至显示基板中的像素电极。
发明内容
根据本公开的实施例，提供一种薄膜晶体管的制备方法。该薄膜晶体管的制备方法包括：在衬底基板上形成有源层；在所述有源层上方形成栅极，该栅极与所述有源层绝缘；以栅极为掩模对所述有源层进行第一次掺杂；在所述栅极上方形成金属层，该金属层与所述栅极绝缘并具有突出部，所述栅极在所述衬底基板上的正投影为第一投影，所述金属层在所述衬底基板上的正投影为第二投影，在所述金属层的所述突出部对应的区域处所述第二投影突出于所述第一投影；以及以所述金属层为掩模对所述有源层进行第二次掺杂。
例如，除所述金属层的所述突出部所对应的区域之外所述第一投影与所述第二投影重合。
例如，所述第一投影位于所述第二投影的内侧。
例如，所述有源层在所述衬底基板上的投影为第三投影，除所述有源层 的要被所述第二次掺杂进行掺杂的部分之外所述第二投影和所述第三投影重合。
例如，所述第二投影和所述第三投影均为S形。
例如，在所述栅极和所述金属层之间具有层间绝缘层，并且所述方法还包括形成过孔，该过孔贯穿所述金属层和所述层间绝缘层以露出所述栅极的一部分。
例如，所述第一次掺杂的掺杂类型与所述第二次掺杂的类型相同；所述有源层包括沟道区、第一掺杂区和第二掺杂区，所述第一掺杂区位于所述沟道区和所述第二掺杂区之间；并且所述沟道区在所述第一次掺杂和所述第二次掺杂中均未被掺杂，所述第一掺杂区在所述第一次掺杂中被掺杂，所述第二掺杂区在所述第一次掺杂和所述第二次掺杂两者中被掺杂。
例如，所述制备方法还包括形成源电极和漏电极，所述源电极与所述第二掺杂区连接。
例如，所述薄膜晶体管用于显示基板，并且所述金属层与所述源电极连接。
例如，所述第一次掺杂的掺杂浓度小于所述第二次掺杂的掺杂浓度。
根据本公开的实施例，提供一种显示基板的制备方法。该显示基板的制备方法包括：采用根据如上所述的制备方法制作薄膜晶体管；以及制作发光二极管，其中，所述薄膜晶体管的漏电极连接到发光二极管，所述薄膜晶体管的源电极以及所述金属层连接到电源线。
例如，在所述栅极和所述金属层之间具有层间绝缘层，所述栅极、所述层间绝缘层和所述金属层构成电容。
根据本公开的实施例，提供一种薄膜晶体管。该薄膜晶体管包括：有源层，形成在衬底基板上；栅极，形成在所述有源层上方，该栅极与所述有源层绝缘；以及金属层，形成在所述栅极上方，该金属层与所述栅极绝缘并具有突出部，所述栅极在所述衬底基板上的正投影为第一投影，所述金属层在所述衬底基板上的正投影为第二投影，在所述金属层的所述突出部对应的区域处所述第二投影突出于所述第一投影。所述有源层包括第一掺杂区和第二掺杂区，所述第一掺杂区的掺杂浓度小于所述第二掺杂区的掺杂浓度。
根据本公开的实施例，提供一种显示基板。该显示基板包括：如上所述的薄膜晶体管，以及发光二极管。所述薄膜晶体管的漏电极连接到发光二极 管，所述薄膜晶体管的源电极以及所述金属层连接到电源线。
例如，在所述栅极和所述金属层之间具有层间绝缘层，所述栅极、所述层间绝缘层和所述金属层构成电容。
根据本公开的实施例，提供一种显示装置。该显示装置包括如上所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是根据本公开实施例的薄膜晶体管的制备方法的流程图；
图2a-2f是根据本公开实施例的薄膜晶体管的制备方法的截面示意图；
图3a是在根据本公开实施例的薄膜晶体管的制备方法中形成金属层之后的平面示意图一；
图3b是在根据本公开实施例的薄膜晶体管的制备方法中形成金属层之后的平面示意图二；
图3c是在根据本公开实施例的薄膜晶体管的制备方法中形成金属层之后的平面示意图三；
图3d是在根据本公开实施例的薄膜晶体管的制备方法中形成过孔之后的平面示意图；
图4是根据本公开实施例的薄膜晶体管的截面示意图；
图5是根据本公开实施例的显示基板的截面示意图；
图6是根据本公开实施例的显示基板的平面示意图；
图7是根据本公开实施例的显示基板的电路图；
图8是根据本公开实施例的显示基板的另一截面示意图；以及
图9是根据本公开实施例的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描 述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
一些情况下，薄膜晶体管处于关闭状态时其内部也会有电流通过，该电流称为漏电流，漏电流过大会严重影响薄膜晶体管的开关性能。为了减小薄膜晶体管的漏电流，例如，薄膜晶体管的源极区和漏极区可以设置为重掺杂区，在源极区与沟道区之间以及漏极区与沟道区之间设置轻掺杂区。然而，目前制作轻掺杂区的工艺太过复杂，有些生产者为了节省成本甚至不制作轻掺杂区。
本公开的实施例提供薄膜晶体管及其制备方法、显示基板及其制备方法、以及显示装置。下面，将结合附图对根据公开实施例的薄膜晶体管及其制备方法、显示基板及其制备方法、以及显示装置进行详细的描述。需要说明的是，为了清晰起见，附图中有些层或区域的尺寸可能会被放大或缩小而不按照实际的比例绘制。
本公开的实施例提供一种薄膜晶体管的制备方法。如图1所示，该方法包括：在衬底基板101上形成有源层103；在有源层103上方形成栅极105，栅极105与有源层103绝缘；以栅极105为掩模对有源层103进行第一次掺杂；在栅极105上方形成金属层107，金属层107与栅极105绝缘并具有突出部1071，该栅极105在衬底基板101上的正投影为第一投影，该金属层107在衬底基板101上的正投影为第二投影，在该金属层107的突出部1071对应的区域处所述第二投影突出于所述第一投影；以及以金属层107为掩模对有源层103进行第二次掺杂。
需要说明的是，“在该金属层107的突出部1071对应的区域处所述第二 投影突出于所述第一投影”可以理解为，与金属层107相对应的第二投影包括金属层107的突出部1071在衬底基板101上的正投影，该突出部1071的正投影突出于与栅极105相对应的第一投影。
需要说明的是，本公开实施例对金属层107的突出部1071的结构和形状不做具体限定，只要在该金属层107的突出部1071对应的区域处所述第二投影突出于所述第一投影即可。
下面，将结合图1和图2a-2f对本公开实施例提供的薄膜晶体管的制备方法进行详细地描述。本公开实施例提供的薄膜晶体管的制备方法例如包括以下步骤。
S101：形成有源层103。
如图2a所示，在衬底基板101上形成有源层103。例如，衬底基板101可以采用玻璃、塑料等材料。例如，有源层103可以采用非晶半导体如非晶硅、结晶半导体如多晶硅、金属氧化物半导体如氧化铟镓锡等材料。
例如，可以首先在衬底基板101上形成半导体薄膜，然后对半导体薄膜进行图案化以形成有源层103。
例如，有源层103采用多晶硅形成。在此情形下，步骤S101例如包括：在衬底基板101上形成非晶硅薄膜；进行准分子激光退火，将非晶硅薄膜变成多晶硅薄膜；对多晶硅薄膜进行图案化，以形成有源层103。
例如，在形成有源层103之前可以在衬底基板101上形成缓冲层102，以防止衬底基板101中的杂质扩散进入有源层103。例如，缓冲层102可以采用氧化硅、氮化硅、氮氧化硅等无机材料。
S102：形成栅极105。
如图2b和2c所示，在有源层103上方形成栅极105。例如，首先在有源层103上采用化学气相沉积等方法形成栅绝缘膜1041，然后在栅绝缘膜1041上采用溅射等方法形成栅极金属膜1051；之后对栅绝缘膜1041和栅极金属膜1051进行图案化，以形成栅绝缘层104和栅极105，有源层103和栅极105通过栅绝缘层104而彼此绝缘。例如，栅绝缘膜1041可以采用氧化硅、氮化硅、氮氧化硅等无机材料，栅极金属膜1051可以采用Mo、Al、Cu等金属或其合金。
S103：以栅极105为掩模对有源层103进行第一次掺杂。
如图2c所示，以栅极105为掩模对有源层103进行第一次掺杂。例如， 第一次掺杂为P型掺杂(例如，在有源层103采用非晶硅或多晶硅形成时可以采用三价的硼、铟、镓等进行掺杂)或N型掺杂(例如，在有源层103采用非晶硅或多晶硅形成时可以采用五价的磷、砷等进行掺杂)。例如，采用离子注入的方式进行第一次掺杂。
例如，如图2c所示，在以栅极105为掩模对有源层103进行第一次掺杂时，栅极105覆盖有源层103的沟道区(稍后描述)而有源层103的除沟道区之外的部分不被栅极105覆盖，有源层103的不被栅极105覆盖的部分被掺杂。
S104：形成与栅极105绝缘并具有突出部1071的金属层107。
如图2d所示，在栅极105上方形成金属层107，该金属层107具有突出部1071。例如，利用化学气相沉积等方法在栅极105上形成层间栅绝缘层106，在层间绝缘层106上利用溅射等方法形成金属膜(图中未示出)，然后对金属膜进行图案化以形成具有突出部1071的金属层107。金属层107和栅极105通过层间绝缘层106而彼此绝缘。在平行于衬底基板101的方向上，金属层107延伸以具有突出部1071，从而使得金属层107的突出部1071在衬底基板101上的正投影突出于所述第一投影。例如，层间绝缘层106可以采用氧化硅、氮化硅、氮氧化硅等无机材料。例如，金属层107可以采用Mo、Al、Cu等金属或其合金。例如，栅极105和金属层107可以由相同的材料形成。
需要说明的是，在图2d中，在平行于衬底基板101的方向上，金属层107延伸以具有突出部1071；然而本公开实施例不局限于此，例如金属层107也可以沿与衬底基板101相交的倾斜方向延伸以具有突出部1071，只要使得金属层107的突出部1071在衬底基板101上的正投影突出于与栅极105相对应的第一投影即可。
在金属层107具有突出部1071的情形下，金属层107的形状可以是任意的。
例如，如下所述，根据本公开实施例的方法制备得到的薄膜晶体管可以用于显示基板；在此情形下，栅极105、层间绝缘层106和金属层107可以一起构成电容。例如，栅极105、层间绝缘层106和金属层107可以一起构成显示基板中的存储电容。为了使该存储电容尽可能地大，需要尽可能地增加栅极105和金属层107之间的重叠面积。例如，如图3a所示，栅极105 在衬底基板101上的正投影为第一投影，金属层107在衬底基板101上的正投影为第二投影(线状阴影部分)，除金属层107的突出部1071所对应的区域(箭头指示的部分)之外第一投影与第二投影完全重合；在此情形下，可以使栅极105和金属层107之间的重叠面积最大化，从而增大存储电容。例如，如图3b所示，栅极105在衬底基板101上的正投影为第一投影，金属层107在衬底基板101上的正投影为第二投影，并且第一投影位于第二投影的内侧；在此情形下，不仅可以使栅极105和金属层107之间的重叠面积最大化，而且可以将金属层107制作为规则的形状(例如，规则的矩形)以使金属层107的制作更容易。
需要说明的是，“第一投影位于第二投影的内侧”是指第一投影不具有超出第二投影的部分。
另外，金属层107还可以具有其他形状。例如，如图3c所示，金属层107在衬底基板101上的正投影为第二投影(线状阴影部分)，有源层103在衬底基板101上的投影为第三投影(点状阴影部分)，第二投影和第三投影具有大体相同的形状，例如均为S形；在此情形下，制作金属层107的掩模板的设计参数与制作有源层103的掩模板的设计参数大体相同或成比例，可以降低工艺难度。例如，除了有源层103的要被第二次掺杂进行掺杂的区域之外，第二投影和第三投影重合；在此情形下，制作金属层107的掩模板与制作有源层103的掩模板更加相似，可以进一步降低工艺难度。例如，如图3c所示，有源层103和金属层107均为S形，除了有源层103的两个端部所在的位置之外有源层103的投影和金属层107的投影重合。
S105：以金属层107为掩模对有源层103进行第二次掺杂。
如图2e所示，以金属层107为掩模对有源层103进行第二次掺杂。例如，第二次掺杂可以是P型掺杂(例如，在有源层103采用非晶硅或多晶硅形成时可以采用三价的硼、铟、镓等进行掺杂)或N型掺杂(例如，在有源层103采用非晶硅或多晶硅形成时，可以采用五价的磷、砷等进行掺杂)。例如，采用离子注入的方式进行第二次掺杂。
例如，如图2e所示，在以金属层107为掩模对有源层103进行第二次掺杂时，金属层107覆盖有源层103的沟道区(稍后描述)和有源层103的经历了第一次掺杂的一部分区域，有源层103的经历了第一次掺杂的另一部分区域不被金属层107覆盖，有源层103的不被金属层107覆盖的部分被掺 杂。
例如，第一次掺杂的掺杂类型可以与第二次掺杂的类型相同，例如同为P型掺杂或N型掺杂。如图2e所示，通过上述第一次掺杂和第二次掺杂，可以在有源层103中形成第一掺杂区1和第二掺杂区2；第一掺杂区1仅经历了第一次掺杂而第二掺杂区2既经历了第一次掺杂又经历了第二次掺杂，所以第一掺杂区1的掺杂浓度小于第二掺杂区2的掺杂浓度。有源层103还具有在上述第一和第二次掺杂中均未被掺杂的沟道区3，沟道区3与栅极105相对应，第一掺杂区1位于沟道区3和第二掺杂区2之间。这样一来，在沟道区3和掺杂浓度高的第二掺杂区2之间形成了掺杂浓度低的第一掺杂区1；该掺杂浓度低的第一掺杂区1可以分担施加在沟道区3上的一部分电压，因此与不具有该掺杂浓度低的第一掺杂区1的薄膜晶体管相比，根据本公开实施例的方法制备得到的薄膜晶体管的漏电流减小。例如，第一次掺杂的掺杂浓度小于第二次掺杂的掺杂浓度，由此可以使第一掺杂区1的掺杂浓度进一步小于第二掺杂区2的掺杂浓度，可以进一步减小薄膜晶体管的漏电流。例如，第一次掺杂的掺杂浓度大约是第二次掺杂的掺杂浓度的1/10，然而本公开实施例不局限于此。
例如，如图2e所示，在沟道区3的两侧均形成了第一掺杂区1和第二掺杂区2，一个第二掺杂区2用作与源极(稍后描述)连接的源极区，另一个第二掺杂区2用作与漏极(稍后描述)连接漏极区。
在根据本公开实施例的薄膜晶体管的制备方法中，采用栅极作为掩模进行第一次掺杂并采用具有突出部的金属层作为掩模进行第二次掺杂，这样可以容易地在沟道区和掺杂浓度高的第二掺杂区之间形成掺杂浓度低的第一掺杂区，从而在减小薄膜晶体管的漏电流的同时降低了工艺难度。另外，在根据本公开实施例的薄膜晶体管的制备方法中，栅极、金属层以及位于栅极和金属层之间的层间绝缘层可以一起构成显示基板的存储电容，该存储电容设置在薄膜晶体管的有源层的正上方，使得该存储电容不用占用额外的空间，从而增加了显示基板的开口率。另外，在根据本公开实施例的薄膜晶体管的制备方法中，栅极和金属层可以兼做显示基板的存储电容的两个极板，从而在薄膜晶体管用于显示基板时不用另外制作存储电容，简化了制作工艺。
例如，参见附图，根据本公开实施例的薄膜晶体管的制备方法还可以如 下步骤。
S106：形成过孔108及源漏极过孔113。
如图2f所示，在进行第二次掺杂之后在金属层107上形成钝化层109，然后进行图案化工艺以形成贯穿钝化层109和层间绝缘层106的源漏极过孔113，该源漏极过孔113露出有源层103的第二掺杂区2。例如，钝化层109可以采用氧化硅、氮化硅、氮氧化硅等无机材料。如图2f所示，形成了两个源漏极过孔113，以露出有源层103的两个第二掺杂区2。
例如，如图3d所示，还可以形成过孔108，该过孔108贯穿钝化层109、金属层107和层间绝缘层106以露出栅极105的一部分，以方便实现栅极105与其他部件的连接。
需要说明是，源漏极过孔113和过孔108可以通过同一次构图工艺同时形成，或者源漏极过孔113和过孔108可以通过两次构图工艺分别形成。
S106：形成源电极111和漏电极110。
例如，在形成源漏极过孔113之后形成源漏极金属膜(未示出)，对源漏极金属膜进行图案化工艺以形成源极111和漏极110。例如，源漏极薄膜可以采用Ti、Al等金属或其合金的单层或多层材料，例如Ti/Al/Ti三层材料。例如，源极111通过过孔113连接到位于有源层103的沟道区3一侧的第二掺杂区2，漏极110通过过孔113连接到位于有源层103的沟道区3另一侧的第二掺杂区2。
例如，根据本公开实施例的方法所制得的薄膜晶体管可以用于有机发光显示基板，该有机发光显示基板包括多个像素单元，每个像素单元例如包括开关晶体管、驱动晶体管、存储电容和发光二极管；在此情形下，根据本公开实施例的方法所制得的薄膜晶体管可以用作有机发光显示基板中的驱动薄膜晶体管，其金属层107和源极111彼此连接并一起连接到电源线(稍后描述)，其漏极110连接到有机发光二极管，其栅极105、层间绝缘层106和金属层107一起构成存储电容。
至此，完成了根据本公开实施例的薄膜晶体管的制备方法，并得到了根据本公开实施例的薄膜晶体管，如图4所示。
根据本公开的实施例，还提供一种薄膜晶体管。如图4所示，该薄膜晶体管包括：有源层103，形成在衬底基板101上；栅极105，形成在有源层103上方，栅极105与有源层103绝缘；金属层107，形成述栅极105上方， 金属层107与栅极105绝缘并具有突出部1071，该栅极105在衬底基板101上的正投影为第一投影，该金属层107在衬底基板101上的正投影为第二投影，在该金属层107的突出部1071对应的区域处所述第二投影突出于所述第一投影；有源层103包括第一掺杂区1和第二掺杂区2，第一掺杂区1的掺杂浓度小于第二掺杂区2的掺杂浓度。
例如，如图4所示，栅极105通过栅绝缘层104与有源层103绝缘，金属层107通过层间绝缘层106与栅极105绝缘。例如，如图4所示，有源层103还具有沟道区3，并且第一掺杂区1位于沟道区3和第二掺杂区2之间。例如，如图4所示，薄膜晶体管还包括源极111和漏极110，源极111连接到位于有源层103的沟道区3一侧的第二掺杂区2，漏极110连接到位于有源层103的沟道区3另一侧的第二掺杂区2。例如，如图4所示，薄膜晶体管还包括过孔113，源极111通过过孔113连接到第二掺杂区2，漏极110通过过孔113连接到第二掺杂区2。例如，如图3d所示，薄膜晶体管还包括过孔108，该过孔108露出栅极105的一部分，以利于栅极105与其他部件实现连接。
例如，在金属层107具有突出部1071的情形下，金属层107的形状可以是任意的，具体可以参见之前的描述。
根据本公开实施例的薄膜晶体管可以用于显示基板；在此情形下，栅极105、层间绝缘层106和金属层107可以一起构成显示基板中的存储电容，金属层107和源极111彼此连接并一起连接到电源线(稍后描述)，漏极110连接到有机发光二极管。
例如，根据本公开实施例的薄膜晶体管采用如上所述的根据本公开实施例的薄膜晶体管的制备方法制备得到。
根据本公开的实施例，还提供一种显示基板的制备方法。该方法包括：采用如上所述的制备方法制作薄膜晶体管；以及制作发光二极管。所述薄膜晶体管的漏电极连接到发光二极管，所述薄膜晶体管的源电极以及所述金属层连接到电源线。
根据本公开的实施例，还提供一种显示基板。该显示基板包括：如上所述的薄膜晶体管，以及发光二极管。所述薄膜晶体管的漏电极连接到发光二极管，所述薄膜晶体管的源电极以及所述金属层连接到电源线。
例如，根据本公开实施例的显示基板采用如上所述的根据本公开实施例 的显示基板的制备方法制备得到。
图5是根据本公开实施例的显示基板的截面示意图，图6是根据本公开实施例的显示基板的平面示意图，以及图7是根据本公开实施例的显示基板的电路图。如图5至图7所示，该显示基板包括多个像素单元，每个像素单元例如包括驱动晶体管T1、开关晶体管T2、存储电容C和发光二极管(Light Emitting Diode，LED)，根据本公开实施例的薄膜晶体管用作驱动晶体管T1；开关晶体管T2的栅极连接到扫描线121，源极连接到数据线122，漏极连接到驱动晶体管T1的栅极105；驱动晶体管T1的源极111和金属层107连接到电源线112，漏极110连接到发光二极管，栅极105和金属层107用作存储电容C的两个极板。
在图5中，左侧为驱动晶体管T1，右侧为开关晶体管T2，附图标记204和205分别指代开关晶体管T2的栅绝缘层和栅极。需要说明的是，图5为截面示意图，其仅示出了开关晶体管T2的一部分，开关晶体管T2的有源层、栅绝缘层204、栅极205、源极和漏极例如可以分别与驱动近体馆T1的有源层103、栅绝缘层104、栅极105、源极111和漏极110同时形成并同层且同材料设置。例如，开关晶体管T2不具有与驱动晶体管T1的金属层107相对应的金属层。
如图5所示，发光二极管包括下电极115、上电极118以及设置在下电极115和上电极118之间的发光层117。附图标记116指代像素界定层，用于将多个像素单元分隔开。如图5所示，驱动晶体管T1的漏极110通过设置在平坦化层114中的过孔连接到发光二极管的下电极115。
如图6和7所示，驱动晶体管T2的栅极105通过过孔108连接到走线112’，并最终连接到开关晶体管T2的漏极。
例如，根据本公开实施例的显示基板为柔性基板。在此情形下，根据本公开的实施例的显示基板的制备方法还包括：在形成薄膜晶体管和发光二极管之前，在衬底基板101上形成柔性缓冲层102，如图8所示；以及在在形成薄膜晶体管和发光二极管之后，将衬底基板101自柔性缓冲层102剥离。例如，柔性缓冲层102包括有机缓冲层1021和无机缓冲层1022。例如，有机缓冲层1021与衬底基板101直接接触，以方便后续剥离衬底基板101；无机缓冲层1022与薄膜晶体管直接接触，以防止杂质扩散进入薄膜晶体管。例如，如图8所示，柔性缓冲层102包括交替设置的多个有机缓冲层1021 和多个无机缓冲层1022。
根据本公开的实施例，还提供一种显示装置。如图9所示，该显示装置1包括如上所述的显示基板10。该显示装置例如可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在根据本公开实施例的薄膜晶体管及其制备方法、显示基板及其制备方法、以及显示装置中，采用栅极作为掩模进行第一次掺杂并采用具有突出部的金属层作为掩模进行第二次掺杂，这样可以容易地在沟道区和掺杂浓度高的第二掺杂区之间形成掺杂浓度低的第一掺杂区，从而在减小薄膜晶体管的漏电流的同时降低了工艺难度。另外，在根据本公开实施例的薄膜晶体管及其制备方法、显示基板及其制备方法、以及显示装置中，栅极、金属层以及位于栅极和金属层之间的层间绝缘层可以一起构成显示基板的存储电容，该存储电容设置在薄膜晶体管的有源层的正上方，使得该存储电容不用占用额外的空间，从而增加了显示基板的开口率。另外，在根据本公开实施例的薄膜晶体管及其制备方法、显示基板及其制备方法、以及显示装置中，栅极和金属层可以兼做显示基板的存储电容的两个极板，从而不用另外制作存储电容，简化了制作工艺。
以上所述仅是本公开的示范性实施例，而非用于限制本公开的保护范围，本公开的保护范围由权利要求确定。

Claims (16)

  1. 一种薄膜晶体管的制备方法，包括：
    在衬底基板上形成有源层；
    在所述有源层上方形成栅极，该栅极与所述有源层绝缘；
    以栅极为掩模对所述有源层进行第一次掺杂；
    在所述栅极上方形成金属层，该金属层与所述栅极绝缘并具有突出部，所述栅极在所述衬底基板上的正投影为第一投影，所述金属层在所述衬底基板上的正投影为第二投影，在所述金属层的所述突出部对应的区域处所述第二投影突出于所述第一投影；以及
    以所述金属层为掩模对所述有源层进行第二次掺杂。
  2. 根据权利要求1所述的制备方法，其中，除所述金属层的所述突出部所对应的区域之外所述第一投影与所述第二投影重合。
  3. 根据权利要求1所述的制备方法，其中，所述第一投影位于所述第二投影的内侧。
  4. 根据权利要求1所述的制备方法，其中，所述有源层在所述衬底基板上的投影为第三投影，除所述有源层的要被所述第二次掺杂进行掺杂的部分之外所述第二投影和所述第三投影重合。
  5. 根据权利要求4所述的制备方法，其中，所述第二投影和所述第三投影均为S形。
  6. 根据权利要求1-5任一项所述的制备方法，其中，
    在所述栅极和所述金属层之间具有层间绝缘层，并且
    所述方法还包括形成过孔，该过孔贯穿所述金属层和所述层间绝缘层以露出所述栅极的一部分。
  7. 根据权利要求1-5任一项所述的制备方法，其中，
    所述第一次掺杂的掺杂类型与所述第二次掺杂的类型相同；
    所述有源层包括沟道区、第一掺杂区和第二掺杂区，所述第一掺杂区位于所述沟道区和所述第二掺杂区之间；并且
    所述沟道区在所述第一次掺杂和所述第二次掺杂中均未被掺杂，所述第一掺杂区在所述第一次掺杂中被掺杂，所述第二掺杂区在所述第一次掺杂和所述第二次掺杂两者中被掺杂。
  8. 根据权利要求7所述的制备方法，还包括形成源电极和漏电极，所述源电极与所述第二掺杂区连接。
  9. 根据权利要求8所述的制备方法，其中，所述薄膜晶体管用于显示基板，并且所述金属层与所述源电极连接。
  10. 根据权利要求1-5任一项所述的制备方法，其中，所述第一次掺杂的掺杂浓度小于所述第二次掺杂的掺杂浓度。
  11. 一种显示基板的制备方法，包括：
    采用根据权利要求1-10任一项所述的制备方法制作薄膜晶体管；以及
    制作发光二极管，
    其中，所述薄膜晶体管的漏电极连接到发光二极管，所述薄膜晶体管的源电极以及所述金属层连接到电源线。
  12. 根据权利要求11所述的制备方法，其中，在所述栅极和所述金属层之间具有层间绝缘层，所述栅极、所述层间绝缘层和所述金属层构成电容。
  13. 一种薄膜晶体管，包括：
    有源层，形成在衬底基板上；
    栅极，形成在所述有源层上方，该栅极与所述有源层绝缘；以及
    金属层，形成在所述栅极上方，该金属层与所述栅极绝缘并具有突出部，所述栅极在所述衬底基板上的正投影为第一投影，所述金属层在所述衬底基板上的正投影为第二投影，在所述金属层的所述突出部对应的区域处所述第二投影突出于所述第一投影，
    其中，所述有源层包括第一掺杂区和第二掺杂区，所述第一掺杂区的掺杂浓度小于所述第二掺杂区的掺杂浓度。
  14. 一种显示基板，包括：如权利要求13所述的薄膜晶体管，以及发光二极管，
    其中，所述薄膜晶体管的漏电极连接到发光二极管，所述薄膜晶体管的源电极以及所述金属层连接到电源线。
  15. 根据权利要求14所述的显示基板，其中，在所述栅极和所述金属层之间具有层间绝缘层，所述栅极、所述层间绝缘层和所述金属层构成电容。
  16. 一种显示装置，包括如权利要求14或15所述的显示基板。
PCT/CN2018/076636 2017-06-16 2018-02-13 薄膜晶体管及制备方法、显示基板及制备方法、显示装置 WO2018227991A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710456964.0 2017-06-16
CN201710456964.0A CN107240610B (zh) 2017-06-16 2017-06-16 薄膜晶体管及制备方法、显示基板及制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2018227991A1 true WO2018227991A1 (zh) 2018-12-20

Family

ID=59986236

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/076636 WO2018227991A1 (zh) 2017-06-16 2018-02-13 薄膜晶体管及制备方法、显示基板及制备方法、显示装置

Country Status (2)

Country Link
CN (1) CN107240610B (zh)
WO (1) WO2018227991A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107240610B (zh) * 2017-06-16 2021-01-22 京东方科技集团股份有限公司 薄膜晶体管及制备方法、显示基板及制备方法、显示装置
CN112420743A (zh) * 2020-11-06 2021-02-26 深圳市华星光电半导体显示技术有限公司 显示面板和显示面板的制作方法
CN114582894A (zh) * 2022-03-10 2022-06-03 广州华星光电半导体显示技术有限公司 阵列基板及显示面板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613407A (ja) * 1992-06-24 1994-01-21 Seiko Epson Corp 薄膜半導体装置及びその製造方法
US20020104995A1 (en) * 2001-01-17 2002-08-08 Shunpei Yamazaki Light emitting device
US20140225075A1 (en) * 2013-02-14 2014-08-14 Zhi-Feng ZHAN Thin film semiconductor device, organic light-emitting display device, and method of manufacturing the thin film semiconductor device
CN104681628A (zh) * 2015-03-17 2015-06-03 京东方科技集团股份有限公司 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
US20160099300A1 (en) * 2014-10-06 2016-04-07 Samsung Display Co., Ltd. Thin film transistor array substrate and organic light-emitting diode display including the same
CN105612620A (zh) * 2014-02-25 2016-05-25 乐金显示有限公司 显示器底板及其制造方法
US20160181339A1 (en) * 2014-12-19 2016-06-23 Samsung Display Co., Ltd. Thin-film transistor array substrate and organic light-emitting diode display including the same
CN107240610A (zh) * 2017-06-16 2017-10-10 京东方科技集团股份有限公司 薄膜晶体管及制备方法、显示基板及制备方法、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7038239B2 (en) * 2002-04-09 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
CN103681494A (zh) * 2012-09-25 2014-03-26 上海天马微电子有限公司 一种薄膜晶体管像素单元及其制造方法
CN106206620B (zh) * 2016-09-05 2019-02-15 昆山国显光电有限公司 薄膜晶体管阵列基板及其制备方法和显示器件
CN106816473B (zh) * 2017-01-16 2020-01-21 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613407A (ja) * 1992-06-24 1994-01-21 Seiko Epson Corp 薄膜半導体装置及びその製造方法
US20020104995A1 (en) * 2001-01-17 2002-08-08 Shunpei Yamazaki Light emitting device
US20140225075A1 (en) * 2013-02-14 2014-08-14 Zhi-Feng ZHAN Thin film semiconductor device, organic light-emitting display device, and method of manufacturing the thin film semiconductor device
CN105612620A (zh) * 2014-02-25 2016-05-25 乐金显示有限公司 显示器底板及其制造方法
US20160099300A1 (en) * 2014-10-06 2016-04-07 Samsung Display Co., Ltd. Thin film transistor array substrate and organic light-emitting diode display including the same
US20160181339A1 (en) * 2014-12-19 2016-06-23 Samsung Display Co., Ltd. Thin-film transistor array substrate and organic light-emitting diode display including the same
CN104681628A (zh) * 2015-03-17 2015-06-03 京东方科技集团股份有限公司 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
CN107240610A (zh) * 2017-06-16 2017-10-10 京东方科技集团股份有限公司 薄膜晶体管及制备方法、显示基板及制备方法、显示装置

Also Published As

Publication number Publication date
CN107240610A (zh) 2017-10-10
CN107240610B (zh) 2021-01-22

Similar Documents

Publication Publication Date Title
TWI464869B (zh) 半導體元件及電致發光元件及其製作方法
CN110649043B (zh) 阵列基板、显示面板、显示装置及阵列基板的制备方法
CN106558593B (zh) 阵列基板、显示面板、显示装置及阵列基板的制备方法
CN106981520B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
US10325938B2 (en) TFT array substrate, method for manufacturing the same, and display device
KR101987218B1 (ko) 어레이 기판, 그것의 제조 방법, 및 디스플레이 장치
WO2015096355A1 (zh) 阵列基板及其制作方法、显示装置
US10615282B2 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
TWI422039B (zh) 薄膜電晶體元件及其製作方法
WO2019109748A1 (zh) 阵列基板及其制备方法、显示装置
WO2017193667A1 (zh) 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
TWI572020B (zh) 陣列基板以及其製作方法
WO2018227991A1 (zh) 薄膜晶体管及制备方法、显示基板及制备方法、显示装置
TW201438251A (zh) 顯示面板及其製作方法
TWI419336B (zh) 半導體元件及其製作方法
US9349759B2 (en) Manufacturing method of low temperature poly-silicon TFT array substrate
US6646308B2 (en) Flat panel display device
US20240063233A1 (en) Array substrate, method for fabricating same, and display panel
TW200409364A (en) Structure of thin film transistor array and driving circuits
US20210376029A1 (en) Array substrate and manufacturing method thereof, and display panel
TWI579926B (zh) 主動元件陣列基板
CN111081719A (zh) 一种阵列基板及其制造方法
KR20190111725A (ko) 수직 나노와이어 반도체 소자 및 그 제조 방법
WO2022001468A1 (zh) 薄膜晶体管、显示基板及显示装置
CN117038739A (zh) 薄膜晶体管及其制作方法、显示基板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18817214

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03.06.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18817214

Country of ref document: EP

Kind code of ref document: A1