WO2017193667A1 - 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 - Google Patents

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 Download PDF

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WO2017193667A1
WO2017193667A1 PCT/CN2017/074772 CN2017074772W WO2017193667A1 WO 2017193667 A1 WO2017193667 A1 WO 2017193667A1 CN 2017074772 W CN2017074772 W CN 2017074772W WO 2017193667 A1 WO2017193667 A1 WO 2017193667A1
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Prior art keywords
amorphous silicon
layer
source
thin film
film transistor
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PCT/CN2017/074772
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English (en)
French (fr)
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白金超
郭会斌
洪永泰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/558,104 priority Critical patent/US10403756B2/en
Priority to EP17761424.5A priority patent/EP3457441B1/en
Publication of WO2017193667A1 publication Critical patent/WO2017193667A1/zh

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Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device.
  • Polycrystalline silicon thin film transistors have been widely used in various displays due to their high electron mobility and stability.
  • the fabrication steps of the polysilicon thin film transistor are numerous, and approximately 10 exposure processes are required.
  • the fabrication process includes: a laser annealing process for forming polysilicon, and a two-ion implantation process for forming an active layer having a lightly doped region, a heavily doped region, and a channel region, And high temperature processes such as dehydrogenation, hydrogenation and activation.
  • These complex processes allow low-temperature polysilicon thin film transistors to be mass-produced on the sixth generation or below, with lower yields, higher equipment investment, and poorer compatibility with amorphous silicon thin film transistors.
  • At least one embodiment of the present invention provides a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device to simplify the fabrication process of the polysilicon thin film transistor.
  • At least one embodiment of the present invention provides a thin film transistor including: an active layer, an amorphous silicon connection layer, and a source/drain electrode layer.
  • the active layer has a channel region, a source region, and a drain region, the formation material of the channel region includes polysilicon;
  • the amorphous silicon connection layer is located on one side of the active layer, and includes spaces apart from each other a first connection portion and a second connection portion;
  • the source/drain electrode layer includes a source and a drain spaced apart from each other, and the source is electrically connected to the source region through the first connection portion, The drain is electrically connected to the drain region through the second connection portion.
  • the source region and the drain region are both undoped regions.
  • the source region and the drain region are formed of undoped amorphous silicon or undoped polysilicon.
  • the amorphous silicon connection layer includes a first amorphous silicon layer and a second amorphous silicon layer which are disposed in a stacked manner, and the second amorphous silicon layer is disposed on the first amorphous silicon layer and the source leakage Between the pole layers, and the electrical conductivity of the second amorphous silicon layer is greater than the electrical conductivity of the first amorphous silicon layer.
  • the forming material of the first amorphous silicon layer is undoped amorphous silicon.
  • the thin film transistor further includes a carrier substrate, and the active layer is disposed between the carrier substrate and the source/drain electrode layer in a direction perpendicular to the carrier substrate.
  • the material of the source/drain electrode layer is a metal material.
  • a distance between outer edges of the active layer is equal to between outer edges of the first connection portion and the second connection portion the distance.
  • the distance between the source and the outer edge of the drain is equal to the distance between the outer edges of the first connection and the second connection.
  • the distance between the source and the outer edge of the drain is equal to the distance between the outer edges of the first connection and the second connection.
  • the thin film transistor further includes a carrier substrate and a gate, and the gate is disposed between the active layer and the carrier substrate.
  • At least one embodiment of the present invention also provides an array substrate comprising a plurality of thin film transistors spaced apart from each other, the thin film transistor being the thin film transistor of any of the above.
  • the array substrate further includes a plurality of pixel electrodes spaced apart from each other, the plurality of pixel electrodes respectively corresponding to the plurality of thin film transistors, and each of the pixel electrodes is electrically connected to a drain of the corresponding thin film transistor.
  • At least one embodiment of the present invention also provides a display device comprising the array substrate of any of the above.
  • At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, comprising: forming an active layer having a channel region, a source region, and a drain region, such that a forming material of the channel region includes polysilicon; Forming an amorphous silicon connection layer on one side of the active layer, the amorphous silicon connection layer including first and second connection portions spaced apart from each other; and being away from the amorphous silicon connection layer One side of the active layer forms a source/drain electrode layer, the source/drain electrode layer includes a source and a drain, and the source is electrically connected to the source region through the first connection portion, The drain is electrically connected to the drain region through the second connection portion.
  • forming the amorphous silicon connection layer includes: forming a stacked first amorphous silicon layer and a second amorphous silicon layer, and forming the second amorphous silicon layer on the first amorphous silicon layer and The source and drain electrode layers are between, and the conductivity of the second amorphous silicon layer is greater than the conductivity of the first amorphous silicon layer.
  • forming the active layer includes: forming an amorphous silicon film; and forming the channel region or the channel region to be formed, the source region, and the drain to the amorphous silicon film Part of the polar zone A laser annealing treatment is performed to form the portion to form polysilicon.
  • the active layer and the amorphous silicon connection layer are formed by a half exposure process; or the active layer, the amorphous silicon connection layer, and the source/drain electrode layer are formed by a half exposure process.
  • forming a laminated amorphous silicon connection layer film and a source/drain electrode layer film For example, forming a laminated amorphous silicon connection layer film and a source/drain electrode layer film; performing an exposure process on the amorphous silicon connection layer film and the source/drain electrode layer film to form the amorphous silicon connection layer and The source drain electrode layer is described.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a plurality of thin film transistors spaced apart from each other, the thin film transistor being fabricated by the fabrication method described in any one of the above.
  • At least one embodiment of the present invention also provides another thin film transistor including an active layer and a source/drain electrode layer.
  • the active layer has a channel region, a source region and a drain region, the formation material of the channel region includes polysilicon, and a forming material of the source region and the drain region includes doped amorphous silicon;
  • the source/drain electrode layer is located at one side of the active layer and includes a source and a drain spaced apart from each other, the source is electrically connected to the source region, the drain and the drain region Electrical connection.
  • FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of another thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present invention
  • 5a to 5c are schematic cross-sectional views showing steps of fabricating the thin film transistor shown in FIG. 2 according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional view showing an insulating layer for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention.
  • 102 insulating layer 110, 210: active layer 100a, 200a: carrier substrate
  • first connection portion 122 second connection portion 130: source/drain electrode layer
  • source 132 drain 140, 240: gate
  • gate insulating layer 120a first amorphous silicon connecting layer
  • amorphous silicon connecting layer film 130' source/drain electrode layer film
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device.
  • the active layer of the thin film transistor has a channel region formed of a polysilicon material, thereby ensuring that the thin film transistor has a large on-state current; further, a source region and a drain region of the active layer
  • the amorphous silicon material is electrically connected to the source and the drain, respectively, or both are doped with an amorphous silicon material to achieve electrical connection with the source and the drain, thereby eliminating the need to fabricate lightly doped regions and heavily doped regions.
  • the two ion implantation processes and the corresponding exposure process. Therefore, the embodiment of the present invention can simplify the fabrication process of the polysilicon thin film transistor under the premise of ensuring that the polysilicon thin film transistor has a large on-state current.
  • At least one embodiment of the present invention provides a thin film transistor 100 including an active layer 110, an amorphous silicon connection layer 120, and a source/drain electrode layer 130.
  • the active layer 110 has a channel region 113, and a source region 111 and a drain region 112 respectively located on both sides of the channel region 113 and connected to the channel region 113.
  • the formation material of the channel region 113 includes polysilicon, for example, a source.
  • the forming material of the polar region 111 and the drain region 112 may be polysilicon or amorphous silicon; the amorphous silicon connecting layer 120 is located at one side of the active layer 110, and includes a first connecting portion 121 and a second connecting portion which are spaced apart from each other
  • the source/drain electrode layer 130 includes a source electrode 131 and a drain electrode 132 which are spaced apart from each other.
  • the source electrode 131 is electrically connected to the source region 111 through the first connection portion 121, and the drain electrode 132 passes through the second connection portion 122 and the drain region. 112 electrical connection.
  • the source region 111 and the drain region 112 of the active layer 110 are electrically connected to the source 131 and the drain 132 through the amorphous silicon connection layer 120, respectively. Therefore, the fabrication process of the thin film transistor 100 provided by the embodiment of the present invention can omit the ion implantation process for forming a light and heavily doped region and the corresponding exposure process, compared with a conventional process for fabricating a polysilicon (p-Si) thin film transistor. This makes the thin film transistor 100 simple in fabrication process, less in equipment investment, suitable for high generation lines and has good compatibility with amorphous silicon (a-Si) thin film transistor production lines.
  • a-Si amorphous silicon
  • the thin film transistor 100 provided by the embodiment of the present invention includes a channel region 113 of the active layer 110 made of a polysilicon material (for example, a low temperature polysilicon material), as the polysilicon material has The larger the electron mobility, the thin film transistor 100 provided by the embodiment of the present invention has a larger on-state current.
  • a polysilicon material for example, a low temperature polysilicon material
  • the source region 111 and the drain region 112 of the active layer 110 may both be undoped regions.
  • the forming materials of the source region 111 and the drain region 112 may be undoped amorphous silicon or non-doped. Polysilicon.
  • the source region 111 and the drain region 112 are electrically connected to the source 131 and the drain 132 through the amorphous silicon connection layer 120, respectively, and are both undoped regions, which is advantageous for the thin film transistor 100 provided by the embodiment of the present invention to have a lower
  • the off-state leakage current especially in the case where the source region 111 and the drain region 112 are both undoped amorphous silicon, the present invention is implemented in comparison with a conventional polysilicon thin film transistor including a light and heavily doped region.
  • the thin film transistor 100 in the example has a lower off-state leakage current.
  • the material forming the source region 111 and the drain region 112 is undoped amorphous silicon or undoped.
  • the first connecting portion 121 and the second connecting portion 122 of the amorphous silicon connecting layer 120 may be formed of doped amorphous silicon, such as P-type doped amorphous silicon or N-type doped amorphous silicon. .
  • the material of the source/drain electrode layer 130 may be a metal material.
  • At least one embodiment of the present invention provides a thin film transistor 100 further including a carrier substrate 100a, and in a direction perpendicular to the carrier substrate 100a, the active layer 110 may be disposed on the carrier substrate 100a and source and drain. Between the pole layers 130. With this arrangement, the fabrication process of the thin film transistor 100 can be made simpler.
  • a typical polysilicon thin film transistor is a top gate structure, so that the active layer can be ion implant doped with a gate as a mask during fabrication. Since the fabrication process of the thin film transistor 100 provided by the embodiment of the present invention may omit the ion implantation doping process, for example, the thin film transistor 100 provided by at least one embodiment of the present invention may be a bottom gate structure, that is, the thin film transistor 100 further includes A gate insulating layer 150 is disposed between the gate electrode 140 and the active layer 110, and the gate electrode 140 is disposed between the active layer 110 and the carrier substrate 100a. Of course, in some embodiments, the thin film transistor 100 can also adopt a top gate structure.
  • the multilayer film included in the thin film transistor 100 may be fabricated by the same exposure process.
  • the distance between the outer edges 110a, 110b of the active layer 110 may be substantially equal to the outer edge 121a of the first connection portion 121 and the second connection portion 122, The distance between 122a.
  • the active layer 110 and the amorphous silicon connection layer 120 can be formed by a single exposure process (for example, a half exposure process) to reduce the number of exposure processes.
  • the distance between the outer edges 131a, 132a of the source 131 and the drain 132 may be substantially equal to the distance between the outer edges 121a, 122a of the first connecting portion 121 and the second connecting portion 122.
  • the source/drain electrode layer 130, the active layer 110, and the amorphous silicon connection layer 120 can be formed by a single exposure process (for example, a half exposure process) to further reduce the number of exposure processes.
  • the distance between the outer edges 131a, 132a of the source 131 and the drain 132 may be substantially equal to the distance between the outer edges 121a, 122a of the first connection portion 121 and the second connection portion 122.
  • the source-drain electrode layer 130 and the amorphous silicon connection layer 120 can be formed by a single exposure process (for example, a half exposure process) to reduce the number of exposure processes.
  • FIG. 1 illustrates an amorphous silicon connection layer 120 as a single layer structure.
  • the amorphous silicon connection layer 120 may have a multilayer structure.
  • the amorphous silicon connection layer 120 includes a first amorphous silicon layer 120a and a second amorphous silicon layer 120b which are stacked,
  • the second amorphous silicon layer 120b is disposed between the first amorphous silicon layer 120a and the source/drain electrode layer 130, and the electrical conductivity of the second amorphous silicon layer 120b is greater than the electrical conductivity of the first amorphous silicon layer 120a.
  • the second amorphous silicon layer 120b may function as an ohmic contact layer to improve electrical connectivity between the first amorphous silicon connection layer 120a and the source/drain electrode layer 130.
  • the second amorphous silicon layer 120b may be N-type doped amorphous silicon or P-type doped amorphous silicon.
  • the first amorphous silicon layer may be undoped amorphous silicon. Since the amorphous silicon connection layer 120 includes the first amorphous silicon layer 120a made of undoped amorphous silicon, it is more advantageous to reduce the off-state leakage current of the thin film transistor 100.
  • the material forming the source region 111 and the drain region 112 may both be undoped polysilicon. This allows the thin film transistor 100 to have a lower off-state leakage current than a typical polysilicon thin film transistor including a light and heavily doped region.
  • At least one embodiment of the present invention further provides an array substrate 10 including a plurality of thin film transistors 100 as described in any of the above embodiments spaced apart from each other. Only one thin film transistor 100 is shown in FIG. 3, and the amorphous silicon connection layer 120 in the thin film transistor 100 has a two-layer structure.
  • the array substrate provided by the embodiment of the present invention includes, but is not limited to, the embodiment shown in FIG. 3 .
  • the array substrate 10 may further include a plurality of pixel electrodes 101 spaced apart from each other, the plurality of pixel electrodes 101 respectively corresponding to the plurality of thin film transistors 100, and each pixel electrode 101 corresponding to The drain 132 of the thin film transistor 100 is electrically connected.
  • the array substrate 10 may further include an insulating layer 102 covering the thin film transistor 100, and the pixel electrode 101 may be electrically connected to the drain 132 of the corresponding thin film transistor 100 through a via hole in the insulating layer 102.
  • the pixel electrode 101 can be made of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide) or a similar transparent conductive material. There is no limit here.
  • the array substrate provided by the embodiment of the invention may be an OLED (Organic Light Emitting Diode) array substrate, or may be an array substrate for a liquid crystal display device.
  • the array substrate 10 may further include structures such as a common electrode line, a gate line, a data line, and the like, and details are not described herein again.
  • At least one embodiment of the present invention also provides a display device comprising the array substrate 10 provided in any of the above embodiments.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present invention further provides a method of fabricating a thin film transistor.
  • the method includes the steps of: forming an active layer having a channel region, a source region, and a drain region, the formation material of the channel region includes polysilicon; and step S2, forming an amorphous silicon connection layer on one side of the active layer.
  • the amorphous silicon connection layer includes a first connection portion and a second connection portion which are spaced apart from each other; and in step S3, a source/drain electrode layer is formed on a side of the amorphous silicon connection layer away from the active layer, so that the source
  • the drain electrode layer includes a source and a drain, the source is electrically connected to the source region through the first connection portion, and the drain is electrically connected to the drain region through the second connection portion.
  • forming the active layer may include: forming an amorphous silicon film; and forming a channel region or a portion to be formed of the channel region, the source region, and the drain region of the amorphous silicon film A laser annealing treatment is performed to form the portion into polysilicon.
  • the embodiment of the present invention facilitates the fabrication method provided by the embodiment of the present invention by performing local laser annealing treatment on the amorphous silicon film to form polycrystalline silicon, compared with the conventional method of laser annealing the entire amorphous silicon thin film. In the high generation production line.
  • steps S1 to S3 in the manufacturing method provided by the embodiment of the present invention is not limited.
  • the active layer and the amorphous silicon connection layer may be formed by a half exposure process, that is, steps S1 and S2 may be performed simultaneously; or, the active layer, the amorphous silicon connection layer, and the source/drain electrode layer may be formed by a half exposure process That is, steps S1 to S3 can be performed simultaneously.
  • the half exposure process refers to a process of exposing a photoresist on a film using a halftone mask or a gray tone mask, followed by development and etching to form a desired pattern.
  • a laminated amorphous silicon connection layer film ie, a film to be formed of an amorphous silicon connection layer
  • a source/drain electrode layer film ie, a film to be formed with a source/drain electrode layer
  • an amorphous silicon connection layer The thin film and source/drain electrode layer films are subjected to a single exposure process to form an amorphous silicon connection layer and a source/drain electrode layer. That is to say, step S2 and step S3 can be produced simultaneously.
  • steps S1 to S3 includes, but is not limited to, the listed sequences.
  • the method provided by the embodiment of the present invention can be used to fabricate the thin film transistor 100 provided in any of the above embodiments.
  • forming the amorphous silicon connection layer 120 may include forming the stacked first amorphous silicon layer 120a and the second The amorphous silicon layer 120b is formed between the first amorphous silicon layer 120a and the source/drain electrode layer 130, and the second amorphous silicon layer 120b has a conductivity higher than that of the first amorphous silicon layer. Conductivity of 120a. This can improve the electrical connectivity between the first amorphous silicon connection layer 120a and the source/drain electrode layer 130.
  • the second amorphous silicon layer 120b may be N-type doped amorphous silicon or P-type doped amorphous silicon;
  • the first amorphous silicon layer may be undoped amorphous silicon.
  • the fabrication method provided by the embodiment of the present invention will be described in detail below by taking the thin film transistor 100 shown in FIG. 2 as an example.
  • the method may include the following steps S01 to S04.
  • Step S01 A gate electrode 140, a gate insulating layer 150, and an amorphous silicon film 110' are sequentially formed on the carrier substrate 100a (for example, a glass substrate) as shown in FIG. 5a.
  • the carrier substrate 100a for example, a glass substrate
  • the gate electrode 140 is formed by a process of deposition, exposure, etching, or the like; then, for example, a silicon nitride layer and a silicon dioxide layer are deposited to form the gate insulating layer 150; then the amorphous silicon film 110' is deposited.
  • Step S02 performing a high temperature dehydrogenation process on the carrier substrate 100a that completes step S01, and then forming an active layer (ie, a channel region 113, a source region 111, and a drain region 112 to be formed) for the amorphous silicon film 110'.
  • the portion 110" is laser annealed to cause the portion 110" to form polysilicon, as shown in Figure 5b.
  • Step S03 sequentially depositing an amorphous silicon connection layer film 120' and a source/drain electrode layer film 130' on the carrier substrate 100a of step S02, and the amorphous silicon connection layer film 120' includes a first amorphous silicon to be formed which is sequentially deposited.
  • a film of a layer for example, undoped amorphous silicon, abbreviated as a-Si
  • a film to be formed with a second amorphous silicon layer for example, doped amorphous silicon, such as N-type doped amorphous silicon, referred to as n+a–Si 120b', as shown in Figure 5c.
  • Step S04 performing a half exposure process on the carrier substrate 100a of the step S03, and then performing etching to form the first amorphous silicon layer 120a and the second amorphous silicon layer 120b of the thin film transistor 100 as shown in FIG.
  • the source layer 110 and the source/drain electrode layer 130 are shown in FIG.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, comprising: forming a plurality of thin film transistors spaced apart from each other, the thin film transistors being fabricated by the fabrication method provided by any of the above embodiments.
  • the thin film transistor may be the thin film transistor 100 provided in any of the above embodiments.
  • the method provided by the embodiment of the present invention may further include: forming an insulating layer 102 covering the thin film transistor 100 and a via hole in the insulating layer 102 (not labeled in FIG. 6) And forming the pixel electrode 101 such that the pixel electrode 101 is electrically connected to the drain 132 of the thin film transistor 100 through a via hole in the insulating layer 102.
  • the manufacturing method provided by the embodiment of the present invention is applicable to various display modes, such as TN (Twisted Nematic), VA (Vertical Alignment), IPS (In-Plane Switch), or ADS (Advanced Super Dimension Switch) mode.
  • TN Transmission Nematic
  • VA Very Alignment
  • IPS In-Plane Switch
  • ADS Advanced Super Dimension Switch
  • the manufacturing method provided by the embodiment of the present invention further includes other steps.
  • a gate line and a common electrode line may also be formed in the process of the gate 140 of the transistor 100; for example, a data line may be formed in a process of forming the source 131 and the drain 132 of the thin film transistor 100; for example, a common electrode may also be formed
  • the common electrode is electrically connected to the common electrode line. I won't go into details here.
  • At least one embodiment of the present invention further provides a thin film transistor 200 including an active layer 210 and a source/drain electrode layer 230.
  • the active layer 210 has a channel region 213, and a source region 211 and a drain region 212 respectively connected to the channel region 213 and connected to the channel region 213.
  • the formation material of the channel region 213 includes polysilicon, a source region.
  • the forming material of the 211 and the drain region 212 includes doped amorphous silicon (for example, N-type doped amorphous silicon or P-type doped amorphous silicon); the source-drain electrode layer 230 is located at one side of the active layer 210 and includes each other The source 231 and the drain 232 are disposed at intervals, the source 231 is electrically connected to the source region 211, and the drain 232 is electrically connected to the drain region 212.
  • doped amorphous silicon for example, N-type doped amorphous silicon or P-type doped amorphous silicon
  • the source-drain electrode layer 230 is located at one side of the active layer 210 and includes each other
  • the source 231 and the drain 232 are disposed at intervals, the source 231 is electrically connected to the source region 211, and the drain 232 is electrically connected to the drain region 212.
  • the manufacturing method of the active layer 210 may include: forming an amorphous silicon film; performing laser annealing treatment on the position of the amorphous silicon film to form the channel region 213 to form polysilicon, and performing exposure, etching, etc. Removing the remaining amorphous silicon film; thereafter, forming a doped amorphous silicon film on the polysilicon channel region (for example, the doped amorphous silicon film can be formed directly by deposition), and performing exposure, etching, etc.
  • the source region 211 and the drain region 212 connected to the channel region 213 are formed, thereby forming the active layer 210.
  • the active layer 210 can also be formed in other ways.
  • the source region 211 and the drain region 212 of the active layer 210 are made of doped amorphous silicon material to achieve electrical connection with the source 131 and the drain 132, respectively. Therefore, the fabrication process of the thin film transistor 200 provided by the embodiment of the present invention can omit the ion implantation process for forming a light and heavily doped region and the corresponding exposure process, compared with a conventional process for fabricating a polysilicon (p-Si) thin film transistor. This makes the thin film transistor 200 simple in fabrication process, low in equipment investment, suitable for high generation lines and has good compatibility with amorphous silicon (a-Si) thin film transistor production lines.
  • a-Si amorphous silicon
  • the thin film transistor 200 provided by the embodiment of the present invention includes a channel region 213 of the active layer 210 made of a polysilicon material (for example, a low temperature polysilicon material), as the polysilicon material has The larger the electron mobility, the thin film transistor 200 provided by the embodiment of the present invention has a larger on-state current.
  • a polysilicon material for example, a low temperature polysilicon material
  • the thin film transistor 200 further includes a carrier substrate 200a, and in a direction perpendicular to the carrier substrate 200a, the channel region 213, the source region 211, and the source 131 may overlap at the same position, the channel region 213, and the drain Region 212 and drain 132 may also overlap at the same location. This can improve the electrical connectivity between the channel region, the source/drain regions, and the source/drain.
  • the thin film transistor 200 provided by the embodiment of the present invention may further include a carrier substrate 200a and a gate.
  • the electrode 240 has a structure such as a gate insulating layer 250 disposed between the gate electrode 240 and the active layer 210.
  • the thin film transistor and the manufacturing method thereof, the array substrate, the manufacturing method thereof and the display device provided by the embodiments of the present invention have at least one of the following advantages.
  • the source and drain regions of the active layer are electrically connected to the source and the drain respectively without ion implantation of the active layer of the thin film transistor, so that ion implantation can be omitted. Process and corresponding exposure process.
  • the channel region of the active layer included in the thin film transistor is made of polysilicon (for example, low temperature polysilicon) material, thereby ensuring high electron mobility.
  • the source region and the drain region of the active layer are both undoped regions, and then are respectively connected to the source and the drain through the amorphous silicon connection layer, thereby reducing the off state. Leakage current.
  • the local laser annealing treatment is performed on the amorphous silicon film to be formed into polycrystalline silicon, the annealing uniformity and the production cycle can be ensured, thereby facilitating the application of the manufacturing method provided by the embodiment of the present invention.
  • the high generation production line In the high generation production line.
  • the manufacturing method provided by the embodiment of the invention only increases the high temperature dehydrogenation and laser annealing treatment, so the equipment investment is small, the process is simple, and the production line of the amorphous silicon thin film transistor is used. Have better compatibility.
  • the thin film transistor and the method of fabricating the same, the array substrate, the method of fabricating the same, and the embodiment of the display device can be referred to each other. Further, the features of the embodiments and the embodiments of the present invention may be combined with each other without conflict.

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Abstract

一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置，薄膜晶体管（100）包括有源层（110）、非晶硅连接层（120）和源漏电极层（130）。有源层（110）具有沟道区（113）、源极区（111）和漏极区（112），沟道区（113）的形成材料包括多晶硅；非晶硅连接层（120）位于有源层（110）的一侧，并且包括彼此间隔设置的第一连接部（121）和第二连接部（122）；源漏电极层（130）包括彼此间隔设置的源极（131）和漏极（132），源极（131）通过第一连接部（121）与源极区（111）电连接，漏极（132）通过第二连接部（122）与漏极区（112）电连接。可以简化多晶硅薄膜晶体管的制作工艺。

Description

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置。
背景技术
多晶硅薄膜晶体管由于具有较高的电子迁移率和稳定性等优点，已经普遍应用于各种显示器中。
然而，多晶硅薄膜晶体管的制作步骤繁多，大约需要10道曝光工艺。以低温多晶硅薄膜晶体管为例，其制作过程包括：用于形成多晶硅的激光退火工艺，用于形成具有轻掺杂区、重掺杂区以及沟道区的有源层的两次离子注入工艺，以及脱氢、加氢和活化等高温工艺。这些复杂的工艺使得低温多晶硅薄膜晶体管通常在六代线或以下开发量产，并且良率较低、设备投资较大、以及与非晶硅薄膜晶体管的产线兼容性较差。
发明内容
本发明的至少一个实施例提供一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置，以简化多晶硅薄膜晶体管的制作工艺。
本发明的至少一个实施例提供一种薄膜晶体管，其包括：有源层、非晶硅连接层和源漏电极层。所述有源层具有沟道区、源极区和漏极区，所述沟道区的形成材料包括多晶硅；所述非晶硅连接层位于所述有源层的一侧，并且包括彼此间隔设置的第一连接部和第二连接部；所述源漏电极层包括彼此间隔设置的源极和漏极，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
例如，所述源极区和所述漏极区都为非掺杂区。
例如，所述源极区和所述漏极区的形成材料为非掺杂非晶硅或者非掺杂多晶硅。
例如，所述非晶硅连接层包括层叠设置的第一非晶硅层和第二非晶硅层，所述第二非晶硅层设置于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
例如，所述第一非晶硅层的形成材料为非掺杂非晶硅。
例如，所述薄膜晶体管还包括承载基板，并且在垂直于所述承载基板的方向上，所述有源层设置于所述承载基板和所述源漏电极层之间。
例如，所述源漏电极层的材料为金属材料。
例如，在从所述源极区到所述漏极区的方向上，所述有源层的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
例如，所述源极和所述漏极的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
例如，所述源极和所述漏极的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
例如，所述薄膜晶体管还包括承载基板和栅极，所述栅极设置于所述有源层与所述承载基板之间。
本发明的至少一个实施例还提供一种阵列基板，其包括多个彼此间隔设置的薄膜晶体管，所述薄膜晶体管为以上任一项所述的薄膜晶体管。
例如，所述阵列基板还包括多个彼此间隔设置的像素电极，所述多个像素电极分别对应所述多个薄膜晶体管，并且每个像素电极与对应的薄膜晶体管的漏极电连接。
本发明的至少一个实施例还提供一种显示装置，其包括上述任一项所述的阵列基板。
本发明的至少一个实施例还提供一种薄膜晶体管的制作方法，其包括：形成具有沟道区、源极区和漏极区的有源层，使所述沟道区的形成材料包括多晶硅；在所述有源层的一侧形成非晶硅连接层，使所述非晶硅连接层包括彼此间隔设置的第一连接部和第二连接部；以及在所述非晶硅连接层的远离所述有源层的一侧形成源漏电极层，使所述源漏电极层包括源极和漏极，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
例如，形成所述非晶硅连接层包括：形成层叠的第一非晶硅层和第二非晶硅层，使所述第二非晶硅层形成于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
例如，形成所述有源层包括：形成非晶硅薄膜；以及对所述非晶硅薄膜的待形成所述沟道区或者待形成所述沟道区、所述源极区和所述漏极区的部分进 行激光退火处理以使所述部分形成多晶硅。
例如，通过半曝光工艺形成所述有源层和所述非晶硅连接层；或者通过半曝光工艺形成所述有源层、所述非晶硅连接层和所述源漏电极层。
例如，形成层叠的非晶硅连接层薄膜和源漏电极层薄膜；对所述非晶硅连接层薄膜和所述源漏电极层薄膜进行一次曝光工艺以形成所述非晶硅连接层和所述源漏电极层。
本发明的至少一个实施例还提供一种阵列基板的制作方法，其包括：形成多个彼此间隔设置的薄膜晶体管，所述薄膜晶体管以上任一项所述的制作方法制作。
本发明的至少一个实施例还提供另一种薄膜晶体管，其包括有源层和源漏电极层。所述有源层具有沟道区、源极区和漏极区，所述沟道区的形成材料包括多晶硅，所述源极区和所述漏极区的形成材料包括掺杂非晶硅；所述源漏电极层位于所述有源层的一侧并且包括彼此间隔设置的源极和漏极，所述源极与所述源极区电连接，所述漏极与所述漏极区电连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的一种薄膜晶体管的剖视示意图；
图2为本发明实施例提供的另一种薄膜晶体管的剖视示意图；
图3为本发明实施例提供的一种阵列基板的剖视示意图；
图4为本发明实施例提供的一种制作薄膜晶体管的方法的流程图；
图5a至图5c为本发明实施例提供的制作如图2所示的薄膜晶体管的各步骤的剖视示意图；
图6为本发明实施例提供的一种制作阵列基板的绝缘层的剖视示意图；
图7为本发明实施例提供的一种薄膜晶体管的剖视示意图。
附图标记
10：阵列基板  100,200：薄膜晶体管  101：像素电极
102：绝缘层  110，210：有源层  100a,200a：承载基板
130,230：源漏电极层  111,211：源极区
112,212：漏极区  113,213：沟道区  120：非晶硅连接层
121：第一连接部  122：第二连接部  130：源漏电极层
131：源极  132：漏极  140，240：栅极
150：栅绝缘层  120a：第一非晶硅连接层
120b：第二非晶硅连接层  110'：非晶硅薄膜
120'：非晶硅连接层薄膜  130'：源漏电极层薄膜
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明实施例提供一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置。在本发明实施例中，薄膜晶体管的有源层具有采用多晶硅材料形成的沟道区，因而可以保证该薄膜晶体管具有较大的开态电流；此外，有源层的源极区和漏极区分别通过非晶硅材料与源极和漏极电连接或者都采用掺杂非晶硅材料制作以实现与源极和漏极的电连接，这样可以省去制作轻掺杂区和重掺杂区的两次离子注入工艺以及相应的曝光工艺。因此，本发明实施例可以在保证多晶硅薄膜晶体管具有较大开态电流的前提下简化多晶硅薄膜晶体管的制作工艺。
下面结合附图对本发明实施例提供的薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置进行详细说明。
如图1所示，本发明的至少一个实施例提供一种薄膜晶体管100，该薄膜晶体管100包括有源层110、非晶硅连接层120和源漏电极层130。有源层110具有沟道区113、以及分别位于沟道区113两侧且与沟道区113连接的源极区111和漏极区112，沟道区113的形成材料包括多晶硅，例如，源极区111和漏极区112的形成材料可以为多晶硅或非晶硅；非晶硅连接层120位于有源层110的一侧，并且包括彼此间隔设置的第一连接部121和第二连接部122；源漏电极层130包括彼此间隔设置的源极131和漏极132，源极131通过第一连接部121与源极区111电连接，漏极132通过第二连接部122与漏极区112电连接。
在本发明实施例提供的薄膜晶体管100中，有源层110的源极区111和漏极区112通过非晶硅连接层120分别与源极131和漏极132电连接。因而，与常见的制作多晶硅(p-Si)薄膜晶体管的工艺相比，本发明实施例提供的薄膜晶体管100的制作工艺可以省略形成轻、重掺杂区的离子注入工艺及相应的曝光工艺，这使得该薄膜晶体管100的制作工艺简单、设备投资较少、适用于高世代线并且与非晶硅(a-Si)薄膜晶体管的产线有较好的兼容性。再一方面，与常见的非晶硅薄膜晶体管相比，本发明实施例提供的薄膜晶体管100包括的有源层110的沟道区113采用多晶硅材料(例如低温多晶硅材料)制作，由于多晶硅材料具有较大的电子迁移率，因而本发明实施例提供的薄膜晶体管100具有较大的开态电流。
例如，有源层110的源极区111和漏极区112可以都为非掺杂区，例如，源极区111和漏极区112的形成材料都可以为非掺杂非晶硅或者非掺杂多晶硅。源极区111和漏极区112通过非晶硅连接层120分别与源极131和漏极132电连接并且都为非掺杂区，有利于使本发明实施例提供的薄膜晶体管100具有较低的关态漏电流，尤其是在源极区111和漏极区112都为非掺杂非晶硅的情况下，与常见的包括轻、重掺杂区的多晶硅薄膜晶体管相比，本发明实施例中的薄膜晶体管100具有更低的关态漏电流。
为了实现源极区111和漏极区112分别与源极131和漏极132电连接，例如，在源极区111和漏极区112的形成材料都为非掺杂非晶硅或者非掺杂多晶硅的情况下，非晶硅连接层120的第一连接部121和第二连接部122的形成材料可以为掺杂非晶硅，例如P型掺杂非晶硅或N型掺杂非晶硅。
例如，为了提高源极区111和漏极区112与源极131和漏极132之间的电连接性，源漏电极层130的材料可以为金属材料。
例如，如图1所示，本发明的至少一个实施例提供的薄膜晶体管100还包括承载基板100a，并且在垂直于承载基板100a的方向上，有源层110可以设置于承载基板100a和源漏电极层130之间。这样设置，可以使薄膜晶体管100的制作工艺更加简单。
通常的多晶硅薄膜晶体管为顶栅结构，这样可以在制作过程中以栅极为掩膜对有源层进行离子注入掺杂。由于本发明实施例提供的薄膜晶体管100的制作过程可以省略离子注入掺杂过程，因此，例如，本发明的至少一个实施例提供的薄膜晶体管100可以为底栅结构，即该薄膜晶体管100还包括栅极140，栅极140与有源层110之间设置有栅绝缘层150，并且栅极140设置于有源层110与承载基板100a之间。当然，在一些实施例中，薄膜晶体管100也可以采用顶栅结构。
在本发明的至少一个实施例中，为了简化薄膜晶体管100的制作工艺，可以通过同一次曝光工艺制作该薄膜晶体管100包括的多层薄膜。
例如，在从源极区111到漏极区112的方向上，有源层110的外边缘110a、110b之间的距离可以大致等于第一连接部121和第二连接部122的外边缘121a、122a之间的距离。这样，有源层110与非晶硅连接层120可以通过一次曝光工艺(例如半曝光工艺)形成，以减少曝光工艺的次数。在此基础上，例如，源极131和漏极132的外边缘131a、132a之间的距离可以大致等于第一连接部121和第二连接部122的外边缘121a、122a之间的距离。这样，源漏电极层130、有源层110与非晶硅连接层120可以通过一次曝光工艺(例如半曝光工艺)形成，以进一步减少曝光工艺的次数。
例如，源极131和漏极132的外边缘131a、132a之间的距离可以大致等于第一连接部121和第二连接部122的外边缘121a、122a之间的距离。这样，源漏电极层130与非晶硅连接层120可以通过一次曝光工艺(例如半曝光工艺)形成，以减少曝光工艺的次数。
图1以非晶硅连接层120为单层结构为例进行说明，当然，非晶硅连接层120也可以为多层结构。
例如，如图2所示，在本发明的至少一个实施例提供的薄膜晶体管100中，非晶硅连接层120包括层叠设置的第一非晶硅层120a和第二非晶硅层120b， 第二非晶硅层120b设置于第一非晶硅层120a和源漏电极层130之间，且第二非晶硅层120b的电导率大于第一非晶硅层120a的电导率。在这种情况下，第二非晶硅层120b可以起到欧姆接触层的作用，以提高第一非晶硅连接层120a与源漏电极层130之间的电连接性。
例如，第二非晶硅层120b可以为N型掺杂非晶硅或P型掺杂非晶硅。
例如，第一非晶硅层可以为非掺杂非晶硅。由于非晶硅连接层120包括采用非掺杂非晶硅制作的第一非晶硅层120a，因而更有利于降低薄膜晶体管100的关态漏电流。
例如，在图2所示的实施方式中，源极区111和漏极区112的形成材料可以都为非掺杂的多晶硅。与常见的包括轻、重掺杂区的多晶硅薄膜晶体管相比，这样可以使薄膜晶体管100具有较低的关态漏电流。
如图3所示，本发明的至少一个实施例还提供一种阵列基板10，其包括多个彼此间隔设置的如上述任一实施例所述的薄膜晶体管100。图3中仅示出了一个薄膜晶体管100，并且该薄膜晶体管100中的非晶硅连接层120为两层结构。当然，本发明实施例提供的阵列基板包括但不限于图3所示的实施方式。
例如，本发明的至少一个实施例提供的阵列基板10还可以包括多个彼此间隔设置的像素电极101，该多个像素电极101分别对应上述多个薄膜晶体管100，并且每个像素电极101与对应的薄膜晶体管100的漏极132电连接。例如，阵列基板10还可以包括覆盖薄膜晶体管100的绝缘层102，像素电极101可以通过绝缘层102中的过孔与对应的薄膜晶体管100的漏极132电连接。
例如，像素电极101可以采用ITO(氧化铟锡)、IZO(氧化铟锌)或类似透明导电材料制作。这里不做限定。
本发明实施例提供的阵列基板可以为OLED(有机发光二极管)阵列基板，也可以为用于液晶显示装置的阵列基板。此外，该阵列基板10还可以包括例如公共电极线、栅线、数据线等结构，这里不再赘述。
本发明的至少一个实施例还提供一种显示装置，其包括以上任一实施例提供的阵列基板10。
例如，该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
如图4所示，本发明的至少一个实施例还提供一种薄膜晶体管的制作方法， 其包括：步骤S1，形成具有沟道区、源极区和漏极区的有源层，使沟道区的形成材料包括多晶硅；步骤S2，在有源层的一侧形成非晶硅连接层120，使非晶硅连接层包括彼此间隔设置的第一连接部和第二连接部；以及步骤S3，在非晶硅连接层的远离有源层的一侧形成源漏电极层，使该源漏电极层包括源极和漏极，源极通过第一连接部与源极区电连接，漏极通过第二连接部与漏极区电连接。
例如，在上述步骤S1中，形成有源层可以包括：形成非晶硅薄膜；以及对该非晶硅薄膜的待形成沟道区或者待形成沟道区、源极区和漏极区的部分进行激光退火处理以使该部分形成多晶硅。本发明实施例通过对非晶硅薄膜进行局部激光退火处理以形成多晶硅，与目前常用的对整个非晶硅薄膜进行激光退火处理的方式相比，有利于使本发明实施例提供的制作方法用于高世代产线。
本发明实施例提供的制作方法中的步骤S1至步骤S3的顺序不限。
例如，可以通过半曝光工艺形成有源层和非晶硅连接层，即步骤S1和步骤S2可以同步进行；或者，可以通过半曝光工艺形成有源层、非晶硅连接层和源漏电极层，即步骤S1至步骤S3可以同步进行。半曝光工艺是指利用半色调掩膜板或灰色调掩膜板对薄膜上的光刻胶进行曝光处理，之后进行显影和刻蚀处理以形成需要的图形的工艺。
例如，可以形成层叠的非晶硅连接层薄膜(即待形成非晶硅连接层的薄膜)和源漏电极层薄膜(即待形成源漏电极层的薄膜)；之后，对非晶硅连接层薄膜和源漏电极层薄膜进行一次曝光工艺以形成非晶硅连接层和源漏电极层。也就是说，步骤S2和步骤S3可以同步制作。
当然，步骤S1至步骤S3的顺序包括但不限于所列举的这些顺序。
本发明实施例提供的方法可以用于制作上述任一实施例提供的薄膜晶体管100。
例如，对于如图2所示的薄膜晶体管100，在本发明的至少一个实施例提供的制作方法中，形成非晶硅连接层120可以包括：形成层叠的第一非晶硅层120a和第二非晶硅层120b，使第二非晶硅层120b形成于第一非晶硅层120a和源漏电极层130之间，且第二非晶硅层120b的电导率大于第一非晶硅层120a的电导率。这样可以提高第一非晶硅连接层120a与源漏电极层130之间的电连接性。
例如，第二非晶硅层120b可以为N型掺杂非晶硅或P型掺杂非晶硅；例 如，第一非晶硅层可以为非掺杂非晶硅。
下面以图2所示的薄膜晶体管100为例，对本发明实施例提供的制作方法进行详细说明。例如，如图5a至图5c所示，该方法可以包括以下步骤S01至步骤S04。
步骤S01：依次在承载基板100a(例如玻璃基板)上形成栅极140、栅绝缘层150和非晶硅薄膜110'，如图5a所示。
例如，通过沉积、曝光、刻蚀等过程形成栅极140；然后沉积例如氮化硅层和二氧化硅层以形成栅绝缘层150；之后再沉积非晶硅薄膜110'。
步骤S02：对完成步骤S01的承载基板100a进行高温脱氢工艺，然后针对非晶硅薄膜110'的待形成有源层(即待形成沟道区113、源极区111和漏极区112)的部分110”进行激光退火处理，以使该部分110”形成多晶硅，如图5b所示。
步骤S03：在完成步骤S02的承载基板100a上依次沉积非晶硅连接层薄膜120'和源漏电极层薄膜130'，非晶硅连接层薄膜120'包括依次沉积的待形成第一非晶硅层的薄膜(例如非掺杂非晶硅，简称为a-Si)120a'、待形成第二非晶硅层的薄膜(例如掺杂非晶硅，例如N型掺杂非晶硅，简称为n+a–Si)120b'，如图5c所示。
步骤S04：对完成步骤S03的承载基板100a进行半曝光工艺，然后进行刻蚀，以形成如图2所示的薄膜晶体管100的第一非晶硅层120a、第二非晶硅层120b、有源层110以及源漏电极层130。
本发明的至少一个实施例还提供一种阵列基板的制作方法，其包括：形成多个彼此间隔设置的薄膜晶体管，该薄膜晶体管采用上述任一实施例提供的制作方法制作。例如，该薄膜晶体管可以上述任一实施例提供的薄膜晶体管100。
例如，在制作完薄膜晶体管之后，如图6所示，本发明实施例提供的方法还可以包括：形成覆盖薄膜晶体管100的绝缘层102以及位于绝缘层102中的过孔(图6中未标出)；以及形成像素电极101，使该像素电极101通过绝缘层102中的过孔与薄膜晶体管100的漏极132电连接。
本发明实施例提供的制作方法适用于各种显示模式，比如TN(Twisted Nematic)、VA(Vertical Alignment)、IPS(In-Plane Switch)或ADS(Advanced Super Dimension Switch)模式。
当然，本发明实施例提供的制作方法还包括其它步骤。例如，在形成薄膜 晶体管100的栅极140的工艺中还可以形成栅线和公共电极线；例如，在形成薄膜晶体管100的源极131和漏极132的工艺中还可以形成数据线；例如，还可以形成公共电极，使该公共电极与公共电极线电连接。这里不做赘述。
如图7所示，本发明的至少一个实施例还提供一种薄膜晶体管200，其包括有源层210和源漏电极层230。有源层210具有沟道区213、以及分别位于沟道区213两侧且与沟道区213连接的源极区211和漏极区212，沟道区213的形成材料包括多晶硅，源极区211和漏极区212的形成材料包括掺杂非晶硅(例如N型掺杂非晶硅或P型掺杂非晶硅)；源漏电极层230位于有源层210的一侧并且包括彼此间隔设置的源极231和漏极232，源极231与源极区211电连接，漏极232与漏极区212电连接。
例如，有源层210的制作方法可以包括：形成非晶硅薄膜；对该非晶硅薄膜的待形成沟道区213的位置进行激光退火处理以形成多晶硅，并且进行曝光、刻蚀等处理以去除其余的非晶硅薄膜；之后，在多晶硅沟道区上形成掺杂非晶硅薄膜(例如可以直接通过沉积方式形成该掺杂非晶硅薄膜)，并对其进行曝光、刻蚀等处理以形成与沟道区213连接的源极区211和漏极区212，由此形成有源层210。当然，也可以采用其它方式制作有源层210。
在本发明实施例提供的薄膜晶体管200中，有源层210的源极区211和漏极区212采用掺杂非晶硅材料制作以实现分别与源极131和漏极132的电连接。因而，与常见的制作多晶硅(p-Si)薄膜晶体管的工艺相比，本发明实施例提供的薄膜晶体管200的制作工艺可以省略形成轻、重掺杂区的离子注入工艺及相应的曝光工艺，这使得该薄膜晶体管200的制作工艺简单、设备投资较少、适用于高世代线并且与非晶硅(a-Si)薄膜晶体管的产线有较好的兼容性。再一方面，与常见的非晶硅薄膜晶体管相比，本发明实施例提供的薄膜晶体管200包括的有源层210的沟道区213采用多晶硅材料(例如低温多晶硅材料)制作，由于多晶硅材料具有较大的电子迁移率，因而本发明实施例提供的薄膜晶体管200具有较大的开态电流。
例如，薄膜晶体管200还包括承载基板200a，并且在垂直于承载基板200a的方向上，沟道区213、源极区211和源极131可以在同一位置处交叠，沟道区213、漏极区212和漏极132也可以在同一位置处交叠。这样可以提高沟道区、源/漏极区和源/漏极之间的电连接性。
当然，本发明实施例提供的薄膜晶体管200还可以包括承载基板200a、栅 极240以及设置于栅极240和有源层210之间的栅绝缘层250等结构。
综上所述，本发明实施例提供的薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置至少具有如下优点之一。
1、本发明实施例中，不需要对薄膜晶体管的有源层进行离子注入即可实现有源层的源极区和漏极区分别与源极和漏极的电连接，从而可以省略离子注入工艺及相应的曝光工艺。
2、在本发明实施例中，薄膜晶体管包括的有源层的沟道区采用多晶硅(例如低温多晶硅)材料制作，因而可以保证较高的电子迁移率。
3、在本发明的一些实施例中，有源层的源极区和漏极区都为非掺杂区，之后通过非晶硅连接层分别与源极和漏极连接，因而可以降低关态漏电流。
4、在本发明实施例提供的制作方法中，通过对待形成多晶硅的非晶硅薄膜进行局部激光退火处理，可以保证退火均一性和生产节拍，从而有利于使本发明实施例提供的制作方法适用于高世代产线。
5、与非晶硅薄膜晶体管的制作工艺相比，本发明实施例提供的制作方法只增加了高温脱氢和激光退火处理，因而设备投资少、工艺简单、与非晶硅薄膜晶体管的产线有较好的兼容性。
上述薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置的实施例可以互相参照。此外，在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年5月11日递交的中国专利申请第201610311349.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种薄膜晶体管，包括：
    有源层，具有沟道区、源极区和漏极区，其中，所述沟道区的形成材料包括多晶硅；
    非晶硅连接层，位于所述有源层的一侧，并且包括彼此间隔设置的第一连接部和第二连接部；以及
    源漏电极层，包括彼此间隔设置的源极和漏极，其中，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述源极区和所述漏极区都为非掺杂区。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述源极区和所述漏极区的形成材料为非掺杂非晶硅或者非掺杂多晶硅。
  4. 根据权利要求1至3中任一项所述的薄膜晶体管，其中，所述非晶硅连接层包括层叠设置的第一非晶硅层和第二非晶硅层，所述第二非晶硅层设置于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述第一非晶硅层的形成材料为非掺杂非晶硅。
  6. 根据权利要求1至5中任一项所述的薄膜晶体管，还包括承载基板，其中，在垂直于所述承载基板的方向上，所述有源层设置于所述承载基板和所述源漏电极层之间。
  7. 根据权利要求1至5中任一项所述的薄膜晶体管，其中，所述源漏电极层的材料为金属材料。
  8. 根据权利要求1至5中任一项所述的薄膜晶体管，其中，在从所述源极区到所述漏极区的方向上，所述有源层的外边缘之间的距离大致等于所述第一连接部和所述第二连接部的外边缘之间的距离。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述源极和所述漏极的外边缘之间的距离大致等于所述第一连接部和所述第二连接部的外边缘之间的距离。
  10. 根据权利要求1至5中任一项所述的薄膜晶体管，其中，所述源极和所述漏极的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
  11. 根据权利要求1至5中任一项所述的薄膜晶体管，还包括承载基板和栅极，其中，所述栅极设置于所述有源层与所述承载基板之间。
  12. 一种阵列基板，包括多个彼此间隔设置的薄膜晶体管，其中，所述薄膜晶体管为权利要求1至11中任一项所述的薄膜晶体管。
  13. 根据权利要求12所述的阵列基板，还包括多个彼此间隔设置的像素电极，
    其中，所述多个像素电极分别对应所述多个薄膜晶体管，并且每个像素电极与对应的薄膜晶体管的漏极电连接。
  14. 一种显示装置，包括根据权利要求12或13所述的阵列基板。
  15. 一种薄膜晶体管的制作方法，包括：
    形成具有沟道区、源极区和漏极区的有源层，其中，所述沟道区的形成材料包括多晶硅；
    在所述有源层的一侧形成非晶硅连接层，其中，所述非晶硅连接层包括彼此间隔设置的第一连接部和第二连接部；以及
    在所述非晶硅连接层的远离所述有源层的一侧形成源漏电极层，其中，所述源漏电极层包括源极和漏极，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
  16. 根据权利要求15所述的制作方法，其中，形成所述非晶硅连接层包括：形成层叠的第一非晶硅层和第二非晶硅层，其中，所述第二非晶硅层形成于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
  17. 根据权利要求15所述的制作方法，其中，形成所述有源层包括：
    形成非晶硅薄膜；以及
    对所述非晶硅薄膜的待形成所述沟道区或者待形成所述沟道区、所述源极区和所述漏极区的部分进行激光退火处理以使所述部分形成多晶硅。
  18. 根据权利要求15至17中任一项所述的制作方法，其中，
    通过半曝光工艺形成所述有源层和所述非晶硅连接层；或者
    通过半曝光工艺形成所述有源层、所述非晶硅连接层和所述源漏电极层。
  19. 根据权利要求15至17中任一项所述的制作方法，其中，
    形成层叠的非晶硅连接层薄膜和源漏电极层薄膜；
    对所述非晶硅连接层薄膜和所述源漏电极层薄膜进行一次曝光工艺以形成所述非晶硅连接层和所述源漏电极层。
  20. 一种阵列基板的制作方法，包括：
    形成多个彼此间隔设置的薄膜晶体管，其中，所述薄膜晶体管采用权利要求15至19中任一项所述的制作方法制作。
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US10403756B2 (en) 2019-09-03
CN105870198A (zh) 2016-08-17
EP3457441B1 (en) 2022-04-20

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