CN105870198A - 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 - Google Patents

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 Download PDF

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CN105870198A
CN105870198A CN201610311349.6A CN201610311349A CN105870198A CN 105870198 A CN105870198 A CN 105870198A CN 201610311349 A CN201610311349 A CN 201610311349A CN 105870198 A CN105870198 A CN 105870198A
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thin film
film transistor
tft
layer
source
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CN105870198B (zh
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白金超
郭会斌
李升玄
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/558,104 priority patent/US10403756B2/en
Priority to PCT/CN2017/074772 priority patent/WO2017193667A1/zh
Priority to EP17761424.5A priority patent/EP3457441B1/en
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Abstract

一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置，所述薄膜晶体管包括有源层、非晶硅连接层和源漏电极层。所述有源层具有沟道区、源极区和漏极区，所述沟道区的形成材料包括多晶硅；所述非晶硅连接层位于所述有源层的一侧，并且包括彼此间隔设置的第一连接部和第二连接部；所述源漏电极层包括彼此间隔设置的源极和漏极，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。本公开可以简化多晶硅薄膜晶体管的制作工艺。

Description

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
技术领域
本发明的实施例涉及一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置。
背景技术
多晶硅薄膜晶体管由于具有较高的电子迁移率和稳定性等优点，已经普遍应用于各种显示器中。
然而，多晶硅薄膜晶体管的制作步骤繁多，大约需要10道曝光工艺。以低温多晶硅薄膜晶体管为例，其制作过程包括：用于形成多晶硅的激光退火工艺，用于形成具有轻掺杂区、重掺杂区以及沟道区的有源层的两次离子注入工艺，以及脱氢、加氢和活化等高温工艺。这些复杂的工艺使得低温多晶硅薄膜晶体管通常在六代线或以下开发量产，并且良率较低、设备投资较大、以及与非晶硅薄膜晶体管的产线兼容性较差。
发明内容
本发明的至少一个实施例提供一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置，以简化多晶硅薄膜晶体管的制作工艺。
本发明的至少一个实施例提供一种薄膜晶体管，其包括：有源层、非晶硅连接层和源漏电极层。所述有源层具有沟道区、源极区和漏极区，所述沟道区的形成材料包括多晶硅；所述非晶硅连接层位于所述有源层的一侧，并且包括彼此间隔设置的第一连接部和第二连接部；所述源漏电极层包括彼此间隔设置的源极和漏极，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
例如，所述源极区和所述漏极区都为非掺杂区。
例如，所述源极区和所述漏极区的形成材料为非掺杂非晶硅或者非掺杂多晶硅。
例如，所述非晶硅连接层包括层叠设置的第一非晶硅层和第二非晶硅层，所述第二非晶硅层设置于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
例如，所述第一非晶硅层的形成材料为非掺杂非晶硅。
例如，所述薄膜晶体管还包括承载基板，并且在垂直于所述承载基板的方向上，所述有源层设置于所述承载基板和所述源漏电极层之间。
例如，所述源漏电极层的材料为金属材料。
例如，在从所述源极区到所述漏极区的方向上，所述有源层的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
例如，所述源极和所述漏极的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
例如，所述源极和所述漏极的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
例如，所述薄膜晶体管还包括承载基板和栅极，所述栅极设置于所述有源层与所述承载基板之间。
本发明的至少一个实施例还提供一种阵列基板，其包括多个彼此间隔设置的薄膜晶体管，所述薄膜晶体管为以上任一项所述的薄膜晶体管。
例如，所述阵列基板还包括多个彼此间隔设置的像素电极，所述多个像素电极分别对应所述多个薄膜晶体管，并且每个像素电极与对应的薄膜晶体管的漏极电连接。
本发明的至少一个实施例还提供一种显示装置，其包括上述任一项所述的阵列基板。
本发明的至少一个实施例还提供一种薄膜晶体管的制作方法，其包括：形成具有沟道区、源极区和漏极区的有源层，使所述沟道区的形成材料包括多晶硅；在所述有源层的一侧形成非晶硅连接层，使所述非晶硅连接层包括彼此间隔设置的第一连接部和第二连接部；以及在所述非晶硅连接层的远离所述有源层的一侧形成源漏电极层，使所述源漏电极层包括源极和漏极，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
例如，形成所述非晶硅连接层包括：形成层叠的第一非晶硅层和第二非晶硅层，使所述第二非晶硅层形成于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
例如，形成所述有源层包括：形成非晶硅薄膜；以及对所述非晶硅薄膜的待形成所述沟道区或者待形成所述沟道区、所述源极区和所述漏极区的部分进行激光退火处理以使所述部分形成多晶硅。
例如，通过半曝光工艺形成所述有源层和所述非晶硅连接层；或者通过半曝光工艺形成所述有源层、所述非晶硅连接层和所述源漏电极层。
例如，形成层叠的非晶硅连接层薄膜和源漏电极层薄膜；对所述非晶硅连接层薄膜和所述源漏电极层薄膜进行一次曝光工艺以形成所述非晶硅连接层和所述源漏电极层。
本发明的至少一个实施例还提供一种阵列基板的制作方法，其包括：形成多个彼此间隔设置的薄膜晶体管，所述薄膜晶体管以上任一项所述的制作方法制作。
本发明的至少一个实施例还提供另一种薄膜晶体管，其包括有源层和源漏电极层。所述有源层具有沟道区、源极区和漏极区，所述沟道区的形成材料包括多晶硅，所述源极区和所述漏极区的形成材料包括掺杂非晶硅；所述源漏电极层位于所述有源层的一侧并且包括彼此间隔设置的源极和漏极，所述源极与所述源极区电连接，所述漏极与所述漏极区电连接。
在本发明实施例中，薄膜晶体管的有源层具有采用多晶硅材料形成的沟道区，因而可以保证该薄膜晶体管具有较大的开态电流；此外，有源层的源极区和漏极区分别通过非晶硅材料与源极和漏极电连接或者都采用掺杂非晶硅材料制作以实现与源极和漏极的电连接，这样可以省去制作轻掺杂区和重掺杂区的两次离子注入工艺以及相应的曝光工艺。因此，本发明实施例可以在保证多晶硅薄膜晶体管具有较大开态电流的前提下简化多晶硅薄膜晶体管的制作工艺。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的一种薄膜晶体管的剖视示意图；
图2为本发明实施例提供的另一种薄膜晶体管的剖视示意图；
图3为本发明实施例提供的一种阵列基板的剖视示意图；
图4为本发明实施例提供的一种制作薄膜晶体管的方法的流程图；
图5a至图5c为本发明实施例提供的制作如图2所示的薄膜晶体管的各步骤的剖视示意图；
图6为本发明实施例提供的一种制作阵列基板的绝缘层的剖视示意图；
图7为本发明实施例提供的一种薄膜晶体管的剖视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明实施例提供一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置。在本发明实施例中，薄膜晶体管的有源层具有采用多晶硅材料形成的沟道区，因而可以保证该薄膜晶体管具有较大的开态电流；此外，有源层的源极区和漏极区分别通过非晶硅材料与源极和漏极电连接或者都采用掺杂非晶硅材料制作以实现与源极和漏极的电连接，这样可以省去制作轻掺杂区和重掺杂区的两次离子注入工艺以及相应的曝光工艺。因此，本发明实施例可以在保证多晶硅薄膜晶体管具有较大开态电流的前提下简化多晶硅薄膜晶体管的制作工艺。
下面结合附图对本发明实施例进行详细说明。
如图1所示，本发明的至少一个实施例提供一种薄膜晶体管100，该薄膜晶体管100包括有源层110、非晶硅连接层120和源漏电极层130。有源层110具有沟道区113、以及分别位于沟道区113两侧且与沟道区113连接的源极区111和漏极区112，沟道区113的形成材料包括多晶硅，例如，源极区111和漏极区112的形成材料可以为多晶硅或非晶硅；非晶硅连接层120位于有源层110的一侧，并且包括彼此间隔设置的第一连接部121和第二连接部122；源漏电极层130包括彼此间隔设置的源极131和漏极132，源极131通过第一连接部121与源极区111电连接，漏极132通过第二连接部122与漏极区112电连接。
在本发明实施例提供的薄膜晶体管100中，有源层110的源极区111和漏极区112通过非晶硅连接层120分别与源极131和漏极132电连接。因而，与常见的制作多晶硅(p-Si)薄膜晶体管的工艺相比，本发明实施例提供的薄膜晶体管100的制作工艺可以省略形成轻、重掺杂区的离子注入工艺及相应的曝光工艺，这使得该薄膜晶体管100的制作工艺简单、设备投资较少、适用于高世代线并且与非晶硅(a-Si)薄膜晶体管的产线有较好的兼容性。再一方面，与常见的非晶硅薄膜晶体管相比，本发明实施例提供的薄膜晶体管100包括的有源层110的沟道区113采用多晶硅材料(例如低温多晶硅材料)制作，由于多晶硅材料具有较大的电子迁移率，因而本发明实施例提供的薄膜晶体管100具有较大的开态电流。
例如，有源层110的源极区111和漏极区112可以都为非掺杂区，例如，源极区111和漏极区112的形成材料都可以为非掺杂非晶硅或者非掺杂多晶硅。源极区111和漏极区112通过非晶硅连接层120分别与源极131和漏极132电连接并且都为非掺杂区，有利于使本发明实施例提供的薄膜晶体管100具有较低的关态漏电流，尤其是在源极区111和漏极区112都为非掺杂非晶硅的情况下，与常见的包括轻、重掺杂区的多晶硅薄膜晶体管相比，本发明实施例中的薄膜晶体管100具有更低的关态漏电流。
为了实现源极区111和漏极区112分别与源极131和漏极132电连接，例如，在源极区111和漏极区112的形成材料都为非掺杂非晶硅或者非掺杂多晶硅的情况下，非晶硅连接层120的第一连接部121和第二连接部122的形成材料可以为掺杂非晶硅，例如P型掺杂非晶硅或N型掺杂非晶硅。
例如，为了提高源极区111和漏极区112与源极131和漏极132之间的电连接性，源漏电极层130的材料可以为金属材料。
例如，如图1所示，本发明的至少一个实施例提供的薄膜晶体管100还包括承载基板100a，并且在垂直于承载基板100a的方向上，有源层110可以设置于承载基板100a和源漏电极层130之间。这样设置，可以使薄膜晶体管100的制作工艺更加简单。
通常的多晶硅薄膜晶体管为顶栅结构，这样可以在制作过程中以栅极为掩膜对有源层进行离子注入掺杂。由于本发明实施例提供的薄膜晶体管100的制作过程可以省略离子注入掺杂过程，因此，例如，本发明的至少一个实施例提供的薄膜晶体管100可以为底栅结构，即该薄膜晶体管100还包括栅极140，栅极140与有源层110之间设置有栅绝缘层150，并且栅极140设置于有源层110与承载基板100a之间。当然，在一些实施例中，薄膜晶体管100也可以采用顶栅结构。
在本发明的至少一个实施例中，为了简化薄膜晶体管100的制作工艺，可以通过同一次曝光工艺制作该薄膜晶体管100包括的多层薄膜。
例如，在从源极区111到漏极区112的方向上，有源层110的外边缘110a、110b之间的距离可以大致等于第一连接部121和第二连接部122的外边缘121a、122a之间的距离。这样，有源层110与非晶硅连接层120可以通过一次曝光工艺(例如半曝光工艺)形成，以减少曝光工艺的次数。在此基础上，例如，源极131和漏极132的外边缘131a、132a之间的距离可以大致等于第一连接部121和第二连接部122的外边缘121a、122a之间的距离。这样，源漏电极层130、有源层110与非晶硅连接层120可以通过一次曝光工艺(例如半曝光工艺)形成，以进一步减少曝光工艺的次数。
例如，源极131和漏极132的外边缘131a、132a之间的距离可以大致等于第一连接部121和第二连接部122的外边缘121a、122a之间的距离。这样，源漏电极层130与非晶硅连接层120可以通过一次曝光工艺(例如半曝光工艺)形成，以减少曝光工艺的次数。
图1以非晶硅连接层120为单层结构为例进行说明，当然，非晶硅连接层120也可以为多层结构。
例如，如图2所示，在本发明的至少一个实施例提供的薄膜晶体管100中，非晶硅连接层120包括层叠设置的第一非晶硅层120a和第二非晶硅层120b，第二非晶硅层120b设置于第一非晶硅层120a和源漏电极层130之间，且第二非晶硅层120b的电导率大于第一非晶硅层120a的电导率。在这种情况下，第二非晶硅层120b可以起到欧姆接触层的作用，以提高第一非晶硅连接层120a与源漏电极层130之间的电连接性。
例如，第二非晶硅层120b可以为N型掺杂非晶硅或P型掺杂非晶硅。
例如，第一非晶硅层可以为非掺杂非晶硅。由于非晶硅连接层120包括采用非掺杂非晶硅制作的第一非晶硅层120a，因而更有利于降低薄膜晶体管100的关态漏电流。
例如，在图2所示的实施方式中，源极区111和漏极区112的形成材料可以都为非掺杂的多晶硅。与常见的包括轻、重掺杂区的多晶硅薄膜晶体管相比，这样可以使薄膜晶体管100具有较低的关态漏电流。
如图3所示，本发明的至少一个实施例还提供一种阵列基板10，其包括多个彼此间隔设置的如上述任一实施例所述的薄膜晶体管100。图3中仅示出了一个薄膜晶体管100，并且该薄膜晶体管100中的非晶硅连接层120为两层结构。当然，本发明实施例提供的阵列基板包括但不限于图3所示的实施方式。
例如，本发明的至少一个实施例提供的阵列基板10还可以包括多个彼此间隔设置的像素电极101，该多个像素电极101分别对应上述多个薄膜晶体管100，并且每个像素电极101与对应的薄膜晶体管100的漏极132电连接。例如，阵列基板10还可以包括覆盖薄膜晶体管100的绝缘层102，像素电极101可以通过绝缘层102中的过孔与对应的薄膜晶体管100的漏极132电连接。
例如，像素电极101可以采用ITO(氧化铟锡)、IZO(氧化铟锌)或类似透明导电材料制作。这里不做限定。
本发明实施例提供的阵列基板可以为OLED(有机发光二极管)阵列基板，也可以为用于液晶显示装置的阵列基板。此外，该阵列基板10还可以包括例如公共电极线、栅线、数据线等结构，这里不再赘述。
本发明的至少一个实施例还提供一种显示装置，其包括以上任一实施例提供的阵列基板10。
例如，该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
如图4所示，本发明的至少一个实施例还提供一种薄膜晶体管的制作方法，其包括：步骤S1，形成具有沟道区、源极区和漏极区的有源层，使沟道区的形成材料包括多晶硅；步骤S2，在有源层的一侧形成非晶硅连接层120，使非晶硅连接层包括彼此间隔设置的第一连接部和第二连接部；以及步骤S3，在非晶硅连接层的远离有源层的一侧形成源漏电极层，使该源漏电极层包括源极和漏极，源极通过第一连接部与源极区电连接，漏极通过第二连接部与漏极区电连接。
例如，在上述步骤S1中，形成有源层可以包括：形成非晶硅薄膜；以及对该非晶硅薄膜的待形成沟道区或者待形成沟道区、源极区和漏极区的部分进行激光退火处理以使该部分形成多晶硅。本发明实施例通过对非晶硅薄膜进行局部激光退火处理以形成多晶硅，与目前常用的对整个非晶硅薄膜进行激光退火处理的方式相比，有利于使本发明实施例提供的制作方法用于高世代产线。
本发明实施例提供的制作方法中的步骤S1至步骤S3的顺序不限。
例如，可以通过半曝光工艺形成有源层和非晶硅连接层，即步骤S1和步骤S2可以同步进行；或者，可以通过半曝光工艺形成有源层、非晶硅连接层和源漏电极层，即步骤S1至步骤S3可以同步进行。半曝光工艺是指利用半色调掩膜板或灰色调掩膜板对薄膜上的光刻胶进行曝光处理，之后进行显影和刻蚀处理以形成需要的图形的工艺。
例如，可以形成层叠的非晶硅连接层薄膜(即待形成非晶硅连接层的薄膜)和源漏电极层薄膜(即待形成源漏电极层的薄膜)；之后，对非晶硅连接层薄膜和源漏电极层薄膜进行一次曝光工艺以形成非晶硅连接层和源漏电极层。也就是说，步骤S2和步骤S3可以同步制作。
当然，步骤S1至步骤S3的顺序包括但不限于所列举的这些顺序。
本发明实施例提供的方法可以用于制作上述任一实施例提供的薄膜晶体管100。
例如，对于如图2所示的薄膜晶体管100，在本发明的至少一个实施例提供的制作方法中，形成非晶硅连接层120可以包括：形成层叠的第一非晶硅层120a和第二非晶硅层120b，使第二非晶硅层120b形成于第一非晶硅层120a和源漏电极层130之间，且第二非晶硅层120b的电导率大于第一非晶硅层120a的电导率。这样可以提高第一非晶硅连接层120a与源漏电极层130之间的电连接性。
例如，第二非晶硅层120b可以为N型掺杂非晶硅或P型掺杂非晶硅；例如，第一非晶硅层可以为非掺杂非晶硅。
下面以图2所示的薄膜晶体管100为例，对本发明实施例提供的制作方法进行详细说明。例如，如图5a至图5c所示，该方法可以包括以下步骤S01至步骤S04。
步骤S01：依次在承载基板100a(例如玻璃基板)上形成栅极140、栅绝缘层150和非晶硅薄膜110'，如图5a所示。
例如，通过沉积、曝光、刻蚀等过程形成栅极140；然后沉积例如氮化硅层和二氧化硅层以形成栅绝缘层150；之后再沉积非晶硅薄膜110'。
步骤S02：对完成步骤S01的承载基板100a进行高温脱氢工艺，然后针对非晶硅薄膜110'的待形成有源层(即待形成沟道区113、源极区111和漏极区112)的部分110”进行激光退火处理，以使该部分110”形成多晶硅，如图5b所示。
步骤S03：在完成步骤S02的承载基板100a上依次沉积非晶硅连接层薄膜120'和源漏电极层薄膜130'，非晶硅连接层薄膜120'包括依次沉积的待形成第一非晶硅层的薄膜(例如非掺杂非晶硅，简称为a-Si)120a'、待形成第二非晶硅层的薄膜(例如掺杂非晶硅，例如N型掺杂非晶硅，简称为n+a–Si)120b'，如图5c所示。
步骤S04：对完成步骤S03的承载基板100a进行半曝光工艺，然后进行刻蚀，以形成如图2所示的薄膜晶体管100的第一非晶硅层120a、第二非晶硅层120b、有源层110以及源漏电极层130。
本发明的至少一个实施例还提供一种阵列基板的制作方法，其包括：形成多个彼此间隔设置的薄膜晶体管，该薄膜晶体管采用上述任一实施例提供的制作方法制作。例如，该薄膜晶体管可以上述任一实施例提供的薄膜晶体管100。
例如，在制作完薄膜晶体管之后，如图6所示，本发明实施例提供的方法还可以包括：形成覆盖薄膜晶体管100的绝缘层102以及位于绝缘层102中的过孔(图6中未标出)；以及形成像素电极101，使该像素电极101通过绝缘层102中的过孔与薄膜晶体管100的漏极132电连接。
本发明实施例提供的制作方法适用于各种显示模式，比如TN(TwistedNematic)、VA(Vertical Alignment)、IPS(In-Plane Switch)或ADS(AdvancedSuper Dimension Switch)模式。
当然，本发明实施例提供的制作方法还包括其它步骤。例如，在形成薄膜晶体管100的栅极140的工艺中还可以形成栅线和公共电极线；例如，在形成薄膜晶体管100的源极131和漏极132的工艺中还可以形成数据线；例如，还可以形成公共电极，使该公共电极与公共电极线电连接。这里不做赘述。
如图7所示，本发明的至少一个实施例还提供一种薄膜晶体管200，其包括有源层210和源漏电极层230。有源层210具有沟道区213、以及分别位于沟道区213两侧且与沟道区213连接的源极区211和漏极区212，沟道区213的形成材料包括多晶硅，源极区211和漏极区212的形成材料包括掺杂非晶硅(例如N型掺杂非晶硅或P型掺杂非晶硅)；源漏电极层230位于有源层210的一侧并且包括彼此间隔设置的源极231和漏极232，源极231与源极区211电连接，漏极232与漏极区212电连接。
例如，有源层210的制作方法可以包括：形成非晶硅薄膜；对该非晶硅薄膜的待形成沟道区213的位置进行激光退火处理以形成多晶硅，并且进行曝光、刻蚀等处理以去除其余的非晶硅薄膜；之后，在多晶硅沟道区上形成掺杂非晶硅薄膜(例如可以直接通过沉积方式形成该掺杂非晶硅薄膜)，并对其进行曝光、刻蚀等处理以形成与沟道区213连接的源极区211和漏极区212，由此形成有源层210。当然，也可以采用其它方式制作有源层210。
在本发明实施例提供的薄膜晶体管200中，有源层210的源极区211和漏极区212采用掺杂非晶硅材料制作以实现分别与源极131和漏极132的电连接。因而，与常见的制作多晶硅(p-Si)薄膜晶体管的工艺相比，本发明实施例提供的薄膜晶体管200的制作工艺可以省略形成轻、重掺杂区的离子注入工艺及相应的曝光工艺，这使得该薄膜晶体管200的制作工艺简单、设备投资较少、适用于高世代线并且与非晶硅(a-Si)薄膜晶体管的产线有较好的兼容性。再一方面，与常见的非晶硅薄膜晶体管相比，本发明实施例提供的薄膜晶体管200包括的有源层210的沟道区213采用多晶硅材料(例如低温多晶硅材料)制作，由于多晶硅材料具有较大的电子迁移率，因而本发明实施例提供的薄膜晶体管200具有较大的开态电流。
例如，薄膜晶体管200还包括承载基板200a，并且在垂直于承载基板200a的方向上，沟道区213、源极区211和源极131可以在同一位置处交叠，沟道区213、漏极区212和漏极132也可以在同一位置处交叠。这样可以提高沟道区、源/漏极区和源/漏极之间的电连接性。
当然，本发明实施例提供的薄膜晶体管200还可以包括承载基板200a、栅极240以及设置于栅极240和有源层210之间的栅绝缘层250等结构。
综上所述，本发明实施例提供的薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置具有如下优点。
1、本发明实施例中，不需要对薄膜晶体管的有源层进行离子注入即可实现有源层的源极区和漏极区分别与源极和漏极的电连接，从而可以省略离子注入工艺及相应的曝光工艺。
2、在本发明实施例中，薄膜晶体管包括的有源层的沟道区采用多晶硅(例如低温多晶硅)材料制作，因而可以保证较高的电子迁移率。
3、在本发明的一些实施例中，有源层的源极区和漏极区都为非掺杂区，之后通过非晶硅连接层分别与源极和漏极连接，因而可以降低关态漏电流。
4、在本发明实施例提供的制作方法中，通过对待形成多晶硅的非晶硅薄膜进行局部激光退火处理，可以保证退火均一性和生产节拍，从而有利于使本发明实施例提供的制作方法适用于高世代产线。
5、与非晶硅薄膜晶体管的制作工艺相比，本发明实施例提供的制作方法只增加了高温脱氢和激光退火处理，因而设备投资少、工艺简单、与非晶硅薄膜晶体管的产线有较好的兼容性。
上述薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置的实施例可以互相参照。此外，在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (21)

1.一种薄膜晶体管，包括：
有源层，具有沟道区、源极区和漏极区，其中，所述沟道区的形成材料包括多晶硅；
非晶硅连接层，位于所述有源层的一侧，并且包括彼此间隔设置的第一连接部和第二连接部；以及
源漏电极层，包括彼此间隔设置的源极和漏极，其中，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
2.根据权利要求1所述的薄膜晶体管，其中，所述源极区和所述漏极区都为非掺杂区。
3.根据权利要求2所述的薄膜晶体管，其中，所述源极区和所述漏极区的形成材料为非掺杂非晶硅或者非掺杂多晶硅。
4.根据权利要求1至3中任一项所述的薄膜晶体管，其中，所述非晶硅连接层包括层叠设置的第一非晶硅层和第二非晶硅层，所述第二非晶硅层设置于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
5.根据权利要求4所述的薄膜晶体管，其中，所述第一非晶硅层的形成材料为非掺杂非晶硅。
6.根据权利要求1至3中任一项所述的薄膜晶体管，还包括承载基板，其中，在垂直于所述承载基板的方向上，所述有源层设置于所述承载基板和所述源漏电极层之间。
7.根据权利要求1至3中任一项所述的薄膜晶体管，其中，所述源漏电极层的材料为金属材料。
8.根据权利要求1至3中任一项所述的薄膜晶体管，其中，在从所述源极区到所述漏极区的方向上，所述有源层的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
9.根据权利要求8所述的薄膜晶体管，其中，所述源极和所述漏极的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
10.根据权利要求1至3中任一项所述的薄膜晶体管，其中，所述源极和所述漏极的外边缘之间的距离等于所述第一连接部和所述第二连接部的外边缘之间的距离。
11.根据权利要求1至3中任一项所述的薄膜晶体管，还包括承载基板和栅极，其中，所述栅极设置于所述有源层与所述承载基板之间。
12.一种阵列基板，包括多个彼此间隔设置的薄膜晶体管，其中，所述薄膜晶体管为权利要求1至11中任一项所述的薄膜晶体管。
13.根据权利要求12所述的阵列基板，还包括多个彼此间隔设置的像素电极，
其中，所述多个像素电极分别对应所述多个薄膜晶体管，并且每个像素电极与对应的薄膜晶体管的漏极电连接。
14.一种显示装置，包括根据权利要求12或13所述的阵列基板。
15.一种薄膜晶体管的制作方法，包括：
形成具有沟道区、源极区和漏极区的有源层，其中，所述沟道区的形成材料包括多晶硅；
在所述有源层的一侧形成非晶硅连接层，其中，所述非晶硅连接层包括彼此间隔设置的第一连接部和第二连接部；以及
在所述非晶硅连接层的远离所述有源层的一侧形成源漏电极层，其中，所述源漏电极层包括源极和漏极，所述源极通过所述第一连接部与所述源极区电连接，所述漏极通过所述第二连接部与所述漏极区电连接。
16.根据权利要求15所述的制作方法，其中，形成所述非晶硅连接层包括：形成层叠的第一非晶硅层和第二非晶硅层，其中，所述第二非晶硅层形成于所述第一非晶硅层和所述源漏电极层之间，且所述第二非晶硅层的电导率大于所述第一非晶硅层的电导率。
17.根据权利要求15所述的制作方法，其中，形成所述有源层包括：
形成非晶硅薄膜；以及
对所述非晶硅薄膜的待形成所述沟道区或者待形成所述沟道区、所述源极区和所述漏极区的部分进行激光退火处理以使所述部分形成多晶硅。
18.根据权利要求15至17中任一项所述的制作方法，其中，
通过半曝光工艺形成所述有源层和所述非晶硅连接层；或者
通过半曝光工艺形成所述有源层、所述非晶硅连接层和所述源漏电极层。
19.根据权利要求15至17中任一项所述的制作方法，其中，
形成层叠的非晶硅连接层薄膜和源漏电极层薄膜；
对所述非晶硅连接层薄膜和所述源漏电极层薄膜进行一次曝光工艺以形成所述非晶硅连接层和所述源漏电极层。
20.一种阵列基板的制作方法，包括：
形成多个彼此间隔设置的薄膜晶体管，其中，所述薄膜晶体管采用权利要求15至19中任一项所述的制作方法制作。
21.一种薄膜晶体管，包括：
有源层，具有沟道区、源极区和漏极区，其中，所述沟道区的形成材料包括多晶硅，所述源极区和所述漏极区的形成材料包括掺杂非晶硅；以及
源漏电极层，位于所述有源层的一侧并且包括彼此间隔设置的源极和漏极，其中，所述源极与所述源极区电连接，所述漏极与所述漏极区电连接。
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