WO2020056805A1 - 阵列基板及其制作方法、显示面板 - Google Patents

阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2020056805A1
WO2020056805A1 PCT/CN2018/109452 CN2018109452W WO2020056805A1 WO 2020056805 A1 WO2020056805 A1 WO 2020056805A1 CN 2018109452 W CN2018109452 W CN 2018109452W WO 2020056805 A1 WO2020056805 A1 WO 2020056805A1
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Prior art keywords
doped region
layer
metal layer
active layer
area
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PCT/CN2018/109452
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English (en)
French (fr)
Inventor
陈彩琴
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武汉华星光电半导体显示技术有限公司
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Priority to US16/325,394 priority Critical patent/US20200127140A1/en
Publication of WO2020056805A1 publication Critical patent/WO2020056805A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/30—Doping active layers, e.g. electron transporting layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L2029/7863—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.
  • LTPS Low temperature poly-silicon
  • TFT Thin Film Transistor
  • CMOS complementary metal-oxide-semiconductor
  • LDD Low-doped Drain regions
  • AMOLED often uses a PMOS structure, and the pixel uses a PMOS device structure that compensates for Vth.
  • the structure is complex and requires higher leakage current. Therefore, if the complexity of the structure can be saved, the LDD structure of PMOS can be increased.
  • AMOLED optical performance has been greatly improved.
  • the LTPS process is complicated.
  • the substrate array is formed with many layers, and a large number of photomasks are required.
  • Increasing the LDD structure of PMOS in AMOLED will lead to more masks, increase product production capacity time, increase lighting costs and operating costs.
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel, so as to solve a technical problem that a PLD LDD structure process is complicated in AMOLED.
  • the present application provides a method for manufacturing an array substrate, including steps:
  • a buffer layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer are sequentially formed on the substrate.
  • An area of the second metal layer is larger than an area of the first metal layer.
  • the step S103 includes steps:
  • the first doped region is processed by using a predetermined process, so that a part of the ions in the first doped region is diffused around the first doped region, so that a part of the active layer forms a second doped region. Miscellaneous area,
  • the ion concentration in the first doped region is greater than the ion concentration in the second doped region.
  • the second doped region surrounds the first doped region.
  • an area of the second doped region is greater than or equal to a difference between an area of the second metal layer and an area of the first metal layer.
  • the step S103 includes steps:
  • the via hole penetrates the third insulating layer, the second insulating layer, and part of the first insulating layer, so that part of the active layer is exposed at the via hole;
  • the first doped region is processed by using a predetermined process, so that a part of the ions in the first doped region is diffused around the first doped region, so that part of the active layer forms the first Two doped regions.
  • the shape of the first doped region is the same as the shape of the via hole, and the shape of the first doped region is a polygon or a circle.
  • forming the first doped region and the second doped region includes steps:
  • the first metal layer as a barrier layer, performing a first ion doping on part of the active layer, so that part of the active layer forms a second doped region;
  • the second metal layer as a barrier layer, performing a second ion doping on part of the active layer, so that part of the active layer forms a first doped region.
  • using the second metal layer as a barrier layer to perform a second ion doping on part of the active layer further includes the following steps:
  • the second metal layer patterned photoresist and the patterned second insulation are used as a barrier layer, and a second ion doping is performed on a part of the active layer to form a part of the active layer. A doped region.
  • the present application also provides an array substrate including a substrate, an active layer on the substrate, a first metal layer on the active layer, and a second metal on the first metal layer.
  • Floor including a substrate, an active layer on the substrate, a first metal layer on the active layer, and a second metal on the first metal layer.
  • the active layer includes a first doped region disposed inside the active layer and a second doped region disposed outside the active layer, and an area of the second doped region is greater than or equal to A difference between an area of the second metal layer and an area of the first metal layer.
  • an area of the second metal layer is larger than an area of the first metal layer.
  • the array substrate further includes at least two via holes and a source / drain layer;
  • the source and drain layers are electrically connected to the second doped region through the vias.
  • a shape of the first doped region is the same as a shape of the via hole.
  • the shape of the first doped region is a polygon or a circle.
  • the second doped region surrounds the first doped region.
  • the ion concentration of the first doped region is greater than the ion concentration of the second doped region.
  • the present application also proposes a display panel, wherein the display panel includes an array substrate, and the array array includes a substrate, an active layer on the substrate, a first metal layer on the active layer, And a second metal layer on the first metal layer;
  • the active layer includes a first doped region disposed inside the active layer and a second doped region disposed outside the active layer, and an area of the second doped region is greater than or equal to A difference between an area of the second metal layer and an area of the first metal layer.
  • an area of the second metal layer is larger than an area of the first metal layer.
  • the array substrate further includes at least two via holes and a source / drain layer;
  • the source and drain layers are electrically connected to the second doped region through the vias.
  • the shape of the first doped region is the same as that of the via hole, and the shape of the first doped region is a polygon or a circle.
  • the second doped region surrounds the first doped region.
  • the ion concentration of the first doped region is greater than the ion concentration of the second doped region.
  • the active layer is ion-doped once, and the doped active layer is formed into a first doped region and a second doped region by using a specific process.
  • the LDD structure of the PMOS is added to the AMOLED, which effectively reduces the cycle in the manufacturing process of the panel array and saves the production cost.
  • FIG. 1 is a step diagram of a manufacturing method of an array substrate according to a first embodiment of the present application
  • 2A ⁇ 2K are process diagrams of a method for fabricating an array substrate according to a first embodiment of the present application
  • FIG. 3 is a first plan view of an array substrate according to an embodiment of the present application.
  • FIG. 4 is a second plan view of an array substrate according to a first embodiment of the present application.
  • FIG. 5 is a step diagram of a method for manufacturing an array substrate according to the second embodiment of the present application.
  • 6A-6J are process diagrams of a method for manufacturing an array substrate according to the second embodiment of the present application.
  • FIG. 7 is a structural diagram of a first film layer of an array substrate according to a third embodiment of the present application.
  • FIG. 8 is a structural diagram of a second film layer of the array substrate according to the third embodiment of the present application.
  • FIG. 1 is a step diagram of a manufacturing method of an array substrate according to an embodiment of the present application.
  • the manufacturing method includes steps:
  • a substrate 101 is provided.
  • the substrate 101 may be one of a glass substrate, a quartz substrate, and a resin substrate.
  • a buffer layer 102, an active layer 103, a first insulating layer 104, a first metal layer 105, a second insulating layer 106, a second metal layer 107, and a third insulating layer 108 are sequentially formed on the substrate 101.
  • an area of the second metal layer 107 is larger than an area of the first metal layer 105.
  • FIGS. 2A to 2K are process diagrams of a method for fabricating an array substrate according to a first embodiment of the present application.
  • step S102 specifically includes:
  • a buffer layer 102 is formed on the substrate 101.
  • An active layer 103 is formed on the buffer layer.
  • an active layer film is first formed on the buffer layer, and the active layer film is made of polysilicon.
  • a first photomask process is used for the active layer film, a first photoresist layer (not shown) is formed on the active layer film, a mask (not shown) is used for exposure, and after development and After the first etching patterning process is performed, the active layer film is formed into the active layer 103 pattern shown in FIG. 2B, and the first photoresist layer is peeled off.
  • a first insulating layer 104 is formed on the active layer 103.
  • the first insulating layer 104 is formed on the active layer 103.
  • the first insulating layer 104 is a first gate insulating layer, and the first gate insulating layer covers the active layer 103.
  • the first gate insulating layer is mainly used to isolate the active layer 103 from other metal layers.
  • a first metal layer 105 is formed on the first insulating layer 104.
  • a metal layer is formed on the first insulating layer 104.
  • the metal material of the metal layer may generally be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the foregoing metal materials.
  • a material of the first metal layer 105 may be molybdenum.
  • a second photomask process is used for the first metal layer, a second photoresist layer is formed on the first metal layer, a mask (not shown) is used for exposure, and the patterning process is performed after development and second etching. After that, the first metal layer is formed into the first metal layer 105 shown in FIG. 2A, and the second photoresist layer is peeled off;
  • the first metal layer 105 is a gate of an array substrate.
  • a second insulating layer 106 is formed on the first metal layer 105.
  • the second insulating layer 106 is a second gate insulating layer, and the first gate insulating layer covers the active layer 103.
  • the second gate insulating layer is mainly used to isolate the first metal layer 105 and the second metal layer 107.
  • the thickness of the second insulating layer 106 is 50-200 nm.
  • materials of the first gate insulating layer and the second gate insulating layer may be silicon nitride, and silicon oxide, silicon oxynitride, or the like may also be used.
  • a second metal layer 107 is formed on the second insulating layer 106.
  • the metal material of the second metal layer 107 is the same as the metal material of the first metal layer 105.
  • metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper can be used, and a combination of the above-mentioned metal materials can also be used.
  • the metal material of the second metal layer 107 may be molybdenum.
  • the thickness of the second metal layer 107 is 150-250 nm.
  • a third photomask process is applied to the metal layer forming the second metal layer 107, a third photoresist layer is formed on the metal layer, and a mask (not shown) is used for exposure, development, and third etching patterning. After the process, the metal layer is formed into the second metal layer 107 of the array substrate.
  • an area of the second metal layer 107 is larger than an area of the first metal layer 105.
  • the orthographic projection of the first metal layer 105 on the second metal layer 107 is within the second metal layer 107.
  • a third insulating layer 108 is formed on the second metal layer 107.
  • the third insulating layer 108 is an inter-insulating layer, and the inter-insulating layer covers the second metal layer 107.
  • the inter-insulating layer is mainly used to isolate the second metal layer 107 from the source and drain electrodes 112.
  • the thickness of the inter-insulating layer is 50-200 nm.
  • step S103 specifically includes:
  • the second metal layer 107 and the first metal layer 105 are used as a barrier layer, and ion implantation is performed on the active layer 103. Ion doping, so that part of the active layer 103 forms a first doped region 109.
  • the doped ions are a high concentration of P +, and the first doped region 109 is also referred to as a heavily doped region.
  • S10312. Process the first doped region 109 by using a predetermined process, so that a part of the ions of the first doped region 109 is diffused around the first doped region 109, so that a part of the active layer 103 is diffused.
  • a second doped region 110 is formed.
  • this step mainly uses a predetermined process to process the first doped region 109.
  • the predetermined process is a high-temperature activation and hydrogenation process, so that a part of the ions of the first doped region 109 are directed toward the first doped region.
  • a doped region 109 is diffused around, so that part of the active layer 103 forms a second doped region 110.
  • the ion concentration of the first doped region 109 is greater than the ion concentration of the second doped region 110.
  • a via hole 111 is formed on the surface of the third insulating layer 108 so that the source and drain electrodes 112 formed later are connected to the first doped region 109.
  • the first metal layer and the second metal layer need to be used as a shielding layer for ion doping to form lightly doped regions and heavily doped regions in different regions. Therefore, the area sizes of the first metal layer and the second metal layer are not the same, and there are certain differences.
  • FIG. 3 is a first plan view of an array substrate according to an embodiment of the present application.
  • 2D is a cross-sectional view of section AA in FIG. 3;
  • the first metal layer 105 is used as a first shielding layer, and the active layer 103 is ion-doped for the first time.
  • the second metal layer 107 is used as the second shielding layer, and the active layer 103 is ion-doped a second time, that is, a pattern shown in FIG. 2D is formed.
  • the active layer 103 may be ion-doped a second time through the via hole 111.
  • the doped ion concentration is adjusted so that the area of the second doped region reaches the pattern shown in FIG. 2D.
  • step S103 may further include:
  • a via hole 111 is formed in the third insulating layer 108.
  • a via hole 111 is formed on a surface of the third insulating layer 108.
  • the via hole 111 penetrates the third insulating layer 108, the second insulating layer 106, and a part of the first insulating layer 104, so that part of the active layer 103 is exposed.
  • the shape of the via hole 111 may be a polygon or a circle.
  • the via hole 111 is circular.
  • S10322 Perform ion doping on an exposed portion of the active layer 103, so that a part of the active layer 103 forms the first doped region 109.
  • this step mainly includes performing ion implantation on the partially exposed active layer 103, so that the partially exposed active layer 103 forms a first doped region 109.
  • the doped ion is a high concentration of P +, and the first doped region 109 may also be referred to as a heavily doped region.
  • the shape of the first doped region 109 is the same as the shape of the via hole 111.
  • the shape of the first doped region 109 is a polygon or a circle.
  • the shape of the first doped region 109 is circular.
  • the boron ions contained in the active layer 103 corresponding to the via hole 111 reach a critical value, and the boron ions will diffuse to the periphery.
  • the shape of the first doped region 109 and the shape of the via hole 111 may be different from each other due to the diffusion of boron ions.
  • the boron ions will diffuse to the surroundings, and the ion implantation amount is set to not exceed the critical value.
  • S10323 Process the first doped region 109 by using a predetermined process, so that a part of the ions of the first doped region 109 diffuses around the first doped region 109, so that part of the active layer 103
  • the second doped region 110 is formed.
  • this step mainly uses a predetermined process to process the first doped region 109.
  • the predetermined process is a high-temperature activation and hydrogenation process, so that a part of the ions of the first doped region 109 diffuses around the first doped region 109, so that a part of the active layer 103 forms a second doped region. 110.
  • the ion concentration of the first doped region 109 is greater than the ion concentration of the second doped region 110.
  • the area of the second doped region 110 is larger than the difference between the area of the second metal layer 107 and the area of the first metal layer 105.
  • the area of the second doped region 110 may appear to be equal to or smaller than the area of the second metal layer 107 and the area of the first metal layer 105. Difference.
  • the second doped region 110 surrounds the first doped region 109.
  • the area of the second doped region 110 is larger than the difference between the area of the second metal layer 107 and the area of the first metal layer 105. value.
  • a pattern shown in FIG. 2G may be formed.
  • the final patterns of the first doped region 109 and the second doped region 110 may be various, and are not limited to the two patterns listed in this embodiment.
  • the size of the first doped region and the second doped region of the active layer is limited to a certain extent; however, in actual production, when the second metal layer is not used as a shielding layer, the size of the second metal layer may be the same as that of the first metal layer.
  • FIG. 4 is a second top view of an array substrate according to an embodiment of the present application.
  • FIG. 2H is a cross-sectional view of section BB in FIG. 4.
  • This embodiment differs from FIG. 3 in that:
  • the second metal layer 107 is not used as the shielding layer for the second ion doping, but the active layer is directly subjected to the second ion doping through the via hole 111. Therefore, the ion concentration of the second ion doping is adjusted so that the area of the second doped region reaches the solution shown in FIG. 2H.
  • a source / drain 112 is formed on the third insulating layer 108.
  • the source and drain electrodes 112 are formed on the third insulating layer 108.
  • the metal materials of the source and drain electrodes 112 and the first metal layer 105 and the second metal layer 107 may be the same.
  • metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper can be used, and a combination of the above-mentioned metal materials can also be used.
  • the metal material of the source / drain 112 may be a titanium aluminum alloy, and the thickness of the source / drain 112 is 400-600 nm.
  • This step includes: applying a fourth photomask process to the metal layer forming the source and drain electrodes 112, forming a fourth photoresist layer on the metal layer, exposing using a mask (not shown), developing and fourth After the etching patterning process is performed, the metal layer is formed into the source and drain electrodes 112.
  • the source and drain electrodes 112 are connected to the first doped region 109 through the via hole 111.
  • a flat layer 113 is formed on the second source / drain 112.
  • the flat layer 113 is used to ensure the flatness of the film layer structure and form the film layer structure in FIG. 2J or FIG. 2K.
  • FIG. 5 is a flowchart of a method for manufacturing an array substrate according to the second embodiment of the present application.
  • the manufacturing method includes steps:
  • a substrate 201 is provided.
  • a buffer layer 202, an active layer 203, a first insulating layer 204, and a first metal layer 205 are sequentially formed on the substrate 201.
  • FIGS. 6A to 6J are process diagrams of a method for manufacturing an array substrate according to the second embodiment of the present application.
  • steps S201 and S202 are the same as those in the first embodiment, which will not be repeated one by one in this embodiment.
  • this step includes using the first metal layer 205 as a barrier layer to perform a first ion implantation on the active layer 203 to form a doped region.
  • the doped ions are high-concentration P-.
  • the second doped region 210 may also be referred to as a lightly doped region.
  • the second doped region 210 is located in the active layer 203. Both sides of the channel region.
  • the photoresist layer patterned with the first metal layer 205 can also serve as a barrier layer simultaneously with the first metal layer 205. After the ion implantation is completed, the photoresist layer is peeled off.
  • a second insulating layer is formed on the first metal layer 205.
  • a second metal layer 207 and a third insulating layer 208 are sequentially formed on the second insulating layer.
  • Step S205 mainly includes:
  • a second metal layer 207 is formed on the second insulating layer.
  • this step includes using the second metal layer 207 as a barrier layer to ion-implant a part of the active layer 203, so that a part of the active layer 203 forms a first doped region. 209.
  • the doped ion is a high concentration of P +, and the first doped region 209 may also be referred to as a heavily doped region.
  • a third insulating layer 208 is formed on the second metal layer 207.
  • step S2051 after the third insulating layer 208 is formed, ion implantation may be performed on part of the active layer 203.
  • This step may also include:
  • the step of forming the second metal layer 207 is the same as that in the first embodiment, but the photoresist layer 214 that patterns the second metal layer 207 remains.
  • this step includes using the second metal layer 207 and a photoresist layer patterned as a barrier layer to perform a second ion implantation on a part of the active layer 203. .
  • a part of the active layer 203 is formed into a first doped region 209.
  • the doped ion is a high concentration of P +, and the first doped region 209 may also be referred to as a heavily doped region.
  • a third insulating layer 208 is formed on the second metal layer 207.
  • the pattern shown in FIG. 6D is mainly formed.
  • This step may also include:
  • a second metal layer 207 and a patterned second insulating layer are formed on the second insulating layer.
  • the metal layer forming the second metal layer 207 and the second insulating layer are patterned simultaneously to form the second metal layer 207 and the patterned second insulating layer. .
  • this step includes using the second metal layer 207 and the patterned second insulating layer as a barrier layer to perform a second ion implantation on part of the active layer 203.
  • a portion of the second doped region 210 is formed into a first doped region 209.
  • the doped ion is a high concentration of P +, and the first doped region 209 may also be referred to as a heavily doped region.
  • a third insulating layer 208 is formed on the second metal layer 207.
  • step S2053 the photoresist layer patterned by the second metal layer 207 can also be retained as a barrier layer. After the second ion doping is completed, the photoresist layer is stripped.
  • step S205 since the first doped region 209 is a high-concentration boron ion, the second doped region 210 is a low-concentration boron ion. Therefore, the ion concentration of the first doped region 209 is greater than the ion concentration of the second doped region 210.
  • first doped region 209 and the second doped region 210 There may be multiple final patterns of the first doped region 209 and the second doped region 210, which are the same as those in the first embodiment.
  • a predetermined process may be used to process the ion concentration of the doped region.
  • a via hole 211 is formed in the third insulating layer 208.
  • a via hole 211 is formed on the surface of the third insulating layer 208.
  • the via hole 211 penetrates the third insulating layer 208, the second insulating layer 206, and a part of the first insulating layer 204, so that a part of the first doped region 209 is exposed.
  • a source and drain electrode 212 is formed on the third insulating layer 208.
  • the source and drain electrodes 212 are connected to the first doped region 209 through the via hole 211.
  • a flat layer 213 is formed on the second source and drain electrodes 212 to ensure the flatness of the film layer structure, and a film layer structure as shown in FIG. 6H or FIG. 2K is formed.
  • This application proposes a method for manufacturing an array substrate.
  • the manufacturing method is to form a first doped region and a doped active layer by using a specific process by ion doping the active layer once.
  • Second doped region 210 By adding the LDD structure of the PMOS to the AMOLED on the basis of the existing process and without adding a photomask, the application effectively reduces the cycle in the manufacturing process of the panel array and saves the manufacturing cost.
  • FIG. 7 is a structural diagram of a first film layer of an array substrate according to a third embodiment of the present application.
  • the array substrate includes a substrate 301, a buffer layer, an active layer 303, a first insulating layer 304, a first metal layer 305, a second insulating layer, a second metal layer 307, a third insulating layer 308, a source and drain electrode 312, and Flattening layer.
  • the substrate 301 may be one of a glass substrate, a quartz substrate, and a resin substrate.
  • the buffer layer is formed on the substrate 301, and is mainly used for buffering the pressure between the layer structures of the membrane, and may also have a function of blocking water and oxygen to a certain extent.
  • the active layer 303 is formed on the buffer layer.
  • the active layer 303 includes a first doped region 309 and a second doped region 310 that are ion-doped.
  • the first doped region 309 is a high-concentration boron ion
  • the second doped region 310 is a low-concentration boron ion.
  • the ion concentration of the first doped region 309 is greater than the ion concentration of the second doped region 310.
  • the first insulating layer 304 is formed on the active layer 303.
  • the first insulating layer 304 is a first gate insulating layer, the first gate insulating layer covers the active layer 303, and the first gate insulating layer is mainly used for The active layer 303 is isolated from other metal layers.
  • the first metal layer 305 is formed on the first insulating layer 304.
  • the metal material of the first metal layer 305 may generally be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the foregoing metal materials.
  • a second insulating layer 306 is formed on the first metal layer 305.
  • the second insulating layer 306 is a second gate insulating layer
  • the first gate insulating layer covers the active layer 303
  • the second gate insulating layer is mainly used for The first metal layer 305 and the second metal layer 307 are isolated.
  • the thickness of the second insulating layer 306 is 50-200 nm.
  • the material of the second gate insulating layer may be silicon nitride, and silicon oxide, silicon oxynitride, or the like may also be used.
  • the second metal layer 307 is formed on the second insulating layer 306.
  • the material of the second metal layer 307 is the same as that of the first metal layer 305.
  • a metal material of the first metal layer 305 and the second metal layer 307 may be molybdenum.
  • the metal layer forming the second metal layer 307 is subjected to a patterning process to form the second metal layer 307 having an area larger than that of the first metal layer 305.
  • the orthographic projection of the first metal layer 305 on the second metal layer 307 is within the second metal layer 307.
  • a third insulating layer 308 is formed on the second metal layer 307.
  • the third insulation layer 308 is an inter-insulation layer, and the inter-insulation layer covers the second metal layer 307.
  • the inter-insulation layer is mainly used to encapsulate the second metal layer 307. It is isolated from the source and drain 312.
  • the thickness of the inter-insulating layer is 50-200 nm.
  • Via holes 311 are formed on the surface of the third insulating layer 308.
  • the via hole 311 penetrates the third insulating layer 308, the second insulating layer 306, and a part of the first insulating layer 304.
  • the shape of the via hole 311 may be a polygon or a circle.
  • the via hole 311 is circular.
  • the source and drain electrodes 312 are formed on the third insulating layer 308.
  • the metal materials of the source and drain electrodes 312 can generally be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, copper, or titanium aluminum alloy. A combination of the above-mentioned several metal materials can be used.
  • the metal material of the source and drain electrodes 312 may be a titanium aluminum alloy.
  • the source and drain electrodes 312 are connected to the first doped region 309 through vias 311.
  • a flat layer 313 is formed on the source and drain electrodes 312 to ensure the flatness of the film structure of the array substrate.
  • the above-mentioned structure is formed mainly by performing an ion implantation on the exposed portion of the active layer 303 through the via 311, so that a portion of the active layer 303 forms a first doped region 309.
  • the doped ions have a high concentration of P +, and the first doped region 309 may also be referred to as a heavily doped region.
  • the first doped region 309 is processed by using a predetermined process, and the predetermined process is a high-temperature activation and hydrogenation process, so that a part of the ions of the first doped region 309 are directed toward the first Diffusion around the doped region 309 causes part of the active layer 303 to form a second doped region 310.
  • the predetermined process is a high-temperature activation and hydrogenation process
  • the shape of the first doped region 309 is the same as the shape of the via 311, that is, the shape of the first doped region 309. It is polygonal or circular.
  • the first doped region 309 is circular.
  • the ion implantation amount of the first doped region 309 exceeds a certain threshold value, boron ions in the region will diffuse to the surroundings, resulting in that the shape of the first doped region 309 and the shape of the via 311 are different.
  • the shape is not limited.
  • the via 311 is close to the edge of the active layer 303, that is, the area of the second doped region 310 is equal to the area of the second metal layer 307 and the area of the first metal layer 305. The difference in area.
  • FIG. 8 is a structural diagram of a second film layer of the array substrate according to the third embodiment of the present application.
  • the second doped region 410 surrounds the first doped region 409, and an area of the second doped region 410 is larger than a difference between an area of the second metal layer 407 and an area of the first metal layer 405. value.
  • the second doped region 410 is mainly used to withstand part of the voltage in the circuit, that is, increasing the area of the second doped region 410 can better prevent the thermal electron degradation effect and reduce the effect of channel leakage current.
  • the shapes of the first doped region and the second doped region are related to ion concentration, ion implantation amount, shape of the active layer, process, and human factors. Therefore, the patterns of the first and second doped regions are not limited to the shapes in the present application.
  • the display panel includes the above-mentioned array substrate.
  • the working principle of the display panel is the same as the working principle of the array substrate, and is not repeated here.
  • the present application proposes an array substrate, a manufacturing method thereof, and a display panel.
  • the manufacturing method is to form the first doped active layer by using a specific process by ion doping the active layer once. A doped region and a second doped region.

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Abstract

一种阵列基板及其制作方法、显示面板，所述制作方法为通过对所述有源层（103）进行一次离子掺杂，利用特定工艺使经过掺杂的所述有源层（103）形成第一掺杂区（109）和第二掺杂区（110）。通过在现有工艺以及未增加光罩的基础上，在AMOLED中增加PMOS的LDD结构，有效的降低了面板阵列制造过程中的周期，节省了制作成本。

Description

阵列基板及其制作方法、显示面板 技术领域
本申请涉及显示领域，特别涉及一种阵列基板及其制作方法、显示面板。
 背景技术
低温多晶硅（Low temperature poly-silicon，LTPS），由于其具有高的电子迁移率，可以有效的减小薄膜晶体管（Thin Film Transistor，TFT）的器件的面积，进而提升像素的开口率，增大面板显示亮度的同时可以降低整体的功耗，使得面板的制造成本大幅度降低，目前已成为液晶显示领域炙手可热的技术。
在传统LTPS LCD中，常常采用互补金属氧化物半导体（CMOS）器件来组成面板驱动电路的基本单元；而为了平衡NMOS和PMOS的器件特性，往往只在NMOS器件中制作低掺杂漏区（Lightly Doped Drain，LDD）结构。现有技术中，AMOLED常采用PMOS结构，像素采用补偿Vth的PMOS器件结构，结构复杂，对漏电流要求更高；故而，若能在节省结构复杂程度的基础上，增加PMOS的LDD结构，对AMOLED光学性能具有较大的提升。
但是LTPS工艺复杂，在阵列工艺中，基板阵列成膜的的层别较多，需要较多的光罩数量。而在AMOLED中增加PMOS的LDD结构，将导致增加更多的光罩数量，使得产品制作产能时间增长，增加了光照成本以及运营成本。
 技术问题
本申请提供一种阵列基板及其制作方法、显示面板，以解决在AMOLED中增加PMOS的LDD结构工艺复杂的技术问题。
 技术解决方案
本申请提供一种阵列基板的制作方法，包括步骤：
S101、提供一基板；
S102、在所述基板上依次形成缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层以及第三绝缘层，
其中，所述第二金属层的面积大于所述第一金属层的面积；
S103、对部分所述有源层进行离子掺杂，使部分所述有源层形成第一掺杂区，利用预定工艺对所述第一掺杂区进行处理，使部分所述有源层形成第二掺杂区；
S104、在所述第三绝缘层上形成源漏极。
在本申请的制作方法中，所述S103包括步骤：
S10311、利用第二金属层和第一金属层作为隔档层，对部分所述有源层进行离子掺杂，使部分所述有源层形成第一掺杂区；
S10312、利用预定工艺对所述第一掺杂区进行处理，使所述第一掺杂区的部分离子向所述第一掺杂区的四周扩散，使部分所述有源层形成第二掺杂区，
其中，所述第一掺杂区的离子浓度大于所述第二掺杂区的离子浓度。
在本申请的制作方法中，所述第二掺杂区包围所述第一掺杂区。
在本申请的制作方法中，所述第二掺杂区的面积大于或等于所述第二金属层的面积与所述第一金属层的面积的差值。
根据本申请一优选实施例，所述S103包括步骤：
S10321、在所述第三绝缘层上形成过孔，
其中，所述过孔贯穿所述第三绝缘层、第二绝缘层以及部分第一绝缘层，使部分所述有源层在所述过孔处裸露；
S10322、对所述有源层裸露的部分进行离子掺杂，以使部分所述有源层形成所述第一掺杂区；
S10323、利用预定工艺对所述第一掺杂区进行处理，使所述第一掺杂区的部分离子向所述第一掺杂区的四周扩散，使部分所述有源层形成所述第二掺杂区。
在本申请的制作方法中，所述第一掺杂区的形状和所述过孔的形状相同，所述第一掺杂区的形状为多边形或圆形。
在本申请的制作方法中，形成所述第一掺杂区和所述第二掺杂区包括步骤：
利用所述第一金属层作为隔档层，对部分所述有源层进行第一次离子掺杂，使部分所述有源层形成第二掺杂区；
利用所述第二金属层作为隔档层，对部分所述有源层进行第二次离子掺杂，使部分所述有源层形成第一掺杂区。
在本申请的制作方法中，利用所述第二金属层作为隔档层，对部分所述有源层进行第二次离子掺杂还包括步骤：
利用所述第二金属层和使所述第二金属层图案化的光刻胶、所述第二金属层和经图案化的所述第二绝缘层、以及所述第二金属层、使所述第二金属层图案化的光刻胶和经图案化的所述第二绝缘作为隔档层，对部分所述有源层进行第二次离子掺杂，使部分所述有源层形成第一掺杂区。
本申请还提出了一种阵列基板，其包括基板、位于所述基板上的有源层、位于所述有源层上的第一金属层、及位于所述第一金属层上的第二金属层；
其中，所述有源层包括设置于所述有源层内侧的第一掺杂区和设置位于所述有源层外侧的第二掺杂区，所述第二掺杂区的面积大于或等于所述第二金属层的面积与所述第一金属层的面积的差值。
在本申请的阵列基板中，所述第二金属层的面积大于所述第一金属层的面积。
在本申请的阵列基板中，所述阵列基板还包括至少两个过孔和源漏极层；
所述源漏极层通过所述过孔与所述第二掺杂区电连接。
在本申请的阵列基板中，所述第一掺杂区的形状和所述过孔的形状相同。所述第一掺杂区的形状为多边形或圆形。
在本申请的阵列基板中，所述第二掺杂区包围所述第一掺杂区。
在本申请的阵列基板中，所述第一掺杂区的离子浓度大于所述第二掺杂区的离子浓度。
本申请还提出了一种显示面板，其中，所述显示面板包括阵列基板，所述阵列阵列包括基板、位于所述基板上的有源层、位于所述有源层上的第一金属层、及位于所述第一金属层上的第二金属层；
其中，所述有源层包括设置于所述有源层内侧的第一掺杂区和设置位于所述有源层外侧的第二掺杂区，所述第二掺杂区的面积大于或等于所述第二金属层的面积与所述第一金属层的面积的差值。
在本申请的显示面板中，所述第二金属层的面积大于所述第一金属层的面积。
在本申请的显示面板中，所述阵列基板还包括至少两个过孔和源漏极层；
所述源漏极层通过所述过孔与所述第二掺杂区电连接。
在本申请的显示面板中，所述第一掺杂区的形状和所述过孔的形状相同，所述第一掺杂区的形状为多边形或圆形。
在本申请的显示面板中，所述第二掺杂区包围所述第一掺杂区。
在本申请的显示面板中，所述第一掺杂区的离子浓度大于所述第二掺杂区的离子浓度。
 有益效果
本申请通过对所述有源层进行一次离子掺杂，利用特定工艺使经过掺杂的所述有源层形成第一掺杂区和第二掺杂区；本申请通过在现有工艺以及未增加光罩的基础上，在AMOLED中增加PMOS的LDD结构，有效的降低了面板阵列制造过程中的周期，节省了制作成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例一阵列基板的制作方法的步骤图；
图2A~2K为本申请实施例一阵列基板的制作方法的工艺图；
图3本申请实施例一阵列基板第一种俯视图；
图4本申请实施例一阵列基板第二种俯视图；
图5为本申请实施例二阵列基板的制作方法的步骤图；
图6A~6J为本申请实施例二阵列基板的制作方法的工艺图；
图7为本申请实施例三阵列基板的第一种膜层结构图；
图8为本申请实施例三阵列基板的第二种膜层结构图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
实施例一
请参阅图1，图1为本申请实施例一阵列基板的制作方法的步骤图。所述制作方法包括步骤：
S101、提供一基板101。
提供一基板101，所述基板101可以为玻璃基板、石英基板、树脂基板等中的一种。
S102、在所述基板101上依次形成缓冲层102、有源层103、第一绝缘层104、第一金属层105、第二绝缘层106、第二金属层107以及第三绝缘层108。
在一种实施例中，所述第二金属层107的面积大于所述第一金属层105的面积。
请参阅图2A~2K，图2A~2K为本申请实施例一阵列基板的制作方法的工艺图。
请参阅图2A，步骤S102具体包括：
S1021、在所述基板101上形成缓冲层102。
S1022、在所述缓冲层上形成有源层103。
在本步骤中，首先在所述缓冲层上形成一有源层薄膜，所述有源层薄膜由多晶硅构成。其次，对所述有源层薄膜使用第一光罩制程工艺，在所述有源层薄膜上形成第一光阻层（未画出），采用掩模板（未画出）曝光，经显影以及第一蚀刻的构图工艺处理后，使所述有源层薄膜形成图2B所示的有源层103图案，并剥离所述第一光阻层。
S1023、在所述有源层103上形成第一绝缘层104。
所述第一绝缘层104，形成于所述有源层103上。
在一种实施例中，所述第一绝缘层104为第一栅绝缘层，所述第一栅绝缘层将所述有源层103覆盖。所述第一栅绝缘层主要用于将所述有源层103与其他金属层隔离。
S1024、在所述第一绝缘层104上形成第一金属层105。
在所述第一绝缘层104上形成一金属层。该金属层的金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物。
在一种实施例中，所述第一金属层105的材料可以为钼。
对所述第一金属层使用第二光罩制程工艺，在所述第一金属层上形成第二光阻层，采用掩模板（未画出）曝光，经显影以及第二蚀刻的构图工艺处理后，使所述第一金属层形成图2A所示的所述第一金属层105，并剥离所述第二光阻层；
在一种实施例中，所述第一金属层105为阵列基板的栅极。
S1025、在所述第一金属层105上形成第二绝缘层106。
本步骤中，所述第二绝缘层106为第二栅绝缘层，所述第一栅绝缘层将所述有源层103覆盖。所述第二栅绝缘层主要用于将所述第一金属层105和第二金属层107隔离。
在一种实施例中，所述第二绝缘层106的厚度为50~200nm。
在一种实施例中，所述第一栅绝缘层和所述第二栅绝缘层的材料可以为氮化硅，也可以使用氧化硅和氮氧化硅等。
S1026、在所述第二绝缘层106上形成第二金属层107。
所述第二金属层107的金属材料和所述第一金属层105的金属材料相同。通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物。
在一种实施例中，所述第二金属层107的金属材料可以为钼。
在一种实施例中，所述第二金属层107的厚度为150~250nm。
此步骤对形成第二金属层107的金属层采用第三光罩制程工艺，在该金属层上形成第三光阻层，采用掩模板（未画出）曝光，经显影以及第三蚀刻的构图工艺处理后，使该金属层形成所述阵列基板的第二金属层107。
在一种实施例中，所述第二金属层107的面积大于所述第一金属层105的面积。所述第一金属层105在所述第二金属层107上的正投影在所述第二金属层107内。
S1027、在所述第二金属层107上形成第三绝缘层108。
本步骤中，所述第三绝缘层108为间绝缘层，所述间绝缘层将所述第二金属层107覆盖。所述间绝缘层主要用于将所述第二金属层107和源漏极112隔离。
在一种实施例中，所述间绝缘层的厚度为50~200nm。
S103、对部分所述有源层103进行离子掺杂，使部分所述有源层103形成第一掺杂区109和第二掺杂区110。
如图2B~图2D所示，步骤S103具体包括：
S10311、利用第二金属层107和第一金属层105作为隔档层，对部分所述有源层103进行离子掺杂，使部分所述有源层103形成第一掺杂区109。
请参阅图2B，本步骤主要以所述第二金属层107和所述第一金属层105作为阻挡层，对所述有源层103进行离子注入。离子掺杂，使部分所述有源层103形成第一掺杂区109。
在一种实施例中，掺杂的离子为高浓度P+，所述第一掺杂区109也被称为重掺杂区。
S10312、利用预定工艺对所述第一掺杂区109进行处理，使所述第一掺杂区109的部分离子向所述第一掺杂区109的四周扩散，使部分所述有源层103形成第二掺杂区110。
请参阅图2C，本步骤主要利用预定工艺对所述第一掺杂区109进行处理，所述预定工艺为高温活化和氢化工艺，使所述第一掺杂区109的部分离子向所述第一掺杂区109的四周扩散，使部分所述有源层103形成第二掺杂区110。
在一种实施例中，所述第一掺杂区109的离子浓度大于所述第二掺杂区110的离子浓度。
请参阅图2D，在所述第三绝缘层108表面形成过孔111，使得后面形成的源漏极112与所述第一掺杂区109连接。
在一种实施例中，由于需要利用所述第一金属层以及所述第二金属层作遮挡层进行离子掺杂，以形成不同区域的轻掺杂区域和重掺杂区域。因此，所述第一金属层以及所述第二金属层的面积大小不一致，存在一定的差异。
请参阅图3，图3本申请实施例一阵列基板第一种俯视图。图2D为图3中截面AA的剖视图；
首先，以第一金属层105作为第一遮挡层，对所述有源层103进行第一次离子掺杂。其次，以第二金属层107作为第二遮挡层，对所述有源层103进行第二次离子掺杂，即形成图2D所示的图案。
本实施例还可以通过所述过孔111对所述有源层103进行第二次离子掺杂。通过调节掺杂的离子浓度，以使所述第二掺杂区的面积达到图2D所示的图案。
如图2E~图2G所示，步骤S103还可以包括：
S10321、在所述第三绝缘层108上形成过孔111。
请参阅图2E，本步骤中，在所述第三绝缘层108表面形成过孔111。所述过孔111贯穿所述第三绝缘层108、第二绝缘层106以及部分第一绝缘层104，使部分所述有源层103裸露。
在一种实施例中，所述过孔111的形状可以为多边形或圆形。
在一种实施例中，所述过孔111为圆形。
S10322、对所述有源层103裸露的部分进行离子掺杂，使部分所述有源层103形成所述第一掺杂区109。
请参阅图2F，本步骤主要包括对部分裸露的所述有源层103进行离子注入，使部分裸露的所述有源层103形成第一掺杂区109。
在一种实施例中，掺杂的离子为高浓度P+，所述第一掺杂区109也可被称为重掺杂区。
由于只有过孔111所对应的所述有源层103进行离子注入，因此所述第一掺杂区109的形状和所述过孔111的形状相同。
在一种实施例中，所述第一掺杂区109的形状为多边形或圆形。
在一种实施例中，所述第一掺杂区109的形状为圆形。
当硼离子的注入量超过一定值，与过孔111对应的部分所述有源层103包含的硼离子达到临界值，硼离子将会向周边扩散。
在一种实施例中，硼离子的扩散也会出现所述第一掺杂区109的形状和所述过孔111的形状不相同的情况。
硼离子将会向周边扩散，设定离子注入量未超过临界值。
S10323、利用预定工艺对所述第一掺杂区109进行处理，使所述第一掺杂区109的部分离子向所述第一掺杂区109的四周扩散，使部分所述有源层103形成所述第二掺杂区110。
请参阅图2G，本步骤主要利用预定工艺对所述第一掺杂区109进行处理。所述预定工艺为高温活化和氢化工艺，使所述第一掺杂区109的部分离子向所述第一掺杂区109的四周扩散，使部分所述有源层103形成第二掺杂区110。
在一种实施例中，所述第一掺杂区109的离子浓度大于所述第二掺杂区110的离子浓度。
当所述过孔111对应所述有源层103的边缘时，形成图2G所示的图案。所述第二掺杂区110的面积大于所述第二金属层107的面积与所述第一金属层105的面积的差值。
当掺杂量增加到一定值，例如超过临界值时，所述第二掺杂区110的面积可能出现等于或小于所述第二金属层107的面积与所述第一金属层105的面积的差值。
当所述过孔111未位于所述有源层103的边缘时，形成图2H所示的图案。所述第二掺杂区110包围所述第一掺杂区109，所述第二掺杂区110的面积大于所述第二金属层107的面积与所述第一金属层105的面积的差值。
在一种实施例中，当离子的注入量超过临界值时，则可能形成图2G所示的图案。
因此，所述第一掺杂区109和所述第二掺杂区110最终的图案可以多种，不限于本实施例中所列举的两种图案。
本申请通过形成不同的第一金属层和第二金属层，从而对所述有源层的第一掺杂区和第二掺杂区的大小进行一定的限定；但在实际生产中，当所述第二金属层不作为遮挡层时，所述第二金属层的大小可以与所述第一金属层的相同。
请参阅图4，图4本申请实施例一阵列基板第二种俯视图。图2H为图4中截面BB的剖视图。
本实施例与图3不同之处在于：
本实施例未以第二金属层107作为遮挡层进行第二次离子掺杂，而直接通过所述过孔111对所述有源层进行第二次离子掺杂。因此，调节第二次离子掺杂的离子浓度，使所述第二掺杂区的面积达到图2H所示的方案。
S104、在所述第三绝缘层108上形成源漏极112。
请参阅图2I，本步骤中，在所述第三绝缘层108上形成所述源漏极112。所述源漏极112的金属材料和所述第一金属层105及所述第二金属层107的材料可以相同。通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物。
在一种实施例中，所述源漏极112的金属材料可以为钛铝合金，所述源漏极112的厚度为400~600nm。
本步骤包括：对形成所述源漏极112的金属层采用第四光罩制程工艺，在该金属层上形成第四光阻层，采用掩模板（未画出）曝光，经显影以及第四蚀刻的构图工艺处理后，使该金属层形成所述源漏极112。
在一种实施例中，所述源漏极112通过所述过孔111与所述第一掺杂区109连接。
在所述第二源漏极112上形成平坦层113。所述平坦层113用于保证膜层结构的平整，形成图2J或图2K中的膜层结构。
最后，进行OLED等相关的工艺。
实施例二
请参阅图5，图5为本申请实施例二阵列基板的制作方法的步骤图。所述制作方法包括步骤：
S201、提供一基板201。
S202、在所述基板201上依次形成缓冲层202、有源层203、第一绝缘层204、第一金属层205。
请参阅图6A~6J，图6A~6J为本申请实施例二阵列基板的制作方法的工艺图。
请参阅图6A，所述步骤S201和所述步骤S202与具体实施例一相同，本实施例不再一一赘述。
S203、对部分所述有源层203进行第一次离子掺杂，使部分所述有源层203形成第二掺杂区210。
请参阅图6B，本步骤包括以所述第一金属层205作为阻挡层，对所述有源层203进行第一次离子注入形成掺杂区。
在一种实施例中，掺杂的离子为高浓度P-，所述第二掺杂区210也可被称为轻掺杂区，所述第二掺杂区210位于所述有源层203沟道区的两侧。
在一种实施例中，使所述第一金属层205图案化的光阻层也可与所述第一金属层205同时作为隔档层，完成离子注入后，剥离该光阻层。
S204、在所述第一金属层205上形成第二绝缘层。
S205、在所述第二绝缘层上依次形成第二金属层207和第三绝缘层208。
步骤S205主要包括：
S20511、在所述第二绝缘层上形成第二金属层207。
S20512、利用所述第二金属层207作为隔档层，对部分所述有源层203进行第二次离子掺杂，使部分所述有源层203形成第一掺杂区209。
请参阅图6C所示，本步骤包括利用所述第二金属层207作为隔档层，对部分所述有源层203进行离子注入，使部分的所述有源层203形成第一掺杂区209。
在一种实施例中，掺杂的离子为高浓度P+，所述第一掺杂区209也可被称为重掺杂区。
S20513、在所述第二金属层207上形成第三绝缘层208。
请参阅图6D所示，本步骤S2051，同样可以在形成第三绝缘层208之后，对部分所述有源层203进行离子注入。
本步骤还可以包括：
S20521、在所述第二绝缘层上形成第二金属层207。
本步骤中，形成所述第二金属层207的步骤与具体实施例一中相同，但是保留使所述第二金属层207图案化的光阻层214。
S20522、利用所述第二金属层207和使所述第二金属层207图案化的光阻层214作为隔档层，对部分所述有源层203进行第二次离子掺杂，使部分所述有源层203形成第一掺杂区209。
请参阅图6E，本步骤包括利用所述第二金属层207和使所述第二金属层207图案化的光阻层作为隔档层，对部分所述有源层203进行第二次离子注入。使部分的所述有源层203形成第一掺杂区209。
在一种实施例中，掺杂的离子为高浓度P+，所述第一掺杂区209也可被称为重掺杂区。
S20523、在所述第二金属层207上形成第三绝缘层208。
本步骤中，主要形成图6D所示图案。
本步骤还可以包括：
S20531、在所述第二绝缘层上形成第二金属层207和经图案化的第二绝缘层。
请参阅图6F，本步骤中，对形成所述第二金属层207的金属层和所述第二绝缘层同时进行图案化，形成所述第二金属层207和经图案化的第二绝缘层。
S20532、利用所述第二金属层207和经图案化的第二绝缘层作为隔档层，对部分所述有源层203进行第二次离子掺杂，使部分所述有源层203形成第一掺杂区209。
请参阅图6F，本步骤包括利用所述第二金属层207和经图案化的第二绝缘层作为隔档层，对部分所述有源层203进行第二次离子注入。使部分的所述第二掺杂区210形成第一掺杂区209。
在一种实施例中，掺杂的离子为高浓度P+，所述第一掺杂区209也可被称为重掺杂区。
S20533、在所述第二金属层207上形成第三绝缘层208。
请参阅图6G，在步骤S2053中，使所述第二金属层207图案化的光阻层，同样可以保留作为隔档层，完成第二次离子掺杂后，剥离该光阻层。
在步骤S205中，由于第一掺杂区209为高浓度硼离子，所述第二掺杂区210为低浓度硼离子。因此所述第一掺杂区209的离子浓度大于所述第二掺杂区210的离子浓度。
所述第一掺杂区209和所述第二掺杂区210最终的图案可以多种，与具体实施例一相同。完成离子注入，为了控制所述第一掺杂区209和第二掺杂区210的面积，可以采用预定工艺对掺杂区的离子浓度进行处理。
S206、在所述第三绝缘层208上形成过孔211。
请参阅图6H，在所述第三绝缘层208表面形成过孔211。所述过孔211贯穿所述第三绝缘层208、第二绝缘层206以及部分所述第一绝缘层204，使得部分所述第一掺杂区209裸露。
S207、在所述第三绝缘层208上形成源漏极212。
请参阅图6I，所述源漏极212通过所述过孔211与所述第一掺杂区209连接。
最后，在所述第二源漏极212上形成平坦层213，保证膜层结构的平正，形成如图6H或图2K所示的膜层结构。
最后，进入OLED等相关的工艺。
本申请提出了一种阵列基板的制作方法，所述制作方法为通过对所述有源层进行一次离子掺杂，利用特定工艺使经过掺杂的所述有源层形成第一掺杂区和第二掺杂区210。本申请通过在现有工艺以及未增加光罩的基础上，在AMOLED中增加PMOS的LDD结构，有效的降低了面板阵列制造过程中的周期，节省制作成本。
实施例三
请参阅图7，图7为本申请实施例三阵列基板的第一种膜层结构图。
所述阵列基板包括基板301、缓冲层、有源层303、第一绝缘层304、第一金属层305、第二绝缘层、第二金属层307、第三绝缘层308、源漏极312以及平坦化层。
所述基板301的可以为玻璃基板、石英基板、树脂基板等中的一种。
所述缓冲层形成于所述基板301上，主要用于缓冲膜层质结构之间的压力，并且还可以具有一定阻水氧的功能。
所述有源层303形成于所述缓冲层上，所述有源层303包括经离子掺杂的第一掺杂区309和第二掺杂区310。第一掺杂区309为高浓度硼离子，所述第二掺杂区310为低浓度硼离子。
在一种实施例中，所述第一掺杂区309的离子浓度大于所述第二掺杂区310的离子浓度。
所述第一绝缘层304形成于所述有源层303上。
在一种实施例中，所述第一绝缘层304为第一栅绝缘层，所述第一栅绝缘层将所述有源层303覆盖，所述第一栅绝缘层主要用于将所述有源层303与其他金属层隔离。
所述第一金属层305形成于所述第一绝缘层304上。所述第一金属层305的金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物。
第二绝缘层306，形成于所述第一金属层305上。
在一种实施例中，所述第二绝缘层306为第二栅绝缘层，所述第一栅绝缘层将所述有源层303覆盖，所述第二栅绝缘层主要用于将所述第一金属层305和第二金属层307隔离。
在一种实施例中，所述第二绝缘层306的厚度为50~200nm。所述第二栅绝缘层的材料可以为氮化硅，也可以使用氧化硅和氮氧化硅等。
所述第二金属层307形成于所述第二绝缘层306上，所述第二金属层307的材料和所述第一金属层305的相同。
在一种实施例中，所述第一金属层305和所述第二金属层307的金属材料可以为钼。
形成所述第二金属层307的金属层经图案化处理，形成面积大于所述第一金属层305的所述第二金属层307。所述第一金属层305在所述第二金属层307上的正投影在所述第二金属层307内。
第三绝缘层308，形成于所述第二金属层307上。
在一种实施例中，所述第三绝缘层308为间绝缘层，所述间绝缘层将所述第二金属层307覆盖，所述间绝缘层主要用于将所述第二金属层307和源漏极312隔离。
在一种实施例中，所述间绝缘层的厚度为50~200nm。
过孔311形成于所述第三绝缘层308成表面。所述过孔311贯穿所述第三绝缘层308、所述第二绝缘层306以及部分所述第一绝缘层304。
在一种实施例中，所述过孔311的形状可以为多边形或圆形。
在一种实施例中，所述过孔311为圆形。
源漏极312形成于所述第三绝缘层308上，所述源漏极312的金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金等金属，也可以使用上述几种金属材料的组合物。
在一种实施例中，所述源漏极312的金属材料可以为钛铝合金。所述源漏极312通过过孔311与所述第一掺杂区309连接。
平坦层313形成于所述源漏极312上，保证所述阵列基板膜层结构的平整性。
本实施例中，形成上述结构主要通过所述过孔311对裸露的部分所述有源层303进行一次离子注入，使部分所述有源层303形成第一掺杂区309。掺杂的离子为高浓度P+，所述第一掺杂区309也可被称为重掺杂区。
在一种实施例中，利用预定工艺对所述第一掺杂区309进行处理，所述预定工艺为高温活化和氢化工艺，使所述第一掺杂区309的部分离子向所述第一掺杂区309的四周扩散，使部分所述有源层303形成第二掺杂区310。
由于只有过孔311所对应的所述有源层303进行离子注入，因此所述第一掺杂区309的形状和所述过孔311的形状相同，即所述第一掺杂区309的形状为多边形或圆形。
在一种实施例中，所述第一掺杂区309为圆形。
当第一掺杂区309的离子注入量超过一定临界值时，该区域的硼离子将向四周扩散，导致所述第一掺杂区309的形状和所述过孔311的形状不相同，具体形状没有一定限制。
请参阅图7，所述过孔311靠近所述有源层303的边缘，即所述第二掺杂区310的面积等于所述第二金属层307的面积与所述第一金属层305的面积的差值。
请参阅图8，图8为本申请实施例三阵列基板的第二种膜层结构图。
所述第二掺杂区410包围所述第一掺杂区409，所述第二掺杂区410的面积大于所述第二金属层407的面积与所述第一金属层405的面积的差值。
所述第二掺杂区410主要用于承受电路中部分电压，即增大所述第二掺杂区410的面积，可更好的防止热电子退化效应，并且降低沟道漏电流的作用。
由于第一掺杂区和第二掺杂区的形状与离子浓度、离子注入量、有源层的形状、工艺以及人为因素等相关。因此，所述第一掺杂区和第二掺杂区的图案不限于本申请中的形状。
本申请还提出了一种显示面板，所述显示面板包括上述阵列基板，所述显示面板的工作原理与所述阵列基板的工作原理相同，此处不再赘述。
本申请提出了一种阵列基板及其制作方法、显示面板，所述制作方法为通过对所述有源层进行一次离子掺杂，利用特定工艺使经过掺杂的所述有源层形成第一掺杂区和第二掺杂区。本申请通过在现有工艺以及未增加光罩的基础上，在AMOLED中增加PMOS的LDD结构，有效的降低了面板阵列制造过程中的周期，节省了制作成本。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板的制作方法，其包括步骤：
    S101、提供一基板；
    S102、在所述基板上依次形成缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层以及第三绝缘层，
    其中，所述第二金属层的面积大于所述第一金属层的面积；
    S103、对部分所述有源层进行离子掺杂，使部分所述有源层形成第一掺杂区和第二掺杂区，
    所述第二掺杂区为所述第一掺杂区经预定工艺而形成；
    S104、在所述第三绝缘层上形成源漏极。
  2. 根据权利要求1所述的制作方法，其中，所述S103包括步骤：
    S10311、利用第二金属层和第一金属层作为隔档层，对部分所述有源层进行离子掺杂，使部分所述有源层形成第一掺杂区；
    S10312、利用预定工艺对所述第一掺杂区进行处理，使所述第一掺杂区的部分离子向所述第一掺杂区的四周扩散，使部分所述有源层形成第二掺杂区，
    其中，所述第一掺杂区的离子浓度大于所述第二掺杂区的离子浓度。
  3. 根据权利要求1所述的制作方法，其中，所述第二掺杂区包围所述第一掺杂区。
  4. 根据权利要求1所述的制作方法，其中，所述第二掺杂区的面积大于或等于所述第二金属层的面积与所述第一金属层的面积的差值。
  5. 根据权利要求1所述的制作方法，其中，所述S103包括步骤：
    S10321、在所述第三绝缘层上形成过孔，
    其中，所述过孔贯穿所述第三绝缘层、第二绝缘层以及部分第一绝缘层，使部分所述有源层在所述过孔处裸露；
    S10322、对所述有源层裸露的部分进行离子掺杂，以使部分所述有源层形成所述第一掺杂区；
    S10323、利用预定工艺对所述第一掺杂区进行处理，使所述第一掺杂区的部分离子向所述第一掺杂区的四周扩散，使部分所述有源层形成所述第二掺杂区。
  6. 根据权利要求5所述的制作方法，其中，所述第一掺杂区的形状和所述过孔的形状相同，所述第一掺杂区的形状为多边形或圆形。
  7. 根据权利要求1所述的制作方法，其中，形成所述第一掺杂区和所述第二掺杂区包括步骤：
    利用所述第一金属层作为隔档层，对部分所述有源层进行第一次离子掺杂，使部分所述有源层形成第二掺杂区；
    利用所述第二金属层作为隔档层，对部分所述有源层进行第二次离子掺杂，使部分所述有源层形成第一掺杂区。
  8. 根据权利要求7所述的制作方法，其中，利用所述第二金属层作为隔档层，对部分所述有源层进行第二次离子掺杂还包括步骤：
    利用所述第二金属层和使所述第二金属层图案化的光刻胶、所述第二金属层和经图案化的所述第二绝缘层、以及所述第二金属层、使所述第二金属层图案化的光刻胶和经图案化的所述第二绝缘作为隔档层，对部分所述有源层进行第二次离子掺杂，使部分所述有源层形成第一掺杂区。
  9. 一种阵列基板，其包括基板、位于所述基板上的有源层、位于所述有源层上的第一金属层、及位于所述第一金属层上的第二金属层；
    其中，所述有源层包括第一掺杂区和第二掺杂区，所述第二掺杂区的面积大于或等于所述第二金属层的面积与所述第一金属层的面积的差值。
  10. 根据权利要求9所述的阵列基板，其中，所述第二金属层的面积大于所述第一金属层的面积。
  11. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括至少两个过孔和源漏极层；
    所述源漏极层通过所述过孔与所述第二掺杂区电连接。
  12. 根据权利要求11所述的阵列基板，其中，所述第一掺杂区的形状和所述过孔的形状相同，所述第一掺杂区的形状为多边形或圆形。
  13. 根据权利要求9所述的阵列基板，其中，所述第二掺杂区包围所述第一掺杂区。
  14. 根据权利要求9所述的阵列基板，其中，所述第一掺杂区的离子浓度大于所述第二掺杂区的离子浓度。
  15. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列阵列包括基板、位于所述基板上的有源层、位于所述有源层上的第一金属层、及位于所述第一金属层上的第二金属层；
    其中，所述有源层包括第一掺杂区和第二掺杂区，所述第二掺杂区的面积大于或等于所述第二金属层的面积与所述第一金属层的面积的差值。
  16. 根据权利要求15所述的显示面板，其中，所述第二金属层的面积大于所述第一金属层的面积。
  17. 根据权利要求15所述的显示面板，其中，所述阵列基板还包括至少两个过孔和源漏极层；
    所述源漏极层通过所述过孔与所述第二掺杂区电连接。
  18. 根据权利要求17所述的显示面板，其中，所述第一掺杂区的形状和所述过孔的形状相同，所述第一掺杂区的形状为多边形或圆形。
  19. 根据权利要求15所述的显示面板，其中，所述第二掺杂区包围所述第一掺杂区。
  20. 根据权利要求15所述的显示面板，其中，所述第一掺杂区的离子浓度大于所述第二掺杂区的离子浓度。
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Families Citing this family (2)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681628A (zh) * 2015-03-17 2015-06-03 京东方科技集团股份有限公司 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
CN105140130A (zh) * 2015-09-29 2015-12-09 信利（惠州）智能显示有限公司 低温多晶硅薄膜晶体管及其制备方法
CN105161496A (zh) * 2015-07-30 2015-12-16 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制造方法、显示装置
CN105390451A (zh) * 2015-12-03 2016-03-09 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法
US20180122955A1 (en) * 2015-04-28 2018-05-03 Sharp Kabushiki Kaisha Semiconductor device and method for manufacturing same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953582A (en) * 1993-02-10 1999-09-14 Seiko Epson Corporation Active matrix panel manufacturing method including TFTS having variable impurity concentration levels
KR100198556B1 (ko) * 1995-11-22 1999-07-01 구자홍 박막트랜지스터의 구조 및 제조방법
KR102081283B1 (ko) * 2013-02-14 2020-04-16 삼성디스플레이 주식회사 박막 반도체 장치, 유기 발광 표시 장치, 및 이의 제조 방법
KR101679252B1 (ko) * 2014-09-30 2016-12-07 엘지디스플레이 주식회사 박막 트랜지스터 기판과 그 제조방법 및 그를 이용한 디스플레이 장치
KR102665322B1 (ko) * 2016-06-24 2024-05-16 삼성디스플레이 주식회사 박막 트랜지스터 기판, 및 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681628A (zh) * 2015-03-17 2015-06-03 京东方科技集团股份有限公司 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
US20180122955A1 (en) * 2015-04-28 2018-05-03 Sharp Kabushiki Kaisha Semiconductor device and method for manufacturing same
CN105161496A (zh) * 2015-07-30 2015-12-16 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制造方法、显示装置
CN105140130A (zh) * 2015-09-29 2015-12-09 信利（惠州）智能显示有限公司 低温多晶硅薄膜晶体管及其制备方法
CN105390451A (zh) * 2015-12-03 2016-03-09 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法

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