WO2020173205A1 - Cmos薄膜晶体管及其制作方法和阵列基板 - Google Patents

Cmos薄膜晶体管及其制作方法和阵列基板 Download PDF

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WO2020173205A1
WO2020173205A1 PCT/CN2019/128284 CN2019128284W WO2020173205A1 WO 2020173205 A1 WO2020173205 A1 WO 2020173205A1 CN 2019128284 W CN2019128284 W CN 2019128284W WO 2020173205 A1 WO2020173205 A1 WO 2020173205A1
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region
type
layer
gate
ion doping
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PCT/CN2019/128284
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English (en)
French (fr)
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姚磊
方业周
李峰
闫雷
薛进进
王成龙
孟艳艳
王金锋
候林
郭志轩
李元博
李晓芳
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/963,937 priority Critical patent/US20210217894A1/en
Publication of WO2020173205A1 publication Critical patent/WO2020173205A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to CMOS thin film transistors, manufacturing methods thereof, and array substrates.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • the existing CMOS (Complementary Metal Oxide Semiconductor) products of TFT-LCD need to be formed by multiple channel doping (P-type ion doping or N-type ion doping) in the manufacturing process of the array substrate (Array substrate) MOS tube (field effect tube), but due to the difference in the design and working principle of PMOS (P-type metal-oxide-semiconductor) and NMOS (N-type metal-oxide-semiconductor), it needs to be carried out in the Array process.
  • the secondary doping (Doping) process includes: Channel Doping, Threshold Voltage Doping (Vth Doping), N+Doping, Lightly Doped Drain Structure (LDD Doping) and P+Doping.
  • Vth Doping Threshold Voltage Doping
  • LDD Doping Lightly Doped Drain Structure
  • P+Doping P+Do
  • the present disclosure provides a method of manufacturing a CMOS thin film transistor.
  • the method of manufacturing a CMOS thin film transistor includes:
  • Step 1 A semiconductor layer is formed on a substrate, the semiconductor layer includes N-type regions and P-type regions spaced apart in the same layer, wherein,
  • the N-type area is sequentially divided into a first area, a second area, a third area, a fourth area, and a fifth area for forming an N-type thin film transistor, wherein the first area is used to form a first heavily doped area.
  • the miscellaneous drain region, the second region and the fourth region are used to form a lightly doped drain region, the third region is used to form the inner region of the first gate, and the fifth region is used to form the second A heavily doped source region,
  • the P-type region is sequentially divided into a sixth region, a seventh region, and an eighth region for forming a P-type thin film transistor, wherein the sixth region is used to form a second heavily doped drain region, and the first The seventh region is used to form the inner region of the second gate, and the eighth region is used to form the second heavily doped source region;
  • Step 2 Perform first N-type ion doping on the first region and the fifth region;
  • Step 3 Performing first P-type ion doping on the N-type region
  • Step 4 Perform a second P-type ion doping on the N-type region and the P-type region in the product obtained in Step 3;
  • Step 5 Perform a second N on the first zone, the second zone, the fourth zone, the fifth zone, the sixth zone, and the eighth zone in the product obtained in step 4.
  • Step 6 Perform third P-type ion doping on the sixth region and the eighth region in the product obtained in step 5, wherein the first N-type ion doping and the first P-type ion doping The doping is done through the same halftone mask.
  • the steps of the first N-type ion doping and the first P-type ion doping include: forming a first N-type ion doping on the upper surface of the semiconductor layer by using the half-tone mask.
  • a patterned photoresist layer includes a first layer and a second layer, the first layer covers the surface of the P-type region, and the second layer covers the On the surfaces of the second area, the third area, and the fourth area, wherein the thickness of the second layer is less than the thickness of the first layer;
  • the first N-type ion doping is performed in the five regions; the second layer is removed, and the first layer is thinned to obtain a second patterned photoresist layer, the second patterned photoresist A layer covering the surface of the P-type region; performing the first P-type ion doping on the exposed N-type region; and removing the second patterned photoresist layer.
  • the second layer is removed through an ashing process, and the first layer is thinned to obtain the second patterned photoresist layer.
  • the thickness of the second layer is 30% to 70% of the thickness of the first layer.
  • the thickness of the first layer is 1 to 2.5 microns
  • the thickness of the second layer is 0.5 to 1.75 microns
  • the ashing time is 10-40 seconds.
  • the thickness of the second patterned photoresist layer is 30% to 70% of the thickness of the first layer.
  • the method further includes: forming a gate on the surface of the N-type region and the P-type region.
  • An insulating layer forming a first gate and a second gate on the surface of the gate insulating layer, wherein the orthographic projection of the first gate on the substrate and the third area on the liner
  • the orthographic projection on the bottom overlaps, the orthographic projection of the second gate on the substrate overlaps the orthographic projection of the seventh area on the substrate, and the second N-type ion doping is based on
  • the first grid and the second grid are performed by a mask.
  • the step of performing the third P-type ion doping includes: forming a third patterned photoresist layer on the surface of the gate insulating layer corresponding to the N-shaped region, the third pattern A photoresist layer covers the first gate, and the sixth area and the eighth area are performed using the third patterned photoresist layer and the second gate as a mask.
  • the third P-type ion doping includes: forming a third patterned photoresist layer on the surface of the gate insulating layer corresponding to the N-shaped region, the third pattern A photoresist layer covers the first gate, and the sixth area and the eighth area are performed using the third patterned photoresist layer and the second gate as a mask.
  • the semiconductor layer is a polysilicon layer.
  • the present disclosure provides a CMOS thin film transistor.
  • the CMOS thin film transistor is manufactured by the foregoing method of manufacturing the CMOS thin film transistor. Therefore, the CMOS thin film transistor has a short production cycle, low production cost, and still has good characteristics and performance.
  • the CMOS thin film transistor has all the features and advantages of the aforementioned method for manufacturing a CMOS thin film transistor, and will not be repeated here.
  • the CMOS thin film transistor includes an N-type thin film transistor and a P-type thin film transistor, wherein the N-type thin film transistor includes a first heavily doped drain region, a lightly doped drain region, and a first The gate inner region and the first heavily doped source region, wherein the orthographic projection of the first gate inner region on the substrate overlaps the orthographic projection of the first gate on the substrate, and the light
  • the doped drain region is arranged at opposite ends of the inner region of the first gate, and the first heavily doped drain region is arranged on the lightly doped drain region away from the inner region of the first gate.
  • the first heavily doped source region is disposed at the other end of the lightly doped drain region away from the inner region of the first gate;
  • the P-type thin film transistor includes a second heavily doped drain region , The second gate inner region and the second heavily doped source region, wherein the orthographic projection of the second gate inner region on the substrate and the orthographic projection of the second gate on the substrate Overlapping, the second heavily doped drain region and the second heavily doped source region are respectively arranged at opposite ends of the inner region of the second gate.
  • the present disclosure provides an array substrate.
  • the array substrate includes the aforementioned CMOS thin film transistor. Therefore, on the basis of ensuring the good characteristics and use performance of the array substrate, the manufacturing process time of the array substrate is shorter, thereby reducing the manufacturing cost of the array substrate and improving the market competitiveness.
  • the array substrate has all the features and advantages of the aforementioned CMOS thin film transistors, which will not be repeated here.
  • FIG. 1 is a flowchart of a method for manufacturing a CMOS thin film transistor in an embodiment of the present disclosure.
  • FIG. 2 is a flow chart of the structure of manufacturing a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 3 is a flow chart of the structure of manufacturing CMOS thin film transistors in another embodiment of the present disclosure.
  • FIG. 4 is a flow chart of the structure of manufacturing a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a method for fabricating a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 6 is a flow chart of the structure of fabricating a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 7 is a flow chart of the structure of manufacturing a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 8 is a structure flow chart of manufacturing a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 9 is a flow chart of the structure of manufacturing CMOS thin film transistors in another embodiment of the present disclosure.
  • FIG. 10 is a flow chart of the structure of fabricating a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 11 is a flow chart of the structure of manufacturing a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 12 is a flow chart of the structure of fabricating CMOS thin film transistors in another embodiment of the present disclosure.
  • FIG. 13 is a flow chart of the structure of fabricating CMOS thin film transistors in another embodiment of the present disclosure.
  • FIG. 14 is a flow chart of the structure of manufacturing a CMOS thin film transistor in another embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the structure of a CMOS thin film transistor in another embodiment of the present disclosure.
  • the present disclosure provides a method of manufacturing a CMOS thin film transistor. It solves one of the technical problems in related technologies at least to a certain extent.
  • An object of the present disclosure is to provide a method for manufacturing CMOS thin film transistors that has the advantages of simplifying the process flow, shortening the manufacturing process time, or reducing the manufacturing cost.
  • a method of manufacturing a CMOS thin film transistor includes:
  • Step 1 A semiconductor layer is formed on the substrate 10.
  • the semiconductor layer includes an N-type region 20 and a P-type region 30 spaced apart in the same layer.
  • the N-type region 20 is sequentially divided into a first region 21 and a second region.
  • the N-type region 20 is used to form an N-type thin film transistor, wherein the first region is used to form a first heavily doped drain region, and the second region And the fourth region are used to form the lightly doped drain region, the third region is used to form the inner region of the first gate, and the fifth region is used to form the first heavily doped source region; the P-type region 30 is divided into the first The sixth region 36, the seventh region 37 and the eighth region 38, the P-type region 30 is used to form a P-type thin film transistor, wherein the sixth region is used to form the second heavily doped drain region, and the seventh region is used to form the Two gate inner regions, and the eighth region is used to form the second heavily doped source region.
  • the first heavily doped drain region and the first heavily doped source region are respectively used for electrical connection with the drain and source of the N-type thin film transistor, and are doped with high-concentration N-type ions (such as phosphorous ions) for The conduction of the N-type thin film transistor provides a large amount of free electrons, and the resistance in this area is small, which can be equivalent to a conductor;
  • the hot carrier effect is improved by low concentration doping.
  • the principle is to implant the second region and the first region with a lower dose (compared with the heavily doped source and drain regions).
  • the ion dose injected is between the heavily doped source and drain area and the doping amount of the gate inner area, thereby forming a certain concentration buffer area, thereby reducing the edge electric field gradient at the drain end and the hot carrier effect , Thereby reducing the leakage current of the N-type thin film transistor;
  • the first gate inner region and the second gate inner region are used to control the conduction of the semiconductor layer.
  • a positive voltage is applied to the N-type thin film transistor, part of the free electrons in the lightly doped drain region is transferred to
  • the surface of the semiconductor (the semiconductor can be polysilicon) in the inner region of the first gate makes the semiconductor layer of the N-type thin film transistor in a conductive state.
  • the drain region is lightly doped The electrons in the inner region of the first gate will not be transferred to the inner region of the first gate.
  • the resistance in the inner region of the first gate is so large that the semiconductor layer of the N-type thin film transistor is turned off; when a negative pressure is applied to the P-type thin film transistor , Part of the holes in the lightly doped drain region are transferred to the inner region of the second gate, so that the semiconductor layer of the P-type thin film transistor is in a conductive state.
  • a positive voltage or no voltage is applied to the P-type thin film transistor, the light The holes in the doped drain region will not be transferred to the inner region of the second gate, and the resistance in the inner region of the first gate is so large that the semiconductor layer of the P-type thin film transistor is turned off;
  • the second heavily doped drain region and the second heavily doped source region are respectively used for electrical connection with the drain and source of the P-type thin film transistor, and are doped with high concentration of P-type ions (such as boron ions) for
  • P-type ions such as boron ions
  • the conduction of the P-type thin film transistor provides a large amount of holes, and the resistance in this area is small, which can be equivalent to a conductor.
  • the material forming the substrate includes, but is not limited to, a polymer substrate or a glass substrate.
  • the semiconductor layer is a polysilicon layer.
  • the semiconductor has larger carriers and better electrical characteristics.
  • there is no restriction on the method of forming the semiconductor layer and those skilled in the art can flexibly choose according to actual conditions.
  • the method of forming a semiconductor layer is: forming amorphous silicon (a-Si) on a substrate by a chemical vapor deposition method (such as plasma enhanced chemical vapor deposition) ) Layer, and then through excimer laser annealing (ELA) to make amorphous silicon form polysilicon, and then obtain a polysilicon layer.
  • a-Si amorphous silicon
  • ELA excimer laser annealing
  • Step 2 Perform the first N-type ion doping (N+Doping) on the first region 21 and the fifth region 25.
  • N+Doping N-type ion doping
  • the doping concentration and energy of the first N-type ion doping are not limited, and those skilled in the art can choose flexibly according to actual conditions.
  • the concentration of the first N-type ion doping is 1E14-8E14, and the energy is 10kEV-60kEV.
  • Step 3 Perform a first P-type ion doping (Vth Doping) on the N-type region 20 (including the first region to the fifth region) in the product obtained in Step 2, and refer to FIG. 4 for the structural diagram.
  • Vth Doping a first P-type ion doping
  • the doping concentration and energy of the first P-type ion doping have no limitation requirements, and those skilled in the art can choose flexibly according to actual conditions.
  • the concentration of the first P-type ion doping is 1E14-8E14, and the energy is 10kEV-60kEV.
  • the first N-type ion doping and the first P-type ion doping are performed through the same halftone mask.
  • the specific steps include:
  • the first patterned photoresist layer includes a first layer 41 and a second layer 42, and the first layer 41 covers On the surface of the P-type region 30, the second layer 42 covers the surfaces of the second region 22, the third region 23, and the fourth region 24, wherein the thickness of the second layer 42 is smaller than the thickness of the first layer 41, a schematic structural view Refer to Figure 6.
  • the thickness of the second layer is 30% to 70% of the thickness of the first layer, for example, 30%, 35%, 40%, 50%, 55%, 60%, 65% or 70%. Therefore, not only can the second layer effectively block the doped ions from entering the second region 22, the third region 23, and the fourth region 24, but also ensure that the second layer can be effectively removed in the subsequent process. It can also be ensured that the thinned first layer will not be too thin, so as to prevent ions from entering the P-type region during the first P-type ion doping and affecting the characteristics of the CMOS thin film transistor.
  • the specific thickness of the first layer and the second layer has no special requirements. Those skilled in the art can flexibly design according to the actual conditions such as the dose and energy of ion doping.
  • the thickness of the first layer The thickness is 1.5 microns, and the thickness of the second layer is 0.75 microns.
  • the method for forming the first patterned photoresist layer by using the halftone mask 50 has no restriction requirements, and those skilled in the art can flexibly choose conventional technical means for implementation according to actual needs, specifically:
  • the positive photoresist layer 40 is first formed on the semiconductor layer, and the positive photoresist layer 40 is exposed by the halftone mask 50, wherein the halftone mask 50 is The fully exposed area 51 corresponds to the positive photoresist layer 40 covered on the surface of the first area 21 and the fifth area 25, and the half-exposed area 52 in the halftone mask 50 corresponds to the second area 22 and the third area 23 And the positive photoresist layer 40 covered on the surface of the fourth region 24, the non-exposed area 53 in the halftone mask 50 is provided corresponding to the positive photoresist layer 40 covered on the surface of the P-type region 30, a schematic structural view Referring to FIG. 7, after exposure and development, the first patterned photoresist layer shown in FIG. 6 including the first layer 41 and the second layer 42 with different thicknesses is obtained.
  • a negative photoresist layer is first formed on the semiconductor layer, and the negative photoresist layer is exposed using a halftone mask, wherein the halftone mask is not exposed
  • the area corresponds to the negative photoresist layer covering the surface of the first area 21 and the fifth area 25, and the half-exposure area 52 in the halftone mask corresponds to the surface of the second area 22, the third area 23 and the fourth area 24
  • the negative photoresist layer covered on the top is set, and the fully exposed area in the halftone mask corresponds to the positive photoresist layer covered on the surface of the P-type region 30 (not shown in the figure), and then after exposure and development ,
  • the first patterned photoresist layer including the first layer 41 and the second layer 42 with different thicknesses as shown in FIG. 6 is obtained.
  • S200 Perform first N-type ion doping on the exposed first region 21 and the fifth region 25. Refer to FIG. 8 for a schematic structural view.
  • the first N-type ion doping performed here is consistent with the first N-type ion doping requirement in step 2 above, and will not be repeated here.
  • the thickness of the second patterned photoresist layer is 30% to 70% of the thickness of the first layer, for example, 30%, 35%, 40%, 50%, 55%, 60%, 65% or 70%. Therefore, the second patterned photoresist layer obtained after the first layer is thinned will not be too thin, and the first P-type ion doping can effectively block ions from entering the P-type region, which affects the characteristics of the CMOS thin film transistor.
  • the second layer 42 is removed by an ashing process, and the first layer 41 is thinned to obtain
  • the second patterned photoresist layer 43 specifically, the second patterned photoresist layer is ashed by using O 2 gas in the ashing process, and the time of ashing is precisely controlled for effective removal
  • the first layer of photoresist (PR), and a certain thickness of the second layer of photoresist is reserved, to obtain the second patterned photoresist layer 43 with this thickness, and the second patterned photoresist layer is guaranteed
  • the doping of ions into the P-type region can be blocked.
  • the thickness of the first layer is 1 ⁇ 2.5 microns (such as 1 micron, 1.2 microns).
  • the thickness of the second layer is 0.5 to 1.75 microns (such as 0.5 microns, 0.7 microns, 0.9 microns, 1.0 microns, 1.1 microns, 1.3 microns, 1.5 microns, 1.6 microns, 1.75 microns), the ashing time is 10-40 seconds, such as 10 seconds, 15 seconds, 20 seconds, 25 seconds, 30 seconds, 35 seconds or 40 seconds.
  • those skilled in the art can flexibly set the ashing time according to the actual conditions such as the specific thickness of the first layer and the second layer, so as to ensure that the second layer is effectively removed while obtaining a second patterned lithography with a suitable thickness.
  • Glue layer
  • S400 Perform first P-type ion doping on the entire exposed N-type region 20. Refer to FIG. 10 for a schematic structural view.
  • the first P-type ion doping performed here is consistent with the first P-type ion doping requirement in the previous step 3, which will not be repeated here.
  • the second patterned photoresist layer can be removed by an ashing process, or a corresponding developer can be used according to the specific photoresist type of the second patterned photoresist layer, so as to effectively and completely The second patterned photoresist layer is removed without affecting the performance of the semiconductor layer.
  • Step 4 Perform a second P-type ion doping (Channel Doping) on the N-type region 20 and the P-type region 30 in the product obtained in Step 3.
  • a second P-type ion doping (Channel Doping) on the N-type region 20 and the P-type region 30 in the product obtained in Step 3.
  • FIG. 11 for the structural diagram. Therefore, through the two steps of doping of the first P-type ion doping and the second P-type ion doping, the difference in the amount of doping ion implantation in the semiconductor layer is generated, thereby adjusting the threshold voltage of the CMOS thin film transistor.
  • the doping concentration and energy of the second P-type ion doping are not limited, and those skilled in the art can choose flexibly according to actual conditions.
  • the concentration of the second P-type ion doping is 1E14-8E14, and the energy is 10kEV-60kEV.
  • Step 5 Perform the second N-type ion doping (LDD) on the first region 21, the second region 22, the fourth region 24, the fifth region 25, the sixth region 36 and the eighth region 38 in the product obtained in step 4.
  • LDD second N-type ion doping
  • Figure 12 for the schematic structure diagram.
  • the doping concentration and energy of the second N-type ion doping are not limited, and those skilled in the art can choose flexibly according to actual conditions.
  • the concentration of the second N-type ion doping is 1E14-8E14, and the energy is 10kEV-60kEV.
  • the second N-type ion doping Before mixing, it further includes: forming a gate insulating layer 60 on the surface of the N-type region 20 and the P-type region 30; forming a first gate 71 and a second gate 72 on the surface of the gate insulating layer 60, wherein the first The orthographic projection of the grid 71 on the substrate 10 overlaps the orthographic projection of the third region 23 on the substrate 10, and the orthographic projection of the second grid 72 on the substrate 10 is identical to that of the seventh region 37 on the substrate 10.
  • the orthographic projections overlap, where the second N-type ion doping is performed using the first grid and the second grid as masks. Therefore, ion doping is performed using the first gate and the second gate as the mask, thereby saving a mask and shortening the process time.
  • the method for forming the insulating layer includes, but is not limited to, chemical vapor deposition (such as plasma enhanced chemical vapor deposition) or physical vapor deposition (such as magnetron sputtering); forming gate insulation
  • the material of the layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, organic insulating materials, and the like.
  • the method and material for forming the first gate and the second gate are not limited, and those skilled in the art can flexibly choose according to actual conditions.
  • the step of forming the first gate and the second gate includes: depositing a gate metal layer on the surface of the gate insulating layer, and then obtaining the first gate through an etching process.
  • the second grid; the materials forming the first grid and the second grid include, but are not limited to, nickel, tungsten, molybdenum, chromium, nickel-manganese alloy, nickel-chromium alloy, nickel-molybdenum-iron alloy, tungsten-molybdenum alloy and other materials. Therefore, the first gate and the second gate made of the above materials have good characteristics.
  • Step 6 Perform the third P-type ion doping (P+Doping) on the sixth region 36 and the eighth region 38 in the product obtained in step 5.
  • P+Doping P-type ion doping
  • the doping concentration and energy of the third-type ion doping are also not limited, and those skilled in the art can choose flexibly according to actual conditions.
  • the concentration of the third-type ion doping is 1E14-8E14, and the energy is 10kEV-60kEV.
  • the step of performing the third P-type ion doping includes: forming a photoresist layer on the surface of the gate insulating layer 60 away from the substrate, and then obtaining the first photoresist layer shown in FIG. 14 through exposure and development.
  • Three patterned photoresist layer 80 that is, a third patterned photoresist layer 80 is formed on the surface of the gate insulating layer 60 corresponding to the N-shaped region 20, and the third patterned photoresist layer 80 covers the first gate 71, and use the third patterned photoresist layer 80 and the second gate 72 as a mask to perform the third P-type ion doping on the sixth region 36 and the eighth region 38.
  • the first N-type ion doping and the first P doping are realized by adjusting the doping sequence in the above-mentioned multiple steps in the prior art and using the same half-tone mask.
  • the two doping steps of type ion doping can reduce a MASK process, thereby shortening the production process time and reducing the production cost, and still can ensure the good characteristics and performance of CMOS thin film transistors;
  • the first N-type ion doping ( The N+Doping) process is performed before the gate insulating layer (GI layer) is formed.
  • the first N-type ion doping and the first P-type ion doping in the present disclosure are compared to using a halftone mask in combination with any two of the above five ion doping steps.
  • Using the same halftone mask is easier to implement and has better process compatibility (for example, the second N-type ion doping uses the first gate and the second gate as the mask, and the third P-type ion doping
  • the impurity step and any of the other ion doping steps are inconvenient to use a halftone mask for doping.
  • the second P-type ion doping involves ion doping both the N-type region and the P region without using a mask. Plate), not only can shorten the production process of CMOS thin film transistors, but also reduce the production cost of CMOS thin film transistors, thereby improving the production efficiency of CMOS thin film transistors.
  • N-type ion doping including the first N-type ion doping and the second N-type ion doping.
  • ions in the aforementioned N-type ion doping can be phosphorus ions and arsenic ions; the specific types of ions in the above-mentioned P-type ion doping (including the first P-type ion doping, the second P-type ion doping and the third P-type ion doping)
  • P-type ion doping including the first P-type ion doping, the second P-type ion doping and the third P-type ion doping
  • those skilled in the art can choose flexibly according to actual needs, such as boron ion and aluminum ion.
  • CMOS thin film transistors also includes the manufacturing processes of other necessary structures in conventional CMOS thin film transistors, such as light-shielding layers, Buffer layer, via hole, source and drain structure manufacturing process.
  • the present disclosure provides a CMOS thin film transistor.
  • the CMOS thin film transistor is manufactured by the foregoing method of manufacturing the CMOS thin film transistor. Therefore, the CMOS thin film transistor has a short production cycle, low production cost, and still has good characteristics and performance.
  • the CMOS thin film transistor has all the features and advantages of the aforementioned method for manufacturing a CMOS thin film transistor, and will not be repeated here.
  • a CMOS thin film transistor includes an N-type thin film transistor and a P-type thin film transistor. Specifically: referring to FIG. 15, the N-type thin film transistor includes a first heavily doped drain region 110 and a lightly doped drain region 120.
  • the lightly doped drain region 120 is disposed at opposite ends of the first gate inner region 130, and the first heavily doped drain region 110 is disposed on the lightly doped drain region 120 away from the first gate inner region 130 At one end, the first heavily doped source region 140 is disposed at the other end of the lightly doped drain region 120 away from the first gate inner region 130;
  • the P-type thin film transistor includes a second heavily doped drain region 210 and a second gate The inner side region 220 and the second heavily doped source region 230, wherein the orthographic projection of the second gate inner region 220 on the substrate 10 overlaps with the orthographic projection of the second gate 72 on the substrate 10, and the second The heavily doped drain region 210 and the second heavily doped source region 230 are respectively disposed at opposite ends of the second gate inner region 220.
  • the CMOS thin film transistor can be fabricated by using the aforementioned fabrication method.
  • the lightly doped drain region 120 is in the same position as the aforementioned second and fourth regions
  • the first gate inner region 130 is in the same position as the aforementioned third region
  • the pole region 140 is in the same position as the fifth region described above
  • the second heavily doped drain region 210 is in the same position as the sixth region described above
  • the second gate inner region 220 is the same as the seventh region described above.
  • the regions are arranged in the same position
  • the second heavily doped source region 230 is arranged in the same position as the aforementioned eighth region.
  • the present disclosure provides an array substrate.
  • the array substrate includes the aforementioned CMOS thin film transistor. Therefore, on the basis of ensuring the good characteristics and use performance of the array substrate, the manufacturing process time of the array substrate is shorter, thereby reducing the manufacturing cost of the array substrate and improving the market competitiveness.
  • the array substrate has all the features and advantages of the aforementioned CMOS thin film transistors, which will not be repeated here.
  • the above-mentioned array substrate also includes other necessary structures in a conventional array substrate, such as connecting wires, common electrodes, pixel electrodes and other structures.
  • the present disclosure provides a display device.
  • the display device includes the aforementioned array substrate. Therefore, the manufacturing time of the display device is short, the manufacturing cost is low, and the display device has good characteristics and performance, which can greatly enhance its market competitiveness. Those skilled in the art can understand that the display device has all the features and advantages of the aforementioned array substrate, which will not be repeated here.
  • the above-mentioned display devices can be mobile phones, tablet computers, game consoles, and smart phones with display functions.
  • Display devices such as equipment.
  • the above-mentioned display device also includes necessary structures or components in a conventional display device, such as a mobile phone.
  • a conventional display device such as a mobile phone.
  • it also includes necessary structures or components such as a color filter substrate, a touch screen, a voice module, a camera module, and a CPU processor.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present disclosure, “plurality” means two or more than two unless specifically defined otherwise.

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Abstract

本公开提供了CMOS薄膜晶体管及其制作方法和阵列基板。制作CMOS薄膜晶体管的方法包括：在衬底上形成半导体层，半导体层同层间隔设置的包括N型区域和P型区域，其中，N型区域依次划分为第一区、第二区、第三区、第四区和第五区，用于形成N型薄膜晶体管，P型区域依次划分为第六区、第七区和第八区，用于形成P型薄膜晶体管；对第一区和第五区进行第一N型离子掺杂；对N型区域进行第一P型离子掺杂；对N型区域和P型区域进行第二P型离子掺杂；对第一区、第二区、第四区、第五区、第六区和第八区进行第二N型离子掺杂；对第六区和第八区进行第三P型离子掺杂，其中，第一N型离子掺杂和第一P型离子掺杂是通过同一个半色调掩膜板进行的。由此，可缩短制作工艺时长，降低制作成本。

Description

CMOS薄膜晶体管及其制作方法和阵列基板
相关申请的交叉引用
本申请要求于2019年2月27日提交的申请号为201910146805.X的中国专利申请的优先权，在此其内容通过引用方式整体并入本文。
技术领域
本公开涉及显示技术领域，具体的，涉及CMOS薄膜晶体管及其制作方法和阵列基板。
背景技术
TFT-LCD现有的CMOS(互补金属氧化物半导体)产品，需在阵列基板(Array基板)的制作工艺中通过多次沟道掺杂(P型离子掺杂或N型离子掺杂)来形成MOS管(场效应管)，但是因PMOS(P型金属-氧化物-半导体)与NMOS(N型金属-氧化物-半导体)的设计及工作原理上的差异，需在Array工艺中先后进行多次掺杂(Doping)工艺，包括：沟道掺杂(Channel Doping)、阈值电压掺杂(Vth Doping)、N+Doping、轻掺杂漏结构(LDD Doping)及P+Doping，工艺流程复杂，所需工艺时间较长，成本较高。
发明内容
在本公开的一个方面，本公开提供了一种制作CMOS薄膜晶体管的方法。根据本公开的实施例，所述制作CMOS薄膜晶体管的方法包括：
步骤1、在衬底上形成半导体层，所述半导体层包括同层间隔设置的N型区域和P型区域，其中，
所述N型区域依次划分为第一区、第二区、第三区、第四区和第五区，用于形成N型薄膜晶体管，其中，所述第一区用于形成第一重掺杂漏极区，所述第二区和所述第四区用于形成轻掺杂漏极区，所述第三区用于形成第一栅极内侧区，所述第五区用于形成第一重掺杂源极区，
所述P型区域依次划分为第六区、第七区和第八区，用于形成P型薄膜晶体管，其中，所述第六区用于形成第二重掺杂漏极区，所述第七区用于形成第二栅极内侧区，所述第八区用于形成第二重掺杂源极区；
步骤2、对所述第一区和所述第五区进行第一N型离子掺杂；
步骤3、对所述N型区域进行第一P型离子掺杂；
步骤4、对步骤3获得的产品中的所述N型区域和所述P型区域进行第二P型离子掺 杂；
步骤5、对步骤4获得的产品中的所述第一区、所述第二区、所述第四区、所述第五区、所述第六区和所述第八区进行第二N型离子掺杂；
步骤6、对步骤5获得的产品中的所述第六区和所述第八区进行第三P型离子掺杂，其中，所述第一N型离子掺杂和所述第一P型离子掺杂是通过同一个半色调掩膜板进行的。
由此，通过调整现有技术中上述多个步骤中的掺杂顺序，并通过同一个半色调掩模板实现第一N型离子掺杂和第一P型离子掺杂两个掺杂步骤，可以减少一道MASK工艺，进而缩短制作工艺时长，降低制作成本，而且依然可以保证CMOS薄膜晶体管良好的特性和使用性能。
根据本公开的实施例，所述第一N型离子掺杂和所述第一P型离子掺杂的步骤包括：利用所述半色调掩膜板在所述半导体层的上表面上形成第一图案化光刻胶层，所述第一图案化光刻胶层包括第一层和第二层，所述第一层覆盖在所述P型区域的表面上，所述第二层覆盖在所述第二区、所述第三区和所述第四区的表面上，其中，所述第二层的厚度小于所述第一层的厚度；对暴露的所述第一区和所述第五区进行所述第一N型离子掺杂；去除所述第二层，并将所述第一层减薄，以便得到第二图案化光刻胶层，所述第二图案化光刻胶层覆盖在所述P型区域的表面上；对暴露的所述N型区域进行所述第一P型离子掺杂；去除所述第二图案化光刻胶层。
根据本公开的实施例，通过灰化工艺去除所述第二层，并将所述第一层减薄，以便得到所述第二图案化光刻胶层。
根据本公开的实施例，所述第二层的厚度为所述第一层的厚度的30％～70％。
根据本公开的实施例，所述第一层的厚度为1～2.5微米，所述第二层的厚度为0.5～1.75微米，所述灰化的时间为10-40秒。
根据本公开的实施例，所述第二图案化光刻胶层的厚度为所述第一层的厚度的30％～70％。
根据本公开的实施例，在所述第二P型离子掺杂之后，所述第二N型离子掺杂之前，进一步包括：在所述N型区域和所述P型区域的表面上形成栅绝缘层；在所述栅绝缘层的表面上形成第一栅极和第二栅极，其中，所述第一栅极在所述衬底上的正投影与所述第三区在所述衬底上的正投影重叠，所述第二栅极在所述衬底上的正投影与所述第七区在所述衬底上的正投影重叠，所述第二N型离子掺杂是以所述第一栅极和所述第二栅极为掩膜板进行的。
根据本公开的实施例，进行所述第三P型离子掺杂的步骤包括：在所述N形区域对应的栅绝缘层的表面上形成第三图案化光刻胶层，所述第三图案化光刻胶层覆盖所述第一栅 极，并以所述第三图案化光刻胶层和所述第二栅极为掩膜板对所述第六区和所述第八区进行所述第三P型离子掺杂。
根据本公开的实施例，所述半导体层为多晶硅层。
在本公开的另一方面，本公开提供了一种CMOS薄膜晶体管。根据本公开的实施例，所述CMOS薄膜晶体管是由前面制作所述CMOS薄膜晶体管的方法制作得到的。由此，该CMOS薄膜晶体管的制作周期短，制作成本低，且依然具有良好的特性和使用性能。本领域技术人员可以理解，该CMOS薄膜晶体管具有前面所述的制作CMOS薄膜晶体管的方法的所有特征和优点，在此不再过多赘述。
根据本公开的实施例，所述CMOS薄膜晶体管包括N型薄膜晶体管和P型薄膜晶体管，其中，所述N型薄膜晶体管包括第一重掺杂漏极区、轻掺杂漏极区、第一栅极内侧区和第一重掺杂源极区，其中，所述第一栅极内侧区在衬底上的正投影与第一栅极在所述衬底上的正投影重叠，所述轻掺杂漏极区设置在所述第一栅极内侧区相对的两端，所述第一重掺杂漏极区设置在所述轻掺杂漏极区远离所述第一栅极内侧区的一端，所述第一重掺杂源极区设置在所述轻掺杂漏极区远离所述第一栅极内侧区的另一端；所述P型薄膜晶体管包括第二重掺杂漏极区、第二栅极内侧区和第二重掺杂源极区，其中，所述第二栅极内侧区在所述衬底上的正投影与第二栅极在所述衬底上的正投影重叠，所述第二重掺杂漏极区和所述第二重掺杂源极区分别设置在所述第二栅极内侧区相对的两端。
在本公开的又一方面，本公开提供了一种阵列基板。根据本公开的实施例，所述阵列基板包括前面所述的CMOS薄膜晶体管。由此，在保证阵列基板良好的特性和使用性能的基础上，该阵列基板的制作工艺时长较短，进而降低阵列基板的制作成本，提高市场竞争力。本领域技术人员可以理解，该阵列基板具有前面所述CMOS薄膜晶体管的所有特征和优点，在此不再过多赘述。
附图说明
图1是本公开一个实施例中制作CMOS薄膜晶体管的方法流程图。
图2是本公开另一个实施例中制作CMOS薄膜晶体管的结构流程图。
图3是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图4是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图5是本公开又一个实施例中制作CMOS薄膜晶体管的方法流程图。
图6是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图7是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图8是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图9是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图10是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图11是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图12是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图13是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图14是本公开又一个实施例中制作CMOS薄膜晶体管的结构流程图。
图15是本公开又一个实施例中CMOS薄膜晶体管的结构示意图。
具体实施方式
下面详细描述本公开的实施例。下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。
在本公开的一个方面，本公开提供了一种制作CMOS薄膜晶体管的方法。其至少在一定程度上解决相关技术中的技术问题之一。本公开的一个目的在于提出一种具有简化工艺流程、缩短制作工艺时长或降低制作成本等优点的制作CMOS薄膜晶体管的方法。根据本公开的实施例，参照图1，制作CMOS薄膜晶体管的方法包括：
步骤1、在衬底10上形成半导体层，半导体层包括同层间隔设置的N型区域20和P型区域30，其中，参照图2，N型区域20依次划分为第一区21、第二区22、第三区23、第四区24和第五区25，N型区域20用于形成N型薄膜晶体管，其中，第一区用于形成第一重掺杂漏极区，第二区和第四区用于形成轻掺杂漏极区，第三区用于形成第一栅极内侧区，第五区用于形成第一重掺杂源极区；P型区域30依次划分为第六区36、第七区37和第八区38，P型区域30用于形成P型薄膜晶体管，其中，第六区用于形成第二重掺杂漏极区，第七区用于形成第二栅极内侧区，第八区用于形成第二重掺杂源极区。
为了便于理解本技术方案，下面对上述各掺杂区进行简单描述一下：
第一重掺杂漏极区和第一重掺杂源极区分别用于与N型薄膜晶体管的漏极和源极电连接，通过高浓度的N型离子(比如磷离子)掺杂，为N型薄膜晶体管的导通提供大量的自由电子，该区域其电阻较小，可等同于导体；
在轻掺杂漏极区中，通过低浓度的掺杂来改善热载流子效应，其原理为是以较低的剂量(与重掺杂源漏极区域相比)注入第二区和第四区，其注入的离子剂量介于重掺杂源漏极区与栅极内侧区的掺杂量之间，从而形成一定的浓度缓冲区，从而降低漏极端边缘电场梯度和热载流子效应，进而降低N型薄膜晶体管的漏电流；
第一栅极内侧区和第二栅极内侧区用于控制半导体层的导通与否，其中，当对N型薄 膜晶体管施加正压时，轻掺杂漏极区中的部分自由电子转移到第一栅极内侧区的半导体(半导体可为多晶硅)的表面，使得N型薄膜晶体管的半导体层处于导通状态，对N型薄膜晶体管施加负压或不施加电压时，轻掺杂漏极区中的电子不会向到第一栅极内侧区中转移，第一栅极内侧区中的电阻很大，使得N型薄膜晶体管的半导体层处于关闭状态；当对P型薄膜晶体管施加负压时，轻掺杂漏极区中的部分空穴转移到第二栅极内侧区中，使得P型薄膜晶体管的半导体层处于导通状态，对P型薄膜晶体管施加正压或不施加电压时，轻掺杂漏极区中的空穴不会向到第二栅极内侧区中转移，第一栅极内侧区中的电阻很大，使得P型薄膜晶体管的半导体层处于关闭状态；
第二重掺杂漏极区和第二重掺杂源极区分别用于与P型薄膜晶体管的漏极和源极电连接，通过高浓度的P型离子(比如硼离子)掺杂，为P型薄膜晶体管的导通提供大量的空穴，该区域其电阻较小，可等同于导体。根据本公开的实施例，形成衬底的材料没有限制要求，本领域技术人员可以根据实际需求灵活选择。在本公开的一些实施例中，形成衬底的材料包括但不限于聚合物衬底或玻璃衬底。
根据本公开的实施例，为保证CMOS薄膜晶体管的良好特性，半导体层为多晶硅层。由此，半导体的载流子较大，电学特性较佳。根据本公开的实施例，形成半导体层方法也没有限制要求，本领域技术人员可以根据实际情况灵活选择。在本公开的一些实施例中，形成半导体层(以多晶硅层为例)的方法为：通过化学气相沉积法(比如等离子体增强化学气相沉积法)在衬底上形成非晶硅(a-Si)层，之后通过准分子激光退火(ELA)使得非晶硅形成多晶硅，进而得到多晶硅层。
步骤2、对第一区21和第五区25进行第一N型离子掺杂(N+Doping)，结构示意图参照图3。由此，通过第一N型离子掺杂，可为N-TFT MOS管(对应N型区域)提供较好的欧姆接触和低的串联电阻。
根据本公开的实施例，第一N型离子掺杂的掺杂浓度和能量没有限制要求，本领域技术人员根据实际情况灵活选择即可。在本公开的一些实施例中，第一N型离子掺杂的浓度1E14～8E14，能量为10kEV～60kEV。
步骤3、对步骤2获得的产品中的N型区域20(包括第一区至第五区)进行第一P型离子掺杂(Vth Doping)，结构示意图参照图4。由此，通过第一P型离子掺杂，为N型薄膜晶体管(N-TFT MOS管，对应P型区域)提供较好的欧姆接触和低的串联电阻。
根据本公开的实施例，第一P型离子掺杂的掺杂浓度和能量没有限制要求，本领域技术人员根据实际情况灵活选择即可。在本公开的一些实施例中，第一P型离子掺杂的浓度1E14～8E14，能量为10kEV～60kEV。
根据本公开的实施例，第一N型离子掺杂和第一P型离子掺杂是通过同一个半色调掩 膜板进行的，参照图5，其具体步骤包括：
S100：利用半色调掩膜板在半导体层的上表面上形成第一图案化光刻胶层，第一图案化光刻胶层包括第一层41和第二层42，第一层41覆盖在P型区域30的表面上，第二层42覆盖在第二区22、第三区23和第四区24的表面上，其中，第二层42的厚度小于第一层41的厚度，结构示意图参照图6。
根据本公开的实施例，第二层的厚度为第一层厚度的30％～70％，比如，30％、35％、40％、50％、55％、60％、65％或70％。由此，不仅可以使得第二层有效阻挡掺杂的离子进入第二区22、第三区23和第四区24中，而且可以保证在后续工艺中，既可保证第二层的有效去除，也可保证减薄后的第一层不会太薄，以免在进行第一P型离子掺杂时离子进入P型区域，影响CMOS薄膜晶体管的特性。
在本公开的实施例中，第一层和第二层的具体厚度没有特殊要求，本领域技术人员可以根据离子掺杂的剂量和能量等实际情况灵活设计，在一些实例中，第一层的厚度为1.5微米，第二层的厚度为0.75微米。
根据本公开的实施例，利用半色调掩膜板50形成第一图案化光刻胶层的方法没有限制要求，本领域技术人员可以根据实际需要灵活选择常规技术手段进行实施，具体的：
在本公开的一些实施例中，首先在半导体层上形成正性光刻胶层40，利用半色调掩膜板50对正性光刻胶层40进行曝光，其中，半色调掩膜板50中的全曝光区51对应第一区21和第五区25表面上覆盖的正性光刻胶层40设置，半色调掩膜板50中的半曝光区52对应第二区22、第三区23和第四区24表面上覆盖的正性光刻胶层40设置，半色调掩膜板50中的不曝光区53对应P型区域30表面上覆盖的正性光刻胶层40设置，结构示意图参照图7，之后通过曝光显影之后，得到图6所示的包括厚度不等的第一层41和第二层42的第一图案化光刻胶层。
在本公开的另一些实施例中，首先在半导体层上形成负性光刻胶层，利用半色调掩膜板对负性光刻胶层进行曝光，其中，半色调掩膜板中的不曝光区对应第一区21和第五区25表面上覆盖的负性光刻胶层设置，半色调掩膜板中的半曝光区52对应第二区22、第三区23和第四区24表面上覆盖的负性光刻胶层设置，半色调掩膜板中的全曝光区对应P型区域30表面上覆盖的正性光刻胶层设置(图中未示出)，之后通过曝光显影之后，得到图6所示的包括厚度不等的第一层41和第二层42的第一图案化光刻胶层。
S200：对暴露的第一区21和第五区25进行第一N型离子掺杂，结构示意图参照图8。
根据本公开的实施例，此处进行的第一N型离子掺杂与前面步骤2中的第一N型离子掺杂要求一致，在此不再过多的赘述。
S300：去除第二层42，并将第一层41减薄，以便得到第二图案化光刻胶层43，第二 图案化光刻胶层43覆盖在P型区域30的表面上，结构示意图参照图9。
根据本公开的实施例，第二图案化光刻胶层的厚度为第一层的厚度的30％～70％，比如，30％、35％、40％、50％、55％、60％、65％或70％。由此，第一层减薄后得到的第二图案化光刻胶层不会太薄，进而在进行第一P型离子掺杂时有效阻挡离子进入P型区域，影响CMOS薄膜晶体管的特性。
根据本公开的实施例，为了较好的控制第二层的去除，以及第一层的减薄，通过灰化(Ashing)工艺去除第二层42，并将第一层41减薄，以便得到第二图案化光刻胶层43，具体的，通过在灰化工艺中使用O 2气体对第二图案化光刻胶层进行灰化处理，并对灰化的时间精准控制，以便有效的去除第一层的光刻胶(PR)，并保留一定厚度的第二层的光刻胶，即得到具有该厚度的第二图案化光刻胶层43，且保证第二图案化光刻胶层在后续进行第一P型离子掺杂时能够阻挡离子掺杂到P型区域中。
根据本公开的实施例，本领域技术人员可以根据第一层和第二层的具体厚度，在本公开的一些实施例中，第一层的厚度为1～2.5微米(比如1微米、1.2微米、1.4微米、1.6微米、1.8微米、2.0微米、2.2微米、2.3微米、2.5微米)，第二层的厚度为0.5～1.75微米(比如0.5微米、0.7微米、0.9微米、1.0微米、1.1微米、1.3微米、1.5微米、1.6微米、1.75微米)，灰化的时间为10-40秒，比如10秒、15秒、20秒、25秒、30秒、35秒或40秒。由此，本领域技术人员可以根据第一层和第二层的具体厚度等实际情况灵活设定灰化时间，以保证在有效去除第二层的同时，得到适宜厚度的第二图案化光刻胶层。
S400：对暴露的整个N型区域20进行第一P型离子掺杂，结构示意图参照图10。
根据本公开的实施例，此处进行的第一P型离子掺杂与前面步骤3中的第一P型离子掺杂要求一致，在此不再过多的赘述。
S500：去除第二图案化光刻胶层43，结构示意图参照图4。
根据本公开的实施例，第二图案化光刻胶层的去除方法没有特殊要求，本领域技术人员可以根据实际灵活选择。在本公开的实施例中，可以采用灰化工艺去除第二图案化光刻胶层，也可以根据第二图案化光刻胶层的具体光刻胶种类采用相应的显影液，以便有效完全的去除第二图案化光刻胶层，且不影响到半导体层的性能。
步骤4、对步骤3获得的产品中的N型区域20和P型区域30进行第二P型离子掺杂(Channel Doping)，结构示意图参照图11。由此，通过第一P型离子掺杂和第二P型离子掺杂两步骤的掺杂，使得半导体层中掺杂离子注入量的产生差异，以此来调节CMOS薄膜晶体管的阈值电压。
根据本公开的实施例，第二P型离子掺杂的掺杂浓度和能量也没有限制要求，本领域技术人员根据实际情况灵活选择即可。在本公开的一些实施例中，第二P型离子掺杂的浓 度为1E14～8E14，能量为10kEV～60kEV。
步骤5、对步骤4获得的产品中的第一区21、第二区22、第四区24、第五区25、第六区36和第八区38进行第二N型离子掺杂(LDD Doping)，结构示意图参照图12。由此，通过第二N型离子掺杂，为CMOS薄膜晶体管提供较好的欧姆接触和低的串联电阻。
根据本公开的实施例，第二N型离子掺杂的掺杂浓度和能量也没有限制要求，本领域技术人员根据实际情况灵活选择即可。在本公开的一些实施例中，第二N型离子掺杂的浓度为1E14～8E14，能量为10kEV～60kEV。
根据本公开的实施例，在保证CMOS薄膜晶体管的良好特性的前提下，为了缩减工艺流程，节省成本，参照图12和图13，在第二P型离子掺杂之后，第二N型离子掺杂之前，进一步包括：在N型区域20和P型区域30的表面上形成栅绝缘层60；在栅绝缘层60的表面上形成第一栅极71和第二栅极72，其中，第一栅极71在衬底10上的正投影与第三区23在衬底10上的正投影重叠，第二栅极72在衬底10上的正投影与第七区37在衬底10上的正投影重叠，其中，第二N型离子掺杂是以第一栅极和第二栅极为掩膜板进行的。由此，以第一栅极和第二栅极为掩膜板进行离子掺杂，进而可以节省一张掩膜板，还可以缩短工艺时长。
根据本公开的实施例，形成栅绝缘层的方法和材料均没有限制要求，本领域技术人员可以采用现有技术中任一种可行的方法。在本公开的一些实施例中，形成产绝缘层的方法包括但不限于化学气相沉积(比如等离子体增强化学的气相沉积法)或物理气相沉积(比如磁控溅射)等方法；形成栅绝缘层的材料包括但不限于氧化硅、氮化硅、氮氧化硅、有机绝缘材料等。由此，制作的栅绝缘层的使用性能良好，且制作工艺成熟，易于工业化生产。
根据本公开的实施例，形成第一栅极和第二栅极的方法和材料也没有限制要求，本领域技术人员可以根据实际情况灵活选择。在本公开的一些实施例中，形成第一栅极和第二栅极的步骤包括：现在栅绝缘层的表面上沉积形成一层栅极金属层，然后通过刻蚀工艺即可得到第一栅极和第二栅极；形成第一栅极和第二栅极的材料包括但不限于镍、钨、钼、铬、镍锰合金、镍铬合金、镍钼铁合金、钨钼合金等材料。由此，上述材料制作的第一栅极和第二栅极具有良好的特性。
步骤6、对步骤5获得的产品中的第六区36和第八区38进行第三P型离子掺杂(P+Doping)，结构示意图参照图14，得到N型薄膜晶体管(N-TFT MOS管，对应N型区域)和P型薄膜晶体管(P-TFT MOS管，对应P型区域)，即得到CMOS薄膜晶体管。由此，通过第三P型离子掺杂，可为P-TFT MOS管提供较好的欧姆接触和低的串联电阻。
根据本公开的实施例，第三型离子掺杂的掺杂浓度和能量也没有限制要求，本领域技 术人员根据实际情况灵活选择即可。在本公开的一些实施例中，第三型离子掺杂的浓度为1E14～8E14，能量为10kEV～60kEV。
根据本公开的实施例，进行所述第三P型离子掺杂的步骤包括：在栅绝缘层60远离衬底的表面上形成光刻胶层，然后通过曝光显影得到图14中所示的第三图案化光刻胶层80，即在N形区域20对应的栅绝缘层60的表面上形成第三图案化光刻胶层80，且第三图案化光刻胶层80覆盖第一栅极71，并以第三图案化光刻胶层80和第二栅极72为掩膜板对第六区36和第八区38进行所述第三P型离子掺杂。当然，本领域技术人员可以理解，之后还包括去除第三图案化光刻胶层80的步骤，其中去除的具体方法没有特殊要求，可以通过灰化工艺去除，也可以通过显影液去除，本领域技术人员根据实际需求灵活选择即可。
由根据本公开的实施例，在上述制作工艺中，通过调整现有技术中上述多个步骤中的掺杂顺序，并通过同一个半色调掩模板实现第一N型离子掺杂和第一P型离子掺杂两个掺杂步骤，可以减少一道MASK工艺，进而缩短制作工艺时长，降低制作成本，而且依然可以保证CMOS薄膜晶体管良好的特性和使用性能；此外，第一N型离子掺杂(N+Doping)工艺在栅绝缘层(GI层)形成之前进行，相比第一N型离子掺杂(N+Doping)工艺在栅绝缘层形成之后进行的方案，没有栅绝缘层的阻挡(若第一N型离子掺杂(N+Doping)工艺在栅绝缘层形成之后进行，在掺杂的离子被加速注入时，大部分离子因受到阻挡残留在GI层，注入效果相对较差)，需注入离子的剂量和能量较低，如此，不仅可以避免原料的浪费，降低成本，而且还可以延缓设备的老化。
根据本公开的实施例，相比与上述五个离子掺杂步骤中其他任两个步骤结合使用半色调掩膜板，本公开中的第一N型离子掺杂和第一P型离子掺杂采用同一个半色调掩膜板，更易于实施，且工艺兼容性更佳(比如，第二N型离子掺杂是以第一栅极和第二栅极为掩膜板，第三P型离子掺杂的步骤与其他任一个离子掺杂步骤都不便于采用半色调掩膜板进行掺杂，第二P型离子掺杂是对N型区域和P区域都进行了离子掺杂，无需使用掩膜板)，不仅可以缩短CMOS薄膜晶体管的制作流程，还可降低CMOS薄膜晶体管的制作成本，进而提升CMOS薄膜晶体管的制作效率。
根据本公开的实施例，上述N型离子掺杂(包括第一N型离子掺杂和第二N型离子掺杂)中离子的具体种类没有限制要求，本领域技术人员根据实际需求灵活选择即可，比如可以为磷离子、砷离子；上述P型离子掺杂(包括第一P型离子掺杂、第二P型离子掺杂和第三P型离子掺杂)中离子的具体种类也没有限制要求，本领域技术人员根据实际需求灵活选择即可，比如可以为硼离子、铝离子。
根据本公开的实施例，上述N型离子掺杂和P型离子掺杂的具体方法也没有限制要求，本领域技术人员可以采用任意一种可行的方法，比如可以为离子注入。由此，工艺成熟， 易于制作。
本领域技术人员可以理解，CMOS薄膜晶体管的制作工艺中除了上述的N型离子掺杂和P型离子掺杂工艺，还包括常规CMOS薄膜晶体管中其他必备结构的制作的工艺，比如遮光层、缓冲层、过孔、源漏极等结构的制作工艺。
在本公开的另一方面，本公开提供了一种CMOS薄膜晶体管。根据本公开的实施例，所述CMOS薄膜晶体管是由前面制作所述CMOS薄膜晶体管的方法制作得到的。由此，该CMOS薄膜晶体管的制作周期短，制作成本低，且依然具有良好的特性和使用性能。本领域技术人员可以理解，该CMOS薄膜晶体管具有前面所述的制作CMOS薄膜晶体管的方法的所有特征和优点，在此不再过多赘述。
根据本公开的实施例，CMOS薄膜晶体管包括N型薄膜晶体管和P型薄膜晶体管，具体的：参照图15，N型薄膜晶体管包括第一重掺杂漏极区110、轻掺杂漏极区120、第一栅极内侧区130和第一重掺杂源极区140，其中，第一栅极内侧区130在衬底10上的正投影与第一栅极71在衬底10上的正投影重叠，轻掺杂漏极区120设置在第一栅极内侧区130相对的两端，第一重掺杂漏极区110设置在轻掺杂漏极区120远离第一栅极内侧区130的一端，第一重掺杂源极区140设置在轻掺杂漏极区120远离第一栅极内侧区130的另一端；P型薄膜晶体管包括第二重掺杂漏极区210、第二栅极内侧区220和第二重掺杂源极区230，其中，第二栅极内侧区220在衬底10上的正投影与第二栅极72在衬底10上的正投影重叠，第二重掺杂漏极区210和第二重掺杂源极区230分别设置在第二栅极内侧区220相对的两端。
根据本公开的实施例，该CMOS薄膜晶体管可以利用前面所述的制作方法进行制作，本领域技术人员可以理解，上述的第一重掺杂漏极区110与前面所述的第一区设置位置一致，轻掺杂漏极区120与前面所述的第二区和第四区设置位置一致，第一栅极内侧区130与前面所述的第三区设置位置一致，第一重掺杂源极区140与前面所述的第五区设置位置一致，第二重掺杂漏极区210与前面所述的第六区设置位置一致，第二栅极内侧区220与前面所述的第七区设置位置一致，以及第二重掺杂源极区230与前面所述的第八区设置位置一致。
在本公开的又一方面，本公开提供了一种阵列基板。根据本公开的实施例，所述阵列基板包括前面所述的CMOS薄膜晶体管。由此，在保证阵列基板良好的特性和使用性能的基础上，该阵列基板的制作工艺时长较短，进而降低阵列基板的制作成本，提高市场竞争力。本领域技术人员可以理解，该阵列基板具有前面所述CMOS薄膜晶体管的所有特征和优点，在此不再过多赘述。
本领域技术人员可以理解，上述阵列基板除了包括前面所述的CMOS薄膜晶体管，还 包括常规阵列基板中其他必备的结构，比如连接导线、公共电极、像素电极等结构。
在本公开的又一方面，本公开提供了一种显示装置。根据本公开的实施例，所述显示装置包括前面所述的阵列基板。由此，该显示装置的制作时长较短，制作成本低，且具有良好的特性和使用性能，可以大大提升其市场竞争力。本领域技术人员可以理解，该显示装置具有前面所述阵列基板的所有特征和优点，在此不再过多赘述。
根据本公开的实施例，上述显示装置的具体种类没特殊的限制要求，本领域技术人员可以根据实际情况灵活选择，比如，上述显示装置可以为手机、平板电脑、游戏机、具有显示功能的智能设备等显示装置。
本领域技术人员可以理解，上述显示装置除了上述的阵列基板，还包括常规显示装置中所必备的结构或部件，以手机为例。除了上述阵列基板，还包括彩膜基板、触控屏、语音模组、照相模组、CPU处理器等必备的结构或部件。
在本公开的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (12)

  1. 一种制作CMOS薄膜晶体管的方法，包括：
    步骤1、在衬底上形成半导体层，所述半导体层包括同层间隔设置的N型区域和P型区域，其中，
    所述N型区域依次划分为第一区、第二区、第三区、第四区和第五区，用于形成N型薄膜晶体管，其中，所述第一区用于形成第一重掺杂漏极区，所述第二区和所述第四区用于形成轻掺杂漏极区，所述第三区用于形成第一栅极内侧区，所述第五区用于形成第一重掺杂源极区，
    所述P型区域依次划分为第六区、第七区和第八区，用于形成P型薄膜晶体管，其中，所述第六区用于形成第二重掺杂漏极区，所述第七区用于形成第二栅极内侧区，所述第八区用于形成第二重掺杂源极区；
    步骤2、对所述第一区和所述第五区进行第一N型离子掺杂；
    步骤3、对所述N型区域进行第一P型离子掺杂；
    步骤4、对步骤3获得的产品中的所述N型区域和所述P型区域进行第二P型离子掺杂；
    步骤5、对步骤4获得的产品中的所述第一区、所述第二区、所述第四区、所述第五区、所述第六区和所述第八区进行第二N型离子掺杂；
    步骤6、对步骤5获得的产品中的所述第六区和所述第八区进行第三P型离子掺杂，
    其中，所述第一N型离子掺杂和所述第一P型离子掺杂是通过同一个半色调掩膜板进行的。
  2. 根据权利要求1所述的方法，其中，所述第一N型离子掺杂和所述第一P型离子掺杂的步骤包括：
    利用所述半色调掩膜板在所述半导体层的上表面上形成第一图案化光刻胶层，所述第一图案化光刻胶层包括第一层和第二层，所述第一层覆盖在所述P型区域的表面上，所述第二层覆盖在所述第二区、所述第三区和所述第四区的表面上，其中，所述第二层的厚度小于所述第一层的厚度；
    对暴露的所述第一区和所述第五区进行所述第一N型离子掺杂；
    去除所述第二层，并将所述第一层减薄，以便得到第二图案化光刻胶层，所述第二图案化光刻胶层覆盖在所述P型区域的表面上；
    对暴露的所述N型区域进行所述第一P型离子掺杂；
    去除所述第二图案化光刻胶层。
  3. 根据权利要求2所述的方法，其中，通过灰化工艺去除所述第二层，并将所述第一层减薄，以便得到所述第二图案化光刻胶层。
  4. 根据权利要求2所述的方法，其中，所述第二层的厚度为所述第一层的厚度的30％～70％。
  5. 根据权利要求4所述的方法，其中，所述第一层的厚度为1～2.5微米，所述第二层的厚度为0.5～1.75微米，所述灰化的时间为10-40秒。
  6. 根据权利要求2所述的方法，其中，所述第二图案化光刻胶层的厚度为所述第一层的厚度的30％～70％。
  7. 根据权利要求1所述的方法，其中，在所述第二P型离子掺杂之后，所述第二N型离子掺杂之前，进一步包括：
    在所述N型区域和所述P型区域的表面上形成栅绝缘层；
    在所述栅绝缘层的表面上形成第一栅极和第二栅极，其中，所述第一栅极在所述衬底上的正投影与所述第三区在所述衬底上的正投影重叠，所述第二栅极在所述衬底上的正投影与所述第七区在所述衬底上的正投影重叠，
    其中，所述第二N型离子掺杂是以所述第一栅极和所述第二栅极为掩膜板进行的。
  8. 根据权利要求7所述的方法，其中，进行所述第三P型离子掺杂的步骤包括：
    在所述N形区域对应的栅绝缘层的表面上形成第三图案化光刻胶层，所述第三图案化光刻胶层覆盖所述第一栅极，并以所述第三图案化光刻胶层和所述第二栅极为掩膜板对所述第六区和所述第八区进行所述第三P型离子掺杂。
  9. 根据权利要求1所述的方法，其中，所述半导体层为多晶硅层。
  10. 一种CMOS薄膜晶体管，是由权利要求1～9所述的方法制作得到的。
  11. 根据权利要求10所述的CMOS薄膜晶体管，包括N型薄膜晶体管和P型薄膜晶体管，其中，
    所述N型薄膜晶体管包括第一重掺杂漏极区、轻掺杂漏极区、第一栅极内侧区和第一重掺杂源极区，其中，所述第一栅极内侧区在衬底上的正投影与第一栅极在所述衬底上的正投影重叠，所述轻掺杂漏极区设置在所述第一栅极内侧区相对的两端，所述第一重掺杂漏极区设置在所述轻掺杂漏极区远离所述第一栅极内侧区的一端，所述第一重掺杂源极区设置在所述轻掺杂漏极区远离所述第一栅极内侧区的另一端；
    所述P型薄膜晶体管包括第二重掺杂漏极区、第二栅极内侧区和第二重掺杂源极区，其中，所述第二栅极内侧区在所述衬底上的正投影与第二栅极在所述衬底上的正投影重叠，所述第二重掺杂漏极区和所述第二重掺杂源极区分别设置在所述第二栅极内侧区相对的两端。
  12. 一种阵列基板，包括权利要求10或11所述的CMOS薄膜晶体管。
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Publication number Priority date Publication date Assignee Title
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186397A (ja) * 1995-11-07 2006-07-13 Semiconductor Energy Lab Co Ltd 半導体装置、液晶表示装置、エレクトロルミネッセンス表示装置
CN105789325A (zh) * 2016-04-18 2016-07-20 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及cmos器件
US20170077091A1 (en) * 2015-09-16 2017-03-16 Vanguard International Semiconductor Corporation Semiconductor structure and method for manufacturing the same
CN107275340A (zh) * 2017-05-24 2017-10-20 厦门天马微电子有限公司 薄膜晶体管制备方法、阵列基板、其制备方法及显示装置
CN108538789A (zh) * 2018-03-30 2018-09-14 武汉华星光电技术有限公司 Cmos晶体管的制备方法、阵列基板的制备方法
CN109860108A (zh) * 2019-02-27 2019-06-07 京东方科技集团股份有限公司 Cmos薄膜晶体管及其制作方法和阵列基板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100796609B1 (ko) * 2006-08-17 2008-01-22 삼성에스디아이 주식회사 Ｃｍｏｓ 박막 트랜지스터의 제조방법
TWI440139B (zh) * 2008-11-21 2014-06-01 Innolux Corp 薄膜電晶體之製造方法及具有該薄膜電晶體陣列基板之製造方法
US20130078787A1 (en) * 2010-06-09 2013-03-28 Sharp Kabushiki Kaisha Method for manufacturing semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186397A (ja) * 1995-11-07 2006-07-13 Semiconductor Energy Lab Co Ltd 半導体装置、液晶表示装置、エレクトロルミネッセンス表示装置
US20170077091A1 (en) * 2015-09-16 2017-03-16 Vanguard International Semiconductor Corporation Semiconductor structure and method for manufacturing the same
CN105789325A (zh) * 2016-04-18 2016-07-20 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及cmos器件
CN107275340A (zh) * 2017-05-24 2017-10-20 厦门天马微电子有限公司 薄膜晶体管制备方法、阵列基板、其制备方法及显示装置
CN108538789A (zh) * 2018-03-30 2018-09-14 武汉华星光电技术有限公司 Cmos晶体管的制备方法、阵列基板的制备方法
CN109860108A (zh) * 2019-02-27 2019-06-07 京东方科技集团股份有限公司 Cmos薄膜晶体管及其制作方法和阵列基板

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