WO2016197399A1 - Ltps阵列基板及其制造方法 - Google Patents

Ltps阵列基板及其制造方法 Download PDF

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WO2016197399A1
WO2016197399A1 PCT/CN2015/081634 CN2015081634W WO2016197399A1 WO 2016197399 A1 WO2016197399 A1 WO 2016197399A1 CN 2015081634 W CN2015081634 W CN 2015081634W WO 2016197399 A1 WO2016197399 A1 WO 2016197399A1
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gate
layer
substrate
forming
region
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PCT/CN2015/081634
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English (en)
French (fr)
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王聪
杜鹏
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/760,750 priority Critical patent/US9893096B2/en
Publication of WO2016197399A1 publication Critical patent/WO2016197399A1/zh
Priority to US15/863,991 priority patent/US10170506B2/en
Priority to US15/863,993 priority patent/US10529750B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a LTPS (Low Temperature Poly-silicon) array substrate and a method of fabricating the same.
  • LTPS Low Temperature Poly-silicon
  • the liquid crystal display device adopting the LTPS process can effectively reduce the area of a TFT (Thin Film Transistor) to increase the aperture ratio of the pixel, and can enhance the display brightness while reducing power consumption and Production costs have become a research hotspot in the field of liquid crystal display.
  • TFT Thin Film Transistor
  • the LTPS process is complicated, and the types and the number of masks required for preparing an array substrate (Array substrate) are large, resulting in a large number of manufacturing processes and incapable of reducing production costs. Therefore, how to reduce the type and quantity of reticle used in the LTPS process is the goal that enterprises need to work hard at present.
  • embodiments of the present invention provide an LTPS array substrate and a method of fabricating the same, which can reduce the type and number of reticle used in the LTPS process.
  • An embodiment of the present invention provides a method for fabricating an LTPS array substrate, comprising: forming a gate of a thin film transistor of an LTPS array substrate on a substrate; forming a buffer layer on the substrate not covered by the gate, and upper surface of the buffer layer Forming a plane with the upper surface of the gate electrode; sequentially forming an insulating layer, a semiconductor layer and a first positive photoresist layer on the substrate including the gate; the upper surface of the insulating layer is a plane; and the back surface of the insulating layer is a gate Exposing the side to retain the first positive photoresist layer only in the first region directly above the gate; injecting the first impurity ions into the semiconductor layer other than the first region; from the substrate back to the gate Exposing is performed on one side to form a first positive photoresist layer of the second region directly above the gate electrode, the second region being smaller than the first region; and implanting the second impurity ions into the semiconductor layer other than the second region; a first
  • the step of forming a buffer layer on the substrate not covered by the gate includes: sequentially forming a buffer layer and a negative photoresist layer on the substrate including the gate; and exposing from the side of the substrate facing the gate to remove a negative photoresist layer directly above the gate; removing the buffer layer directly above the gate and leaving the buffer layer on the substrate not covered by the gate.
  • the step of removing the first positive photoresist layer of the second region further comprises: coating the photoresist layer on the polysilicon layer and exposing according to a predetermined pattern; etching to remove the polysilicon layer other than the predetermined pattern; and removing the remaining photoresist Floor.
  • the first impurity ion and the second impurity ion are respectively N+ and N-type impurity ions.
  • a buffer layer is further formed on the substrate not covered by the gate, and the upper surface of the buffer layer and the upper surface of the gate constitute a plane.
  • the step of forming a buffer layer on the substrate not covered by the gate includes: sequentially forming a buffer layer and a negative photoresist layer on the substrate including the gate; and exposing from the side of the substrate facing the gate to remove a negative photoresist layer directly above the gate; removing the buffer layer directly above the gate and leaving the buffer layer on the substrate not covered by the gate.
  • the step of forming a buffer layer on the substrate not covered by the gate includes: including the gate Forming a buffer layer and a second positive photoresist layer on the substrate; exposing from the side of the substrate toward the gate to remove the second positive photoresist layer directly above the gate; removing the positive photoresist layer directly above the gate
  • the buffer layer retains the buffer layer on the substrate that is not covered by the gate.
  • the step of exposing from the side of the substrate facing the gate to form the polysilicon layer comprises: exposing from a side of the substrate facing away from the gate to retain the first only in the first region corresponding directly above the gate a positive photoresist layer; implanting a first impurity ion to a semiconductor layer other than the first region; and exposing from a side of the substrate facing the gate to form a first positive polarity of the second region directly above the gate a photoresist layer, wherein the second region is smaller than the first region; the second impurity ions are implanted into the semiconductor layer other than the second region; and the first positive photoresist layer of the second region is removed.
  • the step of removing the first positive photoresist layer of the second region further comprises: coating the photoresist layer on the polysilicon layer and exposing according to a predetermined pattern; etching to remove the polysilicon layer other than the predetermined pattern; and removing the remaining photoresist Floor.
  • the first impurity ion and the second impurity ion are respectively N+ and N-type impurity ions.
  • the step of exposing from the side of the substrate facing the gate to form the polysilicon layer comprises: exposing from a side of the substrate facing away from the gate to retain the first only in the first region corresponding directly above the gate a positive photoresist layer; implanting P-type impurity ions into a semiconductor layer other than the first region; and exposing from a side of the substrate facing away from the gate to form a first positive polarity of the second region directly above the gate
  • the photoresist layer, the second region is smaller than the first region; and the first positive photoresist layer of the second region is removed.
  • a further embodiment of the present invention provides an LTPS array substrate, comprising: a substrate; a gate on the substrate; an insulating layer and a polysilicon layer sequentially formed on the substrate including the gate, wherein the upper surface of the insulating layer is a plane; a source and a drain are disposed on the polysilicon layer; a pixel electrode is disposed on the insulating layer and a portion of the source; and a flat passivation layer is disposed on the source/drain electrode layer composed of the source and the drain, and is formed in the flat passivation layer Contact holes to expose surfaces of the gate, source and drain, contact holes outside the polysilicon layer; transparent electrode layers on the flat passivation layer and transparent electrode layers through the contact holes and gate, source and drain Extremely electrical connection.
  • the LTPS array substrate further includes a buffer layer on the substrate not covered by the gate, and the upper surface of the buffer layer and the upper surface of the gate form a plane.
  • the LTPS array substrate and the manufacturing method thereof are exposed from a side of the substrate facing away from the gate, that is, exposure is performed by using an opaque gate to form a polysilicon layer, and a mask is not required in the process of the polysilicon layer. , thereby reducing the type and number of reticle used in the LTPS process. Simplify processes and reduce production costs.
  • FIG. 1 is a flow chart showing a method of fabricating an embodiment of an LTPS array substrate of the present invention
  • FIG. 2 is a schematic view showing the formation of a gate electrode in the manufacturing method of the present invention.
  • FIG. 3 is a schematic view showing formation of an insulating layer, a semiconductor layer, and a positive photoresist layer in the manufacturing method of the present invention
  • FIG. 4 is a schematic view showing formation of an unpatterned polysilicon layer in the manufacturing method of the present invention.
  • Figure 5 is a schematic view showing the formation of a patterned polysilicon layer in the manufacturing method of the present invention.
  • Figure 6 is a schematic view showing the formation of a source and a drain in the manufacturing method of the present invention.
  • Figure 7 is a schematic view showing the formation of a pixel electrode in the manufacturing method of the present invention.
  • Figure 8 is a first cross-sectional view showing the formation of a transparent electrode layer in the manufacturing method of the present invention.
  • Figure 9 is a schematic view showing the formation of a flat passivation layer in the manufacturing method of the present invention.
  • Step 11 forming a gate of the thin film transistor of the LTPS array substrate on the substrate.
  • the substrate 21 is used to form an LTPS array substrate of a liquid crystal display panel, and the substrate 21 may be a glass substrate, a plastic substrate or a flexible substrate.
  • the first metal layer formed on the substrate 21 is exposed by the first mask, and after the exposure, a patterning process such as development, etching, or the like is performed to obtain the gate electrode 22, wherein the phosphoric acid is used.
  • the first metal layer is etched by an etching solution of nitric acid, acetic acid, and deionized water, although dry etching may of course be employed.
  • the gate 22 can be obtained by other methods, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, or low pressure.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • sputtering vacuum evaporation
  • low pressure low pressure
  • the gate electrode 22 directly forms the gate electrode 22 having a predetermined pattern on the substrate 21.
  • the first metal layer may be composed of a metal such as aluminum, molybdenum, titanium, chromium, copper, or a metal oxide such as titanium oxide, or an alloy of metal or other conductive material.
  • Step 12 sequentially forming an insulating layer, a semiconductor layer and a positive photoresist layer on the substrate including the gate, wherein the upper surface of the insulating layer is a plane.
  • the present embodiment needs to form a buffer layer 23 on the substrate 21 not covered by the gate 22.
  • the specific process includes But not limited to:
  • the buffer layer 23 and the negative photoresist layer 24 are sequentially formed on the substrate 21 including the gate electrode 22.
  • the buffer layer 23 may be a combination of a silicon nitride (SiN x ) layer, a silicon oxide (SiO x ) layer, or other non-conductive material, and the buffer layer 23 may be used to prevent impurities in the substrate 21 from being diffused in a subsequent process to be formed after being affected.
  • the quality of the low temperature polysilicon layer, the silicon nitride layer and the silicon oxide layer may be formed by chemical vapor deposition, plasma chemical vapor deposition, sputtering, vacuum evaporation or low pressure chemical vapor deposition, but is not limited thereto.
  • the remaining negative photoresist layer 24 is stripped off, and the buffer layer 23 located directly above the gate electrode 22 is removed by etching, thereby leaving the buffer layer 23 not covering the gate electrode 22.
  • the manner of forming the buffer layer 23 in this embodiment may also be:
  • a buffer layer 23 and a positive photoresist layer are sequentially formed on the substrate 21 including the gate electrode 22, and the positive photoresist layer 27 is formed on the semiconductor layer 26.
  • the positive photoresist layer herein can be understood as the first In the case of a bi-positive photoresist layer, the positive photoresist layer 27 is a first positive photoresist layer.
  • exposure is performed from the side of the substrate 21 toward the gate electrode 22 to remove the positive photoresist layer directly above the gate electrode 22.
  • the buffer layer 23 located directly above the gate electrode 21 is removed, and the buffer layer 23 on the substrate 21 not covered by the gate electrode 22 is left.
  • Step 13 Exposing from the side of the substrate facing away from the gate to form a polysilicon layer.
  • this exposure is formed larger than the intensity of the exposure intensity of Q 1 positive photoresist layer 27 of the first region, the first region located at both ends of a Q positive photoresist layer 27 is removed, thereby forming a second region Q 2 positive photoresist layer 27 is immediately above the gate electrode 22, wherein the second area smaller than the first area Q 2 Q 1.
  • the second impurity ions are implanted into the semiconductor layer 26 other than the second region Q 2 , that is, the semiconductor layer 26 is subjected to a light doping treatment in a conventional sense.
  • the present embodiment exposes the polysilicon layer 28 by using a second mask to form a predetermined pattern. Specifically, in conjunction with FIG. 5, the light is coated on the polysilicon layer 28. The resist layer 29 is exposed and then etched to remove the polysilicon layer 28 other than the predetermined pattern, and the remaining photoresist layer 29 is removed. Wherein, when the photoresist layer 29 is a positive photoresist layer, exposure is performed from a side of the substrate 21 facing away from the gate electrode 22; when the photoresist layer 29 is a negative photoresist layer, from the substrate 21 toward the gate electrode 22 Exposure is performed on one side.
  • Step S14 forming a source and a drain of the thin film transistor on the polysilicon layer.
  • the source S and the drain D of the thin film transistor shown in FIG. 6 can be obtained by exposure, development, and etching using a third mask.
  • Step S15 forming a pixel electrode on the insulating layer and a part of the source.
  • the pixel electrode 30 having a predetermined pattern as shown in FIG. 7 can be obtained by exposure, development, and etching using the fourth mask.
  • Step S17 forming a transparent electrode layer on the flat passivation layer, so that the transparent electrode layer can be connected
  • the contact holes are electrically connected to the gate, the source and the drain.
  • the transparent electrode layer 32 as shown in FIG. 10 can be obtained by exposure, development, and etching using the sixth mask.
  • the transparent electrode layer 32 and the pixel electrode 30 can be made of the same transparent conductive material as the LTPS array substrate. Common electrode.
  • the present embodiment exposes the side of the substrate 21 facing away from the gate 22, that is, by using the opaque gate 22 to form the polysilicon layer 28, and the mask is not required in the process of the polysilicon layer 28. Therefore, the type and number of masks used in the entire LTPS array panel can be reduced, the process can be simplified, and the production cost can be reduced.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Thin Film Transistor (AREA)

Abstract

一种LTPS阵列基板及其制造方法。方法包括：在包括形成栅极（22）的基体（21）上依次形成绝缘层（25）、半导体层（26）和正性光阻层（27）；自基体（21）背向栅极（22）的一侧进行曝光以形成多晶硅层；在多晶硅层上形成源极和漏极；在绝缘层（25）和部分源极上形成像素电极（30）；在源极和漏极上形成具有接触孔的平坦钝化层（31）；在平坦钝化层（31）上形成透明电极层（32），使得透明电极层（32）可通过接触孔与栅极（22）、源极和漏极电连接。能够减少LTPS工艺所使用的光罩的类型及数量，简化制程并降低生产成本。

Description

LTPS阵列基板及其制造方法 【技术领域】
本发明涉及显示技术领域，具体涉及一种LTPS(Low Temperature Poly-silicon，低温多晶硅)阵列基板及其制造方法。
【背景技术】
采用LTPS工艺的液晶显示装置由于具有较高的电子迁移率，能够有效减小TFT(Thin Film Transistor，薄膜晶体管)的面积以提升像素的开口率，并且在增强显示亮度的同时能够降低功耗及生产成本，目前已成为液晶显示领域的研究热点。但是LTPS工艺复杂，制备阵列基板(Array基板)所需的光罩(Mask)的类型及数量较多，导致制造流程繁多，无法降低生产成本。因此如何减少LTPS工艺所使用的光罩的类型及数量，实为目前企业需要努力的目标。
【发明内容】
鉴于此，本发明实施例提供一种LTPS阵列基板及其制造方法，能够减少LTPS工艺所使用的光罩的类型及数量。
本发明一实施例提供一种LTPS阵列基板的制造方法，包括：在基体上形成LTPS阵列基板的薄膜晶体管的栅极；在未被栅极覆盖的基体上形成缓冲层，且缓冲层的上表面和栅极的上表面构成一平面；在包括栅极的基体上依次形成绝缘层、半导体层和第一正性光阻层，绝缘层的上表面为一平面；自基体背向栅极的一侧进行曝光，以仅在对应于栅极的正上方的第一区域保留第一正性光阻层；向除第一区域之外的半导体层注入第一杂质离子；自基体背向栅极的一侧进行曝光，以在栅极的正上方形成第二区域的第一正性光阻层，第二区域小于第一区域；向除第二区域之外的半导体层注入第二杂质离子；除去第二区域的第一正性光阻层以形成多晶硅层；在多晶硅层上形成薄膜晶体管的源极和漏极；在绝缘层和一部分的源极上形成像素电极；在由源极和漏极组成的源漏电极层上形成平坦钝化层，并在平坦钝化层内形成接触孔以暴露栅极、源极和漏极的表面，接触孔位于多 晶硅层以外的区域；在平坦钝化层上形成透明电极层，使得透明电极层可通过接触孔与栅极、源极和漏极电连接。
其中，在未被栅极覆盖的基体上形成缓冲层的步骤包括：在包括栅极的基体上依次形成缓冲层、负性光阻层；自基体背向栅极的一侧进行曝光，以除去位于栅极正上方的负性光阻层；除去位于栅极正上方的缓冲层，且保留未被栅极覆盖的基体上的缓冲层。
其中，在未被栅极覆盖的基体上形成缓冲层的步骤包括：在包括栅极的基体上依次形成缓冲层、第二正性光阻层；自基体朝向栅极的一侧进行曝光，以除去位于栅极正上方的第二正性光阻层；除去位于栅极正上方的缓冲层，且保留未被栅极覆盖的基体上的缓冲层。
其中，除去第二区域的第一正性光阻层的步骤之后还包括：在多晶硅层上涂布光阻层并根据预定图案进行曝光；蚀刻去除预定图案以外的多晶硅层；除去剩余的光阻层。
其中，第一杂质离子和第二杂质离子分别为N+、N-型杂质离子。
本发明另一实施例提供一种LTPS阵列基板的制造方法，包括：在基体上形成LTPS阵列基板的薄膜晶体管的栅极；在包括栅极的基体上依次形成绝缘层、半导体层和第一正性光阻层，绝缘层的上表面为一平面；自基体背向栅极的一侧进行曝光以形成多晶硅层；在多晶硅层上形成薄膜晶体管的源极和漏极；在绝缘层和一部分的源极上形成像素电极；在由源极和漏极组成的源漏电极层上形成平坦钝化层，并在平坦钝化层内形成接触孔以暴露栅极、源极和漏极的表面，接触孔位于多晶硅层以外的区域；在平坦钝化层上形成透明电极层，使得透明电极层可通过接触孔与栅极、源极和漏极电连接。
其中，在包括栅极的基体上形成绝缘层之前，还在未被栅极覆盖的基体上形成缓冲层，且缓冲层的上表面和栅极的上表面构成一平面。
其中，在未被栅极覆盖的基体上形成缓冲层的步骤包括：在包括栅极的基体上依次形成缓冲层、负性光阻层；自基体背向栅极的一侧进行曝光，以除去位于栅极正上方的负性光阻层；除去位于栅极正上方的缓冲层，且保留未被栅极覆盖的基体上的缓冲层。
其中，在未被栅极覆盖的基体上形成缓冲层的步骤包括：在包括栅极 的基体上依次形成缓冲层、第二正性光阻层；自基体朝向栅极的一侧进行曝光，以除去位于栅极正上方的第二正性光阻层；除去位于栅极正上方的缓冲层，且保留未被栅极覆盖的基体上的缓冲层。
其中，自基体背向栅极的一侧进行曝光以形成多晶硅层的步骤包括：自基体背向栅极的一侧进行曝光，以仅在对应于栅极的正上方的第一区域保留第一正性光阻层；向除第一区域之外的半导体层注入第一杂质离子；自基体背向栅极的一侧进行曝光，以在栅极的正上方形成第二区域的第一正性光阻层，第二区域小于第一区域；向除第二区域之外的半导体层注入第二杂质离子；除去第二区域的第一正性光阻层。
其中，除去第二区域的第一正性光阻层的步骤之后还包括：在多晶硅层上涂布光阻层并根据预定图案进行曝光；蚀刻去除预定图案以外的多晶硅层；除去剩余的光阻层。
其中，第一杂质离子和第二杂质离子分别为N+、N-型杂质离子。
其中，自基体背向栅极的一侧进行曝光以形成多晶硅层的步骤包括：自基体背向栅极的一侧进行曝光，以仅在对应于栅极的正上方的第一区域保留第一正性光阻层；向除第一区域之外的半导体层注入P型杂质离子；自基体背向栅极的一侧进行曝光，以在栅极的正上方形成第二区域的第一正性光阻层，第二区域小于第一区域；除去第二区域的第一正性光阻层。
本发明又一实施例提供一种LTPS阵列基板，包括：基体；栅极，位于基体上；依次形成于包括栅极的基体上的绝缘层、多晶硅层，其中绝缘层的上表面为一平面；源极和漏极，位于多晶硅层上；像素电极，位于绝缘层和一部分的源极上；平坦钝化层，位于由源极和漏极组成的源漏电极层上，平坦钝化层内形成接触孔以暴露栅极、源极和漏极的表面，接触孔位于多晶硅层以外的区域；透明电极层，位于平坦钝化层上且透明电极层可通过接触孔与栅极、源极和漏极电连接。
其中，LTPS阵列基板还包括缓冲层，缓冲层位于未被栅极覆盖的基体上，且缓冲层的上表面和栅极的上表面构成一平面。
本发明实施例的LTPS阵列基板及其制造方法，自基体背向栅极的一侧进行曝光，即利用不透光的栅极进行曝光以形成多晶硅层，在多晶硅层的制程中无需使用光罩，从而能够减少LTPS工艺所使用的光罩的类型及数量， 简化制程并降低生产成本。
【附图说明】
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图；
图2是本发明的制造方法中形成栅极的示意图；
图3是本发明的制造方法中形成绝缘层、半导体层和正性光阻层的示意图；
图4是本发明的制造方法中形成未图案化的多晶硅层的示意图；
图5是本发明的制造方法中形成图案化的多晶硅层的示意图；
图6是本发明的制造方法中形成源极和漏极的示意图；
图7是本发明的制造方法中形成像素电极的示意图；
图8是本发明的制造方法中形成透明电极层的第一剖视图；
图9是本发明的制造方法中形成平坦钝化层的示意图；
图10是本发明的制造方法中形成透明电极层的第二剖视图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图。如图1所示，本实施例的制造方法包括以下步骤：
步骤11：在基体上形成LTPS阵列基板的薄膜晶体管的栅极。
如图2所示，基体21用于形成液晶显示面板的LTPS阵列基板，所述基体21可为玻璃基体、塑料基体或可挠式基体。
本实施例可以利用第一光罩对形成于基体21上的第一金属层进行曝光，并在曝光后进行显影、刻蚀等图案化制程以得到形成栅极22，其中可利用包含有磷酸、硝酸、醋酸以及去离子水的蚀刻液对第一金属层进行蚀刻，当然也可以采用干法蚀刻。
当然，本实施例还可以通过其他方式得到栅极22，例如采用化学气相沉积(Chemical vapor deposition，CVD)、等离子化学气相沉积(Plasma Enhanced Chemical vapor deposition，PECVD)、溅射、真空蒸镀或低压化学 气相沉积等方法直接在基体21上形成具有预定图案的栅极22。其中，第一金属层可由金属，例如铝、钼、钛、铬、铜，或金属氧化物，例如氧化钛，或金属的合金或其它导电材料构成。
步骤12：在包括栅极的基体上依次形成绝缘层、半导体层和正性光阻层，其中绝缘层的上表面为一平面。
结合图3所示，在形成绝缘层25、半导体层26和正性光阻层27之前，本实施例需要在未被栅极22覆盖的基体21上形成缓冲层(Buffer layer)23，具体过程包括但不限于：
首先，在包括栅极22的基体21上依次形成缓冲层23、负性光阻层24。缓冲层23可以为氮化硅(SiNx)层、氧化硅(SiOx)层或者其他非导电材料的组合，缓冲层23可用于防止基体21内的杂质在后续工艺中向上扩散而影响之后形成的低温多晶硅层的品质，氮化硅层和氧化硅层可以采用化学气相沉积、等离子化学气相沉积形成、溅射、真空蒸镀或低压化学气相沉积等方法形成，但不限于此。
然后，自基体21背向栅极22的一侧进行曝光，位于栅极22正上方的负性光阻层24由于受到栅极22的遮挡而未曝光，因此可在显影时被灰化去除。
最后，剥离除去剩余的负性光阻层24，再通过刻蚀除去位于栅极22正上方的缓冲层23，从而保留未覆盖栅极22的缓冲层23。
本实施例形成缓冲层23的方式还可以为：
首先，在包括栅极22的基体21上依次形成缓冲层23、正性光阻层，相对形成于半导体层26上的正性光阻层27，此处的正性光阻层可理解为第二正性光阻层，则正性光阻层27为第一正性光阻层。然后，自基体21朝向栅极22的一侧进行曝光，以除去位于栅极22正上方的正性光阻层。最后，除去位于栅极21正上方的缓冲层23，且保留未被栅极22覆盖的基体21上的缓冲层23。
步骤13：自基体背向栅极的一侧进行曝光以形成多晶硅层。
结合图4所示，首先，自基体21背向栅极22的一侧进行曝光，位于栅极22上方的第一区域Q1的正性光阻层27由于受到栅极22的遮挡而未曝光，因此可在显影时被保留，且未被栅极22遮挡而被曝光的正性光阻层 27在显影时可被灰化去除，从而仅仅在对应于栅极22的正上方的第一区域Q1中保留有正性光阻层27。
然后，向除第一区域Q1之外的半导体层26注入第一杂质离子，即对半导体层26进行传统意义上的重掺杂处理。
接着，自基体21背向栅极22的一侧进行曝光，本次曝光的强度大于形成第一区域Q1的正性光阻层27的曝光的强度，因此位于第一区域Q1的两端的正性光阻层27被除去，从而在栅极22的正上方形成第二区域Q2的正性光阻层27，其中第二区域Q2小于第一区域Q1。
进一步，向除第二区域Q2之外的半导体层26注入第二杂质离子，即对半导体层26进行传统意义上的轻掺杂处理。
最后，除去第二区域Q2的正性光阻层27。
本实施例的第一杂质离子可以为N+型杂质离子，对应地第二杂质离子为N-型杂质离子，但是当第一杂质离子为P+型杂质离子时无需掺杂第二杂质离子，即省略了轻掺杂处理的步骤。
在除去第二区域Q2的正性光阻层27之后，本实施例采用第二光罩对多晶硅层28进行曝光以形成预定图案，结合图5具体而言，在多晶硅层28上涂布光阻层29并进行曝光，而后蚀刻去除预定图案以外的多晶硅层28，并除去剩余的光阻层29。其中，在光阻层29为正性光阻层时，自基体21背向栅极22的一侧进行曝光；在光阻层29为负性光阻层时，自基体21朝向栅极22的一侧进行曝光。
步骤S14：在多晶硅层上形成薄膜晶体管的源极和漏极。
本实施例可以利用第三光罩经过曝光、显影、刻蚀得到如图6所示的薄膜晶体管的源极S和漏极D。
步骤S15：在绝缘层和一部分的源极上形成像素电极。
本实施例可以利用第四光罩经曝光、显影、刻蚀得到如图7所示的具有预定图案的像素电极30。
步骤S16：在由源极和漏极组成的源漏电极层上形成平坦钝化层，并在平坦钝化层内形成接触孔以暴露栅极、源极和漏极的表面，接触孔位于多晶硅层以外的区域。
步骤S17：在平坦钝化层上形成透明电极层，使得透明电极层可通过接 触孔与栅极、源极和漏极电连接。
本实施例可以利用第五光罩经曝光、显影、刻蚀得到如图8和图9所示的平坦钝化层31。参阅图8所示，在薄膜晶体管以外的区域，平坦钝化层31具有接触孔O，接触孔O使得所述栅极22、源极S和漏极D的表面暴露出来，并与LTPS阵列基板的走线电连接，例如薄膜晶体管的栅极22与形成于基体21(阵列基板)上的栅极线对应电连接，薄膜晶体管的源极S与形成于阵列基板上的数据线对应电连接，栅极线和数据线垂直交叉形成像素电极33所在的像素显示区域。
本实施例可以利用第六光罩经曝光、显影、刻蚀得到如图10所示的透明电极层32，透明电极层32与像素电极30的可以采用相同的透明导电材质，以作为LTPS阵列基板的公共电极。
承上所述，本实施例自基体21背向栅极22的一侧进行曝光，即利用不透光的栅极22进行曝光以形成多晶硅层28，在多晶硅层28的制程中无需使用光罩，从而能够减少整个LTPS阵列面板所使用的光罩的类型及数量，简化制程并降低生产成本。
本发明实施例还提供一种具有图10所示LTPS阵列面板的液晶显示面板以及液晶显示器，与其具有相同的有益效果。
在此基础上，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种LTPS阵列基板的制造方法，其中，包括：
    在基体上形成所述LTPS阵列基板的薄膜晶体管的栅极；
    在未被所述栅极覆盖的所述基体上形成缓冲层，且所述缓冲层的上表面和所述栅极的上表面构成一平面；
    在包括所述栅极的所述基体上依次形成绝缘层、半导体层和第一正性光阻层，其中所述绝缘层的上表面为一平面；
    自所述基体背向所述栅极的一侧进行曝光，以仅在对应于所述栅极的正上方的第一区域保留所述第一正性光阻层；
    向除所述第一区域之外的所述半导体层注入第一杂质离子；
    自所述基体背向所述栅极的一侧进行曝光，以在所述栅极的正上方形成第二区域的所述第一正性光阻层，所述第二区域小于所述第一区域；
    向除所述第二区域之外的所述半导体层注入第二杂质离子；
    除去所述第二区域的所述第一正性光阻层以形成多晶硅层；
    在所述多晶硅层上形成所述薄膜晶体管的源极和漏极；
    在所述绝缘层和一部分的所述源极上形成像素电极；
    在由所述源极和所述漏极组成的源漏电极层上形成平坦钝化层，并在所述平坦钝化层内形成接触孔以暴露所述栅极、所述源极和所述漏极的表面，所述接触孔位于所述多晶硅层以外的区域；
    在所述平坦钝化层上形成透明电极层，使得所述透明电极层可通过所述接触孔与所述栅极、所述源极和所述漏极电连接。
  2. 根据权利要求1所述的方法，其中，在未被所述栅极覆盖的所述基体上形成所述缓冲层的步骤包括：
    在包括所述栅极的所述基体上依次形成缓冲层、负性光阻层；
    自所述基体背向所述栅极的一侧进行曝光，以除去位于所述栅极正上方的所述负性光阻层；
    除去位于所述栅极正上方的所述缓冲层，且保留未被所述栅极覆盖的所述基体上的所述缓冲层。
  3. 根据权利要求1所述的方法，其中，在未被所述栅极覆盖的所述基 体上形成所述缓冲层的步骤包括：
    在包括所述栅极的所述基体上依次形成缓冲层、第二正性光阻层；
    自所述基体朝向所述栅极的一侧进行曝光，以除去位于所述栅极正上方的所述第二正性光阻层；
    除去位于所述栅极正上方的所述缓冲层，且保留未被所述栅极覆盖的所述基体上的所述缓冲层。
  4. 根据权利要求1所述的方法，其中，所述除去所述第二区域的所述第一正性光阻层的步骤之后还包括：
    在所述多晶硅层上涂布光阻层并根据预定图案进行曝光；
    蚀刻去除所述预定图案以外的所述多晶硅层；
    除去剩余的所述光阻层。
  5. 根据权利要求1所述的方法，其中，所述第一杂质离子为N+型杂质离子，且所述第二杂质离子为N-型杂质离子。
  6. 一种LTPS阵列基板的制造方法，其中，包括：
    在基体上形成所述LTPS阵列基板的薄膜晶体管的栅极；
    在包括所述栅极的所述基体上依次形成绝缘层、半导体层和第一正性光阻层，其中所述绝缘层的上表面为一平面；
    自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层；
    在所述多晶硅层上形成所述薄膜晶体管的源极和漏极；
    在所述绝缘层和一部分的所述源极上形成像素电极；
    在由所述源极和所述漏极组成的源漏电极层上形成平坦钝化层，并在所述平坦钝化层内形成接触孔以暴露所述栅极、所述源极和所述漏极的表面，所述接触孔位于所述多晶硅层以外的区域；
    在所述平坦钝化层上形成透明电极层，使得所述透明电极层可通过所述接触孔与所述栅极、所述源极和所述漏极电连接。
  7. 根据权利要求6所述的方法，其中，在包括所述栅极的所述基体上形成所述绝缘层之前，所述方法还包括：
    在未被所述栅极覆盖的所述基体上形成缓冲层，且所述缓冲层的上表面和所述栅极的上表面构成一平面。
  8. 根据权利要求7所述的方法，其中，在未被所述栅极覆盖的所述基 体上形成所述缓冲层的步骤包括：
    在包括所述栅极的所述基体上依次形成缓冲层、负性光阻层；
    自所述基体背向所述栅极的一侧进行曝光，以除去位于所述栅极正上方的所述负性光阻层；
    除去位于所述栅极正上方的所述缓冲层，且保留未被所述栅极覆盖的所述基体上的所述缓冲层。
  9. 根据权利要求7所述的方法，其中，在未被所述栅极覆盖的所述基体上形成所述缓冲层的步骤包括：
    在包括所述栅极的所述基体上依次形成缓冲层、第二正性光阻层；
    自所述基体朝向所述栅极的一侧进行曝光，以除去位于所述栅极正上方的所述第二正性光阻层；
    除去位于所述栅极正上方的所述缓冲层，且保留未被所述栅极覆盖的所述基体上的所述缓冲层。
  10. 根据权利要求6所述的方法，其中，所述自所述基体背向所述栅极的一侧进行曝光以形成多晶硅层的步骤包括：
    自所述基体背向所述栅极的一侧进行曝光，以仅在对应于所述栅极的正上方的第一区域保留所述第一正性光阻层；
    向除所述第一区域之外的所述半导体层注入第一杂质离子；
    自所述基体背向所述栅极的一侧进行曝光，以在所述栅极的正上方形成第二区域的所述第一正性光阻层，所述第二区域小于所述第一区域；
    向除所述第二区域之外的所述半导体层注入第二杂质离子；
    除去所述第二区域的所述第一正性光阻层。
  11. 根据权利要求10所述的方法，其中，所述除去所述第二区域的所述第一正性光阻层的步骤之后还包括：
    在所述多晶硅层上涂布光阻层并根据预定图案进行曝光；
    蚀刻去除所述预定图案以外的所述多晶硅层；
    除去剩余的所述光阻层。
  12. 根据权利要求10所述的方法，其中，所述第一杂质离子为N+型杂质离子，且所述第二杂质离子为N-型杂质离子。
  13. 根据权利要求6所述的方法，其中，所述自所述基体背向所述栅极 的一侧进行曝光以形成多晶硅层的步骤包括：
    自所述基体背向所述栅极的一侧进行曝光，以仅在对应于所述栅极的正上方的第一区域保留所述第一正性光阻层；
    向除所述第一区域之外的所述半导体层注入P型杂质离子；
    自所述基体背向所述栅极的一侧进行曝光，以在所述栅极的正上方形成第二区域的所述第一正性光阻层，所述第二区域小于所述第一区域；
    除去所述第二区域的所述第一正性光阻层。
  14. 一种LTPS阵列基板，其中，所述LTPS阵列基板包括：
    基体；
    栅极，位于所述基体上；
    依次形成于包括所述栅极的所述基体上的绝缘层、多晶硅层，其中所述绝缘层的上表面为一平面；
    源极和漏极，位于所述多晶硅层上；
    像素电极，位于所述绝缘层和一部分的所述源极上；
    平坦钝化层，位于由所述源极和所述漏极组成的源漏电极层上，所述平坦钝化层内形成接触孔以暴露所述栅极、所述源极和所述漏极的表面，所述接触孔位于所述多晶硅层以外的区域；
    透明电极层，位于所述平坦钝化层上且所述透明电极层可通过所述接触孔与所述栅极、所述源极和所述漏极电连接。
  15. 根据权利要求14所述的LTPS阵列基板，其中，所述LTPS阵列基板还包括缓冲层，所述缓冲层位于未被所述栅极覆盖的所述基体上，且所述缓冲层的上表面和所述栅极的上表面构成一平面。
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