WO2020113598A1 - 薄膜晶体管结构及其制作方法、显示装置 - Google Patents

薄膜晶体管结构及其制作方法、显示装置 Download PDF

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WO2020113598A1
WO2020113598A1 PCT/CN2018/120133 CN2018120133W WO2020113598A1 WO 2020113598 A1 WO2020113598 A1 WO 2020113598A1 CN 2018120133 W CN2018120133 W CN 2018120133W WO 2020113598 A1 WO2020113598 A1 WO 2020113598A1
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amorphous silicon
layer
silicon layer
doped amorphous
type
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PCT/CN2018/120133
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French (fr)
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莫琼花
卓恩宗
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惠科股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1604—Amorphous materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present application relates to the field of display technology, and in particular to a thin film transistor structure, a manufacturing method thereof, and a display device.
  • GOA Gate Driven Array, grid drive integration on array substrate
  • the gate drive circuit is integrated on the display panel array substrate by using the GOA technology, so that the gate can be omitted Drive the integrated circuit part to reduce product cost from both material cost and manufacturing process.
  • the switching elements used to control the progressive scan switch such as TFT (Thin Film Transistor, thin film transistor), often have a variety of defects in the GOA circuit due to their own leakage current characteristics.
  • TFT Thin Film Transistor, thin film transistor
  • a thin film transistor structure that can improve the effect of TFT leakage current on the output of a GOA circuit is provided.
  • a method for manufacturing a thin film transistor structure and a display device are also provided.
  • a thin film transistor structure including:
  • a composite doped layer formed on the active layer A composite doped layer formed on the active layer
  • the composite doped layer includes a first N-type lightly doped amorphous silicon layer, a second N-type lightly doped amorphous silicon layer, a first N-type heavily doped amorphous silicon layer and a second layer sequentially stacked N-type heavily doped amorphous silicon layer, first N-type lightly-doped amorphous silicon layer, second N-type lightly-doped amorphous silicon layer, first N-type heavily-doped amorphous silicon layer, and second N-type
  • the ion doping concentration of the heavily doped amorphous silicon layer increases sequentially; a channel region is located in the middle of the composite doped layer, the channel region penetrates the composite doped layer and partially penetrates to the active Layer, the source and drain are located on both sides of the channel region.
  • a method for manufacturing a thin film transistor structure is used for manufacturing a thin film transistor structure.
  • the thin film transistor structure includes:
  • a composite doped layer formed on the active layer A composite doped layer formed on the active layer
  • the composite doped layer includes a first N-type lightly doped amorphous silicon layer, a second N-type lightly doped amorphous silicon layer, a first N-type heavily doped amorphous silicon layer and a second layer sequentially stacked N-type heavily doped amorphous silicon layer, first N-type lightly-doped amorphous silicon layer, second N-type lightly-doped amorphous silicon layer, first N-type heavily-doped amorphous silicon layer, and second N-type
  • the ion doping concentration of the heavily doped amorphous silicon layer increases sequentially; a channel region is located in the middle of the composite doped layer, the channel region penetrates the composite doped layer and partially penetrates to the active Layer, the source and drain are located on both sides of the channel region;
  • the method includes:
  • the composite doped layer includes a first N-type lightly doped amorphous silicon layer and a second N-type lightly doped amorphous layer stacked in sequence A silicon layer, a first N-type heavily doped amorphous silicon layer and a second N-type heavily doped amorphous silicon layer, wherein the first N-type lightly doped amorphous silicon layer and the second N-type lightly doped amorphous silicon layer
  • the ion doping concentration of the silicon layer, the first N-type heavily doped amorphous silicon layer and the second N-type heavily doped amorphous silicon layer increases sequentially;
  • the active layer, the first N-type lightly doped amorphous silicon layer, the second N-type lightly doped amorphous silicon layer, the first N-type heavily doped amorphous silicon layer and the second N-type heavily doped The amorphous silicon layer is lithographically processed;
  • the active layer, the first N-type lightly doped amorphous silicon layer, the second N-type lightly doped amorphous silicon layer, and the first N-type heavy doping The dry amorphous silicon layer and the second N-type heavily doped amorphous silicon layer are dry etched to obtain a second groove corresponding to the first groove, and the second groove penetrates the first The N-type lightly doped amorphous silicon layer, the second N-type lightly doped amorphous silicon layer, the first N-type heavily doped amorphous silicon layer and the second N-type heavily doped amorphous silicon layer, and partially penetrate to In the active layer, the first groove and the second groove form a channel region.
  • a display device includes a thin film transistor structure.
  • the thin film transistor structure includes:
  • a composite doped layer formed on the active layer A composite doped layer formed on the active layer
  • the composite doped layer includes a first N-type lightly doped amorphous silicon layer, a second N-type lightly doped amorphous silicon layer, a first N-type heavily doped amorphous silicon layer and a second layer sequentially stacked N-type heavily doped amorphous silicon layer, first N-type lightly-doped amorphous silicon layer, second N-type lightly-doped amorphous silicon layer, first N-type heavily-doped amorphous silicon layer, and second N-type
  • the ion doping concentration of the heavily doped amorphous silicon layer increases sequentially; a channel region is located in the middle of the composite doped layer, the channel region penetrates the composite doped layer and partially penetrates to the active Layer, the source and drain are located on both sides of the channel region.
  • the above thin film transistor structure is provided with a composite doped layer with multiple concentration gradients (first N-type lightly doped amorphous silicon layer, second N-type lightly doped amorphous silicon layer, first N-type heavily doped amorphous silicon Layer and the second N-type heavily doped amorphous silicon layer) instead of the original single-layer doped layer, can increase the energy barrier between the source and drain and the composite doped layer, increase the barrier for hole transport, and then reduce Leakage current improves the reliability and stability of thin-film transistors, which in turn improves the stability of GOA circuits.
  • FIG. 1 is a schematic structural diagram of a thin film transistor structure in an embodiment
  • FIG. 2 is a schematic structural diagram of a thin film transistor structure in another embodiment
  • FIG. 3 is a schematic flow chart of a method for manufacturing a thin film transistor structure in an embodiment
  • FIG. 4 is a schematic diagram of the structure formed in FIG. 3 according to step S100;
  • FIG. 5 is a schematic structural view of FIG. 3 formed according to step S200;
  • FIG. 6 is a schematic diagram of the structure formed in FIG. 3 according to steps S300 and S400;
  • step S500 is a schematic diagram of the structure formed in FIG. 3 according to step S500;
  • FIG. 8 is a schematic structural view of FIG. 3 formed according to step S600.
  • the thin film transistor structure may include: a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, a composite doped layer 50 and a source ⁇ 610, Drain 620 ⁇
  • the gate 20 is formed on the substrate 10; the gate insulating layer 30 is formed on the substrate 10, and the gate insulating layer 30 covers the gate 20; the active layer 40 is formed on the gate insulating layer 30; the composite doped layer 50 is formed on the active layer 40; the source electrode 610 and the drain electrode 620 are formed on the composite doped layer 50.
  • the composite doped layer 50 may include a first N-type lightly doped amorphous silicon layer 510, a second N-type lightly doped amorphous silicon layer 520, and a first N-type heavily doped amorphous silicon layer 530 stacked in sequence And a second N-type heavily doped amorphous silicon layer 540, a first N-type lightly doped amorphous silicon layer 510, a second N-type lightly doped amorphous silicon layer 520, a first N-type heavily doped amorphous silicon layer
  • the ion doping concentration of the layer 530 and the second N-type heavily doped amorphous silicon layer 540 increases sequentially; a channel region 80 is located in the middle of the composite doped layer 50, and the channel region 80 penetrates through the composite doped layer 50 and partially Throughout the active layer 40, the source 610 and the drain 620 are located on both sides of the channel region 80.
  • the above thin film transistor structure is provided with a composite doped layer with multiple concentration gradients (first N-type lightly doped amorphous silicon layer, second N-type lightly doped amorphous silicon layer, first N-type heavily doped amorphous silicon Layer and the second N-type heavily doped amorphous silicon layer) instead of the original single-layer doped layer, can increase the energy barrier between the source and drain and the composite doped layer, thereby reducing leakage current and improving the reliability of the thin film transistor Performance and stability, thereby improving the stability of the GOA circuit.
  • the substrate 10 may be a glass substrate or a plastic substrate, wherein the glass substrate may be alkali-free borosilicate ultra-thin glass, and the alkali-free borosilicate glass has higher physical characteristics, better corrosion resistance, and higher Thermal stability and lower density and higher modulus of elasticity.
  • the grid 20 is formed on the substrate 10, wherein the formation process of the grid 20 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the gate 20 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the gate 20 can be one or more of a stack combination of molybdenum, titanium, aluminum, and copper; selecting molybdenum, titanium, aluminum, and copper as the material of the gate 20 can ensure good conductivity. It can be understood that the material of the gate 20 can be selected and adjusted according to the actual application situation and product performance, and is not further limited herein.
  • the thickness of the gate electrode 20 may range from 3000 angstroms to 5000 angstroms. Alternatively, the thickness of the gate electrode 20 may be 3000 angstroms to 4000 angstroms. Further, the thickness of the gate electrode 20 may be 4000 angstroms to 5000 angstroms. It can be understood that the thickness of the gate electrode 20 can be selected and adjusted according to actual application conditions and product performance, which is not further limited herein.
  • the gate insulating layer 30 is formed on the substrate 10, and the forming process of the gate insulating layer 30 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the gate insulating layer 30 may be one or a combination of silicon oxide and silicon nitride, that is, the gate insulating layer 30 may be silicon oxide, silicon nitride, or silicon oxide and nitrogen Silicone mixture.
  • the material of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the thickness of the gate insulating layer 30 may be 3000 angstroms-5000 angstroms. Alternatively, the thickness of the gate insulating layer 30 may be 3500 angstroms-4000 angstroms. Further, the thickness of the gate insulating layer 30 may be 4000 angstroms-5000 angstroms. Egypt. It can be understood that the thickness of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the active layer 40 is formed on the gate insulating layer 30.
  • the formation process of the active layer 40 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the forming process of the active layer 40 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the active layer 40 may be amorphous silicon, and the active layer 40 is generally used as a conductive medium.
  • the thickness of the active layer 40 may be 550 angstroms to 700 angstroms. Alternatively, the thickness of the active layer 40 may be 550 angstroms to 600 angstroms. Further, the thickness of the active layer 40 may be 600 angstroms to 700 angstroms. It can be understood that the thickness of the active layer 40 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the composite doped layer 50 is formed on the active layer 40.
  • the formation process of the composite doped layer 50 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the composite doped layer 50 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the composite doped layer 50 is N-type doped, wherein the doping method may include high-temperature diffusion and ion implantation. High temperature diffusion is the diffusion or deposition of impurity atoms onto the surface of a silicon wafer through a gas phase source or doped oxide. The concentration of these impurities will monotonically decrease from the surface to the body.
  • Ion implantation is to implant doped ions into the semiconductor in the form of an ion beam, and the impurity concentration has a peak distribution in the semiconductor.
  • the impurity distribution is mainly determined by the ion mass and the implantation energy.
  • N-type doping is mainly doped with pentavalent impurity elements such as phosphorus and arsenic in semiconductors.
  • the advantages of ion implantation over high temperature diffusion are: 1.
  • the implanted ions are selected by a mass analyzer. The selected particles have high purity and single energy, thus ensuring that the doping concentration is not affected by the purity of the impurity source.
  • the implantation process is carried out under clean, dry vacuum conditions, and all kinds of pollution are reduced to the lowest level; 2.
  • the number of doped atoms implanted into the wafer can be accurately controlled, and the implantation dose is from 10 11 /cm for adjusting the threshold voltage 2 to 10 17 /cm 2 where the buried insulating layer is formed, with a wide range.
  • the substrate is generally maintained at room temperature or below 400°C. Therefore, silicon dioxide, silicon nitride, aluminum, and photoresist can be used as masking films for selective doping, making the self-aligned masking technology in device manufacturing more flexible.
  • the composite doped layer 50 may include a first N-type lightly doped amorphous silicon layer 510, a second N-type lightly doped amorphous silicon layer 520, and a first N-type heavily doped amorphous silicon layer stacked in this order 530 and the second N-type heavily doped amorphous silicon layer 540.
  • N-- represents the first N-type lightly doped amorphous silicon layer 510
  • N- represents the second N-type lightly doped amorphous silicon layer 520
  • N+ represents the first N-type heavily doped amorphous silicon layer
  • the silicon layer 530, N++ represents the second N-type heavily doped amorphous silicon layer 540.
  • the signs in N--, N-, N+, and N++ indicate the concentration of ion doping.
  • the first N-type lightly doped amorphous silicon layer 510, the second N-type lightly doped amorphous silicon layer 520, the first N-type heavily doped amorphous silicon layer 530 and the second N-type heavily doped amorphous silicon layer The ion doping concentration of the silicon layer 540 increases sequentially, in other words, the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510 is less than the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520 The ion doping concentration of the second N-type lightly doped amorphous silicon layer 520 is less than the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530. The ion doping concentration is less than that of the second N-type heavily doped amorphous silicon layer 540.
  • the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520 is 1.5 times to 3 times the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510.
  • the first The ion doping concentration of the second N-type lightly doped amorphous silicon layer 520 is 1.5 times to 2 times the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510, optionally, the second N-type lightly doped amorphous silicon layer 510
  • the ion doping concentration of the doped amorphous silicon layer 520 is 2 times to 3 times the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510.
  • the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530 is 2-6 times the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520, optionally, the first N-type
  • the ion doping concentration of the heavily doped amorphous silicon layer 530 is 2-4 times the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520; alternatively, the first N-type heavily doped non-crystalline
  • the ion doping concentration of the crystalline silicon layer 530 is 4-6 times that of the second N-type lightly doped amorphous silicon layer 520.
  • the ion doping concentration of the second N-type heavily doped amorphous silicon layer 540 is 1.5 to 3 times the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530, optionally, the second N-type
  • the ion doping concentration of the heavily doped amorphous silicon layer 540 is 1.5 times to 2 times the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530, optionally, the second N-type heavily doped non-crystalline
  • the ion doping concentration of the crystalline silicon layer 540 is 2 times to 3 times the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530.
  • the thickness of the composite doped layer 50 may be 300 angstroms to 600 angstroms.
  • the thickness of the composite doped layer 50 may be 300 angstroms to 400 angstroms; alternatively, the thickness of the composite doped layer 50 may be 400 angstroms to 500 angstroms; alternatively, the thickness of the composite doped layer 50 may be It is between 500 Angstroms and 600 Angstroms. It can be understood that the thickness of the composite doped layer 50 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the composite doped layer 50 includes a first N-type lightly doped amorphous silicon layer 510, a second N-type lightly doped amorphous silicon layer 520, a first N-type heavily doped amorphous silicon layer 530, and a second N-type The heavily doped amorphous silicon layer 540. Therefore, the thickness of the first N-type lightly doped amorphous silicon layer 510 may be 80 angstroms-200 angstroms, optionally, the thickness of the first N-type lightly doped amorphous silicon layer 510 may be 80 angstroms-100 angstroms; Alternatively, the thickness of the first N-type lightly doped amorphous silicon layer 510 may be 100 angstroms to 200 angstroms.
  • the thickness of the second N-type lightly doped amorphous silicon layer 520 may be 80 angstroms-200 angstroms. Alternatively, the thickness of the second N-type lightly doped amorphous silicon layer 520 may be 80 angstroms-100 angstroms; optional The thickness of the second N-type lightly doped amorphous silicon layer 520 may be 100 angstroms to 200 angstroms. The thickness of the first N-type heavily doped amorphous silicon layer 530 may be 80 angstroms-200 angstroms.
  • the thickness of the first N-type heavily doped amorphous silicon layer 530 may be 80 angstroms-100 angstroms; optional The thickness of the first N-type heavily doped amorphous silicon layer 530 may be 100 angstroms to 200 angstroms.
  • the thickness of the second N-type heavily doped amorphous silicon layer 540 may be 80 angstroms-200 angstroms, optionally, the thickness of the second N-type heavily doped amorphous silicon layer 540 may be 80 angstroms-100 angstroms; optional The thickness of the second N-type heavily doped amorphous silicon layer 540 may be 100 angstroms to 200 angstroms.
  • the thickness of the composite doped layer as 400 angstroms as an example, wherein the thickness of the first N-type lightly doped amorphous silicon layer 510 may be 100 angstroms, and the second N-type lightly doped amorphous silicon layer 520 The thickness may be 100 Angstroms, the thickness of the first N-type heavily doped amorphous silicon layer 530 may be 100 Egypt, and the thickness of the second N-type heavily doped amorphous silicon layer 540 may be 100 Angstroms, it can be understood that for the first N-type The thickness of the lightly doped amorphous silicon layer 510, the second N-type lightly doped amorphous silicon layer 520, the first N-type heavily doped amorphous silicon layer 530 and the second N-type heavily doped amorphous silicon layer 540 may be It is selected and adjusted according to the actual production situation and product performance, which is not further limited here.
  • the thickness of the composite doped layer 50 is divided into four sub-doped layers with different ion doping concentrations and the same thickness, which can ensure that the overall size of the original device is not affected, and at the same time, due to the Different concentration gradients can also make electron injection easier, and can effectively increase the energy barrier between the source and drain and the composite doped layer, improve the barrier for hole transport, reduce leakage current, and increase the reliability and reliability of thin-film transistors. stability.
  • the source electrode 610 and the drain electrode 620 are formed on the composite doped layer 50.
  • the formation process of the source electrode 610 and the drain electrode 620 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the source electrode 610 and the drain electrode 620 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the source electrode 610 and the drain electrode 620 can be one or more of a stack combination of molybdenum, titanium, aluminum and copper; the selection of molybdenum, titanium, aluminum and copper as the source electrode 610 and the drain electrode 620 can ensure good Conductive properties.
  • the materials of the source electrode 610 and the drain electrode 620 can be selected and adjusted according to actual application conditions and product performance, and are not further limited herein.
  • the thickness of the source electrode 610 and the drain electrode 620 may be from 3500 angstroms to 5000 angstroms. Alternatively, the thickness of the source electrode 610 and the drain electrode 620 may be from 3500 angstroms to 4000 angstroms. Further, the thickness of the source electrode 610 and the drain electrode 620 The thickness may be 4000 to 5000 Angstroms.
  • the material and thickness of the source electrode 610 and the drain electrode 620 may be the same or different, and the material and thickness of the source electrode 610 and the drain electrode 620 may be selected and adjusted according to the actual application situation and product performance, and no further details will be made here. limited.
  • the channel region 80 is located in the middle of the composite doped layer 50.
  • the channel region 80 penetrates the composite doped layer 50 and partially penetrates the active layer 40.
  • the source electrode 610 and the drain electrode 620 are located on both sides of the channel region 80.
  • "Through" can be achieved by photolithography or etching methods. Specifically, photolithography refers to the use of a reticle with a certain layer of design graphics. After exposure and development, the photosensitive photoresist forms a three-dimensional relief on the substrate Graphics. Etching means that under the masking of photoresist, different microlayer patterns are formed as required, and different etching substances and methods are used to selectively etch the film layers. In this way, after removing the photoresist, the three-dimensional design pattern is transferred to the relevant film layer of the substrate.
  • FIG. 2 is a schematic structural diagram of a thin film transistor structure in another embodiment.
  • the thin film transistor structure may include a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, a compound doped layer 50, a source 610, a drain 620, and a protective layer 70.
  • the gate 20 is formed on the substrate 10; the gate insulating layer 30 is formed on the substrate 10, and the gate insulating layer 30 covers the gate 20; the active layer 40 is formed on the gate insulating layer 30; the composite doped layer 50 is formed on the active layer 40; the source electrode 610 and the drain electrode 620 are formed on the composite doped layer 50, and the protective layer 70 is formed on the source electrode 610 and the drain electrode 620.
  • the composite doped layer 50 may include a first N-type lightly doped amorphous silicon layer 510, a second N-type lightly doped amorphous silicon layer 520, and a first N-type heavily doped amorphous silicon layer 530 stacked in sequence And a second N-type heavily doped amorphous silicon layer 540, a first N-type lightly doped amorphous silicon layer 510, a second N-type lightly doped amorphous silicon layer 520, a first N-type heavily doped amorphous silicon layer
  • the ion doping concentration of the layer 530 and the second N-type heavily doped amorphous silicon layer 540 increases sequentially; a channel region 80 is located in the middle of the composite doped layer 50, and the channel region 80 penetrates through the composite doped layer 50 and partially Throughout to the active layer 40, the source electrode 610 and the drain electrode 620 are located on both sides of the channel region 80, while the protective layer 70 covers the channel region 80.
  • the gate 20, the gate insulating layer 30, the active layer 40, the composite doped layer 50, the source 610, the drain 620 material, forming process, composition, thickness, etc. can refer to the aforementioned thin film The description of the embodiments of the transistor structure will not be repeated here.
  • the protective layer 70 is mainly used to protect the thin film transistor device from pollution and damage. Specifically, the protective layer 70 is also called a PV (passivation) layer.
  • the material of the protective layer 70 may be silicon nitride, silicon oxide, or silicon dioxide. The combination of people. It can be understood that there is no particular limitation on the thickness of the protective layer 70, and those skilled in the art can select and adjust according to actual production conditions and product performance.
  • the above thin film transistor structure is provided with a composite doped layer with multiple concentration gradients (first N-type lightly doped amorphous silicon layer, second N-type lightly doped amorphous silicon layer, first N-type heavily doped amorphous silicon Layer and the second N-type heavily doped amorphous silicon layer) instead of the original single-layer doped layer, can increase the energy barrier between the source and drain and the composite doped layer, thereby reducing leakage current and improving the reliability of the thin film transistor Performance and stability, thereby improving the stability of the GOA circuit. Further, by providing a protective layer, the thin film transistor can be protected from damage.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a thin film transistor structure in an embodiment.
  • the manufacturing method of the thin film transistor structure may include steps: S100-S600.
  • Step S100 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate.
  • the substrate 10 may be a glass substrate or a plastic substrate.
  • the glass substrate may be alkali-free borosilicate ultra-thin glass.
  • the alkali-free borosilicate glass has higher physical characteristics Good corrosion resistance, higher thermal stability and lower density and higher elastic modulus.
  • the deposition of the first metal layer (not shown in FIG. 4) on the substrate 10 may be a radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process.
  • the first metal layer (not shown in FIG. 4) may be a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the patterning process may be to form a desired pattern by photolithography process. That is the gate 20.
  • the thickness of the gate electrode 20 may range from 3000 angstroms to 5000 angstroms. Alternatively, the thickness of the gate electrode 20 may be 3000 angstroms to 4000 angstroms. Further, the thickness of the gate electrode 20 may be 4000 angstroms to 5000 angstroms. It can be understood that the thickness of the gate electrode 20 can be selected and adjusted according to actual application conditions and product performance, which is not further limited herein.
  • Step S200 a gate insulating layer is deposited on the substrate, and the gate insulating layer covers the gate.
  • a gate insulating layer 30 is deposited on the substrate 10, and at the same time, the gate insulating layer 30 covers the gate 20.
  • the deposition process may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process.
  • the thickness of the gate insulating layer 30 may be 3000 angstroms-5000 angstroms. Alternatively, the thickness of the gate insulating layer 30 may be 3000 angstroms-3500 angstroms. Further, the thickness of the gate insulating layer 30 may be 3500 angstroms-4000 angstroms.
  • the thickness of the gate insulating layer 30 may be from 4000 angstroms to 5000 angstroms. It can be understood that the thickness of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the gate insulating layer 30 may be one or a combination of silicon oxide and silicon nitride, that is, the gate insulating layer 30 may be silicon oxide, silicon nitride, or silicon oxide and nitrogen Silicone mixture.
  • the plasma enhanced chemical vapor deposition gate insulating layer 30 can be divided into a first rate deposition, a second rate deposition, and a third rate deposition; wherein, the first rate, the first rate The values of the second rate and the third rate decrease sequentially.
  • the value of the first rate is greater than the value of the second rate
  • the value of the second rate is greater than the value of the third rate.
  • the first rate is the high speed
  • the second rate corresponds to medium speed
  • the third rate corresponds to low speed.
  • the thickness of the gate insulating layer formed by the first rate deposition is 0 angstroms to 2000 angstroms
  • the thickness of the gate insulating layer formed by the second rate deposition is 0 angstroms to 2000 angstroms
  • the gate insulating layer formed by the third rate deposition The thickness of the layer is 0 to 2000 angstroms.
  • the thickness of the gate insulating layer formed by the first rate deposition is 500 angstroms
  • the thickness of the gate insulating layer formed by the second rate deposition is 2000 angstroms
  • the thickness of the gate insulating layer formed by the third rate deposition is 1000 Egypt.
  • the thickness of the gate insulating layer formed by the first rate deposition is 500 angstroms
  • the thickness of the gate insulating layer formed by the second rate deposition is 1000 angstroms
  • the thickness of the gate insulating layer formed by the third rate deposition is 2000 Egypt.
  • the deposition formation of the gate insulating layer 30 is divided into three deposition stages, first using the first rate deposition can increase the deposition rate and increase the productivity, then using the second rate deposition to perform the rate transition, and transitioning to the third deposition rate for the deposition
  • the channel region to be formed subsequently has good interface characteristics, and at the same time, the unevenness of the interface between the amorphous silicon and the gate insulating layer can be reduced, and the electron mobility can be improved.
  • Step S300 an active layer and a composite doped layer are sequentially deposited on the gate insulating layer;
  • the composite doped layer includes a first N-type lightly doped amorphous silicon layer and a second N-type lightly doped layer sequentially stacked A hetero-amorphous silicon layer, a first N-type heavily doped amorphous silicon layer and a second N-type heavily doped amorphous silicon layer, wherein the first N-type lightly-doped amorphous silicon layer and the second N-type lightly-doped layer.
  • the ion doping concentration of the hetero-amorphous silicon layer, the first N-type heavily doped amorphous silicon layer, and the second N-type heavily doped amorphous silicon layer increases sequentially.
  • the active layer 40, the first N-type lightly doped amorphous silicon layer 510, and the second N-type light-weight layer may be deposited by radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition processes
  • the doped amorphous silicon layer 520, the first N-type heavily doped amorphous silicon layer 530, and the second N-type heavily doped amorphous silicon layer 540 may be deposited by radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition processes.
  • the doped amorphous silicon layer 520, the first N-type heavily doped amorphous silicon layer 530, and the second N-type heavily doped amorphous silicon layer 540 may be deposited by radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition processes
  • the active layer 40 can be deposited using SiH4 gas, the first N-type lightly doped amorphous silicon layer 510, the second N-type lightly doped amorphous silicon layer 520, and the first N-type heavy doping can be deposited using PH3 and SiH4 gas.
  • the gas flow ratio of PH3 and SiH4 may be 0.5-1.5; alternatively, PH3
  • the gas flow ratio with SiH4 can also be 0.5-1; alternatively, the gas flow ratio of PH3 and SiH4 can also be 1-1.5.
  • the gas flow ratio of PH3 and SiH4 may be 1.8-4.5; alternatively, the gas of PH3 and SiH4 The flow ratio can also be 1.8-3; alternatively, the gas flow ratio of PH3 and SiH4 can also be 3-4.5.
  • the first N-type lightly doped amorphous silicon layer 510, the second N-type lightly doped amorphous silicon layer 520, the first N-type heavily doped amorphous silicon layer 530 and the second N-type heavily doped increases sequentially.
  • the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510 is less than that of the second N-type lightly doped amorphous silicon layer 520 Impurity concentration
  • the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520 is less than the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530
  • the ion doping concentration of 530 is less than that of the second N-type heavily doped amorphous silicon layer 540.
  • the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520 is 1.5 times to 3 times the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510.
  • the first The ion doping concentration of the second N-type lightly doped amorphous silicon layer 520 is 1.5 times to 2 times the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510, optionally, the second N-type lightly doped amorphous silicon layer 510
  • the ion doping concentration of the doped amorphous silicon layer 520 is 2 times to 3 times the ion doping concentration of the first N-type lightly doped amorphous silicon layer 510.
  • the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530 is 2-6 times the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520, optionally, the first N-type
  • the ion doping concentration of the heavily doped amorphous silicon layer 530 is 2-4 times the ion doping concentration of the second N-type lightly doped amorphous silicon layer 520; alternatively, the first N-type heavily doped non-crystalline
  • the ion doping concentration of the crystalline silicon layer 530 is 4-6 times that of the second N-type lightly doped amorphous silicon layer 520.
  • the ion doping concentration of the second N-type heavily doped amorphous silicon layer 540 is 1.5 to 3 times the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530, optionally, the second N-type
  • the ion doping concentration of the heavily doped amorphous silicon layer 540 is 1.5 times to 2 times the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530, optionally, the second N-type heavily doped non-crystalline
  • the ion doping concentration of the crystalline silicon layer 540 is 2 times to 3 times the ion doping concentration of the first N-type heavily doped amorphous silicon layer 530.
  • Step S400 the active layer, the first N-type lightly doped amorphous silicon layer, the second N-type lightly doped amorphous silicon layer, the first N-type heavily doped amorphous silicon layer and the second N-type
  • the heavily doped amorphous silicon layer is subjected to photolithography.
  • the active layer 40 the first N-type lightly doped amorphous silicon layer 510, the second N-type lightly doped amorphous silicon layer 520, the first N-type heavily doped amorphous layer
  • the silicon layer 530 and the second N-type heavily doped amorphous silicon layer 540 are subjected to photolithography to obtain a three-dimensional pattern as shown in FIG. 6.
  • Photolithography refers to the use of a reticle with a certain layer of design graphics. After exposure and development, a photosensitive photoresist is used to form a three-dimensional relief pattern on the substrate.
  • Step S500 Deposit a second metal layer on the second N-type heavily doped amorphous silicon layer, and perform photolithography and wet etching on the second metal layer to obtain a layer located on the second metal layer A first groove in the middle and penetrating the second metal layer.
  • the second metal layer is separated into a source electrode and a drain electrode by the first groove.
  • FIG. 7 deposit a second metal layer (not shown in FIG. 7) on the second N-type heavily doped amorphous silicon layer 540, and perform photolithography and wet etching on the second metal layer.
  • a first groove 81 located in the middle of the second metal layer and penetrating the second metal layer is obtained.
  • the second metal layer is separated by the first groove 81 into a source electrode 610 and a drain electrode 620.
  • a photoresist layer can be coated on the second metal layer, and then a photomask can be used to expose and develop the photoresist layer.
  • the second metal layer is wet-etched with the photoresist layer as a shield to obtain a first groove 81 located in the middle of the second metal layer and penetrating the first metal layer, as shown in FIG. 7
  • On the left and right sides of the first groove 81 are a source electrode 610 and a drain electrode 620, respectively.
  • Step S600 using the source electrode and the drain electrode as an etch stop layer, the active layer, the first N-type lightly doped amorphous silicon layer, the second N-type lightly doped amorphous silicon layer, the first N Type heavily doped amorphous silicon layer and the second N type heavily doped amorphous silicon layer are dry etched to obtain a second groove corresponding to the first groove, the second groove penetrates through the The first N-type lightly doped amorphous silicon layer, the second N-type lightly doped amorphous silicon layer, the first N-type heavily doped amorphous silicon layer and the second N-type heavily doped amorphous silicon layer, and Partly penetrating the active layer, the first groove and the second groove form a channel region.
  • the source electrode 610 and the drain electrode 620 are used as etch stop layers to lightly dope the active layer 40 and the first N-type amorphous silicon.
  • the layer 510, the second N-type lightly-doped amorphous silicon layer 520, the first N-type heavily-doped amorphous silicon layer 530 and the second N-type heavily-doped amorphous silicon layer 540 are dry etched to obtain The second groove corresponding to the first groove 81 (not shown in FIG. 8).
  • the second groove penetrates the first N-type lightly doped amorphous silicon layer 510, the second N-type lightly doped amorphous silicon layer 520, the first N-type heavily doped amorphous silicon layer 530, and the second N-type heavily doped
  • the hetero-amorphous silicon layer 540 partially penetrates the active layer 40. "Partial penetration” means that the active layer part located in the second groove is not completely etched. Because the active layer serves as a conductive medium, it cannot be completely etched. It can be understood that the specific thickness of the "part" can be selected and adjusted according to the actual production situation and product performance.
  • the first groove 81 and the second groove form a channel region 80.
  • the manufacturing method of the above thin film transistor structure is provided with a composite doped layer with multiple concentration gradients (first N-type lightly doped amorphous silicon layer, second N-type lightly doped amorphous silicon layer, first N-type heavily doped Amorphous silicon layer and the second N-type heavily doped amorphous silicon layer) instead of the original single-layer doped layer, can increase the energy barrier between the source and drain and the composite doped layer, thereby reducing leakage current and improving the film The reliability and stability of the transistor, which in turn improves the stability of the GOA circuit.
  • the manufacturing method of the thin film transistor structure may further include the following steps:
  • the channel region is placed in a preset gas atmosphere for heating; wherein, the channel region is first heated for 0s-50s, then placed in a nitrogen atmosphere for 0s-20s, and finally placed in ammonia gas 0s-20s heating in the atmosphere; or
  • the active layer the first N-type lightly doped amorphous silicon layer, the second N-type lightly doped amorphous silicon layer, the first N-type heavily doped amorphous silicon layer and the second N-type heavy
  • the channel region will be damaged. Therefore, in order to repair the damage of the channel region, the channel region may be subjected to gas heating treatment.
  • the specific heating environment and heating time can be: under the heating temperature of 275 °C-285 °C, the channel area is first heated for 0s-50s, optionally, first heated for 25s; then placed in a nitrogen atmosphere and heated for 0s-20s Alternatively, the channel region may be heated in an atmosphere of nitrogen for 15 s; finally placed in an atmosphere of ammonia for 0 s-20 s, and optionally, heated in an atmosphere of ammonia for 7 s. Finally, it is heated in an atmosphere of ammonia for 0s-20s, and optionally, heated in an atmosphere of ammonia for 7s.
  • the weak bonds in the amorphous silicon can be reduced, the illumination and illumination stability of the thin film transistor structure can be enhanced, the threshold voltage drift can be reduced, and the final display effect of the display device can be improved.
  • a display device may include the aforementioned thin film transistor structure embodiment.
  • the above display device has a thin film transistor structure, and the thin film transistor structure is provided with a composite doped layer (first N-type lightly doped) (Amorphous silicon layer, second N-type lightly doped amorphous silicon layer, first N-type heavily doped amorphous silicon layer and second N-type heavily doped amorphous silicon layer) instead of the original single-layer doped layer
  • first N-type lightly doped Amorphous silicon layer, second N-type lightly doped amorphous silicon layer, first N-type heavily doped amorphous silicon layer and second N-type heavily doped amorphous silicon layer

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Abstract

一种薄膜晶体管结构及其制作方法、显示装置。该薄膜晶体管结构包括依次形成于基板(10)上的栅极(20)、栅极绝缘层(30)、有源层(40)、复合掺杂层(50)及源极(610)与漏极(620)；其中，复合掺杂层(50)包括依次层叠的第一N型轻掺杂非晶硅层(510)、第二N型轻掺杂非晶硅层(520)、第一N型重掺杂非晶硅层(530)及第二N型重掺杂非晶硅层(540)，第一N型轻掺杂非晶硅层(510)、第二N型轻掺杂非晶硅层(520)、第一N型重掺杂非晶硅层(530)及第二N型重掺杂非晶硅层(540)的离子掺杂浓度依次递增。

Description

薄膜晶体管结构及其制作方法、显示装置
相关申请的交叉引用
本申请要求于2018年12月03日提交中国专利局、申请号为201811466315.X、申请名称为“薄膜晶体管结构及其制作方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种薄膜晶体管结构及其制作方法、显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
GOA(Gate Driven on Array，阵列基板上栅驱动集成)技术，能实现显示面板的逐行扫描驱动功能，利用GOA技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
而用于控制逐行扫描开关的开关元件，例如TFT(Thin Film Transistor，薄膜晶体管)由于自身存在漏电电流的特性，常常会导致GOA电路出现多种不良。例如：在内嵌式触控显示器中，将一帧时间分为触控阶段和显示阶段，并采用分时驱动的方式进行驱动，在进行触控驱动时，由于TFT漏电电流的存在，暂停输出栅极驱动信号的那一级GOA电路的高电位会逐渐变低，且在重新进入显示阶段时，该级GOA电路的输出电压也会低于正常的栅极驱动信号的电压，因此会在显示屏上出现一条由于显示亮度较暗形成的暗线，并且该问题在每次由触控阶段切换到显示阶段时都会出现，最终用户会在显示屏上看到多条暗线。如何减小TFT漏电电流对GOA电路的输出的影响，进而提高显示器的显示效果是本领域技术人员亟待解决的问题。
申请内容
根据本申请的各种实施例，提供一种可以改善TFT漏电电流对GOA电路输出产生影响的薄膜晶体管结构。
此外，还提供一种薄膜晶体管结构的制作方法、显示装置。
一种薄膜晶体管结构，包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
有源层，形成于所述栅极绝缘层上；
复合掺杂层，形成于所述有源层上；及
形成于所述复合掺杂层上的源极与漏极；
其中，所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；一沟道区位于所述复合掺杂层的中部，所述沟道区贯穿所述复合掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
一种薄膜晶体管结构的制作方法，用于制造薄膜晶体管结构，所述薄膜晶体管结构，包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
有源层，形成于所述栅极绝缘层上；
复合掺杂层，形成于所述有源层上；及
形成于所述复合掺杂层上的源极与漏极；
其中，所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；一沟道区位于所述复合掺杂层的中部，所述沟道区贯穿所述复合掺杂层、并部分贯穿至 所述有源层，所述源极与漏极位于所述沟道区的两侧；
所述方法包括：
提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
在所述栅极绝缘层上依次沉积有源层、复合掺杂层；所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，其中，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；
对所述有源层、第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层进行光刻处理；
在所述第二N型重掺杂非晶硅层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层被所述第一凹槽间隔成源极、漏极；
以所述源极、漏极为刻蚀阻挡层，对所述有源层、第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区。
一种显示装置，包括薄膜晶体管结构，所述薄膜晶体管结构，包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
有源层，形成于所述栅极绝缘层上；
复合掺杂层，形成于所述有源层上；及
形成于所述复合掺杂层上的源极与漏极；
其中，所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二 N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；一沟道区位于所述复合掺杂层的中部，所述沟道区贯穿所述复合掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
上述薄膜晶体管结构，设置具有多浓度梯度的复合掺杂层(第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层)代替原有的单层掺杂层，可增加源漏极与复合掺杂层之间的能障，提高空穴传输的势垒，进而降低漏电流，提高薄膜晶体管的可靠性和稳定性，进而提高GOA电路的稳定性。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的薄膜晶体管结构的结构示意图；
图2为另一实施例中的薄膜晶体管结构的结构示意图；
图3为一实施例中的薄膜晶体管结构的制作方法流程示意图；
图4为图3中根据步骤S100形成的结构示意图；
图5为图3中根据步骤S200形成的结构示意图；
图6为图3中根据步骤S300和S400形成的结构示意图；
图7为图3中根据步骤S500形成的结构示意图；
图8为图3中根据步骤S600形成的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的可选的实施例。但是，本申请可以以许多不同的形式 来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参照图1，为一实施例中的薄膜晶体管结构的结构示意图；该薄膜晶体管结构可以包括：基板10，栅极20，栅极绝缘层30，有源层40，复合掺杂层50及源极610、漏极620。其中，栅极20形成于基板10上；栅极绝缘层30形成于基板10上，同时栅极绝缘层30覆盖栅极20；有源层40形成于栅极绝缘层30上；复合掺杂层50形成于有源层40上；源极610、漏极620形成于复合掺杂层50上。其中，复合掺杂层50可以包括依次层叠的第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540，第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540的离子掺杂浓度依次递增；一沟道区80位于复合掺杂层50的中部，沟道区80贯穿复合掺杂层50、并部分贯穿至有源层40，源极610与漏极620位于沟道区80的两侧。
上述薄膜晶体管结构，设置具有多浓度梯度的复合掺杂层(第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层)代替原有的单层掺杂层，可增加源漏极与复合掺杂层之间的能障，进而降低漏电流，提高薄膜晶体管的可靠性和稳定性，进而提高GOA电路的稳定性。
基板10可以是玻璃基板或塑料基板，其中，玻璃基板可以为无碱硼硅酸盐超薄玻璃，无碱硼硅酸盐玻璃具有较高的物理特性、较好的耐腐蚀性能、较高的热稳定性以及较低的密度和较高的弹性模量。
栅极20形成于基板10上，其中，栅极20的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，栅极20的形成工艺可以根据实际应用情况以及产品性能进行 选择和调整，在此不作进一步的限定。栅极20的材料可以为钼、钛、铝和铜中的一种或者多种的堆栈组合；选用钼、钛、铝和铜作为栅极20材料可以保证良好的导电性能。可以理解，栅极20的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极20的厚度范围可以为3000埃-5000埃，可选地，栅极20的厚度可以为3000埃-4000埃，进一步地，栅极20的厚度可以为4000埃-5000埃。可以理解，栅极20的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
栅极绝缘层30，形成于基板10上，栅极绝缘层30的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，栅极绝缘层30的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极绝缘层30的材料可以是氧化硅、氮化硅中的一种或者二者的组合，即栅极绝缘层30可以是氧化硅，也可以是氮化硅，还可以是氧化硅和氮化硅的混合物。可以理解，栅极绝缘层30的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极绝缘层30的厚度可以为3000埃-5000埃，可选地，栅极绝缘层30的厚度可以为3500埃-4000埃，进一步地，栅极绝缘层30的厚度可以为4000埃-5000埃。可以理解，栅极绝缘层30的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
有源层40，形成于栅极绝缘层30上，有源层40的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，有源层40的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。有源层40的材料可以为非晶硅，有源层40通常作为导电的介质。有源层40的厚度可以为550埃-700埃，可选地，有源层40的厚度为550埃-600埃，进一步地，有源层40的厚度可以为600埃-700埃。可以理解，有源层40的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
复合掺杂层50，形成于有源层40上，复合掺杂层50的形成工艺可以 包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，复合掺杂层50的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。复合掺杂层50为N型掺杂，其中，掺杂方式可以包括高温扩散和离子注入。高温扩散是将杂质原子通过气相源或掺杂过的氧化物扩散或淀积到硅晶片的表面，这些杂质浓度将从表面到体内单调下降，在高温扩散中，杂质的分布主要是由高温与扩散时间来决定。离子注入即将掺杂离子以离子束的形式注入半导体内，杂质浓度在半导体内有峰值分布，在离子注入中，杂质分布主要由离子质量和注入能量决定。N型掺杂主要是在半导体内掺入五价杂质元素，例如：磷、砷。离子注入相对于高温扩散的优点是：1、注入的离子是通过质量分析器选取出来的，被选取的粒子纯度高，能量单一，从而保证了掺杂浓度不受杂质源纯度的影响。另外，注入过程在清洁、干燥的真空条件下进行，各种污染降到最低水平；2、可以精确控制注入到晶片中的掺杂原子数目，注入剂量从用于调整阈值电压的10 11/cm 2到形成绝缘埋层的10 17/cm 2，范围较宽。3、离子注入时，衬底一般保持在室温或低于400℃的温度环境下。因此，像二氧化硅、氮化硅、铝和光刻胶等都可以用来作为选择掺杂的掩蔽膜，使器件制造中的自对准掩蔽技术更加灵活。
进一步地，复合掺杂层50可以包括依次层叠的第一N型轻掺杂非晶硅层510，第二N型轻掺杂非晶硅层520，第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540。如图1所示，N--表示第一N型轻掺杂非晶硅层510，N-表示第二N型轻掺杂非晶硅层520，N+表示第一N型重掺杂非晶硅层530，N++表示第二N型重掺杂非晶硅层540。N--、N-、N+、N++中的正负号表示离子掺杂的浓度。其中，第一N型轻掺杂非晶硅层510，第二N型轻掺杂非晶硅层520，第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540的离子掺杂浓度依次递增，换句话说，第一N型轻掺杂非晶硅层510的离子掺杂浓度小于第二N型轻掺杂非晶硅层520的离子掺杂浓度，第二N型轻掺杂非晶硅层520的离子掺杂浓度小于第一N型重掺杂非晶硅层530的离子掺杂浓度，第一N型重掺杂非晶硅层530的离子掺杂浓度小于第二N型重掺杂非晶硅层540的离子掺杂浓度。
具体地，第二N型轻掺杂非晶硅层520的离子掺杂浓度为第一N型轻掺杂非晶硅层510的离子掺杂浓度的1.5倍-3倍，可选地，第二N型轻掺杂非晶硅层520的离子掺杂浓度为第一N型轻掺杂非晶硅层510的离子掺杂浓度的1.5倍-2倍，可选地，第二N型轻掺杂非晶硅层520的离子掺杂浓度为第一N型轻掺杂非晶硅层510的离子掺杂浓度的2倍-3倍。第一N型重掺杂非晶硅层530的离子掺杂浓度为第二N型轻掺杂非晶硅层520的离子掺杂浓度的2倍-6倍，可选地，第一N型重掺杂非晶硅层530的离子掺杂浓度为第二N型轻掺杂非晶硅层520的离子掺杂浓度的2倍-4倍；可选地，第一N型重掺杂非晶硅层530的离子掺杂浓度为第二N型轻掺杂非晶硅层520的离子掺杂浓度的4倍-6倍。第二N型重掺杂非晶硅层540的离子掺杂浓度为第一N型重掺杂非晶硅层530的离子掺杂浓度的1.5倍-3倍，可选地，第二N型重掺杂非晶硅层540的离子掺杂浓度为第一N型重掺杂非晶硅层530的离子掺杂浓度的1.5倍-2倍，可选地，第二N型重掺杂非晶硅层540的离子掺杂浓度为第一N型重掺杂非晶硅层530的离子掺杂浓度的2倍-3倍。
更进一步地，复合掺杂层50的厚度可以为300埃-600埃。可选地，复合掺杂层50的厚度可以为300埃-400埃；可选地，复合掺杂层50的厚度可以为400埃-500埃；可选地，复合掺杂层50的厚度可以为500埃-600埃。可以理解，复合掺杂层50的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。由于复合掺杂层50包括第一N型轻掺杂非晶硅层510，第二N型轻掺杂非晶硅层520，第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540。所以，第一N型轻掺杂非晶硅层510的厚度可以为80埃-200埃，可选地，第一N型轻掺杂非晶硅层510的厚度可以为80埃-100埃；可选地，第一N型轻掺杂非晶硅层510的厚度可以为100埃-200埃。第二N型轻掺杂非晶硅层520的厚度可以为80埃-200埃，可选地，第二N型轻掺杂非晶硅层520的厚度可以为80埃-100埃；可选地，第二N型轻掺杂非晶硅层520的厚度可以为100埃-200埃。第一N型重掺杂非晶硅层530的厚度可以为80埃-200埃，可选地，第一N型重掺杂非晶硅层530的厚度可以为80埃-100埃；可选 地，第一N型重掺杂非晶硅层530的厚度可以为100埃-200埃。第二N型重掺杂非晶硅层540的厚度可以为80埃-200埃，可选地，第二N型重掺杂非晶硅层540的厚度可以为80埃-100埃；可选地，第二N型重掺杂非晶硅层540的厚度可以为100埃-200埃。示例性地，以复合掺杂层的厚度为400埃为例，其中，第一N型轻掺杂非晶硅层510的厚度可以为100埃，第二N型轻掺杂非晶硅层520的厚度可以为100埃，第一N型重掺杂非晶硅层530的厚度可以为100埃及第二N型重掺杂非晶硅层540可以为100埃，可以理解，对于第一N型轻掺杂非晶硅层510，第二N型轻掺杂非晶硅层520，第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540的厚度可根据实际生产情况和产品性能进行选择和调整，在此不作进一步地限定。将复合掺杂层50的厚度均分为四个不同离子掺杂浓度、且厚度相同的子掺杂层，可以保证不影响原本的器件的整体尺寸，同时，由于各子掺杂层之间具有不同的浓度梯度，还可以使得电子注入更加容易，并且可有效增加源漏极与复合掺杂层之间的能障，提高空穴传输的势垒，降低漏电流，增加薄膜晶体管的可靠性和稳定性。
源极610、漏极620形成于复合掺杂层上50，源极610、漏极620的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，源极610、漏极620的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。源极610、漏极620的材料可以为钼、钛、铝和铜中的一种或者多种的堆栈组合；选用钼、钛、铝和铜作为源极610、漏极620材料可以保证良好的导电性能。可以理解，源极610、漏极620的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。源极610、漏极620的厚度可以为3500埃-5000埃，可选地，源极610、漏极620的厚度可以为3500埃-4000埃，更进一步地，源极610、漏极620的厚度可以为4000埃-5000埃。可以理解，源极610、漏极620的材料和厚度可以相同也可以不相同，源极610、漏极620的材料和厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
沟道区80位于复合掺杂层50的中部，沟道区80贯穿复合掺杂层50、 并部分贯穿有源层40。源极610与漏极620就位于沟道区80的两侧。“贯穿”可以通过光刻或者刻蚀方法实现，具体的，光刻是指使用带有某一层设计图形的掩模版，经过曝光和显影，使光敏的光刻胶在衬底上形成三维浮雕图形。刻蚀是指在光刻胶掩蔽下，根据需要形成微图形的膜层不同，采用不同的刻蚀物质和方法在膜层上进行选择性刻蚀。这样，去掉光刻胶以后，三维设计图形就转移到了衬底的相关膜层上。
请参阅图2，为另一实施例中的薄膜晶体管结构的结构示意图。该薄膜晶体管结构可以包括基板10，栅极20，栅极绝缘层30，有源层40，复合掺杂层50，源极610、漏极620及保护层70。其中，栅极20形成于基板10上；栅极绝缘层30形成于基板10上，同时栅极绝缘层30覆盖栅极20；有源层40形成于栅极绝缘层30上；复合掺杂层50形成于有源层40上；源极610、漏极620形成于复合掺杂层50上，保护层70形成于源极610、漏极620上。其中，复合掺杂层50可以包括依次层叠的第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540，第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540的离子掺杂浓度依次递增；一沟道区80位于复合掺杂层50的中部，沟道区80贯穿复合掺杂层50、并部分贯穿至有源层40，源极610与漏极620位于沟道区80的两侧，同时保护层70覆盖沟道区80。
可以理解，对于基板10、栅极20、栅极绝缘层30、有源层40、复合掺杂层50、源极610、漏极620的材料、形成工艺、组成、厚度等，可以参照前述薄膜晶体管结构实施例的描述，在此不再进一步进行赘述。
保护层70，主要用于保护薄膜晶体管器件免受污染和损伤，具体的，保护层70也称为PV(Passivation,钝化)层，保护层70的材料可以是氮化硅、氧化硅或者二者的结合。可以理解，对于保护层70的厚度没有特殊限制，本领域技术人员可根据实际生产情况和产品性能进行选择和调整。
上述薄膜晶体管结构，设置具有多浓度梯度的复合掺杂层(第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层 及第二N型重掺杂非晶硅层)代替原有的单层掺杂层，可增加源漏极与复合掺杂层之间的能障，进而降低漏电流，提高薄膜晶体管的可靠性和稳定性，进而提高GOA电路的稳定性。进一步地，通过设置保护层，可保护薄膜晶体管免受损伤。
请参阅图3，为一实施例中的薄膜晶体管结构的制作方法流程示意图。该薄膜晶体管结构的制作方法可以包括步骤：S100-S600。
步骤S100，提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极。
具体地，请辅助参阅图4，基板10可以是玻璃基板或塑料基板，其中，玻璃基板可以为无碱硼硅酸盐超薄玻璃，无碱硼硅酸盐玻璃具有较高的物理特性、较好的耐腐蚀性能、较高的热稳定性以及较低的密度和较高的弹性模量。在基板10上沉积第一金属层(图4未标示)可以是射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。第一金属层(图4未标示)可以是钼、钛、铝和铜中的一种或者多种的堆栈组合。图案化处理可以是通过光刻处理形成所需的图案。也就是栅极20。栅极20的厚度范围可以为3000埃-5000埃，可选地，栅极20的厚度可以为3000埃-4000埃，进一步地，栅极20的厚度可以为4000埃-5000埃。可以理解，栅极20的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
步骤S200，在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极。
具体地，请辅助参阅图5，在基板10上沉积栅极绝缘层30，同时，栅极绝缘层30将栅极20覆盖住。沉积工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。栅极绝缘层30的厚度可以为3000埃-5000埃，可选地，栅极绝缘层30的厚度可以为3000埃-3500埃，进一步地，栅极绝缘层30的厚度可以为3500埃-4000埃，更进一步地，栅极绝缘层30的厚度可以为4000埃-5000埃。可以理解，栅极绝缘层30的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极绝缘层30的材料可以是氧化硅、氮化硅中 的一种或者二者的组合，即栅极绝缘层30可以是氧化硅，也可以是氮化硅，还可以是氧化硅和氮化硅的混合物。
更进一步地，以等离子增强化学气相沉积工艺为例，采用等离子增强化学气相沉积栅极绝缘层30可以分为第一速率沉积、第二速率沉积和第三速率沉积；其中，第一速率、第二速率及第三速率的数值依次递减，换句话说，第一速率的数值大于第二速率的数值，第二速率的数值大于第三速率的数值，可以这样理解，以第一速率为高速为例，第二速率相应为中速，第三速率相应为低速。当然，对于具体的数值本申请没有特殊限制，本领域人员可以实际生产情况和产品性能进行调整和选择。进一步地，第一速率沉积形成的栅极绝缘层的厚度为0埃-2000埃，第二速率沉积形成的栅极绝缘层的厚度为0埃-2000埃，第三速率沉积形成的栅极绝缘层的厚度为0埃-2000埃。可选地，第一速率沉积形成的栅极绝缘层的厚度为500埃，第二速率沉积形成的栅极绝缘层的厚度为2000埃，第三速率沉积形成的栅极绝缘层的厚度为1000埃。可选地，第一速率沉积形成的栅极绝缘层的厚度为500埃，第二速率沉积形成的栅极绝缘层的厚度为1000埃，第三速率沉积形成的栅极绝缘层的厚度为2000埃。将栅极绝缘层30的沉积形成分为三个沉积阶段，先使用第一速率沉积可以增加沉积速率，提高产能，然后使用第二速率沉积进行速率的过渡，过渡到第三沉积速率进行沉积可以使得后续形成的沟道区有良好的界面特性，同时还可减少非晶硅和栅极绝缘层界面的凹凸特性，提高电子迁移率。
步骤S300，在所述栅极绝缘层上依次沉积有源层、复合掺杂层；所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，其中，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增。
具体地，可以通过射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺来沉积有源层40、第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540。示例性地，以等离子增强化学气相沉积为例。可 采用SiH4气体来沉积有源层40，采用PH3和SiH4气体来沉积第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540。更进一步地，沉积第一N型轻掺杂非晶硅层510和第二N型轻掺杂非晶硅层520时，PH3和SiH4的气体流量比可以为0.5-1.5；可选地，PH3和SiH4的气体流量比还可以为0.5-1；可选地，PH3和SiH4的气体流量比还可以为1-1.5。沉积第一N型重掺杂非晶硅层530和第二N型重掺杂非晶硅层540时，PH3和SiH4的气体流量比可以为1.8-4.5；可选地，PH3和SiH4的气体流量比还可以为1.8-3；可选地，PH3和SiH4的气体流量比还可以为3-4.5。
更进一步地，第一N型轻掺杂非晶硅层510，第二N型轻掺杂非晶硅层520，第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540的离子掺杂浓度依次递增，换句话说，第一N型轻掺杂非晶硅层510的离子掺杂浓度小于第二N型轻掺杂非晶硅层520的离子掺杂浓度，第二N型轻掺杂非晶硅层520的离子掺杂浓度小于第一N型重掺杂非晶硅层530的离子掺杂浓度，第一N型重掺杂非晶硅层530的离子掺杂浓度小于第二N型重掺杂非晶硅层540的离子掺杂浓度。
具体地，第二N型轻掺杂非晶硅层520的离子掺杂浓度为第一N型轻掺杂非晶硅层510的离子掺杂浓度的1.5倍-3倍，可选地，第二N型轻掺杂非晶硅层520的离子掺杂浓度为第一N型轻掺杂非晶硅层510的离子掺杂浓度的1.5倍-2倍，可选地，第二N型轻掺杂非晶硅层520的离子掺杂浓度为第一N型轻掺杂非晶硅层510的离子掺杂浓度的2倍-3倍。第一N型重掺杂非晶硅层530的离子掺杂浓度为第二N型轻掺杂非晶硅层520的离子掺杂浓度的2倍-6倍，可选地，第一N型重掺杂非晶硅层530的离子掺杂浓度为第二N型轻掺杂非晶硅层520的离子掺杂浓度的2倍-4倍；可选地，第一N型重掺杂非晶硅层530的离子掺杂浓度为第二N型轻掺杂非晶硅层520的离子掺杂浓度的4倍-6倍。第二N型重掺杂非晶硅层540的离子掺杂浓度为第一N型重掺杂非晶硅层530的离子掺杂浓度的1.5倍-3倍，可选地，第二N型重掺杂非晶硅层540的离子掺杂浓度为第一N型重掺杂非晶硅层530的离子掺杂浓度的1.5倍-2倍，可选 地，第二N型重掺杂非晶硅层540的离子掺杂浓度为第一N型重掺杂非晶硅层530的离子掺杂浓度的2倍-3倍。
步骤S400，对所述有源层、第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层进行光刻处理。
具体地，请辅助参阅图6，对有源层40、第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540进行光刻处理得到如图6所示的立体图案。光刻是指使用带有某一层设计图形的掩模版，经过曝光和显影，使光敏的光刻胶在衬底上形成三维浮雕图形。
步骤S500，在所述第二N型重掺杂非晶硅层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层通过所述第一凹槽间隔成源极、漏极。
具体地，请辅助参阅图7，在第二N型重掺杂非晶硅层540上沉积第二金属层(图7未标示)，对第二金属层进行光刻、湿法刻蚀处理，得到一位于第二金属层中部、并贯穿所述第二金属层的第一凹槽81，第二金属层被第一凹槽81间隔成源极610、漏极620。进一步地，可以通过在第二金属层上涂布一层光阻层，然后采用一道光罩对光阻层进行曝光、显影。更进一步地，然后以光阻层为遮挡，对第二金属层进行湿法刻蚀，得到一位于第二金属层中部、并贯穿第一金属层的第一凹槽81，得到如图7所示的立体图案。在第一凹槽81的左右两侧分别为源极610和漏极620。
步骤S600，以所述源极、漏极为刻蚀阻挡层，对所述有源层、第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区。
具体地，请辅助参阅图8，在形成源极610和漏极620之后，以源极 610和漏极620为刻蚀阻挡层，对有源层40、第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540进行干法刻蚀处理，得到与第一凹槽81对应的第二凹槽(图8未标示)。第二凹槽贯穿第一N型轻掺杂非晶硅层510、第二N型轻掺杂非晶硅层520、第一N型重掺杂非晶硅层530及第二N型重掺杂非晶硅层540、并部分贯穿至有源层40。“部分贯穿”即没有全部刻蚀掉位于第二凹槽中的有源层部分，因为有源层作为导电的介质，所以不能被全部刻蚀掉。可以理解，对于“部分”的具体厚度，可以根据实际生产情况和产品性能作出选择和调整。第一凹槽81与第二凹槽形成沟道区80。
上述薄膜晶体管结构的制作方法，设置具有多浓度梯度的复合掺杂层(第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层)代替原有的单层掺杂层，可增加源漏极与复合掺杂层之间的能障，进而降低漏电流，提高薄膜晶体管的可靠性和稳定性，进而提高GOA电路的稳定性。
在一个实施例中，薄膜晶体管结构的制作方法还可以包括步骤：
将所述沟道区置于预设的气体氛围中进行加热处理；其中，先对所述沟道区加热0s-50s，然后置于氮气的气氛中加热0s-20s，最后置于氨气的气氛中加热0s-20s；或
先对所述沟道区加热0s-50s，最后置于氨气的气氛中加热0s-20s。
具体地，在对有源层、第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层进行蚀刻形成沟道区的时候，会造成沟道区的损伤，因此，为了修复沟道区的损伤，可以对沟道区进行气体加热处理。具体的加热环境和加热时间可以为：在加热温度275℃-285℃之下，先对沟道区加热0s-50s，可选地，先加热25s；然后置于氮气的气氛中加热0s-20s，可选地，可将沟道区置于氮气的气氛中加热15s；最后置于氨气的气氛中加热0s-20s，可选地，在氨气的气氛中加热7s。最后置于氨气的气氛中加热0s-20s，可选地，在氨气的气氛中加热7s。或者，在加热温度275℃-285℃之下，先对沟道区加热0s-50s， 可选地，先加热25s；最后置于氨气的气氛中加热0s-20s，可选地，在氨气的气氛中加热10s。
通过采用上述处理方式来对沟道区进行处理，可以减少非晶硅中的弱键，增强薄膜晶体管结构的照光以及照光稳定性，减少阈值电压的漂移，进而可提高显示装置的最终显示效果。
一种显示装置，可以包括前述所述的薄膜晶体管结构实施例，上述显示装置，由于采用薄膜晶体管结构，同时上述薄膜晶体管结构设置具有多浓度梯度的复合掺杂层(第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层)代替原有的单层掺杂层，可增加源漏极与复合掺杂层之间的能障，进而降低漏电流，同时薄膜晶体管结构中对沟道区进行了气体加热处理，可使得最终的显示装置的显示效果得以进一步提高。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种薄膜晶体管结构，包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
    有源层，形成于所述栅极绝缘层上；
    复合掺杂层，形成于所述有源层上；及
    形成于所述复合掺杂层上的源极与漏极；
    其中，所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；一沟道区位于所述复合掺杂层的中部，所述沟道区贯穿所述复合掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
  2. 根据权利要求1所述的薄膜晶体管结构，其中，所述复合掺杂层的厚度为300埃-600埃；其中，所述第一N型轻掺杂非晶硅层的厚度为80埃-200埃，所述第二N型轻掺杂非晶硅层的厚度为80埃-200埃，所述第一N型重掺杂非晶硅层的厚度为80埃-200埃，所述第二N型重掺杂非晶硅层的厚度为80埃-200埃。
  3. 根据权利要求2所述的薄膜晶体管结构，其中，所述复合掺杂层的厚度为400埃；其中，所述第一N型轻掺杂非晶硅层的厚度为100埃，所述第二N型轻掺杂非晶硅层的厚度为100埃，所述第一N型重掺杂非晶硅层的厚度为100埃，所述第二N型重掺杂非晶硅层的厚度为100埃。
  4. 根据权利要求1所述的薄膜晶体管结构，其中，所述栅极的厚度范围为3000埃-5000埃。
  5. 根据权利要求4所述的薄膜晶体管结构，其中，所述栅极包括钼、钛、铝和铜中的至少一种。
  6. 根据权利要求1所述的薄膜晶体管结构，其中，所述第二N型轻掺杂非晶硅层的离子掺杂浓度为所述第一N型轻掺杂非晶硅层的离子掺杂浓度的 1.5倍-3倍；所述第一N型重掺杂非晶硅层的离子掺杂浓度为所述第二N型轻掺杂非晶硅层的离子掺杂浓度的2倍-6倍；所述第二N型重掺杂非晶硅层的离子掺杂浓度为所述第一N型重掺杂非晶硅层的离子掺杂浓度的1.5倍-3倍。
  7. 根据权利要求1所述的薄膜晶体管结构，其中，所述栅极绝缘层的厚度范围为3000埃-5000埃。
  8. 根据权利要求7所述的薄膜晶体管结构，其中，所述栅极绝缘层包括氧化硅和氮化硅中的至少一种。
  9. 根据权利要求1所述的薄膜晶体管结构，其中，还包括：
    保护层，形成于所述源极、漏极上。
  10. 一种薄膜晶体管结构的制作方法，其中，用于制造薄膜晶体管结构，所述薄膜晶体管结构，包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
    有源层，形成于所述栅极绝缘层上；
    复合掺杂层，形成于所述有源层上；及
    形成于所述复合掺杂层上的源极与漏极；
    其中，所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；一沟道区位于所述复合掺杂层的中部，所述沟道区贯穿所述复合掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧；
    所述方法包括：
    提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
    在所述栅极绝缘层上依次沉积有源层、复合掺杂层；所述复合掺杂层包 括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，其中，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；
    对所述有源层、第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层进行光刻处理；
    在所述第二N型重掺杂非晶硅层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层被所述第一凹槽间隔成源极、漏极；
    以所述源极、漏极为刻蚀阻挡层，对所述有源层、第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区。
  11. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中，所述第一金属层的沉积工艺包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺中的一种。
  12. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中，所述沉积栅极绝缘层分为第一速率沉积、第二速率沉积和第三速率沉积；其中，所述第一速率、第二速率及第三速率的数值依次递减。
  13. 根据权利要求12所述的薄膜晶体管结构的制作方法，其中，所述第一速率沉积形成的栅极绝缘层的厚度为0埃-2000埃，所述第二速率沉积形成的栅极绝缘层的厚度为0埃-2000埃，所述第三速率沉积形成的栅极绝缘层的厚度为0埃-2000埃。
  14. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中，沉积所述第一N型轻掺杂非晶硅层和所述第二N型轻掺杂非晶硅层时，采用PH3和SiH4气体进行沉积，其中，PH3和SiH4的气体流量比为0.5-1.5。
  15. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中，沉积所 述第一N型重掺杂非晶硅层和所述第二N型重掺杂非晶硅层时，采用PH3和SiH4气体进行沉积，其中，PH3和SiH4的气体流量比为1.8-4.5。
  16. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中，所述源极的厚度范围为3500埃-5000埃；所述漏极的厚度范围为3500埃-5000埃。
  17. 根据权利要求16所述的薄膜晶体管结构的制作方法，其中，所述源极包括钼、钛、铝和铜中的至少一种；所述漏极包括钼、钛、铝和铜中的至少一种。
  18. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中，还包括：
    将所述沟道区置于预设的气体氛围中进行加热处理；其中，先对所述沟道区加热0s-50s，然后置于氮气的气氛中加热0s-20s，最后置于氨气的气氛中加热0s-20s。
  19. 根据权利要求10所述的薄膜晶体管结构的制作方法，其中，还包括：
    将所述沟道区置于预设的气体氛围中进行加热处理；其中，先对所述沟道区加热0s-50s，最后置于氨气的气氛中加热0s-20s。
  20. 一种显示装置，其中，包括薄膜晶体管结构，所述薄膜晶体管结构，包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
    有源层，形成于所述栅极绝缘层上；
    复合掺杂层，形成于所述有源层上；及
    形成于所述复合掺杂层上的源极与漏极；
    其中，所述复合掺杂层包括依次层叠的第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层，第一N型轻掺杂非晶硅层、第二N型轻掺杂非晶硅层、第一N型重掺杂非晶硅层及第二N型重掺杂非晶硅层的离子掺杂浓度依次递增；一沟道区位于所述复合掺杂层的中部，所述沟道区贯穿所述复合掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
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