WO2017059722A1 - 阵列基板及其制作方法、显示装置、掩膜板 - Google Patents

阵列基板及其制作方法、显示装置、掩膜板 Download PDF

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WO2017059722A1
WO2017059722A1 PCT/CN2016/090998 CN2016090998W WO2017059722A1 WO 2017059722 A1 WO2017059722 A1 WO 2017059722A1 CN 2016090998 W CN2016090998 W CN 2016090998W WO 2017059722 A1 WO2017059722 A1 WO 2017059722A1
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region
heavily doped
layer
forming
mask
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PCT/CN2016/090998
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English (en)
French (fr)
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李付强
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US15/325,623 priority Critical patent/US10283536B2/en
Publication of WO2017059722A1 publication Critical patent/WO2017059722A1/zh

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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method for fabricating the same, a display device including the array substrate, and a mask.
  • Low temperature poly-silicon (LTPS) thin film transistor liquid crystal display is different from traditional amorphous silicon thin film transistor liquid crystal display, and its electron mobility is high, which can effectively reduce the area of the thin film transistor device, thereby improving the aperture ratio. And while improving the brightness of the display, it can also reduce the overall power consumption.
  • LTPS Low temperature poly-silicon
  • a part of the driving circuit can be integrated on the glass substrate, which reduces the cost of the driving circuit, and can also greatly improve the reliability of the liquid crystal display panel, thereby greatly reducing the manufacturing cost of the panel. Therefore, low-temperature polysilicon thin film transistor liquid crystal displays have gradually become a research hotspot.
  • an active layer, a gate, a via, a source and a drain are separately formed by a patterning process, and the active layer is ion doped.
  • the via includes a first via for connecting the source drain to the active layer, and a second via for connecting the gate line and a signal line for providing a scan signal to the gate line.
  • the gate in the step of performing ion doping, can be used as a mask for ion doping, but in order to prevent the influence of light on the active layer, it is necessary to additionally form the light shielding layer by one patterning process.
  • the top gate type low temperature polysilicon thin film transistor requires at least five patterning processes, resulting in a large number of masks to be used.
  • the light shielding layer can be omitted, but when ion doping is performed, it is necessary to use the mask again.
  • An object of the present disclosure is to provide an array substrate, a manufacturing method thereof, a display device, and a mask to reduce the use of a mask during fabrication.
  • the present disclosure provides a method of fabricating an array substrate, including:
  • the mask pattern comprising a hollow portion, a first portion and a second portion, the hollow portion for exposing a corresponding insulating layer of a portion of the gate line, the second portion corresponding to the a portion of the second region, the first portion being a portion other than the hollow portion and the second portion on the mask pattern, the second portion having a thickness smaller than a thickness of the first portion;
  • the second region includes an ion heavily doped region and an ion lightly doped region between the ion heavily doped region and the first region, and step S4 includes:
  • step S6 includes:
  • the photoresist is a positive photoresist
  • the mask comprises a transparent region, an opaque region and a semi-transmissive region
  • the transparent region of the mask corresponds to the gate A portion of the line
  • the semi-transmissive region of the mask corresponds to the ion heavily doped region
  • the portion of the mask that is outside the semi-transmissive region and the semi-transmissive region is an opaque region.
  • the manufacturing method further includes:
  • the manufacturing method further includes:
  • a common electrode is formed.
  • step S3 includes:
  • the polysilicon layer is patterned to form the active layer.
  • the present disclosure also provides an array substrate including a thin film transistor and a gate line connected to a gate of the thin film transistor.
  • the active layer of the thin film transistor includes a polysilicon region corresponding to the gate and a heavily doped source region and a heavily doped drain region respectively located on both sides of the polysilicon region, the active layer further including a polysilicon region and a heavy A lightly doped drain region between the doped source regions and between the polysilicon regions and the heavily doped source regions.
  • the source of the thin film transistor is electrically connected to the heavily doped source region, and the drain of the thin film transistor is electrically connected to the heavily doped drain region.
  • the gate of the thin film transistor is located below the active layer, and an insulating layer is disposed between the gate and the gate line and the active layer.
  • the array substrate further includes a conductive lead electrically connected to the gate line through a via extending through the insulating layer.
  • the source is overlapped in the heavily doped source region
  • the drain is overlapped in the heavily doped drain region.
  • the conductive lead and the source and the drain are made of the same material.
  • the present disclosure also provides a display device including the above array substrate provided by the present disclosure.
  • the present disclosure further provides a mask for fabricating an array substrate, the array substrate being the above array substrate provided by the disclosure, the mask comprising a light transmitting region, an opaque region, and a half a light transmissive region for corresponding to a portion of the gate line, the semi-transmissive region being for corresponding to the heavily doped source region and the heavily doped drain region, the mask plate A portion other than the light transmitting region and the semi-light transmitting region is formed as an opaque region.
  • the gate since the gate is formed before the active layer, it can function as a light blocking. Therefore, it is not necessary to make a light shielding layer, and a mask pattern is formed before the via holes are formed.
  • the mask pattern can be formed by using a mask once, and only a mask pattern is required as a mask when ion implantation is performed, and it is not necessary. The mask is used separately, which reduces the use of the mask and reduces the process cost.
  • FIG. 1 is a schematic view of a gate and a gate line formed in an embodiment of the present disclosure
  • Figure 2 is a schematic view after forming an insulating layer
  • FIG. 3 is a schematic view after forming an active layer
  • FIG. 4 is a schematic view of forming a photoresist layer
  • Figure 5 is a schematic view of the photoresist after development
  • Figure 6 is a schematic view showing the formation of via holes
  • Figure 7 is a schematic view of the photoresist layer after the first ashing
  • Figure 8 is a schematic view showing the first ion implantation
  • Figure 9 is a schematic view of the photoresist layer after the second ashing
  • Figure 10 is a schematic view showing the second ion implantation
  • Figure 11 is a schematic view showing the formation of a wire lead, a source, and a drain;
  • FIG. 12 is a partial structural schematic view of an array substrate in another embodiment of the present disclosure.
  • the reference numerals are: 11, the gate; 12, the gate line; 20, the insulating layer; 30, the active layer; 31, the heavily doped source region; 32, the heavily doped drain region; Miscellaneous region; 34, polysilicon region; 40, photoresist layer; 50, mask; A1, first region; A2, second region; A21, ion heavily doped region; A22, ion lightly doped region; A3, third region; 60, via; 71, source; 72, drain; 73, conductive leads.
  • a method for fabricating an array substrate including:
  • the region where the active layer is located includes a first area A1 corresponding to the gate and a second area A2 located on both sides of the first area A1;
  • the mask pattern comprising a hollow portion, a first portion and a second portion, the hollow portion for exposing a corresponding insulating layer of a portion of the gate line, the second portion corresponding to the a portion of the second region, the first portion being a portion other than the hollow portion and the second portion on the mask pattern, the second portion having a thickness smaller than a thickness of the first portion;
  • step S5 is used to expose a portion of the gate line, thereby forming a gate in a subsequent process.
  • the line provides conductive leads for the scan signal.
  • the thin film transistor on the array substrate is a top gate type low temperature polysilicon thin film transistor
  • a separate light shielding layer needs to be formed, and if a bottom gate type thin film transistor is fabricated,
  • the active layer is ion implanted using a mask alone.
  • the gate since the gate is formed before the active layer, it can function as a light blocking. It is not necessary to make a light shielding layer, and a mask pattern is formed before the formation of the via holes, and the mask pattern can be formed using a primary mask. In the ion implantation, the mask pattern only needs to be used as a mask, and the mask board is not required to be used separately, thereby reducing the use of the mask and reducing the process cost.
  • step S3 includes:
  • the polysilicon layer is patterned to form an active layer.
  • the second region A2 includes an ion heavily doped region A21 and an ion lightly doped region A22 between the ion heavily doped region A21 and the first region A1.
  • the ion heavily doped region A21 is a region that needs to be heavily doped in the subsequent process
  • the ion lightly doped region A22 is a region that needs to be lightly doped in the subsequent process.
  • step S4 includes:
  • step S5 the portion of the insulating layer corresponding to the hollow portion may be etched away to form a via 60, as shown in FIG.
  • step S6 includes:
  • the first ion implantation is a heavy doping process, doping trivalent or pentavalent elements to increase half Conductivity of the conductor
  • the second ion implantation is a lightly doped process
  • the lightly doped drain region acts as a larger resistor in series, thereby reducing leakage current.
  • the types of ions implanted in the two doping processes may be the same, but at different concentrations.
  • the concentration of ions doped in the heavy doping process is greater than the concentration of ions doped in the light doping process.
  • the formed thin film transistor is an N-type transistor
  • a phosphorus atom or a germanium atom may be doped into the active layer
  • a boron atom or an indium atom may be doped into the active layer.
  • the process of ashing the photoresist is to pass an oxygen-containing gas and perform an oxidation reaction with the photoresist. Therefore, after ashing, not only the thickness of the photoresist layer is reduced, but also the width thereof is made. Narrowed.
  • the photoresist is a positive photoresist
  • the mask 50 may be a halftone mask or a gray mask, as shown in FIG. 5, which includes a light transmitting region (the mask in FIG. 5).
  • the light transmitting region of the mask 50 corresponds to a portion of the gate line 12
  • the semi-transmissive region of the mask 50 corresponds to the ion heavily doped region A21, the light transmitting region of the mask 50 and the portion other than the semi-transmissive region.
  • the opaque region is such that the positive photoresist corresponding to the light-transmitting region is completely soluble in the developer after being exposed to light, and the positive photoresist corresponding to the semi-transmissive region is partially dissolved in the developer after being exposed to light, and is not transparent.
  • the positive photoresist corresponding to the light region is insoluble in the developer.
  • the photoresist may also be a negative photoresist. When the photoresist is a negative photoresist, it is only necessary to interchange the positions of the opaque region and the transparent region of the mask.
  • the manufacturing method further includes a step S7 performed after the step S6, forming a pattern including the source 71, the drain 72, and the conductive lead 73.
  • the source 71 is overlapped in the heavily doped source region 31
  • the drain 72 is overlapped in the heavily doped drain region 32
  • the conductive leads 73 are connected to the gate line 12 through the via holes, thereby providing the gate line 12 Scan the signal as shown in Figure 11.
  • the gate line 12 and the gate electrode 11 are formed by the first patterning process, and the active layer 30 is formed by the second patterning process, and is formed by the third patterning process.
  • a mask pattern wherein the mask pattern is used as a mask for etching a via hole, and the mask pattern is also used as a mask for ion implantation, and the conductive lead 73, the source 71, and the conductive layer 73 are formed by a fourth patterning process. Drain 72. Therefore, in the fabrication of the thin film transistor, four masks are required, which reduces the use of the mask and reduces the process cost compared with the related art.
  • the method further includes the step of forming a passivation layer and forming a pixel electrode via hole on the passivation layer; forming a pixel electrode to pass the pixel electrode through the pixel electrode via hole. Connected to the drain; and form a common electrode.
  • the thin film transistor is a double gate thin film transistor. That is, the thin film transistor has two gate electrodes 11 including two of the first regions in the region where the active layer is located, and when performing the first ion implantation, as shown in FIG. 7, on both sides of each of the first regions The two ion heavily doped regions are heavily doped; in the second ion implantation, the two ion lightly doped regions on both sides of each first region are lightly doped, thereby forming the active layer into four A lightly doped drain region 33.
  • the thin film transistor may also be a single-gate thin film transistor, as shown in FIG. 12, at this time, after the first ion implantation, the active layer forms a heavily doped source region 31 and a heavily doped drain region 32, both of which The conductive region is formed. After the second ion implantation, the conductive region forms a polysilicon region 34 and a lightly doped drain region 33 on both sides of the polysilicon region.
  • an array substrate is provided, which can be fabricated by the above-described fabrication method.
  • the array substrate includes a thin film transistor and a gate line connected to a gate of the thin film transistor.
  • the active layer of the thin film transistor includes a polysilicon region 34 corresponding to the gate and a polysilicon region.
  • the heavily doped source region 31 and the heavily doped drain region 32 on both sides of the 34, the active layer further includes a polysilicon region 34 and a heavily doped source region 31, and a polysilicon region and a heavily doped drain
  • the lightly doped drain region 33 between the regions 32, the source 71 of the thin film transistor is electrically connected to the heavily doped source region 31, and the drain 72 of the thin film transistor is electrically connected to the heavily doped drain region 32
  • the gate 11 of the thin film transistor is located below the active layer, and the insulating layer 20 is disposed between the gate 11 and the gate line 12 and the active layer, and the array substrate further includes a conductive lead 73, and the conductive lead 73 passes through The via of the insulating layer 20 is electrically connected to the gate line 12.
  • the source 71 overlaps the heavily doped source region 31 and the drain 72 overlaps the heavily doped drain region 32.
  • the gate of the thin film transistor is located under the active layer, it can function as a light shielding, and it is not necessary to separately fabricate a light shielding layer, and the source and the drain are directly connected to the active layer, and do not need to be in the active layer as in the related art.
  • the insulating layer and the source via and the drain via are formed again on the upper side, so that the source is connected to the active layer through the source via and the drain is connected to the active layer through the drain via, thereby simplifying the thin film crystal The structure of the body tube.
  • the conductive lead 73 is made of the same material as the source 71 and the drain 72. At the time of fabrication, the conductive lead 73, the source 71, and the drain 72 can be formed simultaneously.
  • a display device including the above array substrate provided by the present disclosure is provided.
  • a mask for fabricating the above array substrate, the mask comprising a light transmitting region, an opaque region and a semi-transmissive region, wherein the transparent region is used Corresponding to a portion of the gate line, the semi-transmissive region is adapted to correspond to the heavily doped source region and the heavily doped drain region, the light transmissive region and the semi-transmissive region of the mask Part of the formation is an opaque area.
  • the mask can be used to form the mask pattern in the method for fabricating the array substrate.
  • a photoresist layer 40 is formed on a substrate on which an active layer is formed, using a mask pair.
  • the photoresist layer 40 is exposed, and the exposed photoresist is developed. After the development, a portion of the photoresist corresponding to the gate line is removed, a region to be formed into the heavily doped source region, and a heavily doped to be formed.
  • the photoresist corresponding to the region of the drain region i.e., the ion heavily doped region A21 described above
  • the photoresist at the remaining positions is completely retained.

Abstract

一种阵列基板及其制作方法、一种显示装置、掩膜板。阵列基板的制作方法包括：S1、形成包括栅极（11）和栅线（12）的图形；S2、形成绝缘层（20）；S3、形成包括有源层（30）的图形，其中，有源层（30）所在的区域包括对应于栅极（11）的第一区域和位于第一区域两侧的第二区域；S4、形成掩膜图形，掩膜图形包括镂空部、第一部和第二部，第二部的厚度小于第一部的厚度；S5、对绝缘层进行刻蚀，以形成露出栅线（12）的一部分的过孔（60）；S6、对掩膜图形对应于第二区域的部分进行灰化，以将掩膜图形对应于第二区域的部分去除，并对有源层（30）进行离子注入。

Description

阵列基板及其制作方法、显示装置、掩膜板
相关申请的交叉引用
本申请主张在2015年10月10日在中国提交的中国专利申请号No.201510653779.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体涉及一种阵列基板及其制作方法、一种包括该阵列基板的显示装置、一种掩膜板。
背景技术
低温多晶硅(low temperature poly-silicon，LTPS)薄膜晶体管液晶显示器有别于传统的非晶硅薄膜晶体管液晶显示器，其电子迁移率较高，可有效减小薄膜晶体管器件的面积，从而可以提高开口率，并且在增进显示器亮度的同时还可以降低整体的功耗。另外，由于其具有较高的电子迁移率，因此可以将部分驱动电路集成在玻璃基板上，减少了驱动电路成本，还可以大幅提升液晶显示面板的可靠性，从而使得面板的制造成本大幅降低。因此，低温多晶硅薄膜晶体管液晶显示器逐步成为研究的热点。
在制作低温多晶硅薄膜晶体管的过程中，需要通过构图工艺分别形成有源层、栅极、过孔、源漏极，并对有源层进行离子掺杂。其中，过孔包括用于将源漏极与有源层相连的第一过孔、用于将栅线和为栅线提供扫描信号的信号线相连的第二过孔。对于顶栅型薄膜晶体管，在进行离子掺杂的步骤中，可以利用栅极作为掩膜进行离子掺杂，但是为了防止光照对有源层的影响，需要另外通过一次构图工艺形成遮光层。因此，顶栅型低温多晶硅薄膜晶体管至少需要五次构图工艺，导致使用的掩膜板数量较多。而对于底栅型薄膜晶体管，可以省去遮光层，但是在进行离子掺杂时，需要再次使用掩膜板。
可以看出，现有技术中低温多晶硅薄膜晶体管的制作工艺较复杂，使用掩膜板数量和次数较多，制作成本较高。
发明内容
本公开的目的在于提供一种阵列基板及其制作方法、显示装置、掩膜板，以减少制作过程中掩膜板的使用。
一方面，本公开提供了一种阵列基板的制作方法，包括：
S1、形成包括栅极和栅线的图形；
S2、形成绝缘层；
S3、形成包括有源层的图形，其中，所述有源层所在的区域包括对应于栅极的第一区域和位于第一区域两侧的第二区域；
S4、形成掩膜图形，所述掩膜图形包括镂空部、第一部和第二部，所述镂空部用于将栅线的一部分对应的绝缘层露出，所述第二部对应于所述第二区域中的一部分区域，所述第一部为所述掩膜图形上镂空部和第二部以外的部分，所述第二部的厚度小于所述第一部的厚度；
S5、对所述绝缘层进行刻蚀，以形成露出所述栅线的一部分的过孔；
S6、对所述掩膜图形对应于所述第二区域的部分进行灰化，以将所述掩膜图形对应于第二区域的部分去除，并对所述有源层进行离子注入。
可选地，所述第二区域包括离子重掺杂区域和位于离子重掺杂区域与第一区域之间的离子轻掺杂区域，步骤S4包括：
S4a、形成光刻胶层；
S4b、利用掩膜板对光刻胶层进行曝光并显影，并使得显影后，栅线的一部分对应的光刻胶完全溶解，对应于离子重掺杂区域的光刻胶溶解掉一部分，形成所述第二部，其余部分的光刻胶完全保留，形成所述第一部。
可选地，步骤S6包括：
S6a、对显影后的所述光刻胶层进行第一次灰化，以将所述第二部去除；
S6b、对所述有源层进行第一次离子注入，形成重掺杂源极区和重掺杂漏极区；
S6c、对第一次灰化后的光刻胶层进行第二次灰化，以将对应于所述离子轻掺杂区域的光刻胶去除；
S6d、对所述有源层进行第二次离子注入，形成轻掺杂漏区。
可选地，所述光刻胶为正性光刻胶，所述掩膜板包括透光区、不透光区和半透光区，所述掩膜板的透光区对应于所述栅线的一部分，所述掩膜板的半透光区对应于所述离子重掺杂区域，所述掩膜板的透光区和半透光区以外的部分为不透光区。
可选地，在步骤S6之后，所述制作方法还包括：
S7、形成包括源极、漏极和导电引线的图形，所述源极搭接在所述重掺杂源极区，所述漏极搭接在所述重掺杂漏极区，所述导电引线通过所述过孔与所述栅线相连。
可选地，在步骤S7之后，所述制作方法还包括：
形成钝化层，并在钝化层上形成像素电极过孔；
形成像素电极，以使像素电极通过所述像素电极过孔与漏极相连；以及
形成公共电极。
可选地，步骤S3包括：
形成非晶硅膜层；
对所述非晶硅膜层进行退火工艺形成多晶硅层；
对所述多晶硅层进行构图工艺形成所述有源层。
相应地，本公开还提供一种阵列基板，包括薄膜晶体管和与该薄膜晶体管的栅极相连的栅线。所述薄膜晶体管的有源层包括对应于栅极的多晶硅区以及分别位于多晶硅区两侧的重掺杂源极区和重掺杂漏极区，所述有源层还包括位于多晶硅区与重掺杂源极区之间以及多晶硅区与重掺杂源极区之间的轻掺杂漏区。所述薄膜晶体管的源极与重掺杂源极区电连接，所述薄膜晶体管的漏极与重掺杂漏极区电连接。所述薄膜晶体管的栅极位于有源层的下方，所述栅极和栅线与有源层之间设置有绝缘层。所述阵列基板还包括导电引线，该导电引线通过贯穿所述绝缘层的过孔与所述栅线电连接。
可选地，所述源极搭接在所述重掺杂源极区，所述漏极搭接在所述重掺杂漏极区。
可选地，所述导电引线和所述源极、漏极的材料相同。
相应地，本公开还提供一种显示装置，包括本公开提供的上述阵列基板。
相应地，本公开还提供一种掩膜板，用于进行阵列基板的制作，所述阵列基板为本公开提供的上述阵列基板，所述掩膜板包括透光区、不透光区和半透光区，所述透光区用于与栅线的一部分对应，所述半透光区用于与对应于重掺杂源极区和重掺杂漏极区对应，所述掩膜板的透光区和半透光区以外的部分形成为不透光区。
在本公开中，由于栅极在有源层之前制作，可以起到遮光的作用。因此，无需制作遮光层，并且在形成过孔之前形成了掩膜图形，该掩膜图形的形成可以使用一次掩膜板，在进行离子注入时只需要掩膜图形作为掩膜即可，不需要再单独使用掩膜板，从而减少了掩膜板的使用，降低了工艺成本。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是本公开的实施例中形成栅极和栅线后的示意图；
图2是形成绝缘层后的示意图；
图3是形成有源层后的示意图；
图4是形成光刻胶层的示意图；
图5是光刻胶显影后的示意图；
图6是形成过孔的示意图；
图7是对光刻胶层第一次灰化后的示意图；
图8是进行第一次离子注入的示意图；
图9是对光刻胶层第二次灰化后的示意图；
图10是进行第二次离子注入的示意图；
图11是形成导线引线、源极、漏极的示意图；
图12是本公开的另一实施例中阵列基板的部分结构示意图。
其中，附图标记为：11、栅极；12、栅线；20、绝缘层；30、有源层；31、重掺杂源极区；32、重掺杂漏极区；33、轻掺杂漏区；34、多晶硅区；40、光刻胶层；50、掩膜板；A1、第一区域；A2、第二区域；A21、离子重掺杂区域；A22、离子轻掺杂区域；A3、第三区域；60、过孔；71、源极；72、漏极；73、导电引线。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描 述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
作为本发明的一方面，提供一种阵列基板的制作方法，包括：
S1、形成包括栅极11和栅线12的图形，如图1所示；
S2、形成绝缘层20，如图2所示；
S3、形成包括有源层30的图形，如图3所示，所述有源层所在的区域包括对应于栅极的第一区域A1和位于第一区域A1两侧的第二区域A2；
S4、形成掩膜图形，所述掩膜图形包括镂空部、第一部和第二部，所述镂空部用于将栅线的一部分对应的绝缘层露出，所述第二部对应于所述第二区域中的一部分区域，所述第一部为所述掩膜图形上镂空部和第二部以外的部分，所述第二部的厚度小于第一部的厚度；
S5、对所述绝缘层进行刻蚀，以形成露出所述栅线的一部分的过孔；
S6、对所述掩膜图形对应于所述第二区域的部分进行灰化，并以将所述掩膜图形对应于第二区域的部分去除，并对所述有源层进行离子注入。
应当理解的是，在包括所述阵列基板的显示面板进行显示时，需要向栅线提供扫描信号，步骤S5中形成的过孔用于将栅线的一部分露出，从而在后续工艺中形成为栅线提供扫描信号的导电引线。
通常在制作阵列基板的工艺中，当阵列基板上的薄膜晶体管为顶栅型低温多晶硅薄膜晶体管时，为了防止光照对有源层的影响，需要单独制作遮光层，如果制作底栅型薄膜晶体管，需要单独使用掩膜板对有源层进行离子注入。而本公开中，由于栅极在有源层之前制作，可以起到遮光的作用，因此， 无需制作遮光层，并且在形成过孔之前形成了掩膜图形，该掩膜图形的形成可以使用一次掩膜板。而在进行离子注入时只需要将该掩膜图形作为掩膜即可，不需要再单独使用掩膜板，从而减少了掩膜板的使用，降低了工艺成本。
可选地，步骤S3包括：
形成非晶硅膜层；
对所述非晶硅膜层进行退火工艺形成多晶硅层；
对所述多晶硅层进行构图工艺形成有源层。
具体地，如图3所示，第二区域A2包括离子重掺杂区域A21和位于离子重掺杂区域A21与第一区域A1之间的离子轻掺杂区域A22。离子重掺杂区域A21即为后续工艺中需要进行离子重掺杂的区域，离子轻掺杂区域A22即为后续工艺中需要进行离子轻掺杂的区域。可选地，步骤S4包括：
S4a、形成光刻胶层40，如图4所示；
S4b、利用掩膜板对光刻胶层40进行曝光并显影，并使得显影后，栅线的一部分对应的光刻胶(即，图5中的第三区域A3的光刻胶)完全溶解，形成所述镂空部，对应于离子重掺杂区域A21的光刻胶溶解掉一部分，形成所述第二部，其余部分的光刻胶完全保留，形成所述第一部，如图5所示。
步骤S5中对绝缘层20刻蚀时，就可以将绝缘层对应于所述镂空部的部分刻蚀掉，形成过孔60，如图6所示。
可选地，步骤S6包括：
S6a、对显影后的光刻胶层进行第一次灰化，以将所述第二部(即光刻胶层的位于离子重掺杂区域A21中的部分)去除，如图7所示；
S6b、以第一次灰化后的光刻胶层为掩膜，对所述有源层进行第一次离子注入，形成重掺杂源极区31和重掺杂漏极区32，如图8所示；
S6c、对第一次灰化后的光刻胶层进行第二次灰化，以将对应于离子轻掺杂区域A22的光刻胶去除，如图9所示；
S6d、以第二次灰化后的光刻胶层作为掩膜，对有源层进行第二次离子注入，形成轻掺杂漏区33，如图10所示。重掺杂源极区31、重掺杂漏极区32和轻掺杂漏区33形成后，将剩余的光刻胶剥离即可。
这里，第一次离子注入为重掺杂工艺，掺杂三价或五价元素，以提高半 导体的导电性，第二次离子注入为轻掺杂工艺，轻掺杂漏区的作用等同于串联一个较大的电阻，从而减小漏电流。两次掺杂工艺所注入的离子的种类可以相同，但浓度不同。重掺杂工艺中所掺杂的离子浓度大于轻掺杂工艺中所掺杂的离子浓度。当形成的薄膜晶体管为N型晶体管时，可以向有源层掺入磷原子或锑原子；当形成的薄膜晶体管为P型晶体管时，可以向有源层掺入硼原子或铟原子。
对光刻胶进行灰化(Ashing)的过程为，通入含氧气体，与光刻胶进行氧化反应，因此，灰化后，不仅使得光刻胶层的厚度减小，还会使得其宽度变窄。
具体地，所述光刻胶为正性光刻胶，掩膜板50可以为半色调掩膜板或灰色调掩膜板，如图5所示，其包括透光区(图5中掩膜板50上的开口部分)、不透光区(图5中掩膜板50上黑色部分)和半透光区(图5中掩膜板50上画剖面线的部分)。掩膜板50的透光区对应于栅线12的一部分，掩膜板50的半透光区对应于离子重掺杂区域A21，掩膜板50的透光区和半透光区以外的部分为不透光区，从而使得透光区对应的正性光刻胶受到光照后可以完全溶于显影液，半透光区对应的正性光刻胶受到光照后部分溶于显影液，不透光区对应的正性光刻胶不溶于显影液。当然，所述光刻胶也可以为负性光刻胶。当光刻胶为负性光刻胶时，只需要将掩膜板的不透光区和透光区的位置互换即可。
可选地，所述制作方法还包括在步骤S6之后进行的步骤S7、形成包括源极71、漏极72和导电引线73的图形。源极71搭接在重掺杂源极区31，漏极72搭接在所述重掺杂漏极区32，导电引线73通过所述过孔与栅线12相连，从而为栅线12提供扫描信号，如图11所示。
可以看出，利用本公开的制作工艺在形成薄膜晶体管时，通过第一次构图工艺形成栅线12和栅极11，通过第二次构图工艺形成有源层30，通过第三次构图工艺形成掩膜图形，以所述掩膜图形作为刻蚀过孔时的掩膜，同时所述掩膜图形也作为离子注入时的掩膜，通过第四次构图工艺形成导电引线73、源极71和漏极72。因此，在薄膜晶体管制作时，需要四张掩膜板即可，和相关技术中相比，减少了掩膜板的使用，减低了工艺成本。
当然，在本公开的制作方法中，还包括步骤S7之后进行的：形成钝化层，并在钝化层上形成像素电极过孔；形成像素电极，以使像素电极通过所述像素电极过孔与漏极相连；以及形成公共电极。
如图1至图11中，薄膜晶体管为双栅型薄膜晶体管。即，薄膜晶体管具有两个栅极11，有源层所在区域中包括两个所述第一区域，在进行第一次离子注入时，如图7所示，在每个第一区域两侧的两个离子重掺杂区域进行重掺杂；在进行第二次离子注入时，在每个第一区域两侧的两个离子轻掺杂区域进行轻掺杂，从而使有源层形成了四个轻掺杂漏区33。
薄膜晶体管也可以为单栅型薄膜晶体管，如图12所示，这时，第一次离子注入后，有源层形成重掺杂源极区31和重掺杂漏极区32，二者之间为导电区，第二次离子注入后，所述导电区形成多晶硅区34和位于多晶硅区两侧的轻掺杂漏区33。
作为本发明的另一方面，提供一种阵列基板，所述阵列基板可以采用上述制作方法制作而成。
具体地，所述阵列基板包括薄膜晶体管和与该薄膜晶体管的栅极相连的栅线，如图11所示，所述薄膜晶体管的有源层包括对应于栅极的多晶硅区34以及位于多晶硅区34两侧的重掺杂源极区31和重掺杂漏极区32，所述有源层还包括位于多晶硅区34与重掺杂源极区31之间以及多晶硅区与重掺杂漏极区32之间的轻掺杂漏区33，所述薄膜晶体管的源极71与重掺杂源极区31电连接，所述薄膜晶体管的漏极72与重掺杂漏极区32电连接，所述薄膜晶体管的栅极11位于有源层的下方，栅极11和栅线12与有源层之间设置有绝缘层20，所述阵列基板还包括导电引线73，该导电引线73通过贯穿绝缘层20的过孔与栅线12电连接。
可选地，源极71搭接在所述重掺杂源极区31，漏极72搭接在重掺杂漏极区32。
由于薄膜晶体管的栅极位于有源层下方，可以起到遮光的作用，无需单独制作遮光层，同时源极和漏极直接与有源层相连，不需要像相关技术中那样，在有源层上方再次形成绝缘层以及源极过孔、漏极过孔，使源极通过源极过孔与有源层相连、漏极通过漏极过孔与有源层相连，从而简化了薄膜晶 体管的结构。
具体地，导电引线73和源极71、漏极72的材料相同，在制作时，可以同步形成导电引线73和源极71、漏极72。
作为本公开的再一方面，提供一种显示装置，包括本公开提供的上述阵列基板。
作为本公开的又一方面，提供一种掩膜板，用于进行上述阵列基板的制作，所述掩膜板包括透光区、不透光区和半透光区，所述透光区用于与栅线的一部分对应，所述半透光区用于与对应于重掺杂源极区和重掺杂漏极区对应，所述掩膜板的透光区和半透光区以外的部分形成为不透光区。
所述掩膜板可以用于在上述阵列基板的制作方法中形成所述掩膜图形，如图5所示，在形成有源层的衬底上形成光刻胶层40，利用掩膜板对光刻胶层40进行曝光，并对曝光后的光刻胶进行显影，显影后，栅线的一部分对应的光刻胶被去除，待形成重掺杂源极区的区域和待形成重掺杂漏极区的区域(即上述离子重掺杂区A21)对应的光刻胶被去除一部分，其余位置的光刻胶全部保留。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (12)

  1. 一种阵列基板的制作方法，包括：
    S1、形成包括栅极和栅线的图形；
    S2、形成绝缘层；
    S3、形成包括有源层的图形，其中，所述有源层所在的区域包括对应于栅极的第一区域和位于第一区域两侧的第二区域；
    S4、形成掩膜图形，所述掩膜图形包括镂空部、第一部和第二部，所述镂空部用于将栅线的一部分对应的绝缘层露出，所述第二部对应于所述第二区域中的一部分区域，所述第一部为所述掩膜图形上镂空部和第二部以外的部分，所述第二部的厚度小于所述第一部的厚度；
    S5、对所述绝缘层进行刻蚀，以形成露出所述栅线的一部分的过孔；
    S6、对所述掩膜图形对应于所述第二区域的部分进行灰化，以将所述掩膜图形对应于第二区域的部分去除，并对所述有源层进行离子注入。
  2. 根据权利要求1所述的制作方法，其中，所述第二区域包括离子重掺杂区域和位于离子重掺杂区域与第一区域之间的离子轻掺杂区域，步骤S4包括：
    S4a、形成光刻胶层；
    S4b、利用掩膜板对光刻胶层进行曝光并显影，并使得显影后，栅线的一部分对应的光刻胶完全溶解，对应于离子重掺杂区域的光刻胶溶解掉一部分，形成所述第二部，其余部分的光刻胶完全保留，形成所述第一部。
  3. 根据权利要求2所述的制作方法，其中，步骤S6包括：
    S6a、对显影后的所述光刻胶层进行第一次灰化，以将所述第二部去除；
    S6b、对所述有源层进行第一次离子注入，形成重掺杂源极区和重掺杂漏极区；
    S6c、对第一次灰化后的光刻胶层进行第二次灰化，以将对应于所述离子轻掺杂区域的光刻胶去除；
    S6d、对所述有源层进行第二次离子注入，形成轻掺杂漏区。
  4. 根据权利要求2所述的制作方法，其中，所述光刻胶为正性光刻胶， 所述掩膜板包括透光区、不透光区和半透光区，所述掩膜板的透光区对应于所述栅线的一部分，所述掩膜板的半透光区对应于所述离子重掺杂区域，所述掩膜板的透光区和半透光区以外的部分为不透光区。
  5. 根据权利要求3或4所述的制作方法，其中，在步骤S6之后，所述制作方法还包括：
    S7、形成包括源极、漏极和导电引线的图形，所述源极搭接在所述重掺杂源极区，所述漏极搭接在所述重掺杂漏极区，所述导电引线通过所述过孔与所述栅线相连。
  6. 根据权利要求5所述的制作方法，其中，在步骤S7之后，所述制作方法还包括：
    形成钝化层，并在钝化层上形成像素电极过孔；
    形成像素电极，以使像素电极通过所述像素电极过孔与漏极相连；以及
    形成公共电极。
  7. 根据权利要求1至4中任意一项所述的制作方法，其中，步骤S3包括：
    形成非晶硅膜层；
    对所述非晶硅膜层进行退火工艺形成多晶硅层；
    对所述多晶硅层进行构图工艺形成所述有源层。
  8. 一种阵列基板，包括：
    薄膜晶体管，以及
    与该薄膜晶体管的栅极相连的栅线，
    其中，所述薄膜晶体管的有源层包括对应于栅极的多晶硅区以及分别位于多晶硅区两侧的重掺杂源极区和重掺杂漏极区，所述有源层还包括位于多晶硅区与重掺杂源极区之间以及多晶硅区与重掺杂源极区之间的轻掺杂漏区，
    所述薄膜晶体管的源极与重掺杂源极区电连接，所述薄膜晶体管的漏极与重掺杂漏极区电连接，
    所述薄膜晶体管的栅极位于有源层的下方，所述栅极和栅线与有源层之间设置有绝缘层，
    所述阵列基板还包括导电引线，该导电引线通过贯穿所述绝缘层的过孔 与所述栅线电连接。
  9. 根据权利要求8所述的阵列基板，其中，所述源极搭接在所述重掺杂源极区，所述漏极搭接在所述重掺杂漏极区。
  10. 根据权利要求9所述的阵列基板，其中，所述导电引线和所述源极、漏极的材料相同。
  11. 一种显示装置，包括权利要求8至10中任意一项所述的阵列基板。
  12. 一种掩膜板，用于制作根据权利要求8至10中任意一项所述的阵列基板，所述掩膜板包括透光区、不透光区和半透光区，
    其中，所述透光区用于与栅线的一部分对应，
    所述半透光区用于与对应于重掺杂源极区和重掺杂漏极区对应，并且
    所述掩膜板的透光区和半透光区以外的部分形成为不透光区。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105355631A (zh) * 2015-10-10 2016-02-24 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置、掩膜板
CN108257975B (zh) * 2018-01-02 2022-10-04 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置、薄膜晶体管的制备方法
CN111446264B (zh) * 2020-04-15 2023-03-24 Tcl华星光电技术有限公司 阵列基板及其制造方法
CN113820894B (zh) * 2021-08-30 2023-04-25 厦门天马微电子有限公司 阵列基板、掩膜板、有源结构制备方法及显示面板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020053576A (ko) * 2000-12-27 2002-07-05 주식회사 현대 디스플레이 테크놀로지 반사형 표시장치의 제조방법
US20070287235A1 (en) * 2006-06-13 2007-12-13 Au Optronics Corporation Method of Manufacturing an Array Substrate of a Transflective Liquid Crystal Display
US20120069257A1 (en) * 2010-09-20 2012-03-22 Kum Mi Oh Liquid Crystal Display Device with a Built-in Touch Screen and Method for Manufacturing the Same
CN102522410A (zh) * 2011-12-22 2012-06-27 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102881688A (zh) * 2012-09-19 2013-01-16 北京京东方光电科技有限公司 一种阵列基板、显示面板及阵列基板的制造方法
CN104300002A (zh) * 2013-07-15 2015-01-21 信利半导体有限公司 一种薄膜晶体管及其制造方法、光刻工艺
CN104517896A (zh) * 2014-12-12 2015-04-15 深圳市华星光电技术有限公司 一种阵列基板的掺杂方法及制造设备
CN105355631A (zh) * 2015-10-10 2016-02-24 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置、掩膜板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295109B1 (en) * 1997-12-26 2001-09-25 Sharp Kabushiki Kaisha LCD with plurality of pixels having reflective and transmissive regions
JP3612525B2 (ja) 2002-06-04 2005-01-19 Ｎｅｃ液晶テクノロジー株式会社 薄膜半導体装置の製造方法及びそのレジストパターン形成方法
JP4062171B2 (ja) * 2003-05-28 2008-03-19 ソニー株式会社 積層構造の製造方法
KR101086478B1 (ko) * 2004-05-27 2011-11-25 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 및 그 제조 방법
KR101139522B1 (ko) * 2004-12-04 2012-05-07 엘지디스플레이 주식회사 반투과형 박막 트랜지스터 기판 및 그 제조 방법
KR100724485B1 (ko) * 2005-04-19 2007-06-04 엘지.필립스 엘시디 주식회사 액정표시장치의 박막트랜지스터 제조방법
TWI354377B (en) * 2007-05-30 2011-12-11 Au Optronics Corp Pixel structure of lcd and fabrication method ther
KR101074788B1 (ko) * 2009-01-30 2011-10-20 삼성모바일디스플레이주식회사 평판 표시 장치 및 이의 제조 방법
KR101764902B1 (ko) * 2010-12-06 2017-08-14 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020053576A (ko) * 2000-12-27 2002-07-05 주식회사 현대 디스플레이 테크놀로지 반사형 표시장치의 제조방법
US20070287235A1 (en) * 2006-06-13 2007-12-13 Au Optronics Corporation Method of Manufacturing an Array Substrate of a Transflective Liquid Crystal Display
US20120069257A1 (en) * 2010-09-20 2012-03-22 Kum Mi Oh Liquid Crystal Display Device with a Built-in Touch Screen and Method for Manufacturing the Same
CN102522410A (zh) * 2011-12-22 2012-06-27 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102881688A (zh) * 2012-09-19 2013-01-16 北京京东方光电科技有限公司 一种阵列基板、显示面板及阵列基板的制造方法
CN104300002A (zh) * 2013-07-15 2015-01-21 信利半导体有限公司 一种薄膜晶体管及其制造方法、光刻工艺
CN104517896A (zh) * 2014-12-12 2015-04-15 深圳市华星光电技术有限公司 一种阵列基板的掺杂方法及制造设备
CN105355631A (zh) * 2015-10-10 2016-02-24 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置、掩膜板

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