WO2015027590A1 - 阵列基板及其制备方法和显示装置 - Google Patents

阵列基板及其制备方法和显示装置 Download PDF

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Publication number
WO2015027590A1
WO2015027590A1 PCT/CN2013/088046 CN2013088046W WO2015027590A1 WO 2015027590 A1 WO2015027590 A1 WO 2015027590A1 CN 2013088046 W CN2013088046 W CN 2013088046W WO 2015027590 A1 WO2015027590 A1 WO 2015027590A1
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Prior art keywords
layer
electrode
via hole
common electrode
array substrate
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PCT/CN2013/088046
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English (en)
French (fr)
Inventor
孙建
李成
安星俊
柳奉烈
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020147018128A priority Critical patent/KR101621635B1/ko
Priority to EP13863698.0A priority patent/EP2881785B1/en
Priority to JP2016537081A priority patent/JP6294488B2/ja
Priority to US14/369,320 priority patent/US20150311232A1/en
Publication of WO2015027590A1 publication Critical patent/WO2015027590A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate, a method for fabricating the same, and a display device. Background technique
  • the low temperature polysilicon thin film transistor array substrate of the prior art includes: a substrate substrate 101, a buffer layer 102, an active region 103, a gate electrode 106, a source electrode 105, a drain electrode 104, a data line 107, The transparent common electrode 108, the pixel electrode 109, the gate insulating layer 111, the intermediate dielectric layer 112, the flat layer 113, and the deuterated layer 114.
  • a common electrode line 201 is disposed in the array substrate.
  • the common electrode line 201 is disposed in the same layer as the gate electrode 106 and forms a storage capacitor together with the pixel electrode 109 located above it.
  • the fabrication process of the low temperature polysilicon thin film transistor array substrate shown in FIG. 2 includes:
  • a buffer layer 102 is formed on the base substrate 101.
  • the active region 103 is formed by a patterning process.
  • a silicon oxide or silicon nitride layer is deposited to form a gate insulating layer 111.
  • the gate electrode 106 and the common electrode line 201 are formed by a patterning process.
  • a high concentration of n-type impurity ions is doped to both sides of the active layer 103 by ion implantation, and a source electrode 105 and a drain electrode 104 are formed on opposite sides of the active layer 103, respectively.
  • a silicon oxide or silicon nitride layer is deposited to form an intermediate dielectric layer 112; and through the patterning process, through the gate insulating layer 111 and the middle Via VI of dielectric layer 112.
  • a data line 107 is formed on the base substrate fabricated by the intermediate dielectric layer 112, and the source electrode 105 is electrically connected to the data line 107 through the via VI.
  • a flat layer 113 is formed, and a via hole V2 penetrating the insulating layer 113 is formed by a patterning process.
  • a transparent conductive film is deposited on the flat layer 113 by magnetron sputtering, and then a transparent common electrode 108 is formed by a patterning process.
  • a deuterated layer 114 is formed, and a via hole V3 penetrating the deuterated layer 114 is formed by a patterning process.
  • a layer of indium tin oxide ITO transparent conductive film is deposited on the insulating layer 113 by magnetron sputtering, and then a pixel is formed by a patterning process.
  • the electrode 109 is such that the pixel electrode 109 is electrically connected to the drain electrode 104 through the via VI, the via V2, and the via V3.
  • the common electrode line 201 and the gate electrode 106 are formed by one exposure process, at least in the manufacturing process.
  • the patterning process is required by eight exposure etchings, and the manufacturing process of the array substrate still has problems such as complicated manufacturing process, numerous manufacturing processes, high cost, and long time. Summary of the invention
  • the embodiment of the invention provides an array substrate, a preparation method thereof and a display panel, which solve the problems of complicated process, high cost and long time in the prior art, and at the same time achieve the purpose of increasing the storage capacitor.
  • the array substrate includes: a substrate substrate and data lines and scan lines disposed on the base substrate, wherein the data lines and the scan lines enclose a plurality of pixel regions, wherein the pixel regions Provided with a thin film transistor including a gate electrode, a source electrode, a drain electrode, and an active layer, the thin film transistor being disposed above the active layer, the source electrode and the The drain electrodes are respectively disposed on opposite sides of the active layer, wherein the data lines and the common electrode lines are disposed on the base substrate in the same layer, and are located under the active layer, The data line and the common electrode line are disposed apart from each other, and the common electrode is provided with a connection region, and the connection region is at least partially electrically connected to the first via of the common electrode line in the orthogonal projection direction.
  • the common electrode line and the pixel electrode located above thereof form a storage capacitor to achieve the purpose of increasing the storage capacitor; and, since the common electrode line is disposed in the same layer as the data line, the exposure is performed once.
  • the process can form the common electrode line and the data line, which reduces the manufacturing process, reduces the manufacturing process, and achieves the purpose of saving production cost and shortening the production time.
  • the data line and the common electrode line are made of the same conductive material, so that the data line and the common electrode line can be fabricated by one process, and the manufacturing cost can be saved.
  • the active layer is made of a low temperature polysilicon material, and the source electrode and the drain electrode are formed on opposite sides of the active layer by ion implantation to form a source electrode and a drain electrode.
  • a conductive channel, the common electrode line being formed under the drain electrode.
  • the array substrate further includes a buffer layer disposed under the active layer and above the base substrate, and the data line and the common electrode line are buffered Layer covering; the buffer layer is used to block the base in the subsequent process
  • the impurities contained in the board diffuse into the active layer of the thin film transistor, preventing the characteristics such as the threshold voltage and the leakage current of the thin film transistor, and improving the quality of the thin film transistor.
  • the array substrate further includes a gate insulating layer disposed above the active layer and below the gate electrode for isolating the active layer from the gate electrode.
  • the array substrate further includes an intermediate dielectric layer disposed over the gate electrode for isolating the gate electrode from other electrodes on the intermediate dielectric layer.
  • the buffer layer, the gate insulating layer and the intermediate dielectric layer are provided with a second via hole at a position corresponding to the data line, and the gate insulating layer and the intermediate dielectric layer are correspondingly
  • a third via is formed at a position of the source electrode, and the data line and the source electrode are electrically connected through the second via and the third via.
  • the array substrate further includes a pixel electrode disposed above the intermediate dielectric layer, and a deuterated layer disposed between the pixel electrode and the common electrode; the pixel electrode and the common electrode are orthographically projected At least partially overlapping in direction;
  • the common electrode is located above the deuterated layer, and the pixel electrode is located below the deuterated layer, and the gate insulating layer and the intermediate dielectric layer are provided with a fourth via hole at a position corresponding to the drain electrode.
  • the pixel electrode and the drain electrode are electrically connected through the fourth via hole, the common electrode is in a slit shape, and the pixel electrode is in a plate shape or a slit shape, and a connection between the connection region and the common electrode line a via hole penetrating the buffer layer, the gate insulating layer, the intermediate dielectric layer, and the deuterated layer; or, the common electrode is located under the deuterated layer, and the pixel electrode is located above the deuterated layer, the gate insulating layer
  • the intermediate dielectric layer is provided with a fourth via hole at a position corresponding to the drain electrode, and the deuterated layer is provided with a fifth via hole at a position corresponding to the drain electrode, and the pixel electrode and the The drain electrode is electrically connected through
  • the array substrate further includes a light shielding metal layer, the light shielding metal layer is disposed on the base substrate in the same layer as the data line and the common electrode line, and the light shielding metal layer is disposed on the active layer Lower, and at least partially overlapping the active layer in a front projection direction;
  • the light shielding metal layer is disposed between the source electrode and a region corresponding to the drain electrode, and at least partially overlaps the gate electrode in a front projection direction for irradiating the drain electrode and the source Part of the light in the area between the electrodes is blocked, thereby reducing the leakage current of the thin film transistor.
  • a lightly doped drain electrode is further disposed in the active layer, and the lightly doped drain electrode is disposed between the source electrode and the drain electrode, and is distributed in two regions corresponding to the gate electrode.
  • the lightly doped drain electrode can simultaneously reduce the leakage current of the thin film transistor.
  • the embodiment of the invention provides a display panel, and the display panel comprises the above array substrate.
  • Embodiments of the present invention provide a method of fabricating an array substrate, the method including the steps of forming a data line, a scan line, a common electrode, and a common electrode line, and forming a thin film transistor, including forming a gate electrode, a step of forming a source electrode, a drain electrode, and an active layer, wherein the common electrode, the common electrode line, and the thin film transistor are formed in a plurality of pixel regions surrounded by the scan line and the data line, wherein the data a line and the common electrode line are formed on the base substrate in the same layer, and under the active layer, a connection region is formed on the same layer on the common electrode, and the connection region is at least partially and common in a front projection direction
  • the electrode lines overlap, and the common electrode and the common electrode line are electrically connected through a first via formed between the connection region and the common electrode line.
  • the preparation method specifically includes:
  • the buffer layer covers the common electrode line and the data line, and the pattern including the active layer is formed on the buffer layer;
  • the preparation method further includes the following steps of forming a common electrode, a connection region, and a pixel electrode:
  • an intermediate dielectric layer and a pattern including a first via, a second via, a third via, and a fourth via wherein: the first via is formed in the connection region and the common electrode line
  • the second via hole is formed at a position corresponding to the data line and penetrates the buffer layer, the gate insulating layer, and the intermediate dielectric layer, through the buffer layer, the gate insulating layer, and the intermediate dielectric layer.
  • the third via hole is formed at a position corresponding to the source electrode and penetrates the gate insulating layer and the intermediate dielectric layer
  • the fourth via hole is formed at a position corresponding to the drain electrode and penetrates the a gate insulating layer and an intermediate dielectric layer;
  • the above method of forming a common electrode, a connection region, and a pixel electrode is applied to the array substrate in which the common electrode is located under the pixel electrode. And for the array substrate in which the common electrode is located above the pixel electrode, the preparation method further comprises the following steps of forming a common electrode, a connection region and a pixel electrode:
  • the second via is formed at a position corresponding to the data line and penetrates the buffer layer, The gate insulating layer and the intermediate dielectric layer
  • the third via hole is formed at a position corresponding to the source electrode and penetrates the gate insulating layer and the intermediate dielectric layer
  • the fourth via hole Forming at a position corresponding to the drain electrode and penetrating the gate insulating layer and the intermediate dielectric layer;
  • Forming a pattern including the pixel electrode wherein the second via hole, the third via hole, and the fourth via hole are simultaneously filled with a conductive material for forming the pixel electrode, and the data line and the source electrode pass through
  • the second via hole and the third via hole are electrically connected, and the pixel electrode and the drain electrode are electrically connected through the fourth via hole;
  • the deuterated layer and a pattern including a common electrode Forming the deuterated layer and a pattern including a common electrode, the deuterated layer completely covering the pixel electrode, the pattern including the common electrode and the connection region being formed over the deuterated layer, and forming a first via between the connection region and the common electrode line, the through hole passing through the buffer layer, the gate insulating layer, the intermediate dielectric layer and the deuterated layer.
  • the step of forming the source electrode and the drain electrode further includes: forming a lightly doped drain electrode in the active layer by ion implantation, the lightly doped drain electrode being formed at the source electrode and The drain electrodes are distributed on both sides of a corresponding region of the gate electrode; the lightly doped drain electrode simultaneously serves to reduce leakage current of the thin film transistor.
  • the step of forming a pattern including the data line and the common electrode line further includes: forming a light shielding metal layer on the base substrate, wherein the light shielding metal layer is formed in the same layer as the data line and the common electrode line, The light shielding metal layer is formed under the active layer and at least partially overlaps the active layer in a right projection direction.
  • the light shielding metal layer formed in the step of forming a pattern including the data line and the common electrode line is at least one piece, and the gate electrode formed in a pattern in which a gate insulating layer and the gate electrode are formed is formed At least one of the light shielding metal layers is formed corresponding to the position of the gate electrode for reducing leakage current of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view of an array substrate in the prior art
  • FIG. 2 is a cross-sectional structural view of another array substrate in the prior art
  • FIG. 3 to FIG. 10 are preparations of the array substrate shown in FIG. Method flow chart
  • FIG. 11 is a schematic plan view showing a planar structure of an array substrate according to an embodiment of the present invention
  • Figure 12 is a cross-sectional structural view of the array substrate taken along the line A-A1 of Figure 11;
  • FIG. 13 is a cross-sectional structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 14 to FIG. 18 are flowcharts showing a method for preparing an array substrate according to Embodiment 1 of the present invention.
  • FIG. 19 is a schematic cross-sectional structural view of an array substrate provided in Embodiment 2 of the intermediate dielectric layer preparation;
  • Fig. 20 is a cross-sectional structural view showing the array substrate provided in the second embodiment of the pixel electrode preparation. detailed description
  • the embodiment of the invention provides an array substrate, a preparation method thereof and a display panel, which solve the problems of complicated process, high cost and long time in the prior art, and at the same time achieve the purpose of increasing the storage capacitor.
  • the present invention provides an array substrate including a substrate substrate and data lines and scan lines disposed on the substrate, the data lines and the scan lines enclosing a plurality of pixel regions, the pixel regions Provided with a thin film transistor including a gate electrode, a source electrode, a drain electrode, and an active layer, the thin film transistor being disposed above the active layer, the source electrode and the The drain electrodes are respectively disposed on opposite sides of the active layer, and the data lines and the common electrode lines are disposed on the base substrate in the same layer, and are located under the active layer, the data lines Separating from the common electrode line, the common electrode is provided with a connection region, the connection region at least partially overlapping the common electrode line in the orthogonal projection direction, and the common electrode and the common electrode line are located at the connection region and the common The first via between the electrode lines enables electrical connection.
  • the data line and the common electrode line set in the same layer can adopt the same conductive Material.
  • the active layer is formed of a low temperature polysilicon material, and the source electrode and the drain electrode are formed on opposite sides of the active layer by ion implantation, and the common electrode line is formed under the drain electrode.
  • the array substrate further includes a buffer layer, the buffer layer is disposed under the active layer and above the base substrate, and the data line and the common electrode line are Cover layer.
  • the position at which the buffer layer is disposed may be not limited thereto, for example, disposed above the substrate and below the data lines and the common electrode lines.
  • the array substrate further includes a gate insulating layer, and the gate insulating layer is disposed above the active layer and below the gate electrode.
  • the array substrate further includes an intermediate dielectric layer disposed above the gate electrode.
  • the buffer layer, the gate insulating layer and the intermediate dielectric layer are provided with a second via hole at a position corresponding to the data line, and the gate insulating layer and the intermediate dielectric layer are correspondingly
  • a third via is formed at a position of the source electrode, and the data line and the source electrode are electrically connected through the second via and the third via.
  • the array substrate further includes a pixel electrode disposed above the intermediate dielectric layer, and a deuterated layer disposed between the pixel electrode and the common electrode; the pixel electrode and the common electrode are positive At least partially overlapping in a projection direction; when the common electrode is located above the deuterated layer, and the pixel electrode is located below the deuterated layer, the gate insulating layer and the intermediate dielectric layer are corresponding to the drain electrode a fourth via hole is formed in the position, the pixel electrode and the drain electrode are electrically connected through the fourth via hole, the common electrode is in a slit shape, and the pixel electrode is in a plate shape or a slit shape, and is common a first via between the electrode connection region and the common electrode line extends through the buffer layer, the gate insulating layer, the intermediate dielectric layer, and the deuterated layer;
  • the gate insulating layer and the intermediate dielectric layer are opened fourth at a position corresponding to the drain electrode.
  • a fifth via hole at a position corresponding to the drain electrode, wherein the pixel electrode and the drain electrode are electrically connected through the fourth via hole and the fifth via hole, the common The electrode is in the shape of a plate or a slit, and the pixel The electrode is slit-shaped, and the first via between the common electrode connection region and the common electrode line penetrates through the buffer layer, the gate insulating layer and the intermediate dielectric layer.
  • the array substrate further includes a light shielding metal layer, wherein the light shielding metal layer is disposed on the substrate in the same layer as the data line and the common electrode line, and the light shielding metal layer is disposed on the active layer Below the layer, and at least partially overlapping the active layer in the forward projection direction.
  • the light shielding metal layer is disposed between the source electrode and the region corresponding to the drain electrode, and at least partially overlaps the gate electrode in a right projection direction.
  • a lightly doped drain electrode is disposed in the active layer, and the lightly doped drain electrode is disposed between the source electrode and the drain electrode, and is distributed in a region corresponding to the gate electrode. Or on both sides.
  • Embodiment 1 of the present invention provides an array substrate, see FIG. 11 and FIG. 12, FIG. 11 is a schematic cross-sectional structural view of an array substrate according to Embodiment 1 of the present invention, and FIG. 12 is a schematic plan view of the array substrate shown in FIG. 11 and FIG. 12, it can be seen that the array substrate includes: a substrate substrate 101, a common electrode line 201, a data line 107, a buffer layer 102, an active layer 103, a drain electrode 104, a source electrode 105, and a gate electrode. 106.
  • the common electrode 108, the pixel electrode 109, the scan line 110 disposed at the intersection of the data line 107, and the gate insulating layer 111 between the active layer 103 and the gate electrode 106 are located between the gate electrode 106 and the common electrode 108.
  • the common electrode line 201 is disposed in the same layer as the data line 107 between the base substrate 101 and the buffer layer 102; and, the common electrode line 201 is the same material as the data line 107; The common electrode line 201 and the data line 107 may be formed in the same patterning process.
  • the buffer layer 102 is located above the common electrode line 201 and the data line 107, below the active layer 103, and the buffer layer 102 covers the data line 107 and the common electrode line 201 located below it;
  • the buffer layer 102 is used to block diffusion of impurities contained in the substrate substrate into the active layer 103 of the thin film transistor in the subsequent process to prevent the film crystal
  • the characteristics such as the threshold voltage and the leakage current of the tube are affected, and at the same time, due to the active layer
  • the buffer layer 102 can be provided to prevent impurities caused by excimer laser annealing in the subsequent process of fabricating the active layer 103. Diffusion improves the quality of low-temperature polysilicon to form thin film transistors.
  • the active layer 103 is located above the buffer layer 102 below the gate insulating layer 111, and the active layer 103 is made of a low temperature polysilicon material.
  • the drain electrode 104 and the source electrode 105 are respectively located on opposite sides of the active layer 103, and the drain electrode 104 and the source electrode 105 are formed by ion implantation.
  • the gate electrode 106 is disposed in the same layer as the scan line 110 between the gate insulating layer 111 and the intermediate dielectric layer 112. Moreover, the material of the gate electrode 106 is the same as that of the scan line 110, and the two can be utilized. The same patterning process is formed.
  • the common electrode 108 is located above the intermediate dielectric layer 112 and below the deuterated layer 114.
  • the common electrode 108 may be made of a transparent conductive material such as indium tin oxide, and the common electrode 108 is plate-shaped or narrow. Sewed.
  • connection region 115 is disposed in the same layer as the common electrode 108, using the same transparent conductive material, and at least partially overlapping the common electrode line 201 in the right projection direction.
  • the pixel electrode 109 is located above the deuterated layer 114, and may be made of a transparent conductive material such as indium tin oxide, and the pixel electrode 109 has a slit shape.
  • the pixel electrode 109 and the common electrode 108 overlap at least partially in the forward projection direction.
  • the array substrate further includes a first via 401, a second via 402, a third via 403, a fourth via 404 and a fifth via 405;
  • the first via 401 is used to sequentially penetrate the intermediate dielectric layer 112, the gate insulating layer 111, and the buffer layer 102, so that the common electrode line 201 is electrically connected to the common electrode 108, and provides common to the common electrode 108.
  • Voltage signal
  • the second via 402 is disposed at a position corresponding to the buffer layer 102, the gate insulating layer 111, and the intermediate dielectric layer 112 corresponding to the data line 107;
  • the third via 403 is disposed at a position corresponding to the gate insulating layer 111 and the intermediate dielectric layer 112 and the source electrode 105, such that the source electrode 105 and the data line 107 pass the first
  • the second via 402 and the third via 403 are electrically connected;
  • the fourth via 404 is disposed at a position corresponding to the gate insulating layer 111 and the intermediate dielectric layer 112 and the drain electrode 104;
  • the fifth via 405 is disposed at a position corresponding to the drain layer 114 and the drain electrode 104, such that the drain electrode 104 and the pixel electrode 109 pass through the fourth via 404 and The fifth via 405 is electrically connected.
  • the 404 is filled with a transparent conductive material for fabricating the common electrode 108
  • the fifth via 405 is filled with a transparent conductive material for fabricating the pixel electrode 109.
  • the array substrate further includes a light shielding metal layer 116, and the light shielding metal layer 116 is disposed on the substrate substrate 101 in the same layer as the data line 107 and the common electrode line 201. a layer 116 is disposed on the active layer
  • the light shielding metal layer 116 is disposed between the source electrode 105 and the region corresponding to the drain electrode 104, and The gate electrode 106 at least partially overlaps in the forward projection direction.
  • the metal light shielding layer 116 is configured to cover a channel region of the active layer 103 so that part of the light that is irradiated to the active layer 103 can be blocked, thereby reducing the active layer.
  • the leakage current of 103 can further reduce the leakage current of the active layer.
  • the light shielding metal layer 116, the common electrode line 201, and the data line 107 are made of the same conductive material, so that the light shielding metal layer 116, the common electrode line 201, and the data line 107 disposed in the same layer can be simultaneously formed by one patterning process; Since the conductive material is an opaque conductive material, the light-shielding metal layer 116 simultaneously blocks a portion of the light that is incident on the active layer 103, thereby reducing the leakage current of the thin film transistor.
  • the array substrate provided in this embodiment further includes a lightly doped drain 117 disposed in the active layer 103, and the lightly doped drain 117 is located between the drain electrode 104 and the source electrode 105, and is distributed over In the embodiment, the lightly doped drain 117 can simultaneously reduce the leakage current of the thin film transistor.
  • the gate electrode 106 is at least one, and the light shielding metal layer 116 is at least one piece. In this embodiment, two gate electrodes 106 are disposed, and the gate electrodes are disposed to reduce the leakage current of the thin film transistor.
  • the light-shielding metal layer 116 is two pieces.
  • a planar layer may be disposed between the intermediate dielectric layer 112 and the common electrode 108, and the planar layer can keep the intermediate dielectric layer 112 flat; of course, the intermediate dielectric layer 112 and the common electrode 108 A flat layer may not be provided between them, as described in this embodiment, so that the thickness of the array substrate is relatively thin.
  • FIG. 13 Another embodiment of the present invention provides another array substrate.
  • the cross-sectional structure is as shown in FIG. 13.
  • the array substrate and the array substrate shown in FIG. 12 have substantially the same structure. The difference is as follows: 1.
  • the pixel electrode 109 is located above the deuterated layer 114, the common electrode 108 is located below the deuterated layer 114, and in the array substrate shown in FIG. 13, the pixel electrode 109 is located below the deuterated layer 114, the common electrode 108 is located above the deuterated layer 114;
  • Second, the fifth via hole is not required in the array substrate shown in FIG. 13; 3.
  • the array substrate shown in FIG. 13 In the array substrate shown in FIG.
  • the first via for connecting the common electrode and the common electrode line sequentially penetrates the intermediate dielectric layer 112, the gate insulating layer 111, and the buffer layer 102, and is used to connect the common electrode and the common electrode in the array substrate shown in FIG.
  • the first via 401 of the line sequentially passes through the deuterated layer 114, the intermediate dielectric layer 112, the gate insulating layer 111 and the buffer layer 102.
  • the structure of the array substrate provided in the second embodiment of the present invention is further simplified. The production process is streamlined, production time is reduced, and production costs are reduced.
  • a method for fabricating an array substrate according to a third embodiment of the present invention includes a step of forming a data line, a scan line, a common electrode, and a common electrode line, and a step of forming a thin film transistor, including forming a gate electrode, a step of a source electrode, a drain electrode, and an active layer, the common electrode, a common electrode line, and a thin film crystal
  • the tubes are each formed in a plurality of pixel regions surrounded by the scan lines and the data lines, wherein the data lines and the common electrode lines are formed on the base substrate in the same layer, and the active Below the layer, a connection region is formed on the same layer on the common electrode, the connection region at least partially overlapping the common electrode line in the front projection direction, and the common electrode and the common electrode line are formed in the connection region and the common electrode line.
  • the first via is electrically connected.
  • the method for preparing the array substrate specifically includes: Step 1: forming a pattern including the data line and the common electrode line by using a patterning process on the substrate, the data line and the The common electrode lines are spaced apart;
  • a second step forming a buffer layer and a pattern including an active layer on the base substrate on which the first step is completed; the buffer layer covering the common electrode line and the data line, the active layer a pattern is formed on the buffer layer;
  • the third step forming a gate insulating layer and a pattern including the gate electrode on the substrate on which the second step is completed;
  • the fourth step forming the source electrode and the drain electrode on the substrate of the third step, wherein the source electrode and the drain electrode are formed on opposite sides of the active layer by ion implantation;
  • a fifth step forming an intermediate dielectric layer on the substrate of the fourth step and a pattern including the first via, the second via, the third via, and the fourth via, wherein: the first pass a hole is formed between the connection region and the common electrode line, penetrates the buffer layer, the gate insulating layer, and the intermediate dielectric layer, and the second via hole is formed at a position corresponding to the data line and penetrates The buffer layer, the gate insulating layer and the intermediate dielectric layer, the third via hole is formed at a position corresponding to the source electrode and penetrates the gate insulating layer and the intermediate dielectric layer, the fourth via hole Forming at a position corresponding to the drain electrode and penetrating the gate insulating layer and the intermediate dielectric layer;
  • Step 6 forming a pattern including the common electrode and the connection region on the base substrate completing the fifth step, wherein the first via hole, the second via hole, the third via hole, and the fourth via hole are simultaneously filled a conductive material for forming the common electrode, the connection region and the common electrode line being electrically connected through the first via, the data line and the The source electrode is electrically connected through the second via hole and the third via hole;
  • the seventh step forming the deuterated layer on the substrate substrate completing the sixth step and forming in the deuterated layer a pattern of five via holes, the fifth via hole being formed at a position corresponding to the drain electrode, and a position of the fifth via hole corresponding to a position of the fourth via hole;
  • the eighth step forming a pattern including a pixel electrode on the base substrate on which the seventh step is completed, the fifth via hole is filled with a conductive material for forming the pixel electrode, and the pixel electrode and the drain electrode pass The fourth via is electrically connected to the fifth via.
  • the method described in the fifth step to the eighth step is applicable to the array substrate in which the common electrode is located under the pixel electrode. And for the array substrate in which the common electrode is located above the pixel electrode, the preparation method further comprises the steps of forming a common electrode, a connection region and a pixel electrode:
  • the fifth step forming an intermediate dielectric layer on the substrate of the fourth step and a pattern including the second via, the third via, and the fourth via, wherein: the second via is formed in correspondence Positioning the data line through the buffer layer, the gate insulating layer, and the intermediate dielectric layer, wherein the third via hole is formed at a position corresponding to the source electrode and penetrates the gate insulating layer And the intermediate dielectric layer, the fourth via hole is formed at a position corresponding to the drain electrode and penetrates the gate insulating layer and the intermediate dielectric layer;
  • a sixth step forming a pattern including the pixel electrode on the substrate of the fifth step, wherein the second via, the third via, and the fourth via are simultaneously filled with a pixel for forming the pixel electrode a conductive material, the data line is electrically connected to the source electrode through the second via hole and the third via hole, and the pixel electrode and the drain electrode are electrically connected through the fourth via hole;
  • a seventh step forming the deuterated layer and a pattern including a common electrode and a connection region on the substrate of the sixth step, the deuterated layer completely covering the pixel electrode, the common electrode and the connection region a pattern formed over the deuterated layer and forming a first via between the connection region and the common electrode line, the first via extending through the buffer layer, the gate insulating layer, and the middle Dielectric layer and deuterated layer.
  • the fourth step further includes: forming a lightly doped drain electrode in the active layer by using an ion implantation method, wherein the lightly doped drain electrode is formed between the source electrode and the drain electrode, And distributed on both sides of the corresponding region of the gate electrode; the lightly doped drain electrode simultaneously acts to reduce leakage current of the thin film transistor.
  • the first step further includes: forming a light shielding metal layer on the base substrate, wherein the light shielding metal layer is formed in the same layer as the data line and the common electrode line, and the light shielding metal layer is formed in the Below the source layer, and at least partially overlapping the active layer in the forward projection direction.
  • the light shielding metal layer formed in the first step is at least one piece, and the gate electrode formed in the third step is at least one; the light shielding metal layer is formed corresponding to the gate electrode position, and is used for Reduce the leakage current of the thin film transistor.
  • the method for fabricating the array substrate according to the third embodiment of the present invention is described in detail below with reference to the accompanying drawings.
  • the method for fabricating the array substrate according to the first embodiment of the present invention is as follows.
  • a metal thin film is deposited on the base substrate 101, and then processed by the first patterning process to form a pattern including the data line 107, the light shielding metal layer 116, and the common electrode line 201, the data.
  • the line 107, the light shielding metal layer 116 and the common electrode line 201 are spaced apart.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.; A process of forming a pattern using a photoresist, a mask, an exposure machine, or the like, including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the patterning process includes: first, forming (such as sputtering or coating, etc.) a layer of metal for forming the data line 107, the light shielding metal layer 116, and the common electrode line 201 on the base substrate 101. a thin film; then, a photoresist is coated on the metal film; then, the photoresist is exposed by a mask provided with a pattern including the data line 107, the light-shielding metal layer 116, and the common electrode line 201; After the etching, a pattern including the data line 107, the light shielding metal layer 116, and the common electrode line 201 is formed.
  • the method for preparing the array substrate of the embodiment the method is formed by a patterning process. The preparation process of the film layer is the same as this, and will not be described in detail later.
  • a silicon dioxide or silicon nitride layer is deposited by plasma enhanced chemical vapor deposition on the substrate of the first step to form a buffer layer 102, and the buffer layer 102 covers the data.
  • an amorphous silicon thin film layer is formed over the buffer layer 102 by plasma enhanced chemical vapor deposition or the like, and then subjected to laser annealing.
  • a process such as a process or a solid phase crystallization process, crystallization of amorphous silicon, formation of a polysilicon thin film layer, and formation of a pattern including the low temperature polysilicon active layer 103 by a second patterning process; pattern formation of the active layer 103 On the buffer layer 102, and the pattern of the active layer 103 overlaps the common electrode 201 in the forward projection direction.
  • the fourth step referring to FIG. 16, depositing a silicon nitride (SiNx) or silicon oxide (SiOx) layer on the substrate of the third step to form a gate insulating layer 111, wherein the gate insulating layer 111 is disposed Above the source layer 103 and below the gate electrode 106.
  • SiNx silicon nitride
  • SiOx silicon oxide
  • a metal layer such as molybdenum (Mo), aluminum (A1) or cadmium (Cr) is deposited on the substrate of the fourth step, and then processed by a third patterning process to form the gate electrode 106. And scan lines;
  • Mo molybdenum
  • Al aluminum
  • Cr cadmium
  • the opposite sides of the active layer are heavily doped by ion implantation to form the drain electrode 104 and the source electrode 105, and are located at the source electrode.
  • a portion of the active layer region between the drain electrode 104 and the drain electrode 104 is lightly doped to form a lightly doped drain 117 formed between the drain electrode 104 and the source electrode 105 and distributed over the gate. Both sides of the region corresponding to the electrode 106.
  • the seventh step see Figure 17, depositing silicon nitride on the substrate of the sixth step
  • a (SiNx) or silicon oxide (SiOx) layer forming an intermediate dielectric layer 112; and forming a first via 401, a second via 402, a third via 403, and a fourth via 404 by a fourth patterning process ;
  • the first via hole 401 is formed between the connection region 115 and the common electrode line 201, penetrates the buffer layer 102, the gate insulating layer 111, and the intermediate dielectric layer. a layer 112, the second via 402 is disposed at a position corresponding to the data line 107 in the buffer layer 102, the gate insulating layer 111, and the intermediate dielectric layer 112; a hole 403 disposed at a position corresponding to the source electrode 105 in the gate insulating layer 111 and the intermediate dielectric layer 112 such that the source electrode 105 and the data line 107 pass through the second via 402
  • the third via hole 403 is electrically connected; the fourth via hole 404 is disposed at a position corresponding to the drain electrode 104 in the gate insulating layer 111 and the intermediate dielectric layer 112.
  • a layer of indium tin oxide ITO transparent conductive film is deposited on the intermediate dielectric layer 112 by magnetron sputtering, and passes through the fifth patterning process.
  • Forming the common electrode 108 and the connection region 115; the first via 401, the second via 402, the third via 403, and the fourth via 404 are simultaneously filled with a conductive material for forming the common electrode 108,
  • the connection region 115 is electrically connected to the common electrode line 201 through the first via 401, and the data line 107 and the source electrode 105 are electrically connected through the second via 402 and the third via 403. .
  • the ninth step referring to FIG. 18, forming a deuterated layer 114 on the substrate of the eighth step, and forming a fifth via 405 through the sixth patterning process, the fifth via 405 penetrating through the deuteration
  • the layer 114 corresponds to the drain electrode 104 and is configured to electrically connect the pixel electrode and the drain 104 to the fifth via 405 through the fourth via 404.
  • a layer of indium tin oxide ITO transparent conductive film is deposited on the deuterated layer 114 by magnetron sputtering, and the seventh patterning process is performed.
  • the seventh patterning process is performed.
  • the fifth via 405 is filled with a conductive material for forming the pixel electrode 109,
  • the pixel electrode 109 is electrically connected to the drain electrode 104 through the fourth via 404 and the fifth via 405.
  • the array substrate of the first embodiment of the present invention having the structure shown in FIG. 12 is formed.
  • the preparation method specifically includes: First, referring to FIG. 14, a metal thin film is deposited on the substrate 101, and then processed by the first patterning process to form a data line. 107, light-shielding metal layer 116 and a pattern of the common electrode line 201, the data line 107, the light shielding metal layer 116, and the common electrode line 201 are disposed apart from each other.
  • a buffer layer 102 is formed on the base substrate on which the first step is completed, and the buffer layer 102 completely covers the data line 107, the light-shielding metal layer 116, and the common electrode line 201.
  • a pattern including the low-temperature polysilicon active layer 103 is formed by a second patterning process; the pattern of the active layer 103 is formed in the On the stamp layer 102, the pattern of the active layer 103 overlaps the common electrode 201 in the forward projection direction.
  • the fourth step referring to FIG. 16, depositing a silicon nitride (SiNx) or silicon oxide (SiOx) layer on the substrate of the third step to form a gate insulating layer 111, wherein the gate insulating layer 111 is disposed Above the source layer 103 and below the gate electrode.
  • SiNx silicon nitride
  • SiOx silicon oxide
  • a metal layer such as molybdenum (Mo), aluminum (A1) or cadmium (Cr) is deposited on the substrate of the fourth step, and then processed by a third patterning process to form the gate electrode 106. And scan lines;
  • Mo molybdenum
  • Al aluminum
  • Cr cadmium
  • the opposite sides of the active layer are heavily doped by ion implantation to form the drain electrode 104 and the source electrode 105, and are located at the source electrode.
  • a portion of the active layer region between the drain electrode 104 and the drain electrode 104 is lightly doped to form a lightly doped drain 117 formed between the drain electrode 104 and the source electrode 105 and distributed over the gate. Both sides of the region corresponding to the electrode 106.
  • the seventh step referring to FIG. 19, depositing a silicon nitride (SiNx) or silicon oxide (SiOx) layer on the substrate of the sixth step to form an intermediate dielectric layer 112; and forming a fourth through a fourth patterning process a second via 402, a third via 403, and a fourth via 404; wherein the second via 402 is disposed on the buffer layer 102, the gate insulating layer 111, and the intermediate dielectric layer 112 a position corresponding to the data line 107; the third via 403 is disposed at a position corresponding to the gate insulating layer 111 and the intermediate dielectric layer 112 and the source electrode 105, such that the source electrode 105 The data line 107 is electrically connected to the second via hole 402 and the third via hole 403; the fourth via hole 404 is disposed in the gate insulating layer 111 and the intermediate dielectric layer 112 A position corresponding to the drain electrode 104.
  • SiNx silicon nitride
  • SiOx silicon
  • a transparent conductive film of indium tin oxide (ITO) is deposited on the intermediate dielectric layer 112 by magnetron sputtering, and passed through the fifth time.
  • the patterning process forms the pixel electrode 109, and the second via 402, the third via 403, and the fourth via 404 are simultaneously filled with a transparent conductive material for forming the pixel electrode, and the pixel electrode 109 passes through the
  • the four vias 404 are electrically connected to the drain 104.
  • a deuterated layer 114 is formed on the substrate of the eighth step, and a first via 401 is formed through a sixth patterning process, the first via 401 penetrating through the deuteration
  • the layer 114, the intermediate dielectric layer 112, the gate insulating layer 111, and the buffer layer 102 are used to electrically connect the connection region 115 of the common electrode to the common electrode line 201 through the first via hole 401.
  • a layer of indium tin oxide ITO transparent conductive film is deposited on the deuterated layer 114 by magnetron sputtering, and the seventh patterning process is performed.
  • the seventh patterning process is performed.
  • a pattern including the common electrode 108 and the connection region 115 is formed, and the first via hole 401 is filled with a transparent film for forming the common electrode 108.
  • the conductive material, the common electrode 108 and the common electrode line 201 are electrically connected through the first via 401.
  • the array substrate provided in the second embodiment of the present invention has the structure shown in FIG. It is to be noted that each of the above steps may be executed in the order described above, or may be changed in the order as needed, and executed in another order.
  • a common electrode line is disposed between the buffer layer and the substrate, so that the common electrode line and the pixel electrode located above thereof form a storage capacitor.
  • the purpose of increasing the storage capacitor is achieved; and, since the common electrode line is disposed in the same layer as the data line and the light shielding metal layer, the common electrode line, the data line, and the light shielding metal layer can be formed by one exposure process, thereby reducing fabrication The process, the production process is completed, and the production cost is saved and the production time is shortened.

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Abstract

一种阵列基板及其制备方法和显示装置，用以解决现有技术中工艺复杂、成本高、耗时长的问题，同时达到增大存储电容的目的。阵列基板上的数据线（107）和公共电极线（201）同层设置在衬底基板（101）上，且位于有源层（103）下方，数据线（107）和公共电极线（201）相隔设置，公共电极（108）上设置有连接区（115），连接区（115）在正投影方向上至少部分与公共电极线（201）重叠，公共电极（108）与公共电极线（201）通过位于连接区（115）与公共电极线（201）之间的第一过孔（401）实现电连接。

Description

阵列基板及其制备方法和显示装置 技术领域
本发明涉及液晶显示技术领域， 尤其涉及阵列基板及其制备 方法和显示装置。 背景技术
由于非晶硅存在因本身自有的缺陷而导致的开态电流低、 迁 移率低、 稳定性差等问题， 使它在很多领域受到了限制， 为了弥 补非晶硅本身缺陷， 扩大在相关领域的应用， 低温多晶硅 (Low
Temperature Poly-Silicon, LTPS) 技术应运而生。
随着薄膜晶体管液晶显示技术 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )技术的发展， 基于低温多晶硅的显 示技术逐渐成为主流。 如图 1 所示， 现有技术中的低温多晶硅薄 膜晶体管阵列基板包括： 衬底基板 101、 緩冲层 102、有源区 103、 栅电极 106、 源电极 105、 漏电极 104、 数据线 107、 透明公共电 极 108、 像素电极 109、 栅绝缘层 111、 中间介电层 112、 平坦层 113和飩化层 114。
随着像素技术开发的需求， 如何增大存储电容成为一个重要 的关注点， 现有技术中为达到增大存储电容的目的， 如图 2所示， 在阵列基板中设置有公共电极线 201 ,所述公共电极线 201与栅电 极 106同层设置， 并与位于其上方的像素电极 109共同形成存储 电容。
图 2中所示的低温多晶硅薄膜晶体管阵列基板的制作流程具 体包括：
第一步， 参见图 3 , 在衬底基板 101上形成緩冲层 102。
第二步， 参见图 3 , 在完成緩冲层 102制作的衬底基板上， 通过构图工艺， 形成有源区 103。
第三步， 参见图 4, 在完成有源区 103制作的衬底基板上， 沉积氧化硅或氮化硅层， 形成栅绝缘层 111。 第四步， 参见图 4, 在完成栅绝缘层 111制作的衬底基板上， 利用构图工艺， 制作栅电极 106和公共电极线 201。
第五步， 参见图 4, 采用离子注射方式将高浓度的 n型杂质 离子掺杂到有源层 103的两侧， 在有源层 103的相对两侧分别形 成源电极 105、 漏电极 104。
第六步， 参见图 5, 在完成第五步的衬底基板上， 沉积氧化 硅或氮化硅层， 形成中间介电层 112; 并通过构图工艺， 形成贯穿 所述栅绝缘层 111和中间介电层 112的过孔 VI。
第七步， 参见图 6, 在完成中间介电层 112制作的衬底基板 上形成数据线 107, 且所述源电极 105通过所述过孔 VI与数据线 107电连接。
第八步， 参见图 7, 在完成数据线 107、 源电极 105和漏电极 104制作的衬底基板上， 形成平坦层 113, 并通过构图工艺， 形成 贯穿该绝缘层 113的过孔 V2。
第九步， 参见图 8, 在完成平坦层 113制作的衬底基板上， 使用磁控溅射法在平坦层 113上沉积一层透明导电薄膜， 然后利 用构图工艺， 形成透明公共电极 108。
第十步， 参见图 9, 在完成透明公共电极 108制作的衬底基 板上， 形成飩化层 114, 并通过构图工艺， 形成贯穿该飩化层 114 的过孔 V3。
第十一步，参见图 10,在完成绝缘层 114制作的衬底基板上， 使用磁控溅射法在绝缘层 113上沉积一层氧化铟锡 ITO透明导电 薄膜， 然后利用构图工艺， 形成像素电极 109, 使得所述像素电极 109通过过孔 VI、 过孔 V2和过孔 V3与漏电极 104电连接。
通过上述对现有技术中的低温多晶硅薄膜晶体管阵列基板制 作方法的具体论述可知， 在该阵列基板中， 虽然所述公共电极线 201与栅电极 106是经过一次曝光工艺形成，但制作过程中至少需 要通过八次曝光刻蚀等构图工艺， 该阵列基板的制作过程中仍存 在制造工艺流程复杂， 制造流程繁多， 成本高， 耗时长等问题。 发明内容
本发明实施例提供了一种阵列基板及其制备方法和显示面 板， 用以解决现有技术中工艺复杂、 成本高、 耗时长的问题， 同 时达到增大存储电容的目的。
本发明实施例提供的阵列基板包括： 衬底基板以及设置在所 述衬底基板上的数据线和扫描线， 所述数据线和所述扫描线围成 多个像素区域， 所述像素区域内设置有薄膜晶体管、 公共电极及 公共电极线， 所述薄膜晶体管包括栅电极、 源电极、 漏电极和有 源层， 所述栅电极设置在所述有源层的上方， 所述源电极和所述 漏电极分别设在所述有源层的相对两侧， 其中， 所述数据线和所 述公共电极线同层设置在所述衬底基板上， 且位于所述有源层下 方， 所述数据线和所述公共电极线相隔设置， 所述公共电极上设 置有连接区， 所述连接区在正投影方向上至少部分与公共电极线 的第一过孔实现电连接。 所述阵列基板中， 所述公共电极线与位 于其上方的像素电极共同形成存储电容， 达到增大存储电容的目 的； 并且， 由于所述公共电极线与数据线同层设置， 使得经过一 次曝光工艺即可形成所述公共电极线与数据线， 减少了制作流程， 筒化了制作工艺， 同时还达到了节省制作成本、 缩短了制作时间 的目的。
例如， 所述数据线和所述公共电极线采用相同的导电材料制 成，使得通过一道工艺就可以制得所述数据线和所述公共电极线， 同时能够节省制作成本。
例如， 所述有源层采用低温多晶硅材料制成， 所述源电极和 所述漏电极采用离子注入的方式形成在所述有源层的相对两侧， 以便在源电极和漏电极之间形成导电沟道， 所述公共电极线形成 在漏电极的下方。
例如， 所述阵列基板还包括緩冲层， 所述緩冲层设置在所述 有源层的下方以及所述衬底基板的上方， 所述数据线和所述公共 电极线被所述緩冲层覆盖； 所述緩冲层， 用于阻挡后续工艺中基 板中所含的杂质扩散进入薄膜晶体管的有源层， 防止对薄膜晶体 管的阔值电压和漏电流等特性产生影响， 提高薄膜晶体管的质量。
例如， 所述阵列基板还包括栅绝缘层， 所述栅绝缘层设置在 所述有源层的上方以及所述栅电极的下方， 用于将所述有源层和 所述栅电极 隔离。
例如， 所述阵列基板还包括设置在所述栅电极上方的中间介 电层， 用于将所述栅电极和位于该中间介电层上的其它电极隔离。
例如， 所述緩冲层、 所述栅绝缘层和所述中间介电层在对应 着所述数据线的位置开设有第二过孔， 所述栅绝缘层和所述中间 介电层在对应着所述源电极的位置开设有第三过孔， 所述数据线 和所述源电极通过所述第二过孔以及所述第三过孔电连接。
例如， 所述阵列基板还包括设置在中间介电层上方的像素电 极， 以及设置在所述像素电极和所述公共电极之间的飩化层； 所 述像素电极与所述公共电极在正投影方向上至少部分重叠；
所述公共电极位于飩化层的上方， 所述像素电极位于飩化层 的下方， 所述栅绝缘层、 所述中间介电层在对应着所述漏电极的 位置开设有第四过孔， 所述像素电极和所述漏电极通过所述第四 过孔电连接， 所述公共电极为狭缝状， 所述像素电极为板状或狭 缝状， 连接区与公共电极线之间的第一过孔贯穿緩冲层、 栅绝缘 层、 中间介电层和飩化层； 或者， 所述公共电极位于飩化层的下 方， 所述像素电极位于飩化层的上方， 所述栅绝缘层、 所述中间 介电层在对应着所述漏电极的位置开设有第四过孔， 所述飩化层 在对应着所述漏电极的位置开设有第五过孔， 所述像素电极和所 述漏电极通过所述第四过孔和第五过孔电连接， 所述公共电极为 板状或狭缝状， 所述像素电极为狭缝状， 所述连接区与公共电极 线之间的第一过孔贯穿緩冲层、 栅绝缘层和中间介电层。
例如， 所述阵列基板中还包括遮光金属层， 所述遮光金属层 与所述数据线和公共电极线同层设置在所述衬底基板上， 所述遮 光金属层设置在所述有源层下方， 且在正投影方向上与所述有源 层至少部分重叠； 所述遮光金属层设置在所述源电极和所述漏电极对应的区域 之间， 且在正投影方向上与所述栅电极至少部分重叠， 用于将照 射到所述漏电极和所述源电极之间的区域的部分光线遮住， 从而 减小薄膜晶体管的漏电流。
例如， 所述有源层中还设置有轻掺杂漏电极， 所述轻掺杂漏 电极设置在所述源电极和所述漏电极之间， 且分布在所述栅电极 对应的区域的两侧； 所述轻掺杂漏电极能够同时起到降低薄膜晶 体管的漏电流的作用。
本发明实施例提供了一种显示面板， 所述显示面板包括上述 的阵列基板。
本发明实施例提供了一种阵列基板的制备方法， 所述方法包 括形成数据线、 扫描线、 公共电极和公共电极线的步骤和形成薄 膜晶体管的步骤， 形成所述薄膜晶体管包括形成栅电极、 源电极、 漏电极和有源层的步骤， 所述公共电极、 公共电极线和薄膜晶体 管均形成在由所述扫描线和所述数据线围成的多个像素区域内， 其中， 所述数据线和所述公共电极线同层形成在衬底基板上， 且 在所述有源层下方， 所述公共电极上同层形成有连接区， 所述连 接区在正投影方向上至少部分与公共电极线重叠， 所述公共电极 与公共电极线通过形成在连接区与公共电极线之间的第一过孔实 现电连接。
例如， 所述制备方法具体包括：
在衬底基板上采用构图工艺同时形成包括所述数据线、 公共 电极线的图形， 所述数据线、 所述遮光金属层和所述公共电极线 相隔设置；
形成緩冲层和包括有源层的图形； 所述緩冲层覆盖所述公共 电极线和所述数据线， 所述包括有源层的图形形成在所述緩冲层 上；
形成栅绝缘层和包括所述栅电极的图形；
形成所述源电极和所述漏电极的图形， 所述源电极和所述漏 电极采用离子注入方式形成在所述有源层的相对两侧； 例如， 所述制备方法还包括形成公共电极、连接区和像素电 极的以下步骤：
形成中间介电层以及包括第一过孔、 第二过孔、 第三过孔以 及第四过孔的图形， 其中： 所述第一过孔形成在所述连接区与所 述公共电极线之间， 贯穿所述緩冲层、 栅绝缘层、 中间介电层， 所述第二过孔形成在对应着所述数据线的位置并贯穿所述緩冲 层、 栅绝缘层和中间介电层， 所述第三过孔形成在对应着所述源 电极的位置并贯穿所述栅绝缘层和中间介电层， 所述第四过孔形 成在对应着所述漏电极的位置并贯穿所述栅绝缘层和中间介电 层；
形成包括所述公共电极和连接区的图形， 所述第一过孔、 第 二过孔、 第三过孔和第四过孔中同时填充有用于形成所述公共电 极的导电材料， 所述数据线与所述源电极通过所述第二过孔和所 述第三过孔电连接；
形成所述飩化层以及在所述飩化层中形成包括第五过孔的图 形， 所述第五过孔形成在对应着所述漏电极的位置， 且所述第五 过孔的位置与所述第四过孔的位置相对应；
形成包括像素电极的图形， 所述第五过孔中填充有用于形成 所述像素电极的导电材料， 所述像素电极与所述漏电极通过所述 第四过孔和所述第五过孔电连接。
上述形成公共电极、 连接区和像素电极的方法， 适用于所述 公共电极位于所述像素电极下方的阵列基板。 而对于所述公共电 极位于所述像素电极上方的阵列基板中， 所述制备方法还包括形 成公共电极、 连接区和像素电极的以下步骤：
形成中间介电层以及包括第二过孔、 第三过孔以及第四过孔 的图形， 其中： 所述第二过孔形成在对应着所述数据线的位置并 贯穿所述緩冲层、 所述栅绝缘层和所述中间介电层， 所述第三过 孔形成在对应着所述源电极的位置并贯穿所述栅绝缘层和所述中 间介电层， 所述第四过孔形成在对应着所述漏电极的位置并贯穿 所述栅绝缘层和所述中间介电层； 形成包括所述像素电极的图形， 所述第二过孔、 第三过孔和 第四过孔中同时填充有用于形成所述像素电极的导电材料， 所述 数据线与所述源电极通过所述第二过孔以及所述第三过孔电连 接， 所述像素电极与所述漏电极通过所述第四过孔电连接；
形成所述飩化层以及包括公共电极和连接区的图形， 所述飩 化层完全覆盖所述像素电极， 所述包括公共电极和连接区的图形 形成在所述飩化层的上方， 以及形成所述连接区与所述公共电极 线之间的第一过孔， 所述过第一孔贯穿所述緩冲层、 栅绝缘层、 中间介电层和飩化层。
例如， 所述形成源电极和所述漏电极的步骤还进一步包括： 采用离子注入方式在所述有源层中形成轻掺杂漏电极， 所述轻掺 杂漏电极形成在所述源电极和所述漏电极之间， 且分布在所述栅 电极对应的区域的两侧； 所述轻掺杂漏电极同时起到降低薄膜晶 体管的漏电流的作用。
例如， 所述形成包括所述数据线、公共电极线的图形的步骤 还进一步包括： 在衬底基板上形成遮光金属层， 所述遮光金属层 与所述数据线和公共电极线同层形成， 所述遮光金属层形成在所 述有源层下方， 且在正投影方向上与所述有源层至少部分重叠。
例如， 所述形成包括所述数据线、公共电极线的图形的步骤 中形成的所述遮光金属层为至少一片， 在形成栅绝缘层和包括所 述栅电极的图形中形成的所述栅电极为至少一个； 所述遮光金属 层与所述栅电极位置对应形成， 用于减少薄膜晶体管的漏电流。 附图说明
图 1为现有技术中的一种阵列基板的剖面结构示意图； 图 2为现有技术中的另一种阵列基板的剖面结构示意图； 图 3至图 10为图 2所示的阵列基板的制备方法流程图； 图 11 为本发明实施例提供的一种阵列基板的平面结构示意 图；
图 12为沿图 11中 A-A1方向的阵列基板的剖面结构示意图； 图 13 为本发明实施例提供的另一种阵列基板的剖面结构示 意图；
图 14至图 18为本发明实施例一提供的一种阵列基板的制备 方法流程图；
图 19 为完成中间介电层制备的实施例二提供的阵列基板的 剖面结构示意图；
图 20 为完成像素电极制备的实施例二提供的阵列基板的剖 面结构示意图。 具体实施方式
本发明实施例提供了一种阵列基板及其制备方法和显示面 板， 用以解决现有技术中工艺复杂、 成本高、 耗时长的问题， 同 时达到增大存储电容的目的。
下面将结合本发明实施例中的附图， 对本发明实施例中的技 术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本 发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施 例， 本领域普通技术人员在没有做出创造性劳动前提下所获得的 所有其他实施例， 都属于本发明保护的范围。
本发明提供了一种阵列基板， 包括衬底基板以及设置在所述 衬底基板上的数据线和扫描线， 所述数据线和所述扫描线围成多 个像素区域， 所述像素区域内设置有薄膜晶体管、 公共电极及公 共电极线， 所述薄膜晶体管包括栅电极、 源电极、 漏电极和有源 层， 所述栅电极设置在所述有源层的上方， 所述源电极和所述漏 电极分别设在所述有源层的相对两侧， 所述数据线和所述公共电 极线同层设置在所述衬底基板上， 且位于所述有源层下方， 所述 数据线和所述公共电极线相隔设置， 所述公共电极上设置有连接 区， 所述连接区在正投影方向上至少部分与公共电极线重叠， 所 述公共电极与公共电极线通过位于连接区与公共电极线之间的第 一过孔实现电连接。
其中， 同层设置的数据线和公共电极线可以采用相同的导电 材料。
其中， 所述有源层采用低温多晶硅材料， 所述源电极和所述 漏电极采用离子注入的方式形成在所述有源层的相对两侧， 所述 公共电极线形成在漏电极的下方。
进一步的， 所述阵列基板还包括緩冲层， 所述緩冲层设置在 所述有源层的下方以及所述衬底基板的上方， 所述数据线和所述 公共电极线被所述緩冲层覆盖。 当然， 緩冲层的设置位置可以不 限于此， 例如设置在基板上方且数据线和公共电极线的下方。
进一步的， 所述阵列基板还包括栅绝缘层， 所述栅绝缘层设 置在所述有源层的上方以及所述栅电极的下方。
进一步的， 所述阵列基板还包括设置在所述栅电极上方 的中间介电层。
其中， 所述緩冲层、 所述栅绝缘层和所述中间介电层在对应 着所述数据线的位置开设有第二过孔， 所述栅绝缘层和所述中间 介电层在对应着所述源电极的位置开设有第三过孔， 所述数据线 和所述源电极通过所述第二过孔以及所述第三过孔电连接。
进一步的， 所述阵列基板还包括设置在中间介电层上方的像 素电极， 以及设置在所述像素电极和所述公共电极之间的飩化层； 所述像素电极与所述公共电极在正投影方向上至少部分重叠； 当所述公共电极位于飩化层的上方， 所述像素电极位于飩化 层的下方时， 所述栅绝缘层、 所述中间介电层在对应着所述漏电 极的位置开设有第四过孔， 所述像素电极和所述漏电极通过所述 第四过孔电连接， 所述公共电极为狭缝状， 所述像素电极为板状 或狭缝状， 公共电极连接区与公共电极线之间的第一过孔贯穿緩 冲层、 栅绝缘层、 中间介电层和飩化层；
当所述公共电极位于飩化层的下方， 所述像素电极位于飩化 层的上方时， 所述栅绝缘层、 所述中间介电层在对应着所述漏电 极的位置开设有第四过孔， 所述飩化层在对应着所述漏电极的位 置开设有第五过孔， 所述像素电极和所述漏电极通过所述第四过 孔和第五过孔电连接， 所述公共电极为板状或狭缝状， 所述像素 电极为狭缝状， 所述公共电极连接区与公共电极线之间的第一过 孔贯穿緩冲层、 栅绝缘层和中间介电层。
进一步的， 所述阵列基板中还包括遮光金属层， 所述遮光金 属层与所述数据线和公共电极线同层设置在所述衬底基板上， 所 述遮光金属层设置在所述有源层下方， 且在正投影方向上与所述 有源层至少部分重叠。
并且， 所述遮光金属层设置在所述源电极和所述漏电极对应 的区域之间， 且在正投影方向上与所述栅电极至少部分重叠。
进一步的， 所述有源层中还设置有轻掺杂漏电极， 所述轻掺 杂漏电极设置在所述源电极和所述漏电极之间， 且分布在所述栅 电极对应的区 i或的两侧。
本发明实施例一提供了一种阵列基板， 参见图 11 和图 12, 图 11为本发明实施例一提供的阵列基板的剖面结构示意图，图 12 为图 11所示阵列基板的平面结构示意图； 结合图 11和图 12, 可 以看出所述阵列基板包括： 衬底基板 101、 公共电极线 201、 数据 线 107、 緩冲层 102、 有源层 103、 漏电极 104、 源电极 105、 栅电 极 106、 公共电极 108、 像素电极 109, 与数据线 107交叉设置的 扫描线 110, 位于有源层 103与栅电极 106之间的栅绝缘层 111 , 位于栅电极 106与公共电极 108之间的中间介电层 112,位于公共 电极 108与像素电极 109之间的飩化层 114,以及设置在公共电极 上的连接区 115。
具体的， 所述公共电极线 201与数据线 107同层设置， 位于 所述衬底基板 101与緩冲层 102之间； 并且， 所述公共电极线 201 与数据线 107的材料相同； 此外， 所述公共电极线 201与数据线 107可以在同一次构图工艺形成。
所述緩冲层 102位于公共电极线 201与数据线 107的上方、 有源层 103的下方， 并且所述緩冲层 102覆盖位于其下方的所述 数据线 107和所述公共电极线 201;
本实施例中， 所述緩冲层 102用于阻挡后续工艺中衬底基板 中所含的杂质扩散进入薄膜晶体管的有源层 103,防止对薄膜晶体 管的阔值电压和漏电流等特性产生影响， 同时， 由于所述有源层
103采用低温多晶硅材料，而低温多晶硅通常是用准分子激光退火 的方法形成， 因此，设置该緩冲层 102能够在后续制作有源层 103 的工艺中起到防止准分子激光退火造成的杂质的扩散， 提高低温 多晶硅形成薄膜晶体管的质量。
所述有源层 103位于所述緩冲层 102的上方、 所述栅绝缘层 111的下方， 所述有源层 103采用低温多晶硅材料。
所述漏电极 104与源电极 105分别位于所述有源层 103的相 对两侧， 所述漏电极 104与所述源电极 105采用离子注入的方式 形成。
所述栅电极 106与扫描线 110同层设置， 位于栅绝缘层 111 与中间介电层 112之间； 并且， 所述栅电极 106的制作材料与扫 描线 110的制作材料相同， 二者可以利用同一次构图工艺形成。
所述公共电极 108位于中间介电层 112的上方、 飩化层 114 的下方， 所述公共电极 108 的制作材料可以为氧化铟锡等透明导 电材料， 且所述公共电极 108为板状或狭缝状。
所述连接区 115, 与所述公共电极 108 同层设置， 采用相同 的透明导电材料，且其在正投影方向上至少部分与公共电极线 201 重叠。
所述像素电极 109, 位于飩化层 114的上方， 其制作材料可 以为氧化铟锡等透明导电材料， 且所述像素电极 109的形状为狭 缝状。 所述像素电极 109与所述公共电极 108在正投影方向上至 少部分重叠。
所述阵列基板中还包括第一过孔 401、 第二过孔 402、 第三过 孔 403、 第四过孔 404和第五过孔 405;
具体的， 所述第一过孔 401 用于依次贯穿所述中间介电层 112、 栅绝缘层 111和緩冲层 102, 使得公共电极线 201与公共电 极 108电连接， 并向公共电极 108提供公共电压信号；
所述第二过孔 402设置在所述緩冲层 102、所述栅绝缘层 111 和所述中间介电层 112与所述数据线 107相对应的位置； 所述第三过孔 403设置在所述栅绝缘层 111和所述中间介电 层 112与所述源电极 105相对应的位置， 使得所述源电极 105与 所述数据线 107通过所述第二过孔 402和所述第三过孔 403电连 接；
所述第四过孔 404设置在所述栅绝缘层 111、 所述中间介电 层 112与所述漏电极 104相对应的位置；
所述第五过孔 405,设置在所述飩化层 114与所述漏电极 104 相对应的位置， 使得所述漏电极 104与所述像素电极 109通过所 述第四过孔 404和所述第五过孔 405电连接。
所述第一过孔 401、 第二过孔 402、 第三过孔 403和第四过孔
404中填充有用于制作公共电极 108的透明导电材料，所述第五过 孔 405中填充有用于制作像素电极 109的透明导电材料。
本实施例中， 所述阵列基板还包括遮光金属层 116, 所述遮 光金属层 116与所述数据线 107和公共电极线 201 同层设置在所 述衬底基板 101的上方， 所述遮光金属层 116设置在所述有源层
103的下方， 且在正投影方向上与所述有源层 103至少部分重叠； 并且， 所述遮光金属层 116设置在所述源电极 105和所述漏电极 104对应的区域之间，且在正投影方向上与所述栅电极 106至少部 分重叠。 所述金属遮光层 116, 用于遮住有源层 103的沟道区域， 使得照射到有源层 103 的部分光线能够被遮住， 进而降低有源层
103的漏电流； 当然， 遮光金属层 116也可以与有源层 103完全重 叠， 这样， 遮光金属层就将有源层 103 完全遮住， 从而使照射到 有源层 103 的光线全部被遮住， 能够更进一步地降低有源层的漏 电流。
其中， 遮光金属层 116、 公共电极线 201和数据线 107采用 相同的导电材料，使得设置在同一层中的遮光金属层 116、公共电 极线 201和数据线 107可以通过一次构图工艺同时形成； 且由于 该导电材料为不透光导电材料， 所以遮光金属层 116 同时起到遮 住照射到有源层 103 的部分光线， 从而降低薄膜晶体管的漏电流 的作用。 本实施例提供的阵列基板中， 还包括设置在有源层 103 中的 轻掺杂漏极 117,所述轻掺杂漏极 117位于所述漏电极 104和源电 极 105之间， 且分布在栅电极 106对应的区域的两侧， 本实施例 中， 轻掺杂漏极 117 能够同时起到降低薄膜晶体管的漏电流的作 用。
其中， 所述栅电极 106至少为一个， 遮光金属层 116至少为 一片； 本实施例中， 设置有两个栅电极 106, 栅电极设置为两个可 以同时起到减少薄膜晶体管的漏电流的作用； 遮光金属层 116为 两片。
需要说明的是， 在中间介电层 112以及公共电极 108之间还 可以设置平坦层， 所述平坦层能使得中间介电层 112保持平坦； 当然， 所述中间介电层 112以及公共电极 108之间也可以不设置 平坦层， 如本实施例所述， 使得阵列基板的厚度相对较薄。
本发明实施例二还提供了另一种阵列基板， 其剖面结构如图 13所示， 从图 13中可以看出， 该阵列基板和图 12所示的阵列基 板的结构基本相同， 两者的区别之处在于： 一、 图 12所示的阵列 基板中， 像素电极 109位于飩化层 114的上方、 公共电极 108位 于飩化层 114的下方， 而图 13所示的阵列基板中， 像素电极 109 位于飩化层 114的下方、 公共电极 108位于飩化层 114的上方； 二、 图 13 所示的阵列基板中不需要设置第五过孔； 三， 在图 12 所示的阵列基板中， 用于连接公共电极和公共电极线的第一过孔 依次贯穿中间介电层 112、栅绝缘层 111和緩冲层 102, 而在图 13 所示的阵列基板中， 用于连接公共电极和公共电极线的第一过孔 401依次贯穿飩化层 114、 中间介电层 112、 栅绝缘层 111和緩冲 层 102, 本发明实施例二提供的阵列基板中结构更加筒单， 进一步 筒化了制作流程， 缩短了生产时间， 降低了生产成本。
本发明实施例三提供的一种阵列基板的制备方法， 该方法包 括形成数据线、 扫描线、 公共电极和公共电极线的步骤和形成薄 膜晶体管的步骤， 形成所述薄膜晶体管包括形成栅电极、 源电极、 漏电极和有源层的步骤， 所述公共电极、 公共电极线和薄膜晶体 管均形成在由所述扫描线和所述数据线围成的多个像素区域内， 其中， 所述数据线和所述公共电极线同层形成在衬底基板上， 且 在所述有源层下方， 所述公共电极上同层形成有连接区， 所述连 接区在正投影方向上至少部分与公共电极线重叠， 所述公共电极 与公共电极线通过形成在连接区与公共电极线之间的第一过孔实 现电连接。
实际制备工艺中， 所述阵列基板的制备方法具体包括： 第一步： 在所述衬底基板上采用构图工艺同时形成包括所述 数据线、 公共电极线的图形， 所述数据线和所述公共电极线相隔 设置；
第二步： 在完成第一步的衬底基板上形成緩冲层和包括有源 层的图形； 所述緩冲层覆盖所述公共电极线和所述数据线， 所述 包括有源层的图形形成在所述緩冲层上；
第三步： 在完成第二步的基板上形成栅绝缘层和包括所述栅 电极的图形；
第四步： 在完成第三步的衬底基板上形成所述源电极和所述 漏电极， 所述源电极和所述漏电极采用离子注入方式形成在所述 有源层的相对两侧；
第五步： 在完成第四步的衬底基板上形成中间介电层以及包 括第一过孔、 第二过孔、 第三过孔以及第四过孔的图形， 其中： 所述第一过孔形成在所述连接区与所述公共电极线之间， 贯穿所 述緩冲层、 栅绝缘层、 中间介电层， 所述第二过孔形成在对应着 所述数据线的位置并贯穿所述緩冲层、 栅绝缘层和中间介电层， 所述第三过孔形成在对应着所述源电极的位置并贯穿所述栅绝缘 层和中间介电层， 所述第四过孔形成在对应着所述漏电极的位置 并贯穿所述栅绝缘层和中间介电层；
第六步： 在完成第五步的衬底基板上形成包括所述公共电极 和连接区的图形， 所述第一过孔、 第二过孔、 第三过孔和第四过 孔中同时填充有用于形成所述公共电极的导电材料， 所述连接区 与所述公共电极线通过所述第一过孔电连接， 所述数据线与所述 源电极通过所述第二过孔和所述第三过孔电连接； 第七步： 在完成第六步的衬底基板上形成所述飩化层以及在 所述飩化层中形成包括第五过孔的图形， 所述第五过孔形成在对 应着所述漏电极的位置， 且所述第五过孔的位置与所述第四过孔 的位置相对应；
第八步： 在完成第七步的衬底基板上形成包括像素电极的图 形， 所述第五过孔中填充有用于形成所述像素电极的导电材料， 所述像素电极与所述漏电极通过所述第四过孔和所述第五过孔电 连接。
上述第五步至第八步中所述的方法， 适用于所述公共电极位 于所述像素电极下方的阵列基板。 而对于所述公共电极位于所述 像素电极上方的阵列基板中， 所述制备方法还包括形成公共电极、 连接区和像素电极的步骤：
第五步： 在完成第四步的衬底基板上形成中间介电层以及包 括第二过孔、 第三过孔以及第四过孔的图形， 其中： 所述第二过 孔形成在对应着所述数据线的位置并贯穿所述緩冲层、 所述栅绝 缘层和所述中间介电层， 所述第三过孔形成在对应着所述源电极 的位置并贯穿所述栅绝缘层和所述中间介电层， 所述第四过孔形 成在对应着所述漏电极的位置并贯穿所述栅绝缘层和所述中间介 电层；
第六步： 在完成第五步的衬底基板上形成包括所述像素电极 的图形， 所述第二过孔、 第三过孔和第四过孔中同时填充有用于 形成所述像素电极的导电材料， 所述数据线与所述源电极通过所 述第二过孔以及所述第三过孔电连接， 所述像素电极与所述漏电 极通过所述第四过孔电连接；
第七步：在完成第六步的衬底基板上形成所述飩化层以及包 括公共电极和连接区的图形， 所述飩化层完全覆盖所述像素电极， 所述包括公共电极和连接区的图形形成在所述飩化层的上方， 以 及形成所述连接区与所述公共电极线之间的第一过孔， 所述第一 过孔贯穿所述緩冲层、 栅绝缘层、 中间介电层和飩化层。 其中， 所述第四步还进一步包括： 采用离子注入方式在所述 有源层中形成轻掺杂漏电极， 所述轻掺杂漏电极形成在所述源电 极和所述漏电极之间， 且分布在所述栅电极对应的区域的两侧； 所述轻掺杂漏电极同时起到降低薄膜晶体管的漏电流的作用。
进一步的， 所述第一步还进一步包括： 在衬底基板上形成遮 光金属层， 所述遮光金属层与所述数据线和公共电极线同层形成， 所述遮光金属层形成在所述有源层下方， 且在正投影方向上与所 述有源层至少部分重叠。
例如， 所述第一步中形成的所述遮光金属层为至少一片， 在 第三步中形成的所述栅电极为至少一个； 所述遮光金属层与所述 栅电极位置对应形成， 用于减少薄膜晶体管的漏电流。
下面结合附图， 详细介绍本发明实施例三提供的阵列基板的 制备方法， 以本发明实施例一提供的阵列基板的结构为例， 所述 阵列基板的制备方法具体包括：
第一步， 参见图 14, 在衬底基板 101上沉积一层金属薄膜， 然后通过第一次构图工艺处理，形成包含数据线 107、遮光金属层 116和公共电极线 201的图形， 所述数据线 107、 遮光金属层 116 和公共电极线 201相隔设置。
在本发明中， 构图工艺， 可只包括光刻工艺， 或， 包括光刻 工艺以及刻蚀步骤， 同时还可以包括打印、 喷墨等其他用于形成 预定图形的工艺； 光刻工艺， 是指包括成膜、 曝光、 显影等工艺 过程的利用光刻胶、 掩模板、 曝光机等形成图形的工艺。 可根据 本发明中所形成的结构选择相应的构图工艺。
在本实施例中， 所述构图工艺包括： 首先， 在衬底基板 101 上形成（如溅射或涂覆等）一层用于形成数据线 107、 遮光金属层 116和公共电极线 201的金属薄膜； 接着，在金属薄膜上涂覆一层 光刻胶； 然后， 用设置有包括数据线 107、 遮光金属层 116和公共 电极线 201 的图形的掩模板对光刻胶进行曝光； 最后经显影、 刻 蚀后形成包括数据线 107、遮光金属层 116和公共电极线 201的图 形。 本实施例阵列基板的制备方法中， 涉及到通过构图工艺形成 的膜层的制备工艺与此相同， 此后不再详细赘述。
第二步， 参见图 15, 在完成第一步的衬底基板上通过等离子 体增强化学气相沉积法沉积二氧化硅或氮化硅层， 形成緩冲层 102, 所述緩冲层 102覆盖数据线 107、 遮光金属层 116和公共电 极线 201。
第三步， 参见图 15, 在完成第二步的衬底基板上， 通过等离 子体增强化学气相沉积法或其他类似方法， 在緩冲层 102的上方 形成非晶硅薄膜层， 然后通过激光退火工艺或固相结晶工艺等工 艺过程， 使得非晶硅结晶化， 形成多晶硅薄膜层， 并通过第二次 构图工艺处理形成包含低温多晶硅有源层 103 的图形； 所述有源 层 103的图形形成在所述緩冲层 102上， 且所述有源层 103的图 形在正投影方向上与所述公共电极 201重叠。
第四步， 参见图 16, 在完成第三步的衬底基板上沉积氮化硅 ( SiNx ) 或氧化硅 ( SiOx )层， 形成栅绝缘层 111 , 所述栅绝缘 层 111设置在所述有源层 103的上方以及栅电极 106的下方。
第五步，参见图 16,在完成第四步的衬底基板上沉积钼（ Mo )、 铝 （A1 ) 或镉 （Cr ) 等金属层， 然后通过第三次构图工艺处理， 形成栅电极 106和扫描线；
第六步， 参见图 16, 在完成第五步的衬底基板上， 采用离子 注入方式对有源层的相对两侧进行重掺杂， 形成漏电极 104和源 电极 105,并对位于源电极 105和漏电极 104之间的部分有源层区 域进行轻掺杂， 形成轻掺杂漏极 117, 所述轻掺杂漏极 117形成在 漏电极 104和源电极 105之间， 且分布在栅电极 106对应的区域 的两侧。
第七步， 参见图 17, 在完成第六步的衬底基板上沉积氮化硅
( SiNx ) 或氧化硅（SiOx )层， 形成中间介电层 112; 并通过第 四次构图工艺， 形成第一过孔 401、 第二过孔 402、 第三过孔 403 和第四过孔 404;
其中， 所述第一过孔 401形成在所述连接区 115与所述公共 电极线 201之间， 贯穿所述緩冲层 102、 栅绝缘层 111、 中间介电 层 112, 所述第二过孔 402设置在所述緩冲层 102、 所述栅绝缘层 111和所述中间介电层 112中与所述数据线 107相对应的位置；所 述第三过孔 403设置在所述栅绝缘层 111和所述中间介电层 112 中与所述源电极 105相对应的位置， 使得所述源电极 105与所述 数据线 107通过所述第二过孔 402和所述第三过孔 403电连接； 所述第四过孔 404设置在所述栅绝缘层 111和所述中间介电层 112 中与所述漏电极 104相对应的位置。
第八步， 参见图 17, 在完成第七步的衬底基板上， 使用磁控 溅射法在中间介电层 112上沉积一层氧化铟锡 ITO透明导电薄膜， 并通过第五次构图工艺， 形成公共电极 108和连接区 115; 所述第 一过孔 401、 第二过孔 402、 第三过孔 403和第四过孔 404中同时 填充有用于形成所述公共电极 108 的导电材料， 所述连接区 115 通过所述第一过孔 401与公共电极线 201电连接，所述数据线 107 与所述源电极 105通过所述第二过孔 402和所述第三过孔 403电 连接。
第九步， 参见图 18, 在完成第八步的衬底基板上形成飩化层 114,并通过第六次构图工艺形成第五过孔 405,所述第五过孔 405 贯穿所述飩化层 114、与漏电极 104相对应， 用于使得像素电极与 所述漏极 104通过所述第四过孔 404与所述第五过孔 405电连接。
第十步， 参见图 12, 在完成第九步的衬底基板上， 使用磁控 溅射法在飩化层 114上沉积一层氧化铟锡 ITO透明导电薄膜， 通 过第七次构图工艺， 即经涂覆光刻胶并曝光显影后， 再进行湿刻、 剥离后， 形成包括像素电极 109的图形； 所述第五过孔 405中填 充有用于形成所述像素电极 109 的导电材料， 所述像素电极 109 通过所述第四过孔 404和第五过孔 405与漏电极 104电连接。
经过上述步骤， 即形成本发明实施例一提供的、 结构如图 12 所示的阵列基板。
对于本发明实施例二提供的阵列基板，其制备方法具体包括： 第一步， 参见图 14, 在衬底基板 101上沉积一层金属薄膜， 然后通过第一次构图工艺处理，形成包含数据线 107、遮光金属层 116和公共电极线 201的图形， 所述数据线 107、 遮光金属层 116 和公共电极线 201相隔设置。
第二步， 参见图 15, 在完成第一步的衬底基板上形成緩冲层 102, 所述緩冲层 102完全覆盖数据线 107、 遮光金属层 116和公 共电极线 201。
第三步， 参见图 15, 在完成第二步的衬底基板上， 通过第二 次构图工艺处理形成包含低温多晶硅有源层 103 的图形； 所述有 源层 103的图形形成在所述緩冲层 102上， 且所述有源层 103的 图形在正投影方向上与所述公共电极 201重叠。
第四步， 参见图 16, 在完成第三步的衬底基板上沉积氮化硅 ( SiNx ) 或氧化硅 ( SiOx )层， 形成栅绝缘层 111 , 所述栅绝缘 层 111设置在所述有源层 103的上方以及所述栅电极的下方。
第五步，参见图 16,在完成第四步的衬底基板上沉积钼（ Mo )、 铝 （A1 ) 或镉 （Cr ) 等金属层， 然后通过第三次构图工艺处理， 形成栅电极 106和扫描线；
第六步， 参见图 16, 在完成第五步的衬底基板上， 采用离子 注入方式对有源层的相对两侧进行重掺杂， 形成漏电极 104和源 电极 105,并对位于源电极 105和漏电极 104之间的部分有源层区 域进行轻掺杂， 形成轻掺杂漏极 117, 所述轻掺杂漏极 117形成在 漏电极 104和源电极 105之间， 且分布在栅电极 106对应的区域 的两侧。
第七步， 参见图 19, 在完成第六步的衬底基板上沉积氮化硅 ( SiNx ) 或氧化硅（SiOx )层， 形成中间介电层 112; 并通过第 四次构图工艺，形成第二过孔 402、第三过孔 403和第四过孔 404; 其中， 所述第二过孔 402设置在所述緩冲层 102、 所述栅绝 缘层 111和所述中间介电层 112与所述数据线 107相对应的位置； 所述第三过孔 403设置在所述栅绝缘层 111和所述中间介电层 112 与所述源电极 105相对应的位置， 使得所述源电极 105与所述数 据线 107通过所述第二过孔 402和所述第三过孔 403电连接； 所 述第四过孔 404设置在所述栅绝缘层 111和所述中间介电层 112 与所述漏电极 104相对应的位置。
第八步， 参见图 20, 在完成第七步的衬底基板上， 使用磁控 溅射法在中间介电层 112上沉积一层氧化铟锡（ ITO )透明导电薄 膜，并通过第五次构图工艺形成像素电极 109,所述第二过孔 402、 第三过孔 403和第四过孔 404中同时填充有用于形成所述像素电 极的透明导电材料， 所述像素电极 109通过所述第四过孔 404与 漏极 104电连接。
第九步， 参见图 13 , 在完成第八步的衬底基板上形成飩化层 114,并通过第六次构图工艺形成第一过孔 401 ,所述第一过孔 401 贯穿所述飩化层 114、中间介电层 112、栅绝缘层 111和緩冲层 102, 用于通过所述第一过孔 401使得公共电极的连接区 115与公共电 极线 201电连接。
第十步， 参见图 13, 在完成第九步的衬底基板上， 使用磁控 溅射法在飩化层 114上沉积一层氧化铟锡 ITO透明导电薄膜， 通 过第七次构图工艺， 即经涂覆光刻胶并曝光显影后， 再进行湿刻、 剥离后， 形成包含公共电极 108和连接区 115的图形， 所述第一 过孔 401 中填充有用于制作所述公共电极 108的透明导电材料， 公共电极 108和公共电极线 201通过所述第一过孔 401电连接。
经过上述步骤， 即形成本发明实施例二提供的、 结构如图 13 所示的阵列基板。 需要说明的是， 上述各个步骤可按照上述的描 述的顺序执行， 也可根据需要变更顺序， 按照其他顺序执行。
综上所述， 本发明实施例提供的阵列基板中， 通过在緩冲层 和衬底基板之间设置公共电极线， 使得所述公共电极线与位于其 上方的像素电极共同形成存储电容， 从而达到增大存储电容的目 的； 并且， 由于所述公共电极线与数据线和遮光金属层同层设置， 经过一次曝光工艺即可形成所述公共电极线、 数据线和遮光金属 层， 减少了制作流程， 筒化了制作工艺， 同时还达到了节省制作 成本、 缩短了制作时间的目的。
显然， 本领域的技术人员可以对本发明进行各种改动和变型 而不脱离本发明的精神和范围。 这样， 倘若本发明的这些修改和 变型属于本发明权利要求及其等同技术的范围之内， 则本发明也 意图包含这些改动和变型在内。 。

Claims

权利要求书
1. 一种阵列基板， 包括衬底基板以及设置在所述衬底基板 上的数据线和扫描线，所述数据线和所述扫描线围成多个像素区 域，所述像素区域内设置有薄膜晶体管、公共电极及公共电极线， 所述薄膜晶体管包括栅电极、 源电极、 漏电极和有源层， 所述栅 电极设置在所述有源层的上方，所述源电极和所述漏电极分别设 在所述有源层的相对两侧， 其特征在于， 所述数据线和所述公共 电极线同层设置在所述衬底基板上， 且位于所述有源层下方， 所 述数据线和所述公共电极线相隔设置，所述公共电极上设置有连 接区， 所述连接区在正投影方向上至少部分与公共电极线重叠， 所述公共电极与公共电极线通过位于连接区与公共电极线之间 的第一过孔实现电连接。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 所述数据 线和所述公共电极线采用相同的导电材料制成。
3. 根据权利要求 1所述的阵列基板， 其特征在于， 所述有源 层采用低温多晶硅材料制成， 所述源电极和所述漏电极采用离子 注入的方式形成在所述有源层的相对两侧， 所述公共电极线形成 在所述漏电极的下方。
4. 根据权利要求 3所述的阵列基板， 其特征在于， 所述阵列 基板还包括緩冲层， 所述緩冲层设置在所述有源层的下方以及所 述衬底基板的上方， 所述数据线和所述公共电极线被所述緩冲层 覆盖。
5. 根据权利要求 4所述的阵列基板， 其特征在于， 所述阵列 基板还包括栅绝缘层， 所述栅绝缘层设置在所述有源层的上方以 及所述栅电极的下方。
6. 根据权利要求 5所述的阵列基板， 其特征在于， 所述阵列 基板还包括设置在所述栅电极上方的中间介电层。
7. 根据权利要求 6所述的阵列基板， 其特征在于， 所述緩冲 层、 所述栅绝缘层和所述中间介电层在对应着所述数据线的位置 开设有第二过孔， 所述栅绝缘层和所述中间介电层在对应着所述 源电极的位置开设有第三过孔， 所述数据线和所述源电极通过所 述第二过孔以及所述第三过孔电连接。
8. 根据权利要求 7所述的阵列基板， 其特征在于， 所述阵列 基板还包括设置在中间介电层上方的像素电极， 以及设置在所述 像素电极和所述公共电极之间的飩化层； 所述像素电极与所述公 共电极在正投影方向上至少部分重叠；
所述公共电极位于飩化层的上方， 所述像素电极位于飩化层 的下方， 所述栅绝缘层、 所述中间介电层在对应着所述漏电极的 位置开设有第四过孔， 所述像素电极和所述漏电极通过所述第四 过孔电连接， 所述公共电极为狭缝状， 所述像素电极为板状或狭 缝状， 连接区与公共电极线之间的第一过孔贯穿緩冲层、 栅绝缘 层、 中间介电层和飩化层； 或者， 所述公共电极位于飩化层的下 方， 所述像素电极位于飩化层的上方， 所述栅绝缘层、 所述中间 介电层在对应着所述漏电极的位置开设有第四过孔， 所述飩化层 在对应着所述漏电极的位置开设有第五过孔， 所述像素电极和所 述漏电极通过所述第四过孔和第五过孔电连接， 所述公共电极为 板状或狭缝状， 所述像素电极为狭缝状， 所述连接区与公共电极 线之间的第一过孔贯穿緩冲层、 栅绝缘层和中间介电层。
9. 根据权利要求 6所述的阵列基板， 其特征在于， 所述阵列 基板中还包括遮光金属层， 所述遮光金属层与所述数据线和公共 电极线同层设置在所述衬底基板上， 所述遮光金属层设置在所述 有源层下方， 且在正投影方向上与所述有源层至少部分重叠。
10. 根据权利要求 9所述的阵列基板， 其特征在于， 所述遮 光金属层设置在与所述源电极和所述漏电极对应的区域之间， 且 在正投影方向上与所述栅电极至少部分重叠。
11. 根据权利要求 1所述的阵列基板， 其特征在于， 所述有 源层中还设置有轻掺杂漏电极， 所述轻掺杂漏电极设置在所述源 电极和所述漏电极之间， 且分布在与所述栅电极对应的区域的两 侧。
12. 一种显示装置， 其特征在于， 所述显示装置包括权利要 求 1至 11中任一项所述的阵列基板。
13. 一种阵列基板的制备方法， 包括形成数据线、 扫描线、 公共电极和公共电极线的步骤和形成薄膜晶体管的步骤， 形成所 述薄膜晶体管包括形成栅电极、 源电极、 漏电极和有源层的步骤， 所述公共电极、 公共电极线和薄膜晶体管均形成在由所述扫描线 和所述数据线围成的多个像素区域内， 其特征在于， 所述数据线 和所述公共电极线同层形成在衬底基板上， 且在所述有源层下方， 所述公共电极上同层形成有连接区， 所述连接区在正投影方向上 至少部分与公共电极线重叠， 所述公共电极与公共电极线通过形 成在连接区与公共电极线之间的第一过孔实现电连接。
14. 根据权利要求 13所述的阵列基板的制备方法， 其特征在 于， 所述制备方法具体包括：
在衬底基板上采用构图工艺同时形成包括所述数据线、 公共 电极线的图形， 所述数据线和所述公共电极线相隔设置；
形成緩冲层和包括有源层的图形； 所述緩冲层覆盖所述公共 电极线和所述数据线， 所述包括有源层的图形形成在所述緩冲层 上；
形成栅绝缘层和包括所述栅电极的图形； 形成所述源电极和所述漏电极的图形， 所述源电极和所述漏 电极采用离子注入方式形成在所述有源层的相对两侧。
15. 根据权利要求 14所述的阵列基板的制备方法， 其特征在 于， 所述制备方法还包括形成公共电极、 连接区和像素电极的以 下步骤：
形成中间介电层以及包括第一过孔、 第二过孔、 第三过孔以 及第四过孔的图形， 其中： 所述第一过孔形成在所述连接区与所 述公共电极线之间， 贯穿所述緩冲层、 栅绝缘层、 中间介电层， 所述第二过孔形成在对应着所述数据线的位置并贯穿所述緩冲 层、 栅绝缘层和中间介电层， 所述第三过孔形成在对应着所述源 电极的位置并贯穿所述栅绝缘层和中间介电层， 所述第四过孔形 成在对应着所述漏电极的位置并贯穿所述栅绝缘层和中间介电 层；
形成包括所述公共电极和连接区的图形， 所述第一过孔、 第 二过孔、 第三过孔和第四过孔中同时填充有用于形成所述公共电 极的导电材料， 所述连接区与所述公共电极线通过所述第一过孔 电连接， 所述数据线与所述源电极通过所述第二过孔和所述第三 过孔电连接；
形成所述飩化层以及在所述飩化层中形成包括第五过孔的图 形， 所述第五过孔形成在对应着所述漏电极的位置， 且所述第五 过孔的位置与所述第四过孔的位置相对应；
形成包括像素电极的图形， 所述第五过孔中填充有用于形成 所述像素电极的导电材料， 所述像素电极与所述漏电极通过所述 第四过孔和所述第五过孔电连接。
16. 根据权利要求 14所述的阵列基板的制备方法， 其特征在 于， 所述制备方法还包括形成公共电极、 连接区和像素电极的以 下步骤：
形成中间介电层以及包括第二过孔、 第三过孔以及第四过孔 的图形， 其中： 所述第二过孔形成在对应着所述数据线的位置并 贯穿所述緩冲层、 所述栅绝缘层和所述中间介电层， 所述第三过 孔形成在对应着所述源电极的位置并贯穿所述栅绝缘层和所述中 间介电层， 所述第四过孔形成在对应着所述漏电极的位置并贯穿 所述栅绝缘层和所述中间介电层；
形成包括所述像素电极的图形， 所述第二过孔、 第三过孔和 第四过孔中同时填充有用于形成所述像素电极的导电材料， 所述 数据线与所述源电极通过所述第二过孔以及所述第三过孔电连 接， 所述像素电极与所述漏电极通过所述第四过孔电连接；
形成所述飩化层以及包括所述公共电极和连接区的图形， 所 述飩化层覆盖所述像素电极， 包括所述公共电极和连接区的图形 形成在所述飩化层的上方， 以及形成所述连接区与所述公共电极 线之间的第一过孔， 所述第一过孔贯穿所述緩冲层、 栅绝缘层、 中间介电层和飩化层。
17. 根据权利要求 14至 16中任一项所述的阵列基板的制备 方法， 其特征在于， 所述形成源电极和所述漏电极的步骤还包括： 采用离子注入方式在所述有源层中形成轻掺杂漏电极， 所述轻掺 杂漏电极形成在所述源电极和所述漏电极之间， 且分布在所述栅 电极对应的区 i或的两侧。
18. 根据权利要求 14至 16中任一项所述的阵列基板的制备 方法， 其特征在于， 所述形成包括所述数据线、 公共电极线的图 形的步骤还包括： 在衬底基板上形成遮光金属层， 所述遮光金属 层与所述数据线和公共电极线同层形成， 所述遮光金属层形成在 所述有源层下方， 且在正投影方向上与所述有源层至少部分重叠。
19. 根据权利要求 18所述的阵列基板的制备方法， 其特征在 于， 所述形成包括所述数据线、 公共电极线的图形的步骤中形成 的所述遮光金属层为至少一片， 在形成栅绝缘层和包括所述栅电 极的图形中形成的所述栅电极为至少一个， 所述遮光金属层与所 述栅电极位置对应形成。
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US20150311232A1 (en) 2015-10-29
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