CN107490917A - 一种薄膜晶体管阵列基板及显示装置 - Google Patents

一种薄膜晶体管阵列基板及显示装置 Download PDF

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CN107490917A
CN107490917A CN201710927745.6A CN201710927745A CN107490917A CN 107490917 A CN107490917 A CN 107490917A CN 201710927745 A CN201710927745 A CN 201710927745A CN 107490917 A CN107490917 A CN 107490917A
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film transistor
thin
array base
transistor array
drain electrode
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洪光辉
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2017/107152 priority patent/WO2019061601A1/zh
Priority to US15/740,985 priority patent/US10756120B2/en
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Abstract

本发明公开了一种薄膜晶体管阵列基板及显示装置。薄膜晶体管阵列基板包括多条扫描线、数据线以及像素单元，其中，每个像素单元包括一个薄膜晶体管和和像素电极，薄膜晶体管包括栅极、源极以及漏极，栅极与扫描线电连接，源极与数据线电连接，漏极与像素电极电连接，其中，源极与数据线同层设置，漏极与源极分别设置在不同层。因此，发明能够在保证像素单元的开口率和产品良率的情况下实现显示装置的高PPI。

Description

一种薄膜晶体管阵列基板及显示装置
技术领域
本发明涉及显示技术领域，尤其是涉及一种薄膜晶体管阵列基板及显示装置。
背景技术
In_Cell，是将TP(touch panel，触控面板)功能集成在薄膜晶体管液晶显示器(TFT-LCD)中的一种面板设计方案，可以实现面板乃至整机的轻薄化。现有的In_Cell面板像素结构中，为实现In_Cell面板的高PPI(Pixels Per Inch，每英寸所拥有的像素数目)化，通常是通过牺牲像素结构的开口率或者产品的良率来实现。
发明内容
本发明主要解决的技术问题是提供一种薄膜晶体管阵列基板及显示装置，能够在保证像素单元的开口率和产品良率的情况下实现显示装置的高PPI。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种薄膜晶体管阵列基板，薄膜晶体管阵列基板包括：玻璃基板；在玻璃基板上形成的多条扫描线、与多条扫描线相交的多条数据线以及由多条扫描线和多条数据线形成的多个像素单元，其中，每个像素单元包括一个薄膜晶体管和与薄膜晶体管电连接的像素电极，其中：薄膜晶体管包括栅极、源极以及漏极，栅极与扫描线电连接，源极与数据线电连接，漏极与像素电极电连接，其中，源极与数据线同层设置，漏极与源极分别设置在不同层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，该显示装置包括薄膜晶体管阵列基板，薄膜晶体管阵列基板包括前文任一项所述的薄膜晶体管阵列基板。
本发明的有益效果是：区别于现有技术的情况，本发明提供一种薄膜晶体管阵列基板及显示装置。该薄膜晶体管阵列基板包括玻璃基板、在玻璃基板上形成的多条扫描线、与多条扫描线相交的多条数据线以及由多条扫描线和多条数据线形成的多个像素单元，其中，每个像素单元包括一个薄膜晶体管和与薄膜晶体管电连接的像素电极，薄膜晶体管包括栅极、源极以及漏极，栅极与扫描线电连接，源极与数据线电连接，漏极与像素电极电连接，其中，源极与数据线同层设置，漏极与源极分别设置在不同层。因此，本发明通过设置相同层的源极和数据线以及不同层的源极和漏极，使得通过减小相邻的两根数据线的距离来设置小尺寸的像素单元时，不会减小漏极与数据线之间的距离，即小尺寸的像素单元的设置不受到漏极的影响，因此，漏极和源极的位置和大小可往保证像素单元的开口率和产品良率的方向设置。即能够在保证像素单元的开口率和产品良率的情况下实现显示装置的高PPI。
附图说明
图1是本发明实施例提供的一种薄膜晶体管阵列基板的结构示意图；
图2是沿图1所示的像素单元的I-II线的剖面结构示意图；
图3是图1所示的薄膜晶体管阵列基板的单个像素单元的放大结构示意图；
图4是本发明实施例提供的一种显示装置的结构示意图。
具体实施方式
请一并参阅图1-图3，图1是本发明实施例提供的一种薄膜晶体管阵列基板的结构示意图，图2是沿图1所示的像素单元的I-II线的剖面结构示意图，图3是图1所示的薄膜晶体管阵列基板的单个像素单元的放大结构示意图。首先如图1所示，本实施例的薄膜晶体管阵列基板10包括玻璃基板11、在玻璃基板11上形成的多条扫描线12、与多条扫描线12相交的多条数据线13以及由多条扫描线12和多条数据线13形成的多个像素单元14。其中，每个像素单元14包括一个薄膜晶体管T和与薄膜晶体管T电连接的像素电极100。
请一并参阅图2和图3所示，本实施例中的薄膜晶体管T包括栅极G、源极S以及漏极D。其中，栅极G与扫描线12电连接，源极S与数据线13电连接，漏极D与像素电极100电连接。本实施例中，源极S与数据线13同层设置，D漏极与源极S分别设置在不同层。
因此，本实施例通过设置相同层的源极S和数据线13以及不同层的源极S和漏极D，使得通过减小相邻的两根数据线13的距离来设置小尺寸的像素单元100时，不会减小漏极D与数据线之13间的距离，即小尺寸的像素单元100的设置不受到漏极D的影响，因此，漏极D和源极S的位置和大小可往保证像素单元的开口率和产品良率的方向设置。即能够在保证像素单元100的开口率和产品良率的情况下实现显示装置的高PPI。
本实施例中，薄膜晶体管阵列基板10还包括有源层16，设置在玻璃基板11上方，栅极G设置在有源层16上方，且扫描线12和栅极G同层设置，源极S以及漏极D设置在栅极G上方，其中，漏极D设置在源极S的上方。源极S以及漏极G分别与有源层16电连接。
在其他实施例中，漏极D还可以设置在源极S和数据线13的下方或其他位置，只要其与源极S和数据线13不同层并且其可将有源层16与像素电极100进行电连接即可。
本实施例中，薄膜晶体管阵列基板10还包括第一绝缘层17、第二绝缘层18、第三绝缘层19以及第四绝缘层101。其中，第一绝缘层17设置在有源层16和栅极G之间。第二绝缘层18设置在栅极G和源极S之间，在第二绝缘层18上设置第一导通孔103，第一导通孔103穿过第一绝缘层17和第二绝缘层18并露出有源层16，源极S通过第一导通孔103与有源层16电连接。第三绝缘层19设置在源极S与漏极D之间，在第三绝缘层19上设置第二导通孔104，第二导通孔104穿过第一绝缘层17、第二绝缘层18以及第三绝缘层19并露出有源层16，漏极D通过第二导通孔104与有源层16电连接。第四绝缘层101设置在漏极D上，在第四绝缘层101上设置第三导通孔105，第三导通孔105露出漏极D，像素电极100设置在第四绝缘层101上并通过第三导通孔105与漏极D电连接。
本实施例中，栅极G、源极S和漏极D可采用三种不同的金属材质或其他导电材质形成。也可以采用相同的金属材质或其他导电材质形成。
本实施例的薄膜晶体管阵列基板10可形成触摸显示。薄膜晶体管阵列基板10还包括触控信号线15，触控信号线15与漏极D同层设置，并且触控信号线15与漏极D可采用相同的材质，可以通过同一道光罩形成，不需额外增加成本。在其他实施例中，触控信号线15与漏极D也可采用不相同的材质。
其中，触控信号线15与数据线13平行设置并位于数据线13的上方。由于触控信号线15的数量是由触控单元的数量而决定的，而触控单元的数量比像素单元的数量少，因此并不是所有的数据线13的上方都会设置触控信号线15。具体设置为：请参阅图3，像素单元Sub1、Sub2和Sub3为同一行的像素单元，并且可为分别显示不同颜色的像素单元。在同一行的像素单元中，相邻的两个像素单元100至少一个未设置有触控信号线15。如图3所示，像素单元Sub2和Sub3设置了触控信号线15，而像素单元Sub1未设置触控信号线15。在同一行的像素单元中，漏极D与触控信号线15的距离d1大于漏极D与相邻的像素单元的数据线13的距离d2，如像素单元Sub2。由于触控信号线15与数据线13平行设置，因此，漏级D与自身的像素单元Sub2的数据线13的距离d1大于漏极D与相邻的像素单元的数据线13的距离d2。或者漏极D与触控信号线15的距离d2大于漏极D与自身像素单元的数据线13的距离d1，如像素单元Sub3的设置。同理，漏级D与自身的像素单元Sub3的数据线13的距离d1小于漏极D与相邻的像素单元的数据线13的距离d2。由此可以防止漏级D与触控信号线15之间电连接，在保证像素单元正常工作的基础上尽可能的实现像素单元的小尺寸化，进而实现面板的高PPI。
值得注意的是，在未设置触控信号线15的像素单元Sub1中，其漏极D与自身的像素单元的数据线13的距离d1等于漏极D与相邻的像素单元的数据线13的距离d2。
请再参阅图2，薄膜晶体管阵列基板10还包括遮光层102，遮光层102设置在玻璃基板11和有源层16之间，遮光层102用于阻挡从玻璃基板11侧进入的光线传输到有源层16中。
因此，本实施例能够在保证像素单元100的开口率和产品良率的情况下实现显示装置的高PPI。
本发明还提供了一种显示装置，具体请参阅图4。
如图4所示，本实施例的显示装置40包括薄膜晶体管阵列基板41、彩膜基板42以及液晶层43。其中，薄膜晶体管阵列基板41和彩膜基板42相对设置，液晶层43设置在薄膜晶体管阵列基板41和彩膜基板42之间。其中，薄膜晶体管阵列基板41为前文所述的薄膜晶体管阵列基板10，在此不再赘述。
综上所述，本发明能够在保证像素单元100的开口率和产品良率的情况下实现显示装置的高PPI。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板包括：
玻璃基板；
在所述玻璃基板上形成的多条扫描线、与所述多条扫描线相交的多条数据线以及由所述多条扫描线和多条数据线形成的多个像素单元，其中，每个像素单元包括一个薄膜晶体管和与所述薄膜晶体管电连接的像素电极，其中：
所述薄膜晶体管包括栅极、源极以及漏极，所述栅极与所述扫描线电连接，所述源极与所述数据线电连接，所述漏极与所述像素电极电连接，其中，所述源极与所述数据线同层设置，所述漏极与所述源极分别设置在不同层。
2.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板还包括：
有源层，设置在所述玻璃基板上方，所述栅极设置在所述有源层上方，且所述扫描线和所述栅极同层设置，所述源极以及漏极设置在所述栅极上方，并且所述源极以及漏极分别与所述有源层电连接。
3.根据权利要求2所述的薄膜晶体管阵列基板，其特征在于，所述漏极设置在所述源极的上方。
4.根据权利要求3所述的薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板还包括：
第一绝缘层，设置在所述有源层和所述栅极之间；
第二绝缘层，设置在所述栅极和所述源极之间，在所述第二绝缘层上设置第一导通孔，所述第一导通孔穿过所述第一绝缘层和所述第二绝缘层并露出所述有源层，所述源极通过所述第一导通孔与所述有源层电连接；
第三绝缘层，设置在所述源极与所述漏极之间，在所述第三绝缘层上设置第二导通孔，所述第二导通孔穿过所述第一、第二以及第三绝缘层并露出所述有源层，所述漏极通过所述第二导通孔与所述有源层电连接；
第四绝缘层，设置在所述漏极上，在所述第四绝缘层上设置第三导通孔，所述第三导通孔露出所述漏极，所述像素电极设置在所述第四绝缘层上并通过所述第三导通孔与所述漏极电连接。
5.根据权利要求3所述的薄膜晶体管阵列基板，其特征在于，所述源极和所述漏极的材质不同。
6.根据权利要求5所述的薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板还包括触控信号线，所述触控信号线与所述漏极同层设置，并且所述触控信号线与所述漏极采用相同的材质。
7.根据权利要求6所述的薄膜晶体管阵列基板，其特征在于，所述触控信号线与所述数据线平行设置并位于所述数据线的上方，且在同一行的像素单元中，相邻的两个像素单元至少一个未设置有所述触控信号线。
8.根据权利要求7所述的薄膜晶体管阵列基板，其特征在于，在同一行的像素单元中，所述漏极与所述触控信号线的距离大于所述漏极与相邻的像素单元的数据线的距离。
9.根据权利要求2所述的薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板还包括遮光层，所述遮光层设置在所述玻璃基板和所述有源层之间，所述遮光层用于阻挡从所述玻璃基板侧进入的光线传输到所述有源层中。
10.一种显示装置，其特征在于，所述显示装置包括薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括权利要求1-9任一项所述的薄膜晶体管阵列基板。
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