CN104517896A - 一种阵列基板的掺杂方法及制造设备 - Google Patents

一种阵列基板的掺杂方法及制造设备 Download PDF

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CN104517896A
CN104517896A CN201410768331.XA CN201410768331A CN104517896A CN 104517896 A CN104517896 A CN 104517896A CN 201410768331 A CN201410768331 A CN 201410768331A CN 104517896 A CN104517896 A CN 104517896A
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pattern layer
poly
silicon pattern
mask
doped region
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CN104517896B (zh
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薛景峰
张鑫
陈归
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/426,224 priority patent/US9640569B2/en
Priority to PCT/CN2014/095383 priority patent/WO2016090689A1/zh
Publication of CN104517896A publication Critical patent/CN104517896A/zh
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Abstract

本发明公开了一种阵列基板的掺杂方法及制造设备，其方法包括：采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，基板上设有多晶硅图案层，栅极绝缘层覆盖多晶硅图案层，光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应待轻掺杂区域形成第一光阻部，对应不掺杂区域形成第二光阻部，并且，第一光阻部比第二光阻部薄；对多晶硅图案层进行一次掺杂，以一次形成该多晶硅图案层的重掺杂区域和轻掺杂区域。通过上述方式，本发明能够通过一次掺杂形成多晶硅图案层的重掺杂区域和轻掺杂区域，减少LTPS阵列基板的生产工艺。

Description

一种阵列基板的掺杂方法及制造设备
技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板的掺杂方法及制造设备。
背景技术
TFT LCD液晶显示器可分为多晶硅(Poly-Si TFT)与非晶硅(a-Si TFT)两种，而由于低温多晶硅(Low Temperature Poly-silicon；简称LTPS)液晶显示器比传统的TFT-LCD非晶硅显示器具有高分辨率、高色彩饱和度、成本低廉的优势，LTPS-TFT LCD液晶显示器成为新一代液晶显示器的主流。
而LTPS工艺较为复杂，其中一点，就是TFT的关态电流(I off)较大，为了降低I off，通常采用双栅结构(dual gate)或者轻掺杂漏区域(Lightly doped drain；简称LDD)结构，现有技术中，为了实现LDD，一般需要两次掺杂(N型重掺杂和N型轻掺杂)，例如先采用光罩进行曝光后进行一次N型重掺杂，再除去光阻，进行第二次N型轻掺杂，现有技术的两次掺杂不仅增加了制造工序，也增加了成本。
发明内容
有鉴于此，本发明提供一种阵列基板的掺杂方法及制造设备，实现一次掺杂形成多晶硅的重掺杂区域和轻掺杂区域。
为解决上述问题，本发明提供的一种阵列基板的掺杂方法包括：采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，基板上设有多晶硅图案层，栅极绝缘层覆盖多晶硅图案层，该光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应多晶硅图案层的待轻掺杂区域形成第一光阻部，对应多晶硅图案层的不掺杂区域形成第二光阻部，第一光阻部比第二光阻部薄；对多晶硅图案层进行一次掺杂，以一次形成该多晶硅图案层的重掺杂区域和轻掺杂区域。
其中，采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层的步骤包括：在基板上形成多晶硅图案层；在具有多晶硅图案层的基板上形成栅极绝缘层；在栅极绝缘层上形成栅极图案层；采用半调掩膜在具有栅极图案层的栅极绝缘层上形成光阻图案层。
其中，该半调掩膜包括对应镂空部的全透光部，对应第一光阻部的半透光部，及对应第二光阻部的不透光部；采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层包括：利用半调掩膜对光阻图案层进行曝光，在光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对三种曝光层次分别进行刻蚀，以形成对应曝光部的镂空部、对应半曝光部的第一光阻部及对应未曝光部的第二光阻部。
其中，对多晶硅图案层进行一次掺杂包括：采用扩散法或离子注入法对低温多晶硅进行掺杂，以形成多晶硅图案层，该多晶硅图案层包括重掺杂区域和轻掺杂区域。
其中，半调掩膜为半色调光罩或灰阶光罩；该半色调光罩对应所述第一光阻部的半透光部为半透光膜，半透光膜的透过率在0～100％之间；该灰阶光罩对应第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0～100％之间。
为解决上述问题，本发明提供的一种阵列基板的制造设备包括：曝光装置、半调掩膜以及掺杂装置；该曝光装置用于采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，基板上设有多晶硅图案层，栅极绝缘层覆盖多晶硅图案层，光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应多晶硅图案层的待轻掺杂区域形成第一光阻部，对应多晶硅图案层的不掺杂区域形成第二光阻部，第一光阻部比第二光阻部薄；掺杂装置用于对多晶硅图案层进行一次掺杂，以一次形成多晶硅图案层的重掺杂区域和轻掺杂区域。
其中，多晶硅图案层在基板上形成，栅极绝缘层在具有多晶硅图案层的基板上形成，栅极图案层在栅极绝缘层上形成，光阻图案层在具有栅极图案层的栅极绝缘层利用曝光装置通过半调掩膜曝光形成。
其中，半调掩膜包括对应镂空部的全透光部，对应第一光阻部的半透光部，及对应于第二光阻部的不透光部，利用曝光装置通过半调掩膜对光阻图案层进行曝光，以在光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对三种曝光层次进行刻蚀，分别形成对应曝光部的镂空部、对应半曝光部的第一光阻部及对应未曝光部的第二光阻部。
其中，多晶硅图案层通过采用扩散法或离子注入法对低温多晶硅进行掺杂形成，多晶硅图案层包括重掺杂区域和轻掺杂区域。
其中，半调掩膜为半色调光罩或灰阶光罩；其中半色调光罩对应第一光阻部的半透光部为半透光膜，半透光膜的透过率在0～100％之间；灰阶光罩对应第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0～100％之间。
通过上述方案，本发明的有益效果是：区域别于现有技术，本发明通过半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，基板上设有多晶硅图案层，栅极绝缘层覆盖该多晶硅图案层，使光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应多晶硅图案层的待轻掺杂区域形成第一光阻部，对应多晶硅图案层的不掺杂区域形成第二光阻部，并且第一光阻部比所述第二光阻部薄，对该多晶硅图案层进行一次掺杂，从而实现一次形成多晶硅图案层的重掺杂区域和轻掺杂区域，减少了LTPS的制造工艺，降低成本。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术对阵列基板两次掺杂的工艺示意图；
图2是现有技术的罩膜的透光原理示意图；
图3是本发明中阵列基板的掺杂方法第一实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第一实施方式的示意结构；
图4是图3中半调掩膜的透光原理示意图；
图5是本发明阵列基板的掺杂方法第二实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第二实施方式的示意结构；
图6是图5中半调掩膜的透光原理示意图；
图7是本发明阵列基板的掺杂方法第一实施方式的流程示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本发明一部分实施方式，而不是全部实施方式。基于本发明中的实施方式，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施方式，都属于本发明保护的范围。
请参看图1，图1是现有技术的对阵列基板两次掺杂的工艺示意图。需要说明的是，图1中所显示的制造设备放置状态、阵列基板各元件的结构及状态并非实际生产中同一时间内的同一工艺阶段出现，图1只是为了方便说明而同时显示不同工艺阶段(曝光和掺杂)下的制造设备放置的状态、阵列基板的结构及状态。如图1所示，现有技术的阵列基板的制造设备包括曝光装置10、罩膜11及掺杂装置12。这里仅是对利用该制造设备对阵列基板13进行两次掺杂工艺作说明，阵列基板13包括基板14、多晶硅图案层15、栅极绝缘层16及栅极图案层17。
罩膜11包括不透光部110及全透光部111，其中罩膜11的透光原理如图2所示，其中光强曲线20的向下凸起部200表示不透光，向上凸起部201表示透光。结合图1和图2，进一步说明现有技术的阵列基板的掺杂工艺流程。首先是在阵列基板13的基板14上形成多晶硅图层15，其中，多晶硅图层15与基板14之间还设有缓冲层19，优选的，多晶硅图层15设置在缓冲层19上；栅极绝缘层16形成在具有多晶硅图层15的基板14上，再在栅极绝缘层16上形成栅极图案层17；最后利用曝光装置10在具有栅极图案层17的栅极绝缘层16上形成光阻图案层18，其中，利用曝光装置10通过罩膜11对光阻图案层18进行曝光，使罩膜11的全透光部111在光阻图案层18上形成曝光部，不透光部110在光阻图案层18上形成未曝光部，使得光阻图案层18形成曝光部及未曝光部两种曝光层次，进而对曝光后的光阻图案层18进行显彰处理，故而在显彰后曝光部被去除，即光阻图案层18的曝光部在显彰过程中形成镂空部181，而未曝光部在显彰后形成一种厚度的光刻胶。对光阻图案层18的未曝光部形成的光刻胶进行蚀刻，使光阻图案层18的未曝光部形成光阻部180。并且，光阻图案层18的镂空部181对应多晶硅图层15的待重掺杂区域151。通过掺杂装置12对多晶硅图层15进行第一次重掺杂，使多晶硅图层15的待重掺杂区域151形成重掺杂区域。去除待掺杂区域对应的光阻，对多晶硅图层15进行第二次轻掺杂，使多晶硅图层15的待轻掺杂区域152形成轻掺杂区域。至此，通过两次掺杂工艺，使多晶硅图层15形成重掺杂区域及轻掺杂区域。
然而，现有技术通过对多晶硅图层15进行两次掺杂，以形成重掺杂区域及轻掺杂区域，工艺较为复杂，并且成本较高。本发明提出了一种只需一次掺杂形成阵列基板的制造设备，请参看图3，图3是本发明中阵列基板的掺杂方法第一实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第一实施方式的示意结构。通常阵列基板包括N型晶体管及P型晶体管，其中N型晶体管上设有沟道区域、轻掺杂区域及重掺杂区域，而P型晶体管上只有沟道区域及重掺杂区域，本实施方式是针对阵列基板的N型晶体管进行说明。
需要说明的是，图3所显示的制造设备放置状态、阵列基板各元件的结构、状态在实际中并非在同一时间内的同一工艺阶段出现，即图3是为了方便观看而同时显示不同工艺阶段(曝光和掺杂)下制造设备放置状态、阵列基板各元件的结构、状态。类似地，图5同理。如图3所示，阵列基板24的制造设备包括曝光装置21、半调掩膜22及掺杂装置23；阵列基板24包括基板25、多晶硅图案层26、栅极绝缘层27、栅极图案层28及缓冲层30。
其中，曝光装置21用于采用半调掩膜22在基板25的栅极绝缘层27上形成光阻图案层29；基板25上设有多晶硅图案层26，栅极绝缘层27覆盖多晶硅图案层26，使光阻图案层29对应多晶硅图案层26的待重掺杂区域262形成镂空部292，对应多晶硅图案层26的待轻掺杂区域261形成第一光阻部291，对应多晶硅图案层的不掺杂区域260形成第二光阻部290，并且第一光阻291部比第二光阻部290薄；掺杂装置23用于对多晶硅图案层26进行一次掺杂，以一次形成多晶硅图案层26的重掺杂区域和轻掺杂区域。
在本实施方式中，基板25为玻璃基板；多晶硅图案层26在基板25上形成，多晶硅图案层26又称为有源层，并且，在基板25与多晶硅图案层26之间还设有缓冲层30，多晶硅图案层26在基板25的缓冲层30上形成；栅极绝缘层27在具有多晶硅图案层26的基板25上形成，栅极图案层28在栅极绝缘层27上形成，其中，栅极绝缘层27是无机绝缘材料，如氧化硅SiO2或氮化硅SiNX沉积在栅极图案层28上形成，从而在基板25的整个表面上形成栅极绝缘层27；光阻图案层29在具有栅极图案层28的栅极绝缘层27上利用曝光装置21通过半调掩膜22形成。
在本实施方式中，半调掩膜22包括对应光阻图案层29的镂空部292的全透光部222、对应光阻图案层29的第一光阻部291的半透光部221及对应光阻图案层29的第二光阻部290的不透光部220，半调掩膜22的透光原理如图4所示，其中光强曲线31的第一向下凸起部310表示不透光，第二向下凸起部311表示半透光，312表示透光。
本实施方式的制造工艺如下，先是利用曝光装置21通过半调掩膜22对光阻图案层29进行曝光，由于半调掩膜22具有全透光部222、半透光部221及不透光部220的不同透光度，因而在一次曝光后在光阻图案层29上将会形成曝光部、半曝光部及未曝光部共三种曝光层次。其原理为：运用曝光装置21通过半调掩膜22的全透光部222对光阻图案层29进行曝光，形成曝光部，同时，半调掩膜22的半透光部221对光阻图案层29进行半曝光，形成半曝光部，半调掩膜22的不透光部220对光阻图案层29未曝光，形成未曝光部。
其次是对光阻图案层29进行显彰处理，在显彰处理期间，曝光部被去除而形成镂空部292，因而在显彰处理光阻图案层29上形成两种厚度的光刻胶，对光刻胶进行蚀刻，从而使半曝光部形成第一光阻部291，未曝光部形成第二光阻部290，并且，第一光阻部291比第二光阻部290薄。并且，在本实施方式中，光阻图案层29的镂空部292对应多晶硅图案层26的待重掺杂区域262，第一光阻部291对应多晶硅图案层26的待轻掺杂区域261，第二光阻部290对应多晶硅图案层26的不掺杂区域260。
由于最终形成的多晶硅图案层26包括通过一次掺杂形成的重掺杂区域和轻掺杂区域，即待重掺杂区域262经掺杂后形成重掺杂区域，同时，待轻掺杂区域261掺杂后形成轻掺区域。因此，最后的掺杂工艺为：利用掺杂装置23对多晶硅图案层26进行掺杂，其掺杂是通过采用扩散法或离子注入法对低温多晶硅进行掺杂，掺杂后使多晶硅图案层26包括重掺杂区域和轻掺杂区域。在本实施方式中，采用低压化学气相沉积方法形成多晶硅薄膜，即形成有源层(图未示)，采用离子注入法向有源层掺杂磷原子或锑原子从而形成多晶硅图案层26，而由于覆盖多晶硅图案层26的栅极绝缘层27上形成有阶梯状的光阻图案层29，因而对多晶硅图案层26掺杂磷原子或锑原子，只是需要一次掺杂，便能形成重掺杂区域和轻掺杂区域，其原理为：掺杂装置23通过光阻图案层29的镂空部292向多晶硅图案层26的待重掺杂区域262一次掺杂形成重掺杂区域，同时，通过第一光阻部291向待轻掺杂区域261掺杂形成轻掺杂区域，该多晶硅图案层26的重掺杂区域和轻掺杂区域都是在一次掺杂中形成的。此外，多晶硅图案层26的不掺杂区域260将形成沟道区域，其中，轻掺杂区域和沟道区域组成多晶硅图案层26的导电区域，在其他实施方式中，导电区域上还可以覆盖有挡光层(图未示)，以降低漏电流，改善显示质量。至此，对阵列基板24的掺杂工艺完成，只需要一次掺杂，便在多晶硅图案层26上形成重掺杂区域及轻掺杂区域。
在本实施方式中，通过曝光装置21利用半调掩膜22对光阻图案层29进行曝光、半曝光及未曝光，以形成光阻图案层29的镂空部292、第一光阻部291及第二光阻部290，是由半调掩膜22的结构决定的。
在本实施方式中，半调掩膜22为半色调光罩(Halt-tone Mask；简称HTM)，其中，半调掩膜22的半透光部221为一个半透光膜，半透光膜的透过率在0～100％之间。
区域别于现有技术，本发明的通过曝光装置21利用半调掩膜22在基板25的栅极绝缘层27上形成光阻图案层29，由于基板25上设有多晶硅图案层26，栅极绝缘层27覆盖多晶硅图案层26，而半调掩膜22包括全透光部222、半透光部221及不透光部220，半透光部221为一半透光膜，通过控制半透光膜22的透过率实现半曝光的效果，从而在光阻图案层29上形成对应多晶硅图案层26的待轻掺杂区域261的第一光阻部291，对应多晶硅图案层26的待重掺杂区域262形成镂空部292，对应多晶硅图案层26的不掺杂区域260形成第二光阻部290，从而使光阻图案层29形成包括镂空部292、第一光阻部291及第二光阻部290的阶梯状结构，利用该阶梯状结构的光阻图案层29，从而实现通过掺杂装置23对多晶硅图案层26的一次掺杂形成重掺杂区域和轻掺杂区域。
请参看图5和图6，图5是本发明阵列基板的掺杂方法第二实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第二实施方式的示意结构；图6是图5中半调掩膜的透光原理示意图。其中，图5与图3类似，也是为了方便观看而同时显示不同工艺阶段(曝光和掺杂)下制造设备放置状态、阵列基板各元件的结构、状态，并非在同一时间内的同一工艺阶段出现。图5中，制造设备包括曝光装置21、半调掩膜32及掺杂装置23，其中，曝光装置21和掺杂装置23与图3的一致，在此不再赘述。图5中，阵列基板24包括基板25、多晶硅图案层26、栅极绝缘层27、栅极图案层28及缓冲层30，它们的结构和功能与图3中的阵列基板一致，在此不再赘述。而图5的实施方式中与图3的实施方式的区别仅在于，图5的半调掩膜32为灰阶光罩(Gray-tone Mask；简称GTM)，半调掩膜32半透光部321具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0～100％之间。在其他实施方式中，半调掩膜32还可以为单夹缝掩膜(Single slit Mask；简称SSM)。
请一起参看图3和图7，图7是本发明阵列基板的掺杂方法第一实施方式的流程示意图，如图7所示，阵列基板的掺杂流程包括以下步骤：
S11：在基板25上形成多晶硅图案层26。
其中，采用低压化学气相沉积法或直接法在基板25上形成多晶硅图案层26。在其他实施方式中，多晶硅图案层26也可以采用准分子激光晶化法制成。优选的，基板25与多晶硅图案层26之间还设有缓冲层30，多晶硅图案层26设置在缓冲层30上。
其中，基板25为玻璃基板；多晶硅图案层26又称为有源层，它包括待重掺杂区域262、待轻掺杂区域261及不掺杂区域260，其中，待轻掺杂区域261掺杂后形成的轻掺杂区及不掺杂区域260形成的沟道区域组成多晶硅图案层26的导电区域，在其他实施方式中，导电区域上还可以覆盖有挡光层(图未示)，以降低漏电流，改善显示质量。
S12：在具有多晶硅图案层26的基板25上形成栅极绝缘层27。
S13:在栅极绝缘层27上形成栅极图案层28。
其中，栅极绝缘层27是无机绝缘材料，如氧化硅SiO2或氮化硅SiNX沉积在栅极图案层28上形成，从而在基板25的整个表面上形成栅极绝缘层27。
S14：采用半调掩膜22在具有栅极图案层28的栅极绝缘层27上形成光阻图案层29。
采用半调掩膜22在基板25的栅极绝缘层27上形成光阻图案层29，由于基板25上设有多晶硅图案层26，栅极绝缘层27覆盖多晶硅图案层26，使光阻图案层29对应多晶硅图案层26的待重掺杂区域262形成镂空部292，对应多晶硅图案层26的待轻掺杂区域261形成第一光阻部291，对应多晶硅图案层26的不掺杂区域260形成第二光阻部290，且第一光阻部291比第二光阻部290薄；对多晶硅图案层26进行一次掺杂，以一次形成多晶硅图案层26的重掺杂区域和轻掺杂区域。
其中，半调掩膜22包括全透光部222、半透光部221及不透光部220。在本实施方式中，通过曝光装置21利用半调掩膜22对光阻图案层29进行曝光，由于半调掩膜22具有全透光部222、半透光部221及不透光部220的不同透光度，因而在一次曝光后在光阻图案层29上将会形成曝光部、半曝光部及未曝光部共3种曝光层次。其原理是，曝光装置21通过半调掩膜22的全透光部222对光阻图案层29进行曝光，全透光部222对应的光阻图案层29的部分形成曝光部，同理，半调掩膜22的半透光部221对光阻图案层29半曝光，形成半曝光部，半调掩膜22的不透光部220对光阻图案层29未曝光，形成未曝光部。曝光后对光阻图案层29进行显彰处理，在处理期间，曝光部被去除，使光阻图案层29的曝光部对应形成镂空部292，因而在光阻图案层29上形成两种厚度的光刻胶，对光刻胶进行蚀刻，从而使半曝光部形成第一光阻部291，未曝光部形成第二光阻部290，并且，第一光阻部291比第二光阻部290薄，使光阻图案层29形成包括镂空部292、第一光阻部291及第二光阻部290的阶梯状结构。
在本实施方式中，利用曝光装置21通过半调掩膜22对光阻图案层29进行曝光，使光阻图案层29形成根据半调掩膜22的透光特性形成曝光部、半曝光部及未曝光部三种曝光层次，从而在光阻图案层29上形成相应的镂空部292、第一光阻部291及第二光阻部290，是由半调掩膜22的透光结构决定的，在本实施方式中，半调掩膜22为半色调光罩(Halt-tone Mask；简称HTM)，其半透光部221为一个半透光膜，半透光膜的透过率在0～100％之间。
此外，半调掩膜22的透光结构还可以如图5所示，半调掩膜32为灰阶光罩(Gray-tone Mask；简称GTM)，其半透光部321具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0～100％之间。在其他实施方式中，半调掩膜32还可以为单夹缝掩膜(Single slitMask；简称SSM)。
S15：去除半调掩膜22，对多晶硅图案层26一次掺杂，在多晶硅图案层26上形成重掺杂区域和轻掺杂区域。
由于阵列基板通常包括N型晶体管及P型晶体管，其中N型晶体管上设有沟道区域、轻掺杂区域及重掺杂区域，而P型晶体管上只有沟道区域及重掺杂区域，本实施方式是针对阵列基板的N型晶体管进行说明，因此在本实施方式中，通过掺杂装置23对多晶硅图案层26进行N型掺杂，其中，N型掺杂是指采用扩散法或离子注入法向多晶硅图案层26掺入磷原子或锑原子。由于多晶硅图案层26上设置有阶梯状的光阻图案层29，因而只需对多晶硅图案层26进行一次掺杂，便会在对应光阻图案层29的镂空部292的待重掺杂区域262掺杂成重掺杂区域，同时对应第一光阻部291的待轻掺杂区域261掺杂成轻掺杂区，此外，对应第二光阻部291的多晶硅图案层26的不掺杂区域260形成沟道区域，其中，轻掺杂区域和沟道区域组成多晶硅图案层26的导电区域，该多晶硅图案层26的重掺杂区域和轻掺杂区域都是在一次掺杂中形成的。在其他实施方式中，导电区域上还可以覆盖有挡光层(图未示)，以降低漏电流，改善显示质量。
综上所述，区域别于现有技术，本发明的半调掩膜具有全透光部、半透光部及不透光部，并且，基板上设有多晶硅图案层，栅极绝缘层覆盖多晶硅图案层，通过利用半调掩膜在基板的栅极绝缘层上形成光阻图案层，从而使光阻图案层形成具有对应多晶硅图案层的待重掺杂区域的镂空部，对应多晶硅图案层的待轻掺杂区域的第一光阻部，对应多晶硅图案层的不掺杂区域的第二光阻部，并且，第一光阻部比第二光阻部薄；从而在多晶硅图案层上形成有阶梯状的光阻图案层，因而对多晶硅图案层进行一次掺杂，便能在多晶硅图案层上一次形成重掺杂区域、轻掺杂区域及不掺杂的沟道区域，实现一次掺杂形成多晶硅图案层的重掺杂区域和轻掺杂区域，减少LTPS阵列基板的生产工艺，降低成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种阵列基板的掺杂方法，其特征在于，所述掺杂方法包括：
采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，所述基板上设有多晶硅图案层，所述栅极绝缘层覆盖所述多晶硅图案层，所述光阻图案层对应所述多晶硅图案层的待重掺杂区域形成镂空部，对应所述多晶硅图案层的待轻掺杂区域形成第一光阻部，对应所述多晶硅图案层的不掺杂区域形成第二光阻部，所述第一光阻部比所述第二光阻部薄；
对所述多晶硅图案层进行一次掺杂，以一次形成所述多晶硅图案层的重掺杂区域和轻掺杂区域。
2.根据权利要求1所述的掺杂方法，其特征在于，所述采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层的步骤包括：
在所述基板上形成所述多晶硅图案层；
在具有所述多晶硅图案层的基板上形成所述栅极绝缘层；
在所述栅极绝缘层上形成栅极图案层；
采用所述半调掩膜在具有所述栅极图案层的栅极绝缘层上形成所述光阻图案层。
3.根据权利要求1所述的掺杂方法，其特征在于，所述半调掩膜包括对应所述镂空部的全透光部，对应所述第一光阻部的半透光部，及对应所述第二光阻部的不透光部；
所述采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层包括：
利用所述半调掩膜对所述光阻图案层进行曝光，在所述光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对所述三种曝光层次分别进行刻蚀，以形成对应所述曝光部的所述镂空部、对应所述半曝光部的所述第一光阻部及对应所述未曝光部的所述第二光阻部。
4.根据权利要求1所述的掺杂方法，其特征在于，所述对所述多晶硅图案层进行一次掺杂包括：
采用扩散法或离子注入法对低温多晶硅进行掺杂，以形成所述多晶硅图案层，所述多晶硅图案层包括所述重掺杂区域和所述轻掺杂区域。
5.根据权利要求1至4任一项所述的掺杂方法，其特征在于，所述半调掩膜为半色调光罩或灰阶光罩；其中，所述半色调光罩对应所述第一光阻部的半透光部为半透光膜，所述半透光膜的透过率在0～100％之间；所述灰阶光罩对应所述第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝调节控制透过率在0～100％之间。
6.一种阵列基板的制造设备，其特征在于，所述制造设备包括：
曝光装置、半调掩膜以及掺杂装置；
所述曝光装置用于采用所述半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，所述基板上设有多晶硅图案层，所述栅极绝缘层覆盖所述多晶硅图案层，所述光阻图案层对应所述多晶硅图案层的待重掺杂区域形成镂空部，对应所述多晶硅图案层的待轻掺杂区域形成第一光阻部，对应所述多晶硅图案层的不掺杂区域形成第二光阻部，所述第一光阻部比所述第二光阻部薄；
所述掺杂装置用于对所述多晶硅图案层进行一次掺杂，以一次形成所述多晶硅图案层的重掺杂区域和轻掺杂区域。
7.根据权利要求6所述的制造设备，其特征在于，所述多晶硅图案层在所述基板上形成，所述栅极绝缘层在具有所述多晶硅图案层的基板上形成，所述栅极图案层在所述栅极绝缘层上形成；所述光阻图案层在具有所述栅极图案层的栅极绝缘层利用所述曝光装置通过所述半调掩膜曝光形成。
8.根据权利要求6所述的制造设备，其特征在于，所述半调掩膜包括对应所述镂空部的全透光部，对应所述第一光阻部的半透光部，及对应所述第二光阻部的不透光部，利用所述曝光装置通过所述半调掩膜对所述光阻图案层进行曝光，以在所述光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对所述三种曝光层次进行蚀刻，分别形成对应所述曝光部的所述镂空部、对应所述半曝光部的所述第一光阻部及对应所述未曝光部的所述第二光阻部。
9.根据权利要求6所述的制造设备，其特征在于，所述多晶硅图案层通过采用扩散法或离子注入法对低温多晶硅进行掺杂形成，所述多晶硅图案层包括所述重掺杂区域和所述轻掺杂区域。
10.根据权利要求6-9任一项所述的制造设备，其特征在于，所述半调掩膜为半色调光罩或灰阶光罩；其中所述半色调光罩对应所述第一光阻部的半透光部为半透光膜，所述半透光膜的透过率在0～100％之间；所述灰阶光罩对应所述第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝调节控制透过率在0～100％之间。
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