WO2018119866A1 - 一种低温多晶硅阵列基板及其制作方法 - Google Patents

一种低温多晶硅阵列基板及其制作方法 Download PDF

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WO2018119866A1
WO2018119866A1 PCT/CN2016/112991 CN2016112991W WO2018119866A1 WO 2018119866 A1 WO2018119866 A1 WO 2018119866A1 CN 2016112991 W CN2016112991 W CN 2016112991W WO 2018119866 A1 WO2018119866 A1 WO 2018119866A1
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gate
layer
source
light shielding
pattern
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PCT/CN2016/112991
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English (en)
French (fr)
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郭远
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武汉华星光电技术有限公司
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Priority to US15/327,459 priority Critical patent/US10134907B2/en
Publication of WO2018119866A1 publication Critical patent/WO2018119866A1/zh

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    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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Definitions

  • the invention belongs to the technical field of array substrate fabrication, and in particular to a low temperature polysilicon array substrate and a manufacturing method thereof.
  • LTPS Low Temperature Poly-silicon
  • the liquid crystal panel produced by the LTPS process technology is beneficial to increase the panel aperture ratio, improve the brightness of the display, and reduce the power consumption, and is suitable for producing products with thinner, lighter, lower power and high resolution.
  • the traditional LTPS process requires up to 12 processes to achieve the overall process of the array substrate compared to the thin film transistor liquid crystal display.
  • the excessive process will cause a large increase in production time and production cost, and the process is complicated. It is more prone to abnormalities in the process.
  • the present invention provides a low temperature polysilicon array substrate and a manufacturing method thereof for shortening the process of the array substrate.
  • a method for fabricating a low temperature polysilicon array substrate comprising:
  • the light shielding layer includes a light shielding pattern arranged in an array, and an extending portion is symmetrically disposed on both sides of the light shielding pattern disposed at intervals of each row in the column direction, and the light shielding pattern is arranged in the column direction
  • the same shape
  • NMOS channels Performing an N+ heavily doping process on the U-type polysilicon pattern after the channel doping process in the display region to form two NMOS channels and a source region and a drain region of the N-type dual-gate transistor.
  • the two NMOS channels each correspond to an opposite side of the U-shaped polysilicon pattern;
  • the gate insulating layer is formed on the U-type polysilicon pattern of the NMOS channel and the corresponding source and drain regions, the exposed buffer layer and the non-display region, and the first via is etched, the gate is insulated Forming a gate line, a source of the N-type double-gate transistor, and a lightly doped region, wherein a source of the N-type double-gate transistor is connected to a corresponding light-shielding pattern through the first via ;
  • a buffer layer is formed on the light shielding layer and the bare glass substrate, and a U-shaped polysilicon pattern is formed on the buffer layer, and further includes the following steps:
  • a single crystal silicon material is deposited on the buffer layer and subjected to a crystallization treatment to form the U-shaped polysilicon pattern.
  • a gate insulating layer is formed on the U-type polysilicon pattern of the NMOS channel and corresponding source and drain regions, the exposed buffer layer and the non-display region, and the first pass is etched After the hole, forming a gate line on the gate insulating layer, the source and drain of the N-type dual gate transistor, and the lightly doped region further include the following steps:
  • the N-type dual gate structure transistor is N-lightly doped to form lightly doped regions on both sides of the NMOS channel.
  • the gate lines are arranged along a row direction, and the gate lines are to be The width is set equal to the length of the NMOS channel.
  • the source of the N-type double-gate transistor is connected to the N-type double-gate transistor of the adjacent column direction through the corresponding light-shielding pattern and the other first via. Source.
  • the light shielding layer is made of a metal material.
  • the extension is disposed to be equal to a line width of a source of the N-type double gate structure transistor.
  • the opening directions of the U-shaped polysilicon patterns are set to be the same.
  • the method further includes:
  • a pixel electrode layer is formed on the passivation layer, and a drain region of the N-type double gate transistor is connected through a second via.
  • the method of the invention shortens the overall process to 10 channels without changing the structure of the thin film transistor without reducing the resolution, transmittance and performance of the product, thereby greatly shortening the production cost and the production time.
  • FIG. 1 is a flow chart of a method in accordance with one embodiment of the present invention.
  • FIG. 2a is a schematic view of a light shielding pattern according to an embodiment of the present invention.
  • FIG. 2b is a schematic view of a U-shaped polysilicon pattern according to an embodiment of the present invention.
  • 2c is a schematic diagram of a substrate after forming a source drain, in accordance with an embodiment of the present invention.
  • 2d is a schematic diagram of a low temperature polysilicon array substrate in accordance with an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method in accordance with an embodiment of the present invention, and the present invention will be described in detail below with reference to FIG.
  • a light shielding layer is formed on a glass substrate, wherein the light shielding layer includes a light shielding pattern arranged in an array, and an extension portion is symmetrically disposed on both sides of the light shielding pattern disposed at intervals of each row in the column direction, and along the edge
  • the shading pattern in the column direction has the same shape.
  • the light shielding layer is mainly used for shielding the channel region of the display region on the array substrate, so that the light shielding pattern of the light shielding layer is disposed on the display region, and the non-display region may not be disposed.
  • a metal material is usually deposited on the glass substrate, and then the metal material is further etched to form a light shielding layer.
  • the light shielding layer is disposed to include the light shielding pattern 11 and the light shielding pattern 12 arranged in an array, and the light shielding patterns 11 disposed at intervals of each row are symmetrically disposed with an extending portion 111 and 112 on both sides of the column direction, each column
  • the shape of the shading pattern is the same.
  • the row direction here is defined as the horizontal direction facing the array substrate.
  • step S102 a buffer layer is formed on the light shielding layer and the bare glass substrate, and a U-shaped polysilicon pattern is formed on the buffer layer, wherein the two pairs of U-shaped polysilicon patterns are adjacent to each other in the row direction.
  • the shading pattern is shaded.
  • a buffer material is first deposited on the light shielding layer and the bare glass substrate to form a buffer layer for shielding the device defects caused by the defects of the glass substrate itself.
  • the SiO 2 material is usually deposited by a PECVD process to form a buffer layer.
  • a single crystal silicon material is deposited on the buffer layer and subjected to crystallization treatment to form a U-type polysilicon pattern.
  • the U-type polysilicon pattern 21 can be formed by an ELA process. As shown in FIG. 2b, the two opposite sides 211 and 212 of the U-shaped polysilicon pattern 21 are shielded by two light blocking patterns adjacent in the row direction.
  • step S103 a channel doping process is performed on the U-shaped polysilicon pattern located in the display region.
  • the U-type polysilicon pattern is lightly doped with boron ions for adjusting the threshold voltage of the subsequently formed N-type channel region, and the doping process can be performed on the U-type polysilicon pattern 21 of the entire display region.
  • step S104 the U-type polysilicon pattern after the channel doping process in the display region is N+ heavily doped to form two NMOS channels and sources of the N-type double-gate transistor. Zone and drain zones.
  • the NMOS channel is shielded from light by a light blocking pattern. Specifically, as shown in FIG. 2b, an NMOS channel is formed corresponding to the light shielding pattern 11, and another NMOS channel is formed corresponding to the light shielding pattern 12, and the source region and the drain region correspond to the ends of the opposite sides of the U-shaped polysilicon pattern. .
  • a gate insulating layer is formed on the U-type polysilicon pattern of the NMOS channel and the corresponding source and drain regions, the exposed buffer layer and the non-display region, and the first via is etched.
  • a gate line, a source of the N-type double gate structure transistor, and a lightly doped region 213 are formed on the gate insulating layer, wherein the source is connected to the corresponding light shielding pattern through the first via.
  • an insulating material is deposited on the U-type polysilicon pattern of the NMOS channel and the corresponding source and drain regions, the exposed buffer layer and the non-display region to form the gate insulating layer GI.
  • a gate insulating layer is provided on the entire surface of the substrate after the end of step S105.
  • a gate insulating layer is typically formed here using a SiNx material.
  • a first via (not shown) corresponding to the corresponding light shielding pattern extensions 111 and 112 is etched on the gate insulating layer at a position corresponding to the extension portion, and then a metal material is deposited on the gate insulating layer and etched to The gate line 31 and the source 321 are formed, and the drain region of the N-type double gate structure transistor is not processed.
  • the source 321 of the N-type double-gate transistor connects the corresponding light-shielding pattern and the source region of the NMOS channel through a first via, and connects the N in the adjacent column direction through the same light-shielding pattern and the other first via.
  • Source 322 of a dual gate transistor This allows the data signal to be transmitted using a blackout pattern without the need to additionally set the data line.
  • the gate lines 31 are arranged in the row direction and are disposed to overlap the NMOS channel such that the length of the NMOS channel is equal to the width of the gate lines.
  • the U-type polysilicon pattern of the display region is N-lightly doped to form lightly doped regions on both sides of the channel region for mitigating the hot carrier effect of the NMOS channel.
  • the extensions 111 and 112 are set to be equal to the line width of the source of the N-type double gate structure transistor, and the opening directions of all the U-type polysilicon patterns are set to be the same as shown in FIGS. 2b and 2c.
  • step S106 a P+ heavily doping process is performed on the U-type polysilicon pattern of the non-display region to form two PMOS channels and a source region and a drain region of the P-type dual gate structure transistor, wherein The two PMOS channels each correspond to an opposite side of the U-shaped polysilicon pattern.
  • the source region and the drain region of the P-type double gate structure transistor are respectively located at the ends of the opposite sides of the U-shaped polysilicon pattern.
  • step S107 a flat layer is formed on the N-type double gate structure transistor and the exposed gate insulating layer. Specifically, a planarization insulating layer material is deposited on the N-type double gate structure transistor and the exposed gate insulating layer to form a flat layer.
  • a common electrode layer is formed on the flat layer. Specifically, a conductive material is deposited on the flat layer and processed to form a common electrode pattern.
  • step S109 a passivation layer is formed on the common electrode layer and a second via hole connected to the drain of the N-type double gate transistor is etched.
  • a passivation material is deposited on the common electrode layer to form a passivation layer, and an etching process is performed on the layer to form a second via hole 41 connected to the drain of the N-type double gate transistor.
  • a pixel electrode layer is formed on the passivation layer, and a drain region of the N-type double gate transistor is connected through the second via 41.
  • a layer of indium tin oxide material is deposited on the passivation layer and processed to form a pixel electrode layer, and the pixel electrode layer is connected to the drain region of the N-type double gate transistor through the second via 41. It should be noted that when the second via 41 is etched through the common electrode layer, the second via is processed through the common electrode to prevent the pixel electrode from being connected to the common electrode.
  • the method of the invention shortens the overall process to 10 channels without changing the structure of the TFT, without reducing the resolution, penetration rate and performance of the product, thereby greatly shortening the production cost and the production time.
  • a low temperature polysilicon array substrate which is fabricated by the method described above, without changing the structure of the thin film transistor, without reducing product resolution, transmittance and performance.
  • the overall process is shortened to 10 channels, which greatly shortens production costs and production time.

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Abstract

一种低温多晶硅阵列基板及其制作方法，方法包括：在玻璃基底上依次形成遮光层（11，12）、缓冲层、U型多晶硅图案（21）；对位于显示区域的U型多晶硅图案（21）进行沟道掺杂处理、N+重掺杂处理，形成栅绝缘层并蚀刻第一过孔后，形成栅极线（31）、N型双栅结构晶体管源极（321，322）及轻掺杂区；对非显示区域的U型多晶硅图案（21）进行P+重掺杂处理。

Description

一种低温多晶硅阵列基板及其制作方法
相关申请的交叉引用
本申请要求享有2016年12月27日提交的名称为“一种低温多晶硅阵列基板及其制作方法”的中国专利申请CN201611224492.8的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于阵列基板制作技术领域，具体地说，尤其涉及一种低温多晶硅阵列基板及其制作方法。
背景技术
近年来，LTPS(Low Temperature Poly-silicon，低温多晶硅)技术不断发展。采用LTPS工艺技术生产的液晶面板，有利于提高面板开口率，使显示器亮度提升、耗电降低，适用于生产更轻薄、低耗电、高分辨率的产品。
由于高分辨率及高性能需求，目前传统LTPS工艺相比薄膜晶体管液晶显示器需要高达12道工艺才能实现阵列基板的整体制程，制程过多会造成生产时间及生产成本的大幅升高，且工艺复杂化于制程中更易发生异常。
发明内容
为解决以上问题，本发明提供了一种低温多晶硅阵列基板及其制作方法，用以缩短阵列基板的制程。
根据本发明的一个方面，提供了一种用于制作低温多晶硅阵列基板的方法，包括：
在玻璃基底上形成遮光层，其中，所述遮光层包括阵列排布的遮光图案，沿列方向在每行间隔设置的遮光图案的两侧对称设置有一个延伸部，并且沿列方向的遮光图案形状相同；
在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，其中，所述U型多晶硅图案的两对边由行方向相邻的两个遮光 图案进行遮光；
对位于显示区域的所述U型多晶硅图案进行沟道掺杂处理；
对位于显示区域的进行沟道掺杂处理之后的所述U型多晶硅图案进行N+重掺杂处理，用以形成N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区，其中，两个所述NMOS沟道各对应所述U型多晶硅图案的一个对边；
在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极及轻掺杂区，其中，所述N型双栅结构晶体管的源极通过所述第一过孔与对应的遮光图案连接；
对非显示区域的所述U型多晶硅图案进行P+重掺杂处理，以形成P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区，其中，两个所述PMOS沟道各对应所述U型多晶硅图案的一个对边。
根据本发明的一个实施例，在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，进一步包括以下步骤：
在所述遮光层及裸露的玻璃基底上沉积一层缓冲材料以形成缓冲层；
在所述缓冲层上沉积单晶硅材料并进行结晶处理以形成所述U型多晶硅图案。
根据本发明的一个实施例，在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极和漏极及轻掺杂区进一步包括以下步骤：
在所述N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上沉积一层绝缘材料以形成栅绝缘层；
在所述栅绝缘层上对应所述延伸部的位置蚀刻两个连通至对应遮光图案的延伸部的第一过孔；
在所述栅绝缘层上沉积金属材料并进行蚀刻处理以形成栅极线、所述N型双栅结构晶体管的源极和漏极，其中，所述N型双栅结构晶体管的源极通过一个所述第一过孔连接对应的遮光图案和NMOS沟道的源极区；
对所述N型双栅结构晶体管进行N-轻掺杂处理以形成位于NMOS沟道两侧的轻掺杂区。
根据本发明的一个实施例，所述栅极线沿沿行方向设置，并且将所述栅极线 的宽度设置为等于所述NMOS沟道的长度。
根据本发明的一个实施例，所述N型双栅结构晶体管的源极通过对应的所述遮光图案及另一个所述第一过孔连接相邻列方向的所述N型双栅结构晶体管的源极。
根据本发明的一个实施例，所述遮光层采用金属材料制成。
根据本发明的一个实施例，所述延伸部设置为与所述N型双栅结构晶体管的源极的线宽相等。
根据本发明的一个实施例，所述U型多晶硅图案的开口方向设置为相同。
根据本发明的一个实施例，形成所述P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区之后还进一步包括：
在所述N型双栅结构晶体管及裸露的栅绝缘层上形成平坦层；
在所述平坦层上形成公共电极层；
在所述公共电极层上形成钝化层并蚀刻连通至所述N型双栅晶体管的漏极的第二过孔；
在所述钝化层上形成像素电极层，并通过第二过孔连接所述N型双栅晶体管的漏极区。
根据本发明的另一个方面，还提供了一种采用以上所述方法制作的低温多晶硅阵列基板。
本发明的有益效果：
本发明所述的方法在不改变薄膜晶体管结构，不降低产品分辨率、穿透率及性能的前提下，将整体制程缩短至10道，大大缩短了生产成本及生产时间。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1是根据本发明的一个实施例的方法流程图；
图2a是根据本发明的一个实施例的遮光图案示意图；
图2b是根据本发明的一个实施例的U型多晶硅图案示意图；
图2c是根据本发明的一个实施例的形成源漏极之后的基板示意图；
图2d是根据本发明的一个实施例的低温多晶硅阵列基板示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
如图1所示为根据本发明的一个实施例的方法流程图，以下参考图1来对本发明进行详细说明。
首先，在步骤S101中，在玻璃基底上形成遮光层，其中，遮光层包括阵列排布的遮光图案，沿列方向在每行间隔设置的遮光图案的两侧对称设置有一个延伸部，并且沿列方向的遮光图案形状相同。
具体的，遮光层主要用于对阵列基板上显示区域的沟道区进行遮光，所以将遮光层的遮光图案设置于显示区域上，对于非显示区域可不需设置。在形成该遮光层时，通常先在玻璃基底上沉积一层金属材料，然后对该层金属材料再进行蚀刻处理以形成遮光层。如图2a所示，该遮光层设置为包括阵列排布的遮光图案11和遮光图案12，并且每行间隔设置的遮光图案11沿列方向两侧对称设置有一个延伸部111和112，每列遮光图案的形状相同。此处的行方向定义为面对阵列基板的水平方向。
接下来，在步骤S102中，在遮光层及裸露的玻璃基底上形成缓冲层，并在缓冲层上形成U型多晶硅图案，其中，U型多晶硅图案的两对边由行方向相邻的两个遮光图案进行遮光。
具体的，首先在遮光层及裸露的玻璃基底上沉积一层缓冲材料以形成缓冲层，用以屏蔽玻璃基底自身缺陷导致的器件不良，通常可采用PECVD工艺沉积SiO2材料形成缓冲层。接着，在缓冲层上沉积单晶硅材料，并进行结晶处理形成U型多晶硅图案。具体的，可采用ELA工艺形成U型多晶硅图案21。如图2b所示，U型多晶硅图案21的两对边211和212由行方向相邻的两个遮光图案进行遮光。
接下来，在步骤S103中，对位于显示区域的U型多晶硅图案进行沟道掺杂处理。具体的，采用硼离子对U型多晶硅图案进行轻掺杂处理，用于调整后续形成的N型沟道区的阈值电压，该掺杂处理过程可对整个显示区域的U型多晶硅图案21进行。
接下来，在步骤S104中，对位于显示区域的进行沟道掺杂处理之后的U型多晶硅图案进行N+重掺杂处理，用以形成N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区。其中，NMOS沟道由遮光图案进行遮光。具体的，如图2b所示，对应于遮光图案11形成一个NMOS沟道，对应于遮光图案12形成另一个NMOS沟道，源极区和漏极区对应U型多晶硅图案的两对边的末端。
接下来，在步骤S105中，在NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在栅绝缘层上形成栅极线、N型双栅结构晶体管的源极及轻掺杂区213，其中，源极通过第一过孔与对应的遮光图案连接。
具体的，首先，在NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上沉积一层绝缘材料以形成栅绝缘层GI。这样就在结束步骤S105之后的基板上一整面设置一层栅绝缘层。此处通常采用SiNx材料形成栅绝缘层。接着，在该栅绝缘层上对应延伸部的位置蚀刻连通至对应遮光图案延伸部111和112的第一过孔(未示出)，接着，在栅绝缘层上沉积金属材料并进行蚀刻处理以形成栅极线31和源极321，而对N型双栅结构晶体管的漏极区不做处理。其中，N型双栅结构晶体管的源极321通过一个第一过孔连接对应的遮光图案和NMOS沟道的源极区，通过同一遮光图案及另一个第一过孔连接相邻列方向的N型双栅结构晶体管的源极322。这样就可以采用遮光图案传输数据信号，而不需要额外设置数据线。
将栅极线31沿行方向设置，并与NMOS沟道重叠设置，使得NMOS沟道的长度等于栅极线的宽度。最后，对显示区域的U型多晶硅图案进行N-轻掺杂处理以形成沟道区两侧的轻掺杂区，用于减轻NMOS沟道的热载流子效应。
为设计方便，将延伸部111和112设置为与N型双栅结构晶体管源极的线宽相等，并且将所有的U型多晶硅图案的开口方向设置为相同，如图2b和图2c所示。
接下来，在步骤S106中，对非显示区域的U型多晶硅图案进行P+重掺杂处理以形成P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区，其中， 两个PMOS沟道各对应U型多晶硅图案的一个对边。P型双栅结构晶体管的源极区和漏极区分别位于U型多晶硅图案两对边的末端处。
接下来，在步骤S107中，在N型双栅结构晶体管及裸露的栅绝缘层上形成平坦层。具体的，在N型双栅结构晶体管及裸露的栅绝缘层上沉积一层平坦化绝缘层材料形成平坦层。
接下来，在步骤S108中，在平坦层上形成公共电极层。具体的，在平坦层上沉积导电材料并进行处理形成公共电极图案。
接下来，在步骤S109中，在公共电极层上形成钝化层并蚀刻连通至N型双栅晶体管的漏极的第二过孔。具体的，如图2d所示，在公共电极层上沉积钝化材料形成钝化层，并在该层进行蚀刻处理形成连接连通至N型双栅晶体管的漏极的第二过孔41。
最后，在步骤S110中，在钝化层上形成像素电极层，并通过第二过孔41连接N型双栅晶体管的漏极区。具体的，在钝化层上沉积一层氧化铟锡材料并进行处理形成像素电极层，该像素电极层通过第二过孔41与N型双栅晶体管的漏极区连接。需注意的是，蚀刻第二过孔41时经过公共电极层，需对该第二过孔贯穿公共电极处进行处理，以防止像素电极与公共电极连接。
本发明所述的方法在不改变TFT结构，不降低产品分辨率，穿透率及性能的前提下，将整体制程缩短至10道，大大缩短了生产成本及生产时间。
根据本发明的另一个方面，还提供了一种低温多晶硅阵列基板，该阵列基板采用以上所述的方法制成，在不改变薄膜晶体管的结构，不降低产品分辨率，穿透率及性能的前提下，将整体制程缩短至10道，大大缩短了生产成本及生产时间。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种用于制作低温多晶硅阵列基板的方法，包括：
    在玻璃基底上形成遮光层，其中，所述遮光层包括阵列排布的遮光图案，沿列方向在每行间隔设置的遮光图案的两侧对称设置有一个延伸部，并且沿列方向的遮光图案形状相同；
    在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，其中，所述U型多晶硅图案的两对边由行方向相邻的两个遮光图案进行遮光；
    对位于显示区域的所述U型多晶硅图案进行沟道掺杂处理；
    对位于显示区域的进行沟道掺杂处理之后的所述U型多晶硅图案进行N+重掺杂处理，用以形成N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区，其中，两个所述NMOS沟道各对应所述U型多晶硅图案的一个对边；
    在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极及轻掺杂区，其中，所述N型双栅结构晶体管的源极通过所述第一过孔与对应的遮光图案连接；
    对非显示区域的所述U型多晶硅图案进行P+重掺杂处理，以形成P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区，其中，两个所述PMOS沟道各对应所述U型多晶硅图案的一个对边。
  2. 根据权利要求1所述的方法，其中，在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，进一步包括以下步骤：
    在所述遮光层及裸露的玻璃基底上沉积一层缓冲材料以形成缓冲层；
    在所述缓冲层上沉积单晶硅材料并进行结晶处理以形成所述U型多晶硅图案。
  3. 根据权利要求2所述的方法，其中，在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极和漏极及轻掺杂区进一步包括以下步骤：
    在所述N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上沉积一层绝缘材料以形成栅绝缘层；
    在所述栅绝缘层上对应所述延伸部的位置蚀刻两个连通至对应遮光图案的 延伸部的第一过孔；
    在所述栅绝缘层上沉积金属材料并进行蚀刻处理以形成栅极线、所述N型双栅结构晶体管的源极和漏极，其中，所述N型双栅结构晶体管的源极通过一个所述第一过孔连接对应的遮光图案和NMOS沟道的源极区；
    对所述N型双栅结构晶体管进行N-轻掺杂处理以形成位于NMOS沟道两侧的轻掺杂区。
  4. 根据权利要求3所述的方法，其中，所述栅极线沿沿行方向设置，并且将所述栅极线的宽度设置为等于所述NMOS沟道的长度。
  5. 根据权利要求3所述的方法，其中，所述N型双栅结构晶体管的源极通过对应的所述遮光图案及另一个所述第一过孔连接相邻列方向的所述N型双栅结构晶体管的源极。
  6. 根据权利要求3所述的方法，其中，所述遮光层采用金属材料制成。
  7. 根据权利要求3所述的方法，其中，所述延伸部设置为与所述N型双栅结构晶体管的源极的线宽相等。
  8. 根据权利要求1所述的方法，其中，所述U型多晶硅图案的开口方向设置为相同。
  9. 根据权利要求1所述的方法，其中，形成所述P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区之后还进一步包括：
    在所述N型双栅结构晶体管及裸露的栅绝缘层上形成平坦层；
    在所述平坦层上形成公共电极层；
    在所述公共电极层上形成钝化层并蚀刻连通至所述N型双栅晶体管的漏极的第二过孔；
    在所述钝化层上形成像素电极层，并通过第二过孔连接所述N型双栅晶体管的漏极区。
  10. 一种采低温多晶硅阵列基板，在制作所述低温多晶硅阵列基板时采用以下方法，所述方法包括：
    在玻璃基底上形成遮光层，其中，所述遮光层包括阵列排布的遮光图案，沿列方向在每行间隔设置的遮光图案的两侧对称设置有一个延伸部，并且沿列方向的遮光图案形状相同；
    在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，其中，所述U型多晶硅图案的两对边由行方向相邻的两个遮光 图案进行遮光；
    对位于显示区域的所述U型多晶硅图案进行沟道掺杂处理；
    对位于显示区域的进行沟道掺杂处理之后的所述U型多晶硅图案进行N+重掺杂处理，用以形成N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区，其中，两个所述NMOS沟道各对应所述U型多晶硅图案的一个对边；
    在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极及轻掺杂区，其中，所述N型双栅结构晶体管的源极通过所述第一过孔与对应的遮光图案连接；
    对非显示区域的所述U型多晶硅图案进行P+重掺杂处理，以形成P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区，其中，两个所述PMOS沟道各对应所述U型多晶硅图案的一个对边。
  11. 根据权利要求10所述的基板，其中，在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，进一步包括以下步骤：
    在所述遮光层及裸露的玻璃基底上沉积一层缓冲材料以形成缓冲层；
    在所述缓冲层上沉积单晶硅材料并进行结晶处理以形成所述U型多晶硅图案。
  12. 根据权利要求11所述的基板，其中，在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极和漏极及轻掺杂区进一步包括以下步骤：
    在所述N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上沉积一层绝缘材料以形成栅绝缘层；
    在所述栅绝缘层上对应所述延伸部的位置蚀刻两个连通至对应遮光图案的延伸部的第一过孔；
    在所述栅绝缘层上沉积金属材料并进行蚀刻处理以形成栅极线、所述N型双栅结构晶体管的源极和漏极，其中，所述N型双栅结构晶体管的源极通过一个所述第一过孔连接对应的遮光图案和NMOS沟道的源极区；
    对所述N型双栅结构晶体管进行N-轻掺杂处理以形成位于NMOS沟道两侧的轻掺杂区。
  13. 根据权利要求12所述的基板，其中，所述栅极线沿沿行方向设置，并 且将所述栅极线的宽度设置为等于所述NMOS沟道的长度。
  14. 根据权利要求12所述的基板，其中，所述N型双栅结构晶体管的源极通过对应的所述遮光图案及另一个所述第一过孔连接相邻列方向的所述N型双栅结构晶体管的源极。
  15. 根据权利要求12所述的基板，其中，所述遮光层采用金属材料制成。
  16. 根据权利要求12所述的基板，其中，所述延伸部设置为与所述N型双栅结构晶体管的源极的线宽相等。
  17. 根据权利要求10所述的基板，其中，所述U型多晶硅图案的开口方向设置为相同。
  18. 根据权利要求10所述的基板，其中，形成所述P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区之后还进一步包括：
    在所述N型双栅结构晶体管及裸露的栅绝缘层上形成平坦层；
    在所述平坦层上形成公共电极层；
    在所述公共电极层上形成钝化层并蚀刻连通至所述N型双栅晶体管的漏极的第二过孔；
    在所述钝化层上形成像素电极层，并通过第二过孔连接所述N型双栅晶体管的漏极区。
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