WO2016106892A1 - 阵列基板、显示面板及阵列基板的制备方法 - Google Patents

阵列基板、显示面板及阵列基板的制备方法 Download PDF

Info

Publication number
WO2016106892A1
WO2016106892A1 PCT/CN2015/071168 CN2015071168W WO2016106892A1 WO 2016106892 A1 WO2016106892 A1 WO 2016106892A1 CN 2015071168 W CN2015071168 W CN 2015071168W WO 2016106892 A1 WO2016106892 A1 WO 2016106892A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
low temperature
temperature polysilicon
drain
disposed
Prior art date
Application number
PCT/CN2015/071168
Other languages
English (en)
French (fr)
Inventor
王聪
杜鹏
陈黎暄
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/435,468 priority Critical patent/US9530800B2/en
Priority to KR1020177019782A priority patent/KR101999907B1/ko
Priority to JP2017534675A priority patent/JP6570640B2/ja
Priority to GB1710274.0A priority patent/GB2548759B/en
Publication of WO2016106892A1 publication Critical patent/WO2016106892A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of display, and in particular, to a method for preparing an array substrate, a display panel, and an array substrate.
  • a display device such as a liquid crystal display (LCD) is a commonly used electronic device that is favored by users because of its low power consumption, small size, and light weight.
  • LCD liquid crystal display
  • Amorphous silicon has a low electron mobility
  • Ploy-silicon can be fabricated at low temperatures and has a higher electron mobility than amorphous silicon.
  • CMOS devices fabricated from low temperature polysilicon can be applied to make liquid crystal displays have higher resolution and lower power consumption. Therefore, low temperature polysilicon has been widely used and studied.
  • the array substrate including the low temperature polysilicon thin film transistor has a large number of masks in the low temperature polysilicon. Generally, the number of masks of the low temperature polysilicon thin film crystal array substrate is ten times, thereby causing the low temperature polysilicon thin film transistor array substrate. Preparation is difficult and is not conducive to productivity.
  • the present invention provides an array substrate comprising a plurality of low temperature polysilicon thin film transistors distributed in a matrix, the low temperature polysilicon thin film transistors comprising:
  • a low temperature polysilicon layer a source, a drain and a first conductive layer disposed on the same surface of the substrate, the low temperature polysilicon layer being disposed in a middle portion of a surface of the substrate, the source and the drain being disposed at Determining both sides of the low temperature polysilicon layer, and one end of the source is electrically connected to one of the low temperature polysilicon layers An end of the drain is electrically connected to the other end of the low temperature polysilicon layer, and the other end of the drain is electrically connected to the first conductive layer;
  • An insulating layer, the insulating layer is disposed on the low temperature polysilicon layer, the source, the drain, and the first conductive layer;
  • the gate is disposed on the insulating layer and disposed corresponding to the low temperature polysilicon layer;
  • the passivation layer being stacked on the gate
  • the second conductive layer is disposed on the passivation layer and disposed corresponding to the first conductive layer, wherein the first conductive layer is a pixel electrode, and the second conductive layer is a common electrode .
  • the array substrate further includes a light shielding layer, the light shielding layer is disposed on a surface of the substrate, and the low temperature polysilicon layer, the source, the drain, and the first conductive layer pass through the light shielding layer And disposed on a surface of the substrate, and the light shielding layer is disposed corresponding to the low temperature polysilicon layer.
  • the array substrate further includes a buffer layer, the buffer layer is stacked on the light shielding layer, and the low temperature polysilicon layer, the source, the drain, and the first conductive layer pass the buffer
  • the layer and the light shielding layer are disposed on a surface of the substrate.
  • the array substrate further includes a first ohmic contact layer connecting the source and the low temperature polysilicon layer, the first ohmic contact layer for reducing the source and the Contact resistance between low temperature polysilicon layers.
  • the array substrate further includes a second ohmic contact layer connecting the drain and the low temperature polysilicon layer, the second ohmic contact layer for reducing the drain and the Contact resistance between low temperature polysilicon layers.
  • the present invention provides a display panel comprising the array substrate of any of the above embodiments.
  • the present invention also provides a method for preparing an array substrate, and the method for preparing the array substrate comprises:
  • a low temperature polysilicon layer, a source, a drain and a first conductive layer are disposed on one surface of the substrate, the low temperature polysilicon layer is disposed in a middle portion of a surface of the substrate, and the source and the drain are disposed at The two sides of the low temperature polysilicon layer are electrically connected to one end of the low temperature polysilicon layer, one end of the drain is connected to the other end of the low temperature polysilicon layer, and the other end of the drain is electrically connected Connecting the first conductive layer;
  • the method for preparing the array substrate further includes:
  • the other end electrically connecting the first conductive layer is:
  • the low temperature polysilicon layer, the source, the drain, and the first conductive layer are disposed on the light shielding layer.
  • a low temperature polysilicon layer is disposed in a middle portion of a surface of the substrate, the source and the drain are disposed on two sides of the low temperature polysilicon layer, and one end of the source is electrically connected to one end of the low temperature polysilicon layer, The one end of the drain is connected to the other end of the low temperature polysilicon layer, and the other end of the drain is electrically connected to the first conductive layer.
  • the step of "providing a low temperature polysilicon layer, a source, a drain, and a surface on one surface of the substrate a conductive layer, the low temperature polysilicon layer is disposed at a middle portion of a surface of the substrate, the source and the drain are disposed at two sides of the low temperature polysilicon layer, and one end of the source is electrically connected to the One end of the low temperature polysilicon layer, one end of the drain is connected to the other end of the low temperature polysilicon layer, and the other end of the drain is electrically connected to the first conductive layer" is:
  • the low temperature polysilicon layer, the source, the drain, and the first conductive layer are disposed on a surface of the substrate through the buffer layer.
  • the method for preparing the array substrate further includes:
  • first ohmic contact layer Forming a first ohmic contact layer, the first ohmic contact layer connecting the source and the low temperature polysilicon layer;
  • a second ohmic contact layer is formed, the second ohmic contact layer connecting the drain and the low temperature polysilicon layer.
  • the method for preparing the array substrate and the array substrate of the present invention can be completed by only seven masks, thereby reducing the number of masks used in the formation of the array substrate, and improving the productivity of the array substrate.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a display panel according to a preferred embodiment of the present invention.
  • FIG. 3 is a flow chart of a method of fabricating an array substrate according to a preferred embodiment of the present invention.
  • 4 to 15 are cross-sectional views showing processes corresponding to respective steps in the method of fabricating the array substrate of the present invention.
  • FIG. 1 is a cross-sectional structural view of an array substrate according to a preferred embodiment of the present invention.
  • the array substrate 10 includes a substrate 101, a low temperature polysilicon layer 104, a source 107, a drain 108, a first conductive layer 112, an insulating layer 109, a gate electrode 110, a passivation layer 111, and a second conductive layer 113.
  • the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112 are disposed on the same surface of the substrate 101.
  • the low temperature polysilicon layer 104 is disposed at a middle portion of the surface of the substrate 101, the source electrode 107 and the drain electrode 108 are disposed at two sides of the low temperature polysilicon layer 104, and one end of the source electrode 107 is electrically connected One end of the low temperature polysilicon layer 104, one end of the drain 108 is electrically connected to the other end of the low temperature polysilicon layer 104, and the other end of the drain 108 is electrically connected to the first conductive layer 112.
  • the insulating layer 109 is disposed on the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112.
  • the gate 110 is disposed on the insulating layer 109 and disposed corresponding to the low temperature polysilicon layer 104.
  • the passivation layer 111 is disposed on the gate 110.
  • the second conductive layer 113 is disposed on the passivation layer 111 and disposed corresponding to the first conductive layer 112.
  • the first conductive layer 112 is a pixel electrode, and the second conductive layer 113 is a common electrode.
  • the low temperature polysilicon layer 104, the source 107, the drain 108, the insulating layer 109, and the gate 110 constitute a low temperature polysilicon thin film transistor.
  • the substrate 101 includes a first surface a and a second surface b disposed opposite to the first surface a.
  • the low temperature polysilicon layer 104, the source electrode 107, the drain electrode 108, and the first conductive layer 112 are disposed on the first surface a of the substrate 101. It is to be understood that in other embodiments, the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112 are disposed on the second surface b of the substrate 101.
  • the substrate 101 may be, but not limited to, a glass substrate.
  • the array substrate 10 further includes a light shielding layer 102 disposed on a surface of the substrate 101, the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer.
  • the light shielding layer 102 is disposed on the surface of the substrate 101 , and the light shielding layer 102 is disposed corresponding to the low temperature polysilicon layer 104 .
  • the light shielding layer 102 is disposed on the first surface a of the substrate 101.
  • the light shielding layer 102 is configured to prevent light from being emitted toward the second surface b by the corresponding pixel of the low temperature polysilicon thin film transistor.
  • the array substrate 10 further includes a buffer layer 103, the buffer layer 103 is stacked on the light shielding layer 102, the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive
  • the layer 112 is disposed on the surface of the substrate 101 through the buffer layer 103 and the light shielding layer 102.
  • the buffer layer 103 is used to buffer damage to the substrate 101 during the preparation of the array substrate 10.
  • the array substrate 10 further includes a first ohmic contact layer 105 connecting the source 107 and the low temperature polysilicon layer 104, the first ohmic contact layer 105 for reducing the source The contact resistance between the pole 107 and the low temperature polysilicon layer 104.
  • the first ohmic contact layer 105 includes a first heavily doped region 1051 and a first lightly doped region 1052. One end of the first heavily doped region 1051 is connected to the source 107, the other end is connected to the first lightly doped region 1052, and the other end of the first lightly doped region 1052 is connected to the low temperature polysilicon layer. One end of 104 is connected.
  • the first heavily doped region 1051 is partially stacked with the source 107 to increase a contact area of the first heavily doped region 1051 with the source 107.
  • the first heavily doped region 1051 is doped with the same type of ions as the first lightly doped region 1052, for example, may be doped with N-type ions, and the doping concentration of the first heavily doped region 1051 is greater than The doping concentration of the first lightly doped region 1052 is described.
  • the arrangement of the first heavily doped region 1051 and the first lightly doped region 1052 in the present embodiment can reduce the contact resistance between the source 107 and the low temperature polysilicon layer 104, and can be reduced.
  • the leakage current of the low temperature polysilicon thin film transistor is small.
  • the array substrate 10 further includes a second ohmic contact layer 106 connecting the drain electrode 108 and the low temperature polysilicon layer 104, the second ohmic contact layer 106 for reducing the drain Contact resistance between the pole 108 and the low temperature polysilicon layer 104.
  • the second ohmic contact layer 106 includes a second heavily doped region 1061 and a second lightly doped region 1062. One end of the second heavily doped region 1061 is connected to the drain 108, the other end is connected to the second lightly doped region 1062, and the other end of the second lightly doped region 1062 is connected to the low temperature polysilicon layer. One end of 104 is connected.
  • the second heavily doped region 1061 is partially laminated with the drain 108 to increase a contact area of the second heavily doped region 1061 with the drain 108.
  • the second heavily doped region 1061 is of the same type as the second lightly doped region 1062, and may be doped with N-type ions, and the doped concentration of the second heavily doped region 1061 is greater than The doping concentration of the second lightly doped region 1062 is described.
  • the second heavily doped region 1061 and the first in the embodiment The arrangement of the two lightly doped regions 1062 can both reduce the contact resistance between the drain 108 and the low temperature polysilicon layer 104, and can reduce the leakage current of the low temperature polysilicon thin film transistor.
  • FIG. 2 is a schematic structural diagram of a display panel according to a preferred embodiment of the present invention.
  • the display panel 1 includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30.
  • the array substrate 10 is disposed opposite to the color filter substrate 20, and the liquid crystal layer 30 is disposed between the array substrate 10 and the color filter substrate 20.
  • the array substrate 10 includes a substrate 101, a low temperature polysilicon layer 104, a source 107, a drain 108, a first conductive layer 112, an insulating layer 109, a gate electrode 110, a passivation layer 111, and a second conductive layer 113.
  • the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112 are disposed on the same surface of the substrate 101.
  • the low temperature polysilicon layer 104 is disposed at a middle portion of the surface of the substrate 101, the source electrode 107 and the drain electrode 108 are disposed at two sides of the low temperature polysilicon layer 104, and one end of the source electrode 107 is electrically connected
  • One end of the low temperature polysilicon layer 104, one end of the drain 108 is electrically connected to the other end of the low temperature polysilicon layer 104, and the other end of the drain 108 is electrically connected to the first conductive layer 112.
  • the insulating layer 109 is disposed on the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112.
  • the gate 110 is disposed on the insulating layer 109 and disposed corresponding to the low temperature polysilicon side 104.
  • the passivation layer 111 is disposed on the gate 110.
  • the second conductive layer 113 is disposed on the passivation layer 111 and disposed corresponding to the first conductive layer 112.
  • the first conductive layer 112 is a pixel electrode, and the second conductive layer 113 is a common electrode.
  • the low temperature polysilicon layer 104, the source 107, the drain 108, the insulating layer 109, and the gate 110 constitute a low temperature polysilicon thin film transistor.
  • the substrate 101 includes a first surface a and a second surface b disposed opposite to the first surface a.
  • the low temperature polysilicon layer 104, the source electrode 107, the drain electrode 108, and the first conductive layer 112 are disposed on the first surface a of the substrate 101. It is to be understood that in other embodiments, the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112 are disposed on the second surface b of the substrate 101.
  • the substrate 101 may be, but not limited to, a glass substrate.
  • the array substrate 10 further includes a light shielding layer 102 disposed on a surface of the substrate 101, the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer. 112 is disposed on a surface of the substrate 101 through the square, and the light shielding layer 102 corresponds to The low temperature polysilicon layer 104 is disposed.
  • the light shielding layer 102 is disposed on the first surface a of the substrate 101.
  • the light shielding layer 102 is configured to prevent light from being emitted toward the second surface b by the corresponding pixel of the low temperature polysilicon thin film transistor.
  • the array substrate 10 further includes a buffer layer 103, the buffer layer 103 is stacked on the light shielding layer 102, the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive
  • the layer 112 is disposed on the surface of the substrate 101 through the buffer layer 103 and the light shielding layer 102.
  • the buffer or the like 103 is used to buffer damage to the substrate 101 during preparation of the array substrate 10.
  • the array substrate 10 further includes a first ohmic contact layer 105 connecting the source 107 and the low temperature polysilicon layer 104, the first ohmic contact layer 105 for reducing the source The contact resistance between the pole 107 and the low temperature polysilicon layer 104.
  • the first ohmic contact layer 105 includes a first heavily doped region 1051 and a first lightly doped region 1052. One end of the first heavily doped region 1051 is connected to the source 107, the other end is connected to the first lightly doped region 1052, and the other end of the first lightly doped region 1052 is connected to the low temperature polysilicon layer. One end of 104 is connected.
  • the first heavily doped region 1051 is partially stacked with the source 107 to increase a contact area of the first heavily doped region 1051 with the source 107.
  • the first heavily doped region 1051 is doped with the same type of ions as the first lightly doped region 1052, for example, may be doped with N-type ions, and the doping concentration of the first heavily doped region 1051 is greater than The doping concentration of the first lightly doped region 1052 is described.
  • the arrangement of the first heavily doped region 1051 and the first lightly doped region 1052 in the present embodiment can reduce the contact resistance between the source 107 and the low temperature polysilicon layer 104, and can be reduced.
  • the leakage current of the low temperature polysilicon thin film transistor is small.
  • the array substrate 10 further includes a second ohmic contact layer 106 connecting the drain electrode 108 and the low temperature polysilicon layer 104, the second ohmic contact layer 106 for reducing the drain Contact resistance between the pole 108 and the low temperature polysilicon layer 104.
  • the second ohmic contact layer 106 includes a second heavily doped region 1061 and a second lightly doped region 1062. One end of the second heavily doped region 1061 is connected to the drain 108, the other end is connected to the second lightly doped region 1062, and the other end of the second lightly doped region 1062 is connected to the low temperature polysilicon layer. One end of 104 is connected.
  • the second heavily doped region 1061 is partially laminated with the drain 108 to increase a contact area of the second heavily doped region 1061 with the drain 108.
  • the first The double-doped region 1061 is the same as the second light-doped region 1062, and may be doped with N-type ions, and the second heavily doped region 1061 has a doping concentration greater than the second Doping concentration of lightly doped region 1062.
  • the arrangement of the second heavily doped region 1061 and the second lightly doped region 1062 in the present embodiment can reduce the contact resistance between the drain 108 and the low temperature polysilicon layer 104, and can be reduced. The leakage current of the low temperature polysilicon thin film transistor is small.
  • the preparation method of the array substrate of the present invention will be described below with reference to FIG. Referring to FIG. 3, the method for preparing the array substrate includes, but is not limited to, the following steps.
  • a substrate 101 is provided.
  • the substrate 101 includes a first surface a and a second surface b disposed opposite to the first surface a.
  • the low temperature polysilicon layer 104, the source electrode 107, the drain electrode 108, and the first conductive layer 112 are disposed on the first surface a of the substrate 101. It is to be understood that in other embodiments, the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112 are disposed on the second surface b of the substrate 101.
  • the substrate 101 may be, but not limited to, a glass substrate.
  • a light shielding layer 102 is formed on the surface of the substrate 101.
  • a light shielding layer 102 is formed in a middle portion of the first surface a of the substrate 101.
  • the light shielding layer 102 may also be formed in the middle of the second surface b of the substrate 101.
  • the light shielding layer 102 can be formed as follows. First, a whole layer of light shielding layer is formed on the first surface a of the substrate 101, and the entire light shielding layer is exposed, developed, and etched into a predetermined pattern to serve as the light shielding layer 102.
  • a photomask is used once, and for convenience of description, the photomask used in this step becomes the first photomask.
  • the light shielding layer 102 is disposed on the first surface a of the substrate 101. The light shielding layer 102 is configured to prevent light from being emitted toward the second surface b by the corresponding pixel of the low temperature polysilicon thin film transistor.
  • a buffer layer 103 is formed on the light shielding layer 102.
  • a buffer layer 103 is formed on the light shielding layer 102 and the surface of the substrate 101 on which the light shielding layer 102 is not disposed.
  • the buffer layer 103 is used to buffer damage to the substrate 101 during the preparation of the array substrate 10.
  • Step S104 forming a low temperature polysilicon layer 104, a source 107, a drain 108, and a first conductive layer 112, the low temperature polysilicon layer 104 being disposed corresponding to a middle portion of a surface of the substrate 101, the source 107 and the drain 108 is disposed on both sides of the low temperature polysilicon layer 104, and the source 107
  • One end of the low temperature polysilicon layer 104 is electrically connected to one end
  • one end of the drain 108 is connected to the other end of the low temperature polysilicon layer 104
  • the other end of the drain 108 is electrically connected to the first conductive layer 112.
  • a first conductive layer 112 is first formed on the buffer layer 103, and the first conductive layer 112 is disposed on the buffer layer 103 not covering the light shielding layer 102.
  • the buffer layer 103 can be formed as follows. First, an entire conductive layer is formed on the buffer layer 103, and the entire conductive layer is exposed, developed, and etched into a prescribed pattern to form the first conductive layer 112.
  • the first conductive layer 112 functions as a pixel electrode.
  • a photomask is used in the formation of the first conductive layer 112. For convenience of description, the photomask used in the formation of the first conductive layer 112 is referred to as a second photomask.
  • a source 107 and a drain 108 are formed on the buffer layer 103.
  • the source 107 and the drain 108 are respectively disposed corresponding to both ends of the light shielding layer 102.
  • the formation of the source 107 and the drain 108 can be formed as follows. First, an entire metal layer is formed on the buffer layer 103, and the entire metal layer is exposed, developed, and etched into a prescribed pattern to form the source 107 and the drain 108.
  • a photomask is used in the formation of the source 107 and the drain 108. For convenience of description, the photomask used in the formation of the source 107 and the drain 108 is referred to as a third light. cover.
  • a low temperature polysilicon layer 104 is formed on the buffer layer 103.
  • the low temperature polysilicon layer 104 is disposed between the source 107 and the drain 108, and the two ends of the low temperature polysilicon layer 104 are respectively The source 107 is connected to the drain 108.
  • the formation of the buffer layer 104 can be formed as follows. First, an entire layer of low temperature polysilicon is formed on the buffer layer 103, and the entire low temperature polysilicon layer is exposed, developed, and etched into a prescribed shape to form the low temperature polysilicon layer 104. A photomask is used in the formation of the low temperature polysilicon layer 104. For convenience of description, the photomask used in the formation of the low temperature polysilicon layer 104 is referred to as a fourth photomask.
  • step S105 an insulating layer 109 is formed.
  • the insulating layer 109 is formed on the low temperature polysilicon layer 104, the source 107, the drain 108, and the first conductive layer 112. Please refer to Figure 10 together.
  • a gate electrode 110 is formed, and the gate electrode 110 is disposed on the insulating layer 109.
  • the gate 110 can be formed as follows. First, an entire metal layer is disposed on the insulating layer 109, and the entire metal layer is exposed, developed, and etched into a finger. The shape is shaped to form the gate 110. A photomask is used in the formation of the gate electrode 110. For convenience of description, the photomask used in forming the gate electrode 110 is referred to as a fifth photomask.
  • step S107 a first ohmic contact layer 105 is formed, and the first ohmic contact layer 105 is connected to the source 107 and the low temperature polysilicon layer 104.
  • the first ohmic contact layer 105 is connected to the source 107 and the low temperature polysilicon layer 104.
  • FIG. 12 for the formation of the first ohmic contact layer 105. Please refer to the previous description, and details are not described herein again.
  • Step S108 forming a second ohmic contact layer 106, the second ohmic contact layer 106 connecting the drain electrode 108 and the low temperature polysilicon layer 104. Please refer to FIG. 13 for the formation of the second ohmic contact layer 106. Please refer to the previous description, and details are not described herein again.
  • step S109 a passivation layer 111 is formed, and the passivation layer 111 is disposed on the gate 110.
  • a through hole 1111 is formed on the passivation layer 111.
  • a through mask is also required for the through hole 1111. The mask is referred to as a sixth mask.
  • Step S110 forming a second conductive layer 113, the second conductive layer 113 is disposed on the passivation layer 111 and disposed corresponding to the first conductive layer 112, wherein the first to the electrical layer 112 is a pixel electrode
  • the second conductive layer 113 is a common electrode.
  • the formation of the second conductive layer 113 can be formed as follows. First, an entire conductive layer is formed on the passivation layer 111, and the entire conductive layer is exposed, developed, and etched into a prescribed shape to form the second conductive layer 113. A photomask is required for the formation of the second conductive layer 113. For convenience of description, the photomask is referred to as a seventh photomask.
  • the description of the method for preparing the array substrate of the present invention shows that the array substrate and the array substrate of the present invention can be completed by only seven masks, thereby reducing the number of masks used in the formation of the array substrate. It is advantageous to increase the productivity of the array substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种阵列基板（10）、显示面板（1）及阵列基板（10）的制备方法。阵列基板（10）具有呈矩阵分布的多个低温多晶硅薄膜晶体管，阵列基板（10）包括：基板（101）；设置在基板（101）同一表面的低温多晶硅层（104）、源极（107）、漏极（108）以及第一导电层（112），低温多晶硅层（104）设置于基板（101）的表面的中部，源极（107）及漏极（108）设置于低温多晶硅层（104）的两侧，且源极（107）的一端电连接低温多晶硅层（104）的一端，漏极（108）的一端电连接低温多晶硅层（104）的另一端，漏极（108）的另一端电连接第一导电层（112）；绝缘层（109），绝缘层（109）设置于低温多晶硅层（104）、源极（107）、漏极（108）以及第一导电层（112）上；栅极（110），栅极（110）设置于绝缘层（109）上且对应低温多晶硅层（104）设置；钝化层（111），层叠设置于栅极（110）上；以及第二导电层（113），第二导电层（113）设置于钝化层（111）上且对应第一导电层（112）设置。

Description

阵列基板、显示面板及阵列基板的制备方法
本发明要求2014年12月30日递交的发明名称为“阵列基板、显示面板及阵列基板的制备方法”的申请号201410849415.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板、显示面板及阵列基板的制备方法。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。随着平面显示技术的发展，具有高分辨率、低能耗的液晶显示器的需求被提出。非晶硅的电子迁移率较低，而低温多晶硅(Low Temperature Ploy-silicon)可以在低温下制作，且拥有比非晶硅更高的电子迁移率。其次，低温多晶硅制作的CMOS器件可应用于使液晶显示器具有更高的分辨率和低能耗。因此，低温多晶硅得到了广泛地应用和研究。目前，包括低温多晶硅薄膜晶体管的阵列基板由于低温多晶硅中的光罩次数较多，一般而言，所述低温多晶硅薄膜晶体阵列基板的光罩次数为十次，从而造成低温多晶硅薄膜晶体管阵列基板的制备较为困难，且不利于产能的提高。
发明内容
本发明提供一种阵列基板，所述阵列基板包括呈矩阵分布的多个低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括：
基板；
设置在所述基板同一表面的低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一 端，所述漏极的一端电连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
绝缘层，所述绝缘层设置于所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层上；
栅极，所述栅极设置于所述绝缘层上且对应所述低温多晶硅层设置；
钝化层，所述钝化层层叠设置于所述栅极上；以及
第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
其中，所述阵列基板还包括遮光层，所述遮光层设置于所述基板的表面，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述遮光层设置于所述基板的表面，且所述遮光层对应所述低温多晶硅层设置。
其中，所述阵列基板还包括缓冲层，所述缓冲层层叠设置于所述遮光层上，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层及所述遮光层设置于所述基板的表面上。
其中，所述阵列基板还包括第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层，所述第一欧姆接触层用于降低所述源极与所述低温多晶硅层之间的接触电阻。
其中，所述阵列基板还包括第二欧姆接触层，所述第二欧姆接触层连接所述漏极与所述低温多晶硅层，所述第二欧姆接触层用于降低所述漏极与所述低温多晶硅层之间的接触电阻。
另一方面本发明提供了一种显示面板，所述显示面板包括上述各个实施方式中任意一种实施方式的阵列基板。
另一方面，本发明还提供了阵列基板的制备方法，所述阵列基板的制备方法包括：
提供一基板；
在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连 接所述第一导电层；
形成绝缘层，所述绝缘层形成在所述低温多晶硅层、所述源极、所述漏极及所述第一导电层上；
形成栅极，所述栅极设置在所述绝缘层上；
形成钝化层，所述钝化层设置在所述栅极上；
形成第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
其中，在所述步骤“提供一基板”以及所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之间，所述阵列基板的制备方法还包括：
在所述基板的表面上形成遮光层；
所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
在所述遮光层上设置所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层。
其中，在所述步骤“在所述基板的表面上形成遮光层”之后，在所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之前还包括：
在所述遮光层上形成缓冲层；
所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第 一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层设置在所述基板的表面上。
其中，所述阵列基板的制备方法还包括：
形成第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层；
形成第二欧姆接触层，所述第二欧姆接触层连接所述漏极及所述低温多晶硅层。
本发明的阵列基板及阵列基板的制备方法只需要七道光罩就能完成，从而减少了所述阵列基板的形成时所用到的光罩的数量，有利于所述阵列基板的产能的提高。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。
图2为本发明一较佳实施方式的显示面板的结构示意图。
图3为本发明一较佳实施方式的阵列基板的制备方法的流程图。
图4至图15为本发明阵列基板的制备方法中各个步骤对应的制程的剖面图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是 全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。所述阵列基板10包括基板101、低温多晶硅层104、源极107、漏极108、第一导电层112、绝缘层109、栅极110、钝化层111以及第二导电层113。所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的同一表面。所述低温多晶硅层104设置于所述基板101的表面的中部，所述源极107及所述漏极108设置于所述低温多晶硅层104的两侧，且所述源极107的一端电连接所述低温多晶硅层104的一端，所述漏极108的一端电连接所述低温多晶硅层104的另一端，所述漏极108的另一端电连接所述第一导电层112。所述绝缘层109设置于所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112上。所述栅极110设置于所述绝缘层109上且对应所述低温多晶硅层104设置。所述钝化层111设置于所述栅极110上。所述第二导电层113设置于所述钝化层111上且对应所述第一导电层112设置。其中，所述第一导电层112为像素电极，所述第二导电层113为公共电极。所述低温多晶硅层104、所述源极107、所述漏极108、所述绝缘层109及所述栅极110构成了低温多晶硅薄膜晶体管。
所述基板101包括第一表面a及与所述第一表面a相对设置的第二表面b。在本实施方式中，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第一表面a上。可以理解地，在其他实施方式中，低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第二表面b上。所述基板101可以为但不仅限于为玻璃基板。
所述阵列基板10还包括遮光层102，所述遮光层102设置于所述基板101的表面，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112通过所述遮光层102设置于所述基板101的表面，且所述遮光层102对应所述低温多晶硅层104设置。在本实施方式中，所述遮光层102设置于所述基板101的第一表面a上。所述遮光层102用于防止所述低温多晶硅薄膜晶体管对应像素朝向所述第二表面b漏光。
所述阵列基板10还包括缓冲层103，所述缓冲层103层叠设置于所述遮光层102上，所述低温多晶硅层104、所述源极107、所述漏极108以及所述第一导电层112通过所述缓冲层103及所述遮光层102设置于所述基板101的表面上。所述缓冲层103用于缓冲所述阵列基板10的制备过程中对所述基板101的损伤。
所述阵列基板10还包括第一欧姆接触层105，所述第一欧姆接触层105连接所述源极107与所述低温多晶硅层104，所述第一欧姆接触层105用于降低所述源极107与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第一欧姆接触层105包括第一重掺杂区域1051和第一轻掺杂区域1052。所述第一重掺杂区域1051一端与所述源极107相连，另一端与所述第一轻掺杂区域1052相连，所述第一轻掺杂区域1052的另一端与所述低温多晶硅层104的一端相连。所述第一重掺杂区域1051的一端与所述源极107部分层叠设置，以增加所述第一重掺杂区域1051与所述源极107的接触面积。所述第一重掺杂区域1051与所述第一轻掺杂区域1052掺杂的离子类型相同，比如可以同掺杂N型离子，所述第一重掺杂区域1051的掺杂浓度大于所述第一轻掺杂区域1052的掺杂浓度。本实施方式中的所述第一重掺杂区域1051及所述第一轻掺杂区域1052的设置既能够降低所述源极107与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
所述阵列基板10还包括第二欧姆接触层106，所述第二欧姆接触层106连接所述漏极108与所述低温多晶硅层104，所述第二欧姆接触层106用于降低所述漏极108与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第二欧姆接触层106包括第二重掺杂区域1061和第二轻掺杂区域1062。所述第二重掺杂区域1061一端与所述漏极108相连，另一端连接所述第二轻掺杂区域1062相连，所述第二轻掺杂区域1062的另一端与所述低温多晶硅层104的一端相连。所述第二重掺杂区域1061的一端与所述漏极108部分层叠设置，以增加所述第二重掺杂区域1061与所述漏极108的接触面积。所述第二重掺杂区域1061与所述第二轻掺杂区域1062掺杂的离子类型相同，比如可以同掺杂N型离子，所述第二重掺杂区域1061的掺杂浓度大于所述第二轻掺杂区域1062的掺杂浓度。本实施方式中的所述第二重掺杂区域1061及所述第 二轻掺杂区域1062的设置既能够降低所述漏极108与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
下面结合图1对本发明的显示面板进行介绍。请参阅图2，图2为本发明一较佳实施方式的显示面板的结构示意图。所述显示面板1包括阵列基板10、彩色滤光基板20及液晶层30。所述阵列基板10与所述彩色滤光基板20相对设置，所述液晶层30设置在所述阵列基板10和所述彩色滤光基板20之间。所述阵列基板10包括基板101、低温多晶硅层104、源极107、漏极108、第一导电层112、绝缘层109、栅极110、钝化层111以及第二导电层113。所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的同一表面。所述低温多晶硅层104设置于所述基板101的表面的中部，所述源极107及所述漏极108设置于所述低温多晶硅层104的两侧，且所述源极107的一端电连接所述低温多晶硅层104的一端，所述漏极108的一端电连接所述低温多晶硅层104的另一端，所述漏极108的另一端电连接所述第一导电层112。所述绝缘层109设置于所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112上。所述栅极110设置于所述绝缘层109上且对应所述低温多晶硅侧呢过104设置。所述钝化层111设置于所述栅极110上。所述第二导电层113设置于所述钝化层111上且对应所述第一导电层112设置。其中，所述第一导电层112为像素电极，所述第二导电层113为公共电极。所述低温多晶硅层104、所述源极107、所述漏极108、所述绝缘层109及所述栅极110构成了低温多晶硅薄膜晶体管。
所述基板101包括第一表面a及与所述第一表面a相对设置的第二表面b。在本实施方式中，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第一表面a上。可以理解地，在其他实施方式中，低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第二表面b上。所述基板101可以为但不仅限于为玻璃基板。
所述阵列基板10还包括遮光层102，所述遮光层102设置于所述基板101的表面，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112通过所述这广场设置于所述基板101的表面，且所述遮光层102对应 所述低温多晶硅层104设置。在本实施方式中，所述遮光层102设置于所述基板101的第一表面a上。所述遮光层102用于防止所述低温多晶硅薄膜晶体管对应像素朝向所述第二表面b漏光。
所述阵列基板10还包括缓冲层103，所述缓冲层103层叠设置于所述遮光层102上，所述低温多晶硅层104、所述源极107、所述漏极108以及所述第一导电层112通过所述缓冲层103及所述遮光层102设置于所述基板101的表面上。所述缓冲等103用于缓冲所述阵列基板10的制备过程中对所述基板101的损伤。
所述阵列基板10还包括第一欧姆接触层105，所述第一欧姆接触层105连接所述源极107与所述低温多晶硅层104，所述第一欧姆接触层105用于降低所述源极107与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第一欧姆接触层105包括第一重掺杂区域1051和第一轻掺杂区域1052。所述第一重掺杂区域1051一端与所述源极107相连，另一端与所述第一轻掺杂区域1052相连，所述第一轻掺杂区域1052的另一端与所述低温多晶硅层104的一端相连。所述第一重掺杂区域1051的一端与所述源极107部分层叠设置，以增加所述第一重掺杂区域1051与所述源极107的接触面积。所述第一重掺杂区域1051与所述第一轻掺杂区域1052掺杂的离子类型相同，比如可以同掺杂N型离子，所述第一重掺杂区域1051的掺杂浓度大于所述第一轻掺杂区域1052的掺杂浓度。本实施方式中的所述第一重掺杂区域1051及所述第一轻掺杂区域1052的设置既能够降低所述源极107与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
所述阵列基板10还包括第二欧姆接触层106，所述第二欧姆接触层106连接所述漏极108与所述低温多晶硅层104，所述第二欧姆接触层106用于降低所述漏极108与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第二欧姆接触层106包括第二重掺杂区域1061和第二轻掺杂区域1062。所述第二重掺杂区域1061一端与所述漏极108相连，另一端连接所述第二轻掺杂区域1062相连，所述第二轻掺杂区域1062的另一端与所述低温多晶硅层104的一端相连。所述第二重掺杂区域1061的一端与所述漏极108部分层叠设置，以增加所述第二重掺杂区域1061与所述漏极108的接触面积。所述第 二重掺杂区域1061与所述第二轻掺杂区域1062掺杂的离子类型相同，比如可以同掺杂N型离子，所述第二重掺杂区域1061的掺杂浓度大于所述第二轻掺杂区域1062的掺杂浓度。本实施方式中的所述第二重掺杂区域1061及所述第二轻掺杂区域1062的设置既能够降低所述漏极108与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
下面结合图1对本发明的阵列基板的制备方法进行介绍。请参阅图3，所述阵列基板的制备方法包括但不仅限于如下步骤。
步骤S101，提供一基板101。请参阅图4，所述基板101包括第一表面a及与所述第一表面a相对设置的第二表面b。在本实施方式中，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第一表面a上。可以理解地，在其他实施方式中，低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第二表面b上。所述基板101可以为但不仅限于为玻璃基板。
步骤S102，在所述基板101的表面形成遮光层102。请参阅图5，在本实施方式中，在所述基板101的第一表面a的中部形成遮光层102。在其他实施方式中，也可以在所述基板101的第二表面b的中部形成遮光层102。所述遮光层102可以通过如下方式形成。首先，在所述基板101的第一表面a上形成一整层的遮光层，对所述一整层的遮光层进行曝光、显影、蚀刻为指定的图案，以作为所述遮光层102。在本实施方式中，用到一次光罩，为了方便描述，此步骤中用到的光罩成为第一次光罩。在本实施方式中，所述遮光层102设置于所述基板101的第一表面a上。所述遮光层102用于防止所述低温多晶硅薄膜晶体管对应像素朝向所述第二表面b漏光。
步骤S103，在所述遮光层102上形成缓冲层103。请参阅图6，在所述遮光层102上及所述基板101的未设置所述遮光层102的表面形成一整层的缓冲层103。所述缓冲层103用于缓冲所述阵列基板10的制备过程中对所述基板101的损伤。
步骤S104，形成低温多晶硅层104、源极107、漏极108以及第一导电层112，所述低温多晶硅层104对应所述基板101的表面的中部设置，所述源极107及所述漏极108设置于所述低温多晶硅层104的两侧，且所述源极107的 一端电连接所述低温多晶硅层104的一端，所述漏极108的一端连接所述低温多晶硅层104的另一端，所述漏极108的另一端电连接所述第一导电层112。
请一并参阅图7，首先在所述缓冲层103上形成第一导电层112，所述第一导电层112设置在未覆盖所述遮光层102的缓冲层103上。所述缓冲层103的可以通过如下方式形成。首先，在所述缓冲层103上形成一整层的导电层，对所述一整层的导电层进行曝光、显影以及蚀刻成指定的图案，以形成所述第一导电层112。所述第一导电层112作为像素电极。在所述第一导电层112的形成过程中用到一次光罩，为了方便描述，所述第一导电层112形成时用到的光罩称为第二次光罩。
请一并参阅图8，在所述缓冲层103上形成源极107和漏极108。所述源极107及所述漏极108分别对应所述遮光层102的两端设置。所述源极107和所述漏极108的形成可以通过如下方式形成。首先，在所述缓冲层103上形成一整层的金属层，对所述一整层的金属层进行曝光、显影以及蚀刻成指定的图案，以形成所述源极107和所漏极108。在所述源极107和所述漏极108的形成过程中用到了一次光罩，为了方便描述，所述源极107及所述漏极108形成时用到的光罩称为第三次光罩。
请一并参阅图9，在所述缓冲层103上形成低温多晶硅层104，所述低温多晶硅层104设置于源极107和漏极108之间，且所述低温多晶硅层104的两端分别与所述源极107和所述漏极108相连。所述缓冲层104的形成可以通过如下方式形成。首先在所述缓冲层103上形成一整层的低温多晶硅，对所述一整层的低温多晶硅层进行曝光、显影以及蚀刻成指定的形状以形成所述低温多晶硅层104。在所述低温多晶硅层104的形成过程中用到了一次光罩，为了方便描述，所述低温多晶硅层104形成时用到的光罩称为第四次光罩。
步骤S105，形成绝缘层109，所述绝缘层109形成在所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112上。请一并参阅图10。
步骤S106，形成栅极110，所述栅极110设置在所述绝缘层109上。请一并参阅图11，所述栅极110可以通过如下方式形成。首先，在所述绝缘层109上设置一整层的金属层，对所述一整层的金属层进行曝光、显影以及蚀刻成指 定的形状以形成所述栅极110。在所述栅极110的形成过程中用到了一次光罩，为了方便描述，形成所述栅极110时用到的光罩称为第五次光罩。
步骤S107，形成第一欧姆接触层105，所述第一欧姆接触层105连接所述源极107及所述低温多晶硅层104。请参阅图12，关于第一欧姆接触层105的形成请参阅前面的描述，在此不再赘述。
步骤S108，形成第二欧姆接触层106，所述第二欧姆接触层106连接所述漏极108及所述低温多晶硅层104。请参阅图13，关于第二欧姆接触层106的形成请参阅前面的描述，在此不再赘述。
步骤S109，形成钝化层111，所述钝化层111设置在所述栅极110上。请参阅图14，在所述钝化层111上形成贯孔1111，所述贯孔1111的也需要一道光罩，此光罩称为第六次光罩。
步骤S110，形成第二导电层113，所述第二导电层113设置于所述钝化层111上且对应所述第一导电层112设置，其中，所述第一到电层112为像素电极，所述第二导电层113为公共电极。请参阅图15，所述第二导电层113的形成可以通过如下方式形成。首先在所述钝化层111上形成一整层的导电层，对所述一整层的导电层进行曝光、显影以及蚀刻成指定的形状以形成所述第二导电层113。在所述第二导电层113的形成时需要一道光罩，为了方便描述，此次光罩称为第七次光罩。
通过对本发明阵列基板的制备方法的描述可见，本发明的阵列基板及阵列基板的制备方法只需要七道光罩就能完成，从而减少了所述阵列基板的形成时所用到的光罩的数量，有利于所述阵列基板的产能的提高。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (14)

  1. 一种阵列基板，其中，所述阵列基板包括呈矩阵分布的多个低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括：
    基板；
    设置在所述基板同一表面的低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端电连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
    绝缘层，所述绝缘层设置于所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层上；
    栅极，所述栅极设置于所述绝缘层上且对应所述低温多晶硅层设置；
    钝化层，所述钝化层层叠设置于所述栅极上；以及
    第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括遮光层，所述遮光层设置于所述基板的表面，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述遮光层设置于所述基板的表面，且所述遮光层对应所述低温多晶硅层设置。
  3. 如权利要求2所述的阵列基板，其中，所述阵列基板还包括缓冲层，所述缓冲层层叠设置于所述遮光层上，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层及所述遮光层设置于所述基板的表面上。
  4. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层，所述第一欧姆接触层用于降低所述源极与所述低温多晶硅层之间的接触电阻。
  5. 如权利要求4所述的阵列基板，其中，所述阵列基板还包括第二欧姆接触层，所述第二欧姆接触层连接所述漏极与所述低温多晶硅层，所述第二欧姆接触层用于降低所述漏极与所述低温多晶硅层之间的接触电阻。
  6. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括呈矩阵分布的多个低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括：
    基板；
    设置在所述基板同一表面的低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端电连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
    绝缘层，所述绝缘层设置于所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层上；
    栅极，所述栅极设置于所述绝缘层上且对应所述低温多晶硅层设置；
    钝化层，所述钝化层层叠设置于所述栅极上；以及
    第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
  7. 如权利要求6所述的显示面板，其中，所述阵列基板还包括遮光层，所述遮光层设置于所述基板的表面，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述遮光层设置于所述基板的表面，且所述遮光层对应所述低温多晶硅层设置。
  8. 如权利要求7所述的显示面板，其中，所述阵列基板还包括缓冲层，所述缓冲层层叠设置于所述遮光层上，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层及所述遮光层设置于所述基板的表面上。
  9. 如权利要求6所述的显示面板，其中，所述阵列基板还包括第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层，所述第一欧姆接触层用于降低所述源极与所述低温多晶硅层之间的接触电阻。
  10. 如权利要求9所述的显示面板，其中，所述阵列基板还包括第二欧姆接触层，所述第二欧姆接触层连接所述漏极与所述低温多晶硅层，所述第二欧姆接触层用于降低所述漏极与所述低温多晶硅层之间的接触电阻。
  11. 一种阵列基板的制备方法，其中，所述阵列基板的制备方法包括：
    提供一基板；
    在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
    形成绝缘层，所述绝缘层形成在所述低温多晶硅层、所述源极、所述漏极及所述第一导电层上；
    形成栅极，所述栅极设置在所述绝缘层上；
    形成钝化层，所述钝化层设置在所述栅极上；
    形成第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
  12. 如权利要求11所述的阵列基板的制备方法，其中，在所述步骤“提供一基板”以及所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之间，所述阵列基板的制备方法还包括：
    在所述基板的表面上形成遮光层；
    所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
    在所述遮光层上设置所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层。
  13. 如权利要求12所述的薄膜晶体管的制备方法，其中，在所述步骤“在所述基板的表面上形成遮光层”之后，在所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之前还包括：
    在所述遮光层上形成缓冲层；
    所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
    所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层设置在所述基板的表面上。
  14. 如权利要求11所述的阵列基板的制备方法，其中，所述阵列基板的制备方法还包括：
    形成第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层；
    形成第二欧姆接触层，所述第二欧姆接触层连接所述漏极及所述低温多晶硅层。
PCT/CN2015/071168 2014-12-30 2015-01-21 阵列基板、显示面板及阵列基板的制备方法 WO2016106892A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US14/435,468 US9530800B2 (en) 2014-12-30 2015-01-21 Array substrate, display panel and method for preparing array substrate
KR1020177019782A KR101999907B1 (ko) 2014-12-30 2015-01-21 어레이 기판, 디스플레이 패널, 및 어레이 기판의 제조 방법
JP2017534675A JP6570640B2 (ja) 2014-12-30 2015-01-21 配列基板と、表示パネルと、配列基板の調製方法
GB1710274.0A GB2548759B (en) 2014-12-30 2015-01-21 Array substrate, display panel, and manufacturing method for array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410849415.6A CN104600080B (zh) 2014-12-30 2014-12-30 阵列基板、显示面板及阵列基板的制备方法
CN201410849415.6 2014-12-30

Publications (1)

Publication Number Publication Date
WO2016106892A1 true WO2016106892A1 (zh) 2016-07-07

Family

ID=53125739

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/071168 WO2016106892A1 (zh) 2014-12-30 2015-01-21 阵列基板、显示面板及阵列基板的制备方法

Country Status (6)

Country Link
US (1) US9530800B2 (zh)
JP (1) JP6570640B2 (zh)
KR (1) KR101999907B1 (zh)
CN (1) CN104600080B (zh)
GB (1) GB2548759B (zh)
WO (1) WO2016106892A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105789279A (zh) * 2016-03-11 2016-07-20 深圳市华星光电技术有限公司 薄膜晶体管、液晶显示面板及薄膜晶体管的制备方法
CN105845693A (zh) * 2016-03-28 2016-08-10 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板
KR102484382B1 (ko) 2018-03-09 2023-01-04 삼성디스플레이 주식회사 유기 발광 표시 장치
US10826026B2 (en) 2018-04-23 2020-11-03 Samsung Display Co., Ltd. Display device and manufacturing method thereof
US10916617B2 (en) 2018-05-04 2021-02-09 Samsung Display Co., Ltd. Display device
US11910664B2 (en) 2018-06-15 2024-02-20 Samsung Display Co., Ltd. Display device
KR102523400B1 (ko) 2018-08-07 2023-04-20 삼성디스플레이 주식회사 표시 장치
KR20200029681A (ko) 2018-09-10 2020-03-19 삼성디스플레이 주식회사 표시장치
CN109378298B (zh) 2018-10-10 2022-04-29 京东方科技集团股份有限公司 显示背板及其制作方法和显示装置
KR20200047898A (ko) 2018-10-26 2020-05-08 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치
KR102656469B1 (ko) 2019-07-09 2024-04-12 삼성디스플레이 주식회사 유기 발광 표시 장치의 화소, 및 유기 발광 표시 장치
US11705063B2 (en) 2019-08-08 2023-07-18 Samsung Display Co., Ltd. Display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101105615A (zh) * 2006-06-29 2008-01-16 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
US20090096978A1 (en) * 2007-10-16 2009-04-16 Samsung Electronics Co., Ltd. Liquid crystal display
CN101738813A (zh) * 2008-11-25 2010-06-16 乐金显示有限公司 电泳显示器件及其制造方法
CN102799014A (zh) * 2012-09-07 2012-11-28 深圳市华星光电技术有限公司 液晶显示面板的制作方法
CN103529608A (zh) * 2012-07-04 2014-01-22 乐金显示有限公司 用于液晶显示设备的阵列基板及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW575777B (en) * 2001-03-30 2004-02-11 Sanyo Electric Co Active matrix type display device
US6534350B2 (en) * 2001-08-02 2003-03-18 Industrial Technology Research Institute Method for fabricating a low temperature polysilicon thin film transistor incorporating channel passivation step
US6692983B1 (en) * 2002-08-01 2004-02-17 Chih-Chiang Chen Method of forming a color filter on a substrate having pixel driving elements
TWI227565B (en) 2003-04-16 2005-02-01 Au Optronics Corp Low temperature poly-Si thin film transistor and method of manufacturing the same
TW200830426A (en) * 2007-01-12 2008-07-16 Xu-Xin Chen Method for fabricating a bottom-gate low-temperature polysilicon thin film transistor
CN101894807B (zh) 2009-05-22 2012-11-21 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
WO2011070929A1 (en) * 2009-12-11 2011-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
CN102651403A (zh) * 2012-04-16 2012-08-29 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法和显示面板
KR101353284B1 (ko) 2012-04-25 2014-01-21 엘지디스플레이 주식회사 액정 디스플레이 장치와 이의 제조방법
CN103018974B (zh) * 2012-11-30 2016-05-25 京东方科技集团股份有限公司 液晶显示装置、多晶硅阵列基板及制作方法
CN103076703B (zh) * 2012-12-28 2015-11-25 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制造方法
CN103700706B (zh) * 2013-12-16 2015-02-18 京东方科技集团股份有限公司 薄膜晶体管制备方法和阵列基板制备方法
CN103985637B (zh) * 2014-04-30 2017-02-01 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及其制作方法和显示装置
US9437435B2 (en) * 2014-11-11 2016-09-06 Shenzhen China Star Optoelectronics Technology Co., Ltd. LTPS TFT having dual gate structure and method for forming LTPS TFT

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101105615A (zh) * 2006-06-29 2008-01-16 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
US20090096978A1 (en) * 2007-10-16 2009-04-16 Samsung Electronics Co., Ltd. Liquid crystal display
CN101738813A (zh) * 2008-11-25 2010-06-16 乐金显示有限公司 电泳显示器件及其制造方法
CN103529608A (zh) * 2012-07-04 2014-01-22 乐金显示有限公司 用于液晶显示设备的阵列基板及其制造方法
CN102799014A (zh) * 2012-09-07 2012-11-28 深圳市华星光电技术有限公司 液晶显示面板的制作方法

Also Published As

Publication number Publication date
KR101999907B1 (ko) 2019-07-12
US20160190171A1 (en) 2016-06-30
JP6570640B2 (ja) 2019-09-04
GB2548759B (en) 2021-07-28
CN104600080B (zh) 2018-10-19
GB201710274D0 (en) 2017-08-09
US9530800B2 (en) 2016-12-27
CN104600080A (zh) 2015-05-06
GB2548759A (en) 2017-09-27
JP2018503869A (ja) 2018-02-08
KR20170096007A (ko) 2017-08-23

Similar Documents

Publication Publication Date Title
WO2016106892A1 (zh) 阵列基板、显示面板及阵列基板的制备方法
WO2016086531A1 (zh) 阵列基板及其制作方法
US11049889B2 (en) Method for preparing array substrate by stripping first photo-resist layer through wet etching before forming ohm contact layer and active layer
WO2017128565A1 (zh) 低温多晶硅阵列基板的制作方法
JP6359650B2 (ja) アレイ基板、表示装置及びアレイ基板の製作方法
US10409115B2 (en) Liquid crystal display panel, array substrate and manufacturing method thereof
US20210225883A1 (en) Ltps array substrate and method for manufacturing same
WO2018214732A1 (zh) 阵列基板及其制备方法、显示装置
US11106070B2 (en) Array substrate and manufacturing method of the same and display panel
US20170301705A1 (en) Ltps pixel unit and manufacturing method for the same
CN108598086B (zh) Tft阵列基板的制作方法及tft阵列基板
TWI383502B (zh) 畫素結構及其製造方法
KR101963066B1 (ko) Ltps tft 픽셀 유닛 및 그 제조 방법
CN105789325B (zh) 薄膜晶体管、薄膜晶体管的制备方法及cmos器件
WO2018119866A1 (zh) 一种低温多晶硅阵列基板及其制作方法
US9899425B2 (en) Array substrate and manufacturing method thereof
WO2017166337A1 (zh) 薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板
WO2020215547A1 (zh) Tft阵列基板及其制作方法
US20170141139A1 (en) Ltps array substrate and method for producing the same
CN106252277B (zh) 低温多晶硅薄膜晶体管阵列基板、制作方法以及显示装置
US20210335850A1 (en) Display panel and manufacturing method thereof, and electronic equipment
US10192902B2 (en) LTPS array substrate
WO2015196627A1 (zh) 薄膜晶体管制作方法及阵列基板制作方法
CN117476662A (zh) 显示面板及其制作方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14435468

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15874585

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017534675

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 201710274

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20150121

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20177019782

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 15874585

Country of ref document: EP

Kind code of ref document: A1