WO2020215547A1 - Tft阵列基板及其制作方法 - Google Patents

Tft阵列基板及其制作方法 Download PDF

Info

Publication number
WO2020215547A1
WO2020215547A1 PCT/CN2019/102074 CN2019102074W WO2020215547A1 WO 2020215547 A1 WO2020215547 A1 WO 2020215547A1 CN 2019102074 W CN2019102074 W CN 2019102074W WO 2020215547 A1 WO2020215547 A1 WO 2020215547A1
Authority
WO
WIPO (PCT)
Prior art keywords
source
drain
sub
material film
electrode
Prior art date
Application number
PCT/CN2019/102074
Other languages
English (en)
French (fr)
Inventor
蒙艳红
江志雄
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020215547A1 publication Critical patent/WO2020215547A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to the field of display technology, in particular to a TFT array substrate and a manufacturing method thereof.
  • liquid crystal display devices Liquid Crystal Display, LCD
  • organic light emitting diode display devices Organic Light Flat panel display devices such as Emitting Display (OLED)
  • CRT cathode ray tube
  • the liquid crystal display device has many advantages such as thin body, power saving, and no radiation, and has been widely used.
  • liquid crystal display devices which include liquid crystal display panels and backlight modules (backlight module).
  • the LCD panel is composed of a color filter (CF) substrate, thin film transistor (Thin Film Transistor, TFT) array substrate, liquid crystal (Liquid) sandwiched between the color filter substrate and the thin film transistor array substrate Crystal, LC) and sealant frame (Sealant).
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules between two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates. The liquid crystal molecules are controlled to change direction by powering on or not, and the light of the backlight module Refraction produces a picture.
  • TFT array substrates of flat panel display devices including LCD and OLED display devices are mostly manufactured using 5-mask technology.
  • the process of fabricating a TFT array substrate using 5mask technology is as follows: please refer to Figure 1, provide a substrate 100, fabricate a gate 200 on the substrate 100, refer to Figure 2, fabricate a gate insulating layer on the gate 200 and the substrate 100 300.
  • An island-shaped bottom amorphous silicon (a-Si) layer 410 and an island-shaped doped amorphous silicon layer 420 are formed on the gate insulating layer 300 above the gate 200 from bottom to top, and then doped A metal material layer is formed on the hetero amorphous silicon layer 420 and the gate insulating layer 300, and the metal material layer and the doped amorphous silicon layer 420 are patterned, thereby forming two amorphous silicon layers 410 located on the bottom layer as shown in FIG.
  • the doped amorphous silicon layer 420 of the electrode contact block 421 and the drain contact block 422 and the metal material layer forming the source electrode 510 and the drain electrode 520 are patterned with two different masks, resulting in the source contact block 421 and the source
  • the contact resistance between the electrodes 510 and the contact resistance between the drain contact block 422 and the drain 520 are relatively large, resulting in a low on-state current of the TFT device in the manufactured TFT array substrate.
  • the purpose of the present invention is to provide a method for manufacturing a TFT array substrate, which can reduce the contact resistance of the contact interface between the source and the source contact block and the contact interface between the drain and the drain contact block, and improve the product performance.
  • Another object of the present invention is to provide a TFT array substrate, which can reduce the contact resistance of the contact interface between the source electrode and the source contact block and the contact interface between the drain electrode and the drain contact block, and improve the product performance.
  • the present invention first provides a method for manufacturing a TFT array substrate, which includes the following steps:
  • Step S1 Provide a substrate, and sequentially fabricate a gate electrode, a gate insulating layer, an underlying semiconductor material film, a doped semiconductor material film, and a first metal material film on the substrate;
  • Step S2 Use a photomask to pattern the bottom semiconductor material film, the doped semiconductor material film, and the first metal material film to form an island-shaped bottom semiconductor layer and island-shaped doped semiconductor layer arranged in sequence from bottom to top above the gate. Hetero semiconductor layer and island-shaped metal layer;
  • Step S3 forming a second metal material film on the gate insulating layer and the metal layer;
  • Step S4 the second metal material film, the metal layer and the doped semiconductor layer are patterned to form source contact blocks and drain contact blocks located above and spaced apart from the two ends of the bottom semiconductor layer, and the source contact blocks and drain contact blocks respectively.
  • the material of the bottom semiconductor material film is amorphous silicon, and the material of the doped semiconductor material film is ion-doped amorphous silicon.
  • the material of the doped semiconductor material film is amorphous silicon doped with N-type ions.
  • the thickness of the first sub-source is the same as the thickness of the first sub-drain
  • the thickness of the second sub-source is the same as the thickness of the second sub-drain
  • the thickness of the first sub-source is smaller than the thickness of the second sub-source.
  • the manufacturing method of the TFT array substrate further includes step S5, forming a passivation layer on the gate insulating layer, the source electrode and the drain electrode; and patterning the passivation layer to form a passivation layer located above one of the source electrode and the drain electrode.
  • Step S6 forming a pixel electrode on the passivation layer, the pixel electrode being in contact with one of the source and drain electrodes through the hole.
  • the present invention also provides a TFT array substrate including a substrate, a gate provided on the substrate, a gate insulating layer provided on the substrate and the gate, and an island provided on the gate insulating layer and located above the gate
  • the bottom semiconductor layer, the source contact block and the drain contact block arranged above and spaced apart on the two ends of the bottom semiconductor layer, and the source and drain respectively in contact with the source contact block and the drain contact block;
  • the source It includes a first sub-source located on the source contact block and a second sub-source in contact with the first sub-source.
  • the drain includes a first sub-drain located on the drain contact block and a first sub-source The second sub-drain contacted by the drain.
  • the material of the bottom semiconductor layer is amorphous silicon, and the material of the source contact block and the drain contact block is ion-doped amorphous silicon.
  • the material of the source contact block and the drain contact block is amorphous silicon doped with N-type ions.
  • the thickness of the first sub-source is the same as the thickness of the first sub-drain
  • the thickness of the second sub-source is the same as the thickness of the second sub-drain
  • the thickness of the first sub-source is smaller than the thickness of the second sub-source.
  • the TFT array substrate further includes a passivation layer provided on the gate insulating layer, source and drain electrodes, and pixel electrodes provided on the passivation layer; the passivation layer is provided with An upper via hole through which the pixel electrode contacts one of the source electrode and the drain electrode.
  • the manufacturing method of the TFT array substrate of the present invention is to sequentially fabricate the bottom semiconductor material film, the doped semiconductor material film, and the first metal material film on the gate insulating layer, and use a photomask to mask the bottom semiconductor material film ,
  • the doped semiconductor material film and the first metal material film are patterned to form the bottom semiconductor layer, the doped semiconductor layer and the metal layer which are sequentially arranged from bottom to top above the gate, and then are formed on the gate insulating layer and the metal layer
  • the second metal material film is used to pattern the second metal material film, metal layer and doped semiconductor layer to form source contact blocks, drain contact blocks, source and drain electrodes, which can reduce source and source contact blocks
  • the contact interface and the contact resistance of the contact interface between the drain and the drain contact block can improve product performance.
  • the TFT array substrate of the present invention can reduce the contact resistance of the contact interface between the source electrode and the source contact block and the contact interface between the drain electrode and the drain contact block, and improve the product performance.
  • 1 to 3 are schematic diagrams of manufacturing a TFT array substrate using 5mask technology in the prior art
  • step S1 is a schematic diagram of step S1 of the manufacturing method of the TFT array substrate of the present invention.
  • step S2 is a schematic diagram of step S2 of the manufacturing method of the TFT array substrate of the present invention.
  • step S3 is a schematic diagram of step S3 of the manufacturing method of the TFT array substrate of the present invention.
  • step S4 is a schematic diagram of step S4 of the manufacturing method of the TFT array substrate of the present invention.
  • step S5 is a schematic diagram of step S5 of the manufacturing method of the TFT array substrate of the present invention.
  • FIG. 10 is a schematic diagram of step S6 of the manufacturing method of the TFT array substrate of the present invention.
  • the present invention provides a method for manufacturing a TFT array substrate, including the following steps:
  • Step S1 referring to FIG. 5, a substrate 10 is provided, and a gate 20, a gate insulating layer 30, a bottom semiconductor material film 49, a doped semiconductor material film 59, and a first metal material film 67 are sequentially fabricated on the substrate 10.
  • the material of the underlying semiconductor material film 49 is undoped amorphous silicon
  • the material of the doped semiconductor material film 59 is ion-doped amorphous silicon.
  • the material of the doped semiconductor material film 59 is amorphous silicon doped with N-type ions.
  • Step S2 please refer to FIG. 6, using a photomask to pattern the bottom semiconductor material film 49, the doped semiconductor material film 59 and the first metal material film 67 to form an island-like shape which is arranged from bottom to top above the gate 20
  • the bottom semiconductor layer 40, the island-shaped doped semiconductor layer 58 and the island-shaped metal layer 68 please refer to FIG. 6, using a photomask to pattern the bottom semiconductor material film 49, the doped semiconductor material film 59 and the first metal material film 67 to form an island-like shape which is arranged from bottom to top above the gate 20
  • the bottom semiconductor layer 40, the island-shaped doped semiconductor layer 58 and the island-shaped metal layer 68 please refer to FIG. 6, using a photomask to pattern the bottom semiconductor material film 49, the doped semiconductor material film 59 and the first metal material film 67 to form an island-like shape which is arranged from bottom to top above the gate 20
  • the bottom semiconductor layer 40, the island-shaped doped semiconductor layer 58 and the island-shaped metal layer 68 please refer
  • the underlying semiconductor material film 49 and the doped semiconductor material film 59 are patterned by dry etching.
  • the first metal material film 67 can be designed to be thinner so that the first metal material The film 67 can be patterned by dry etching together with the underlying semiconductor material film 49 and the doped semiconductor material film 59.
  • Step S3 referring to FIG. 7, a second metal material film 69 is formed on the gate insulating layer 30 and the metal layer 68.
  • Step S4 referring to FIG. 8, the second metal material film 69, the metal layer 68, and the doped semiconductor layer 58 are patterned to form source contact blocks 51 and drain contacts located above and spaced apart from the two ends of the underlying semiconductor layer 40
  • the block 52 and the source 61 and the drain 62 contacting the source contact block 51 and the drain contact block 52 respectively.
  • the source 61 includes a first sub-source 611 on the source contact block 51 and a second sub-source 612 in contact with the first sub-source 611
  • the drain 62 includes a first sub-source 611 on the drain contact block 52
  • the first sub-drain 621 and the second sub-drain 622 in contact with the first sub-drain 621.
  • the source contact block 51 and the drain contact block 52 are formed by patterning the doped semiconductor layer 58, the first sub-source 611 and the first sub-drain 621 are formed by patterning the metal layer 68, and the second sub-source 612 And the second sub-drain 622 is formed by patterning the second metal material film 69.
  • the second metal material film 69 may be patterned to form the second sub-source 612 and the second sub-drain 622, and then the second sub-source 612 and the second sub-drain 622 is a shield to dry-etch the metal layer 68 and the doped semiconductor layer 58 to form a source contact block 51, a drain contact block 52, a first sub-source 611 and a first sub-drain 621.
  • the thickness of the first sub-source 611 is the same as the thickness of the first sub-drain 621
  • the thickness of the second sub-source 612 is the same as the thickness of the second sub-drain 622
  • the thickness of the first sub-source 611 is less than The thickness of the second sub-source 612.
  • Step S5 referring to FIG. 9, a passivation layer 70 is formed on the gate insulating layer 30, the source electrode 61 and the drain electrode 62.
  • the passivation layer 70 is patterned to form a via 71 located above one of the source 61 and the drain 62.
  • Step S5 referring to FIG. 10, a pixel electrode 80 is formed on the passivation layer 70, and the pixel electrode 80 contacts one of the source 61 and the drain 62 through the hole 71.
  • a bottom semiconductor material film 49, a doped semiconductor material film 59, and a first metal material film 67 are sequentially formed on the gate insulating layer 30, and a photomask is used for the bottom layer.
  • the semiconductor material film 49, the doped semiconductor material film 59, and the first metal material film 67 are patterned to form the bottom semiconductor layer 40, the doped semiconductor layer 58, and the metal layer 68, and then on the gate insulating layer 30 and the metal layer 68
  • a second metal material film 69 is formed, and the second metal material film 69, the metal layer 68 and the doped semiconductor layer 58 are patterned to form a source contact block 51, a drain contact block 52, a source 61 and a drain 62,
  • the source contact block 51 and the drain contact block 52 are formed by patterning the doped semiconductor layer 58, and the first sub-source 611 in the source 61 and the first sub-drain 621 in the drain 62 are patterned by the metal layer 68
  • the second sub-source 612 in the source 61 and the second sub-drain 622 in the drain 62 are patterned and formed by the second metal material film 69, so that the contact interface between the source 61 and the source contact block 51 and The characteristics of
  • the present invention also provides a TFT array substrate, which is manufactured by using the above-mentioned manufacturing method of a TFT array substrate.
  • the TFT array substrate includes a substrate 10 and a gate provided on the substrate 10. Pole 20, a gate insulating layer 30 provided on the substrate 10 and the gate 20, an island-shaped bottom semiconductor layer 40 disposed on the gate insulating layer 30 and above the gate 20, and disposed on both ends of the bottom semiconductor layer 40 The upper and spaced source contact block 51 and the drain contact block 52, and the source 61 and the drain 62 that are in contact with the source contact block 51 and the drain contact block 52, respectively.
  • the source 61 includes a first sub-source 611 on the source contact block 51 and a second sub-source 612 in contact with the first sub-source 611
  • the drain 62 includes a first sub-source 611 on the drain contact block 52
  • the first sub-drain 621 and the second sub-drain 622 in contact with the first sub-drain 621.
  • the material of the bottom semiconductor layer 40 is amorphous silicon
  • the material of the source contact block 51 and the drain contact block 52 is ion-doped amorphous silicon.
  • the material of the source contact block 51 and the drain contact block 52 is amorphous silicon doped with N-type ions.
  • the thickness of the first sub-source 611 is the same as the thickness of the first sub-drain 621
  • the thickness of the second sub-source 612 is the same as the thickness of the second sub-drain 622
  • the thickness of the first sub-source 611 is less than The thickness of the second sub-source 612.
  • the TFT array substrate further includes a passivation layer 70 provided on the gate insulating layer 30, the source electrode 61 and the drain electrode 62, and a pixel electrode 80 provided on the passivation layer 70.
  • the passivation layer 70 is provided with a via hole 71 located above one of the source electrode 61 and the drain electrode 62, and the pixel electrode 80 is in contact with one of the source electrode 61 and the drain electrode 62 through the hole 71.
  • the TFT array substrate of the present invention is manufactured by using the above-mentioned manufacturing method of the TFT array substrate, and the source 61 includes a first sub-source 611 and a first sub-source provided on the source contact block 51. 611 contacts the second sub-source 612, the drain 62 includes a first sub-drain 621 disposed on the drain contact block 52 and a second sub-drain 622 in contact with the first sub-drain 621, the source 61 and The characteristics of the contact interface of the source contact block 51 and the contact interface of the drain 62 and the drain contact layer 52 are not affected by the patterning process, and have a smaller contact resistance, so that the TFT device in the TFT array substrate of the present invention is The on-state current is higher and the product performance is better.
  • the bottom semiconductor material film, the doped semiconductor material film, and the first metal material film are sequentially fabricated on the gate insulating layer, and the bottom semiconductor material film,
  • the doped semiconductor material film and the first metal material film are patterned to form a bottom semiconductor layer, a doped semiconductor layer, and a metal layer that are sequentially arranged above the gate from bottom to top, and then a second layer is formed on the gate insulating layer and the metal layer.
  • Two metal material films patterning the second metal material film, metal layer and doped semiconductor layer to form source contact blocks, drain contact blocks, source and drain electrodes, which can reduce the source and source contact blocks
  • the contact resistance of the contact interface and the contact interface between the drain and the drain contact block improves product performance.
  • the TFT array substrate of the present invention can reduce the contact resistance of the contact interface between the source electrode and the source contact block and the contact interface between the drain electrode and the drain contact block, and improve the product performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种TFT阵列基板及其制作方法。本发明的TFT阵列基板的制作方法在栅极绝缘层上依次制作底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜，并利用一道光罩对底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜进行图案化，形成于栅极上方由下至上依次设置的底层半导体层、掺杂半导体层及金属层，而后在栅极绝缘层及金属层上形成第二金属材料膜，对第二金属材料膜、金属层及掺杂半导体层进行图案化，形成源极接触块、漏极接触块、源极及漏极，能够降低源极与源极接触块的接触界面及漏极与漏极接触块的接触界面的接触电阻，提高产品性能。

Description

TFT阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制作方法。
 背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD) 、有机发光二极管显示装置(Organic Light Emitting Display，OLED)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(Color Filter，CF)基板、薄膜晶体管(Thin Film Transistor，TFT)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal，LC)及密封胶框(Sealant)组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
现有的包括LCD及OLED显示装置在内的平板显示装置的TFT阵列基板的在制作时多采用5光罩（mask）技术。采用5mask技术制作TFT阵列基板的过程为：请参阅图1，提供衬底100，在衬底100上制作栅极200，请参阅图2，在栅极200及衬底100上制作栅极绝缘层300，在栅极绝缘层300上制作于栅极200上方由下至上依次设置的岛状的底层非晶硅（a-Si）层410及岛状的掺杂非晶硅层420，而后在掺杂非晶硅层420及栅极绝缘层300上形成金属材料层，对金属材料层及掺杂非晶硅层420进行图案化，从而如图3所示，形成位于底层非晶硅层410两端上且间隔的源极接触块421及漏极接触块422以及分别与源极接触块421及漏极接触块422连接的源极510及漏极520，采用5mask技术制作TFT阵列基板时形成源极接触块421及漏极接触块422的掺杂非晶硅层420及形成源极510及漏极520的金属材料层采用两道不同的光罩进行图案化，导致源极接触块421与源极510之间的接触电阻以及漏极接触块422与漏极520之间的接触电阻较大，导致制得的TFT阵列基板中TFT器件的开态电流偏低。
 技术问题
本发明的目的在于提供一种TFT阵列基板的制作方法，能够降低源极与源极接触块的接触界面及漏极与漏极接触块的接触界面的接触电阻，提高产品性能。
本发明的另一目的在于提供一种TFT阵列基板，能够降低源极与源极接触块的接触界面及漏极与漏极接触块的接触界面的接触电阻，提高产品性能。
 技术解决方案
为实现上述目的，本发明首先提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、提供衬底，在衬底上依次制作栅极、栅极绝缘层、底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜；
步骤S2、利用一道光罩对底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜进行图案化，形成于栅极上方由下至上依次设置的岛状的底层半导体层、岛状的掺杂半导体层及岛状的金属层；
步骤S3、在栅极绝缘层及金属层上形成第二金属材料膜；
步骤S4、对第二金属材料膜、金属层及掺杂半导体层进行图案化，形成位于底层半导体层两端上方且间隔的源极接触块及漏极接触块以及分别与源极接触块及漏极接触块接触的源极及漏极；所述源极包括位于源极接触块上的第一子源极及与第一子源极接触的第二子源极，所述漏极包括位于漏极接触块上的第一子漏极及与第一子漏极接触的第二子漏极。
所述底层半导体材料膜的材料为非晶硅，所述掺杂半导体材料膜的材料为经过离子掺杂的非晶硅。
所述掺杂半导体材料膜的材料为经过N型离子掺杂的非晶硅。
第一子源极的厚度与第一子漏极的厚度相同，第二子源极的厚度与第二子漏极的厚度相同，第一子源极的厚度小于第二子源极的厚度。
所述TFT阵列基板的制作方法还包括步骤S5、在栅极绝缘层、源极及漏极上形成钝化层；对钝化层进行图案化，形成位于源极及漏极中的一个上方的过孔；
步骤S6、在钝化层上制作像素电极，所述像素电极经过孔与源极漏极中的一个接触。
本发明还提供一种TFT阵列基板，包括衬底、设于衬底上的栅极、设于衬底及栅极上的栅极绝缘层、设于栅极绝缘层且位于栅极上方的岛状的底层半导体层、设于底层半导体层两端上方且间隔的源极接触块及漏极接触块以及分别与源极接触块及漏极接触块接触的源极及漏极；所述源极包括位于源极接触块上的第一子源极及与第一子源极接触的第二子源极，所述漏极包括位于漏极接触块上的第一子漏极及与第一子漏极接触的第二子漏极。
所述底层半导体层的材料为非晶硅，所述源极接触块及漏极接触块的材料为经过离子掺杂的非晶硅。
所述源极接触块及漏极接触块的材料为经过N型离子掺杂的非晶硅。
第一子源极的厚度与第一子漏极的厚度相同，第二子源极的厚度与第二子漏极的厚度相同，第一子源极的厚度小于第二子源极的厚度。
所述TFT阵列基板还包括设于栅极绝缘层、源极及漏极上的钝化层以及设于钝化层上的像素电极；所述钝化层设有位于源极及漏极中的一个上方的过孔，所述像素电极经过孔与源极及漏极中的一个接触。
 有益效果
本发明的有益效果：本发明的TFT阵列基板的制作方法在栅极绝缘层上依次制作底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜，并利用一道光罩对底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜进行图案化，形成于栅极上方由下至上依次设置的底层半导体层、掺杂半导体层及金属层，而后在栅极绝缘层及金属层上形成第二金属材料膜，对第二金属材料膜、金属层及掺杂半导体层进行图案化，形成源极接触块、漏极接触块、源极及漏极，能够降低源极与源极接触块的接触界面及漏极与漏极接触块的接触界面的接触电阻，提高产品性能。本发明的TFT阵列基板能够降低源极与源极接触块的接触界面及漏极与漏极接触块的接触界面的接触电阻，提高产品性能。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1至图3为现有技术中采用5mask技术制作TFT阵列基板的示意图；
图4为本发明的TFT阵列基板的制作方法的流程图；
图5为本发明的TFT阵列基板的制作方法的步骤S1的示意图；
图6为本发明的TFT阵列基板的制作方法的步骤S2的示意图；
图7为本发明的TFT阵列基板的制作方法的步骤S3的示意图；
图8为本发明的TFT阵列基板的制作方法的步骤S4的示意图；
图9为本发明的TFT阵列基板的制作方法的步骤S5的示意图；
图10为本发明的TFT阵列基板的制作方法的步骤S6的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4，本发明提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、请参阅图5，提供衬底10，在衬底10上依次制作栅极20、栅极绝缘层30、底层半导体材料膜49、掺杂半导体材料膜59及第一金属材料膜67。
具体地，所述底层半导体材料膜49的材料为未经掺杂的非晶硅，所述掺杂半导体材料膜59的材料为经过离子掺杂的非晶硅。
优选地，所述掺杂半导体材料膜59的材料为经过N型离子掺杂的非晶硅。
步骤S2、请参阅图6，利用一道光罩对底层半导体材料膜49、掺杂半导体材料膜59及第一金属材料膜67进行图案化，形成于栅极20上方由下至上依次设置的岛状的底层半导体层40、岛状的掺杂半导体层58及岛状的金属层68。
具体地，所述步骤S2中，采用干蚀刻的方式对底层半导体材料膜49、掺杂半导体材料膜59进行图案化，同时，第一金属材料膜67可以设计得较薄以使得第一金属材料膜67能够与底层半导体材料膜49、掺杂半导体材料膜59一起采用干蚀刻的方式进行图案化。
步骤S3、请参阅图7，在栅极绝缘层30及金属层68上形成第二金属材料膜69。
步骤S4、请参阅图8，对第二金属材料膜69、金属层68及掺杂半导体层58进行图案化，形成位于底层半导体层40两端上方且间隔的源极接触块51及漏极接触块52以及分别与源极接触块51及漏极接触块52接触的源极61及漏极62。所述源极61包括位于源极接触块51上的第一子源极611及与第一子源极611接触的第二子源极612，所述漏极62包括位于漏极接触块52上的第一子漏极621及与第一子漏极621接触的第二子漏极622。所述源极接触块51及漏极接触块52由掺杂半导体层58图案化形成，第一子源极611及第一子漏极621由金属层68图案化形成，第二子源极612及第二子漏极622由第二金属材料膜69图案化形成。
具体地，所述步骤S4中，可以先对第二金属材料膜69进行图案化形成第二子源极612及第二子漏极622，而后以第二子源极612及第二子漏极622为遮挡对金属层68及掺杂半导体层58进行干蚀刻，从而形成源极接触块51、漏极接触块52、第一子源极611及第一子漏极621。
优选地，第一子源极611的厚度与第一子漏极621的厚度相同，第二子源极612的厚度与第二子漏极622的厚度相同，第一子源极611的厚度小于第二子源极612的厚度。
步骤S5、请参阅图9，在栅极绝缘层30、源极61及漏极62上形成钝化层70。对钝化层70进行图案化，形成位于源极61及漏极62中的一个上方的过孔71。
步骤S5、请参阅图10，在钝化层70上制作像素电极80，所述像素电极80经过孔71与源极61漏极62中的一个接触。
需要说明的是，本发明的TFT阵列基板的制作方法在栅极绝缘层30上依次制作底层半导体材料膜49、掺杂半导体材料膜59及第一金属材料膜67，并利用一道光罩对底层半导体材料膜49、掺杂半导体材料膜59及第一金属材料膜67进行图案化，形成底层半导体层40、掺杂半导体层58及金属层68，而后在栅极绝缘层30及金属层68上形成第二金属材料膜69，对第二金属材料膜69、金属层68及掺杂半导体层58进行图案化，形成源极接触块51、漏极接触块52、源极61及漏极62，源极接触块51及漏极接触块52由掺杂半导体层58图案化形成，源极61中的第一子源极611及漏极62中的第一子漏极621由金属层68图案化形成，源极61中的第二子源极612及漏极62中的第二子漏极622由第二金属材料膜69图案化形成，使得源极61与源极接触块51的接触界面以及漏极62与漏极接触层52的接触界面的特性不受图案化制程的影响，具有较小的接触电阻，从而使得本发明制得的TFT阵列基板中TFT器件的开态电流较高，产品性能较好。
请参阅图10，基于同一发明构思，本发明还提供一种TFT阵列基板，采用上述的TFT阵列基板的制作方法制得，该TFT阵列基板，包括衬底10、设于衬底10上的栅极20、设于衬底10及栅极20上的栅极绝缘层30、设于栅极绝缘层30且位于栅极20上方的岛状的底层半导体层40、设于底层半导体层40两端上方且间隔的源极接触块51及漏极接触块52以及分别与源极接触块51及漏极接触块52接触的源极61及漏极62。所述源极61包括位于源极接触块51上的第一子源极611及与第一子源极611接触的第二子源极612，所述漏极62包括位于漏极接触块52上的第一子漏极621及与第一子漏极621接触的第二子漏极622。
具体地，所述底层半导体层40的材料为非晶硅，所述源极接触块51及漏极接触块52的材料为经过离子掺杂的非晶硅。
优选地，所述源极接触块51及漏极接触块52的材料为经过N型离子掺杂的非晶硅。
优选地，第一子源极611的厚度与第一子漏极621的厚度相同，第二子源极612的厚度与第二子漏极622的厚度相同，第一子源极611的厚度小于第二子源极612的厚度。
具体地，所述TFT阵列基板还包括设于栅极绝缘层30、源极61及漏极62上的钝化层70以及设于钝化层70上的像素电极80。所述钝化层70设有位于源极61及漏极62中的一个上方的过孔71，所述像素电极80经过孔71与源极61及漏极62中的一个接触。
需要说明的是，本发明的TFT阵列基板由于采用上述的TFT阵列基板的制作方法制得，源极61包括设置在源极接触块51上的第一子源极611及与第一子源极611接触的第二子源极612，漏极62包括设置在漏极接触块52上的第一子漏极621及与第一子漏极621接触的第二子漏极622，源极61与源极接触块51的接触界面以及漏极62与漏极接触层52的接触界面的特性不受图案化制程的影响，具有较小的接触电阻，从而使得本发明的TFT阵列基板中TFT器件的开态电流较高，产品性能较好。
综上所述，本发明的TFT阵列基板的制作方法在栅极绝缘层上依次制作底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜，并利用一道光罩对底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜进行图案化，形成于栅极上方由下至上依次设置的底层半导体层、掺杂半导体层及金属层，而后在栅极绝缘层及金属层上形成第二金属材料膜，对第二金属材料膜、金属层及掺杂半导体层进行图案化，形成源极接触块、漏极接触块、源极及漏极，能够降低源极与源极接触块的接触界面及漏极与漏极接触块的接触界面的接触电阻，提高产品性能。本发明的TFT阵列基板能够降低源极与源极接触块的接触界面及漏极与漏极接触块的接触界面的接触电阻，提高产品性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤S1、提供衬底，在衬底上依次制作栅极、栅极绝缘层、底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜；
    步骤S2、利用一道光罩对底层半导体材料膜、掺杂半导体材料膜及第一金属材料膜进行图案化，形成于栅极上方由下至上依次设置的岛状的底层半导体层、岛状的掺杂半导体层及岛状的金属层；
    步骤S3、在栅极绝缘层及金属层上形成第二金属材料膜；
    步骤S4、对第二金属材料膜、金属层及掺杂半导体层进行图案化，形成位于底层半导体层两端上方且间隔的源极接触块及漏极接触块以及分别与源极接触块及漏极接触块接触的源极及漏极；所述源极包括位于源极接触块上的第一子源极及与第一子源极接触的第二子源极，所述漏极包括位于漏极接触块上的第一子漏极及与第一子漏极接触的第二子漏极。
  2. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述底层半导体材料膜的材料为非晶硅，所述掺杂半导体材料膜的材料为经过离子掺杂的非晶硅。
  3. 如权利要求2所述的TFT阵列基板的制作方法，其中，所述掺杂半导体材料膜的材料为经过N型离子掺杂的非晶硅。
  4. 如权利要求1所述的TFT阵列基板的制作方法，其中，第一子源极的厚度与第一子漏极的厚度相同，第二子源极的厚度与第二子漏极的厚度相同，第一子源极的厚度小于第二子源极的厚度。
  5. 如权利要求1所述的TFT阵列基板的制作方法，还包括步骤S5、在栅极绝缘层、源极及漏极上形成钝化层；对钝化层进行图案化，形成位于源极及漏极中的一个上方的过孔；
    步骤S6、在钝化层上制作像素电极，所述像素电极经过孔与源极漏极中的一个接触。
  6. 一种TFT阵列基板，包括衬底、设于衬底上的栅极、设于衬底及栅极上的栅极绝缘层、设于栅极绝缘层且位于栅极上方的岛状的底层半导体层、设于底层半导体层两端上方且间隔的源极接触块及漏极接触块以及分别与源极接触块及漏极接触块接触的源极及漏极；所述源极包括位于源极接触块上的第一子源极及与第一子源极接触的第二子源极，所述漏极包括位于漏极接触块上的第一子漏极及与第一子漏极接触的第二子漏极。
  7. 如权利要求6所述的TFT阵列基板，其中，所述底层半导体层的材料为非晶硅，所述源极接触块及漏极接触块的材料为经过离子掺杂的非晶硅。
  8. 如权利要求7所述的TFT阵列基板，其中，所述源极接触块及漏极接触块的材料为经过N型离子掺杂的非晶硅。
  9. 如权利要求6所述的TFT阵列基板，其中，第一子源极的厚度与第一子漏极的厚度相同，第二子源极的厚度与第二子漏极的厚度相同，第一子源极的厚度小于第二子源极的厚度。
  10. 如权利要求6所述的TFT阵列基板，还包括设于栅极绝缘层、源极及漏极上的钝化层以及设于钝化层上的像素电极；所述钝化层设有位于源极及漏极中的一个上方的过孔，所述像素电极经过孔与源极及漏极中的一个接触。
PCT/CN2019/102074 2019-04-22 2019-08-22 Tft阵列基板及其制作方法 WO2020215547A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910325701.5A CN109979877A (zh) 2019-04-22 2019-04-22 Tft阵列基板及其制作方法
CN201910325701.5 2019-04-22

Publications (1)

Publication Number Publication Date
WO2020215547A1 true WO2020215547A1 (zh) 2020-10-29

Family

ID=67085747

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/102074 WO2020215547A1 (zh) 2019-04-22 2019-08-22 Tft阵列基板及其制作方法

Country Status (2)

Country Link
CN (1) CN109979877A (zh)
WO (1) WO2020215547A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979877A (zh) * 2019-04-22 2019-07-05 深圳市华星光电半导体显示技术有限公司 Tft阵列基板及其制作方法
CN113113427A (zh) * 2021-03-23 2021-07-13 Tcl华星光电技术有限公司 阵列基板及其制备方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090212288A1 (en) * 2008-02-25 2009-08-27 Joo-Han Kim Thin film transistor, display device including the same, and method of manufacturing the display device
CN108573928A (zh) * 2018-04-13 2018-09-25 深圳市华星光电技术有限公司 一种tft阵列基板的制备方法及tft阵列基板、显示面板
CN108598086A (zh) * 2018-04-20 2018-09-28 武汉华星光电技术有限公司 Tft阵列基板的制作方法及tft阵列基板
CN109979877A (zh) * 2019-04-22 2019-07-05 深圳市华星光电半导体显示技术有限公司 Tft阵列基板及其制作方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100920483B1 (ko) * 2007-07-20 2009-10-08 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조방법
KR101294235B1 (ko) * 2008-02-15 2013-08-07 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090212288A1 (en) * 2008-02-25 2009-08-27 Joo-Han Kim Thin film transistor, display device including the same, and method of manufacturing the display device
CN108573928A (zh) * 2018-04-13 2018-09-25 深圳市华星光电技术有限公司 一种tft阵列基板的制备方法及tft阵列基板、显示面板
CN108598086A (zh) * 2018-04-20 2018-09-28 武汉华星光电技术有限公司 Tft阵列基板的制作方法及tft阵列基板
CN109979877A (zh) * 2019-04-22 2019-07-05 深圳市华星光电半导体显示技术有限公司 Tft阵列基板及其制作方法

Also Published As

Publication number Publication date
CN109979877A (zh) 2019-07-05

Similar Documents

Publication Publication Date Title
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
US10268082B2 (en) Display panel and method of manufacturing the same, and display device
WO2017136967A1 (zh) 阵列基板的制作方法及阵列基板
WO2017147974A1 (zh) 阵列基板的制作方法及制得的阵列基板
KR101999907B1 (ko) 어레이 기판, 디스플레이 패널, 및 어레이 기판의 제조 방법
WO2016086531A1 (zh) 阵列基板及其制作方法
WO2016086539A1 (zh) 液晶面板及其制作方法
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
KR20180098621A (ko) 저온 폴리실리콘 어레이 기판의 제조방법
KR20040082796A (ko) 횡전계형 액정표시장치 및 그 제조방법
KR102314509B1 (ko) Tft 기판의 제조 방법 및 tft 기판
US10971530B2 (en) Manufacturing method for a TFT array substrate and TFT array substrate
KR101788488B1 (ko) 박막 트랜지스터 어레이 기판의 제조방법
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
WO2020093442A1 (zh) 阵列基板的制作方法及阵列基板
WO2020215547A1 (zh) Tft阵列基板及其制作方法
WO2021120378A1 (zh) 一种阵列基板及其制作方法
CN108598086B (zh) Tft阵列基板的制作方法及tft阵列基板
WO2024139870A1 (zh) 阵列基板及其制备方法、显示面板
US20210335849A1 (en) Tft array substrate, fabricating method thereof and display panel having the tft array substrate
WO2017181464A1 (zh) Tft阵列基板及其制作方法
KR20120076221A (ko) 산화물 반도체를 포함한 박막 트랜지스터 기판
WO2016161700A1 (zh) 一种薄膜晶体管阵列基板及其制造方法
US11411101B2 (en) Manufacturing method of TFT substrate
US10714514B2 (en) Back-channel-etched TFT substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19926697

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19926697

Country of ref document: EP

Kind code of ref document: A1