WO2015196627A1 - 薄膜晶体管制作方法及阵列基板制作方法 - Google Patents

薄膜晶体管制作方法及阵列基板制作方法 Download PDF

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WO2015196627A1
WO2015196627A1 PCT/CN2014/088386 CN2014088386W WO2015196627A1 WO 2015196627 A1 WO2015196627 A1 WO 2015196627A1 CN 2014088386 W CN2014088386 W CN 2014088386W WO 2015196627 A1 WO2015196627 A1 WO 2015196627A1
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forming
layer
contact resistance
drain
gate
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刘翔
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation

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  • Embodiments of the present invention relate to a method of fabricating a thin film transistor and a method of fabricating an array substrate.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • Metal oxide TFT is a new technology in recent years. It has large on-state current, high mobility, good uniformity, transparency, simple fabrication process, and can better meet the requirements of large-size liquid crystal displays and active organic electroluminescent displays. Demand has received much attention.
  • the on-state current of the metal oxide TFT is more than 50 times that of the amorphous silicon TFT, and the off-state current is generally between 10 -11 A and 10 -12 A.
  • the current off-state current (also called leakage current) cannot maintain the voltage applied to the liquid crystal display pixels at low frequencies (such as 1 Hz), so the off-state current must be lowered to make the off-state current below 10 -13 .
  • a method of fabricating a thin film transistor comprises the following steps:
  • a pattern including a source and a drain is formed, the source and the drain connecting the contact resistance region via the first via and the second via.
  • the ion implantation dose of the doping is from 10 15 /cm 2 to 10 16 /cm 2 .
  • the doped ion energy is from 30 keV to 100 keV.
  • the method further includes performing an annealing process on the contact resistance region.
  • the annealing process has an annealing temperature of 350 ° C to 500 ° C.
  • the method before forming the first via and the second via, before forming the source and the drain, the method further includes: performing plasma treatment on the first via and the second via.
  • the plasma treatment is performed using a N 2 O plasma.
  • a method of fabricating an array substrate includes the method of fabricating an array substrate as described above.
  • FIG. 1 is a schematic structural view showing formation of an isolation layer and a metal oxide semiconductor layer in a method of fabricating a thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view showing a gate insulating layer and a gate electrode formed on the basis of FIG. 1;
  • FIG. 3 is a schematic view of the metal oxide semiconductor layer doped on the basis of FIG. 2;
  • FIG. 4 is a schematic view showing the formation of a first insulating spacer layer and via holes thereon on the basis of FIG. 3;
  • Figure 5 is a schematic view showing the structure of forming a source and a drain on the basis of Figure 4;
  • FIG. 6 is a schematic view showing formation of a second insulating spacer layer and via holes thereon in the method of fabricating an array substrate according to an embodiment of the present invention
  • Fig. 7 is a schematic view showing the formation of a pixel electrode on the basis of Fig. 6.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor. As shown in FIG. 1 to 6, the manufacturing method includes the following steps:
  • Step One as shown in FIG. 1, a pattern including the isolation layer 2 and the metal oxide semiconductor layer 3 is formed on the base substrate 1.
  • the thickness of the substrate is continuously deposited by PECVD on the substrate.
  • the isolation layer 2 the isolation layer 2 may be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
  • the reaction gases corresponding to silicon oxide are: N 2 O and SiH 4 ;
  • the reaction gases corresponding to silicon oxynitride may be: N 2 O, SiH 4 , NH 3 and N 2 ;
  • the reaction gas may be SiH 4 , NH 3 and N 2 (or SiH 2 Cl 2 , NH 3 and N 2 ).
  • the thickness is deposited on the spacer layer 2 by sputtering or thermal evaporation.
  • the metal oxide semiconductor layer 3 may be IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In 2 O 3 :Sn, In 2 O 3 :Mo, Cd 2 SnO 4 , ZnO:Al, Made of TiO 2 : Nb, Cd-Sn-O or other metal oxides.
  • the pattern of the metal oxide semiconductor layer 3 is formed by a first patterning process including a photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • Step 2 as shown in FIG. 2, a pattern including the gate insulating layer 4 and the gate electrode 13 is formed on the substrate on which the step 1 is completed.
  • the gate insulating layer 4 may be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
  • the thickness of the gate insulating layer 4 by sputtering or thermal evaporation is about
  • the gate metal layer and the gate metal may be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu.
  • the gate metal layer may have a single layer structure or a multilayer structure.
  • the gate electrode 13 is formed by a second patterning process. For example, the gate lines of the array substrate may be formed while the gate electrodes 13 are formed.
  • Step 3 as shown in FIG. 3, the non-gate corresponding region of the MOS layer 3 is doped with the gate electrode 13 as a occlusion to form the contact resistance region 5.
  • the dose to be implanted is from 10 15 /cm 2 to 10 16 /cm 2 and the ion energy is from about 30 to 100 keV. It should be noted that the dose and energy of ion implantation can be appropriately adjusted according to the thickness of the gate insulating layer and the like. If N-doping is performed, for example, PH 3 can be used. If P+ doping is performed, for example, B 2 H 6 can be used.
  • Step 4 forming a pattern including the first insulating spacer layer 6 and the first via hole 71 and the second via hole 72 therein on the substrate on which the step 3 is completed as shown in FIG. 4 to expose the source and the drain and the contact The area where the resistance zone 5 is connected.
  • the first insulating spacer layer 6, the first insulating spacer layer 6 may be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
  • the first via 71 and the second via 72 are respectively formed by the third patterning process, and the source and drain are connected to the contact resistance region 5 via the first via 71 and the second via 72.
  • Step 5 as shown in FIGS. 5-6, a pattern including the source 8 and the drain 9 is formed on the substrate on which the step 4 is completed.
  • first deposit thickness by sputtering or thermal evaporation The source/drain metal layer and the source/drain metal may be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, and the like.
  • the source/drain metal layer may be a single layer or a plurality of layers.
  • the source 8 and the drain 9 are formed by a four-time patterning process. For example, while the source electrode 8 and the drain electrode 9 are formed, a data scan line (not shown) of the array substrate may be formed.
  • the source 8 and the drain 9 are connected to the contact resistance region 5 (ie, the active layer is connected) through the first via 71 and the second via 72, respectively.
  • a method of fabricating an array substrate includes the method of fabricating the thin film transistor as described above.
  • the method for fabricating the array substrate includes the following steps in addition to the steps 1 to 5 above:
  • Step 6 as shown in FIGS. 6-7, a pattern including the second insulating spacer layer 10 and the pixel electrode 12 is formed on the substrate on which the step 5 is completed.
  • the thickness of the continuous deposition using the PECVD method is The second protective layer 10, the second protective layer may be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. Then, through the fifth patterning process, a third via hole 11 is formed through which the pixel electrode is connected to the drain electrode 9.
  • the thickness is deposited, for example by sputtering or thermal evaporation.
  • the transparent conductive layer, the transparent conductive layer may be ITO or IZO, or other transparent metal oxide.
  • the pixel electrode 12 is formed by the sixth patterning process, and the pixel electrode 12 is connected to the drain electrode 9 through the third via hole 11.
  • the gate electrode is used as an occlusion to protect the metal oxide of the channel, and the contact resistance region is formed by doping, thereby reducing the off-state current of the thin film transistor (TFT). So that at low refresh frequencies, the TFT can still stay plus The voltage of the pixel is displayed in the liquid crystal.
  • TFT thin film transistor
  • a high-temperature annealing process may be performed before the formation of the first insulating spacer layer 6 after doping to activate the doped ions.
  • the annealing temperature can be controlled between 350 ° C and 500 ° C.
  • the high-temperature annealing can move the doped ions to the lattice position, and can also reduce the defects of the semiconductor layer to improve the stability of the device.
  • the method further comprises: performing plasma treatment on the first via 71 and the second via 72, such as N 2 O plasma treatment was performed.
  • plasma treatment such as N 2 O plasma treatment was performed.

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Abstract

一种薄膜晶体管制作方法和阵列基板制作方法。该薄膜晶体管制作方法包括如下步骤：在衬底基板上形成包括隔离层和金属氧化物半导体层的图形；形成包括栅绝缘层及栅极的图形；以所述栅极为遮挡对所述金属氧化物半导体层的非栅极对应区域进行掺杂，以形成接触电阻区；形成包括第一绝缘间隔层及其中的第一过孔和第二过孔的图形，以暴露出源极和漏极与接触电阻区连接的区域；形成包括源极和漏极的图形，所述源极和漏极经由所述第一过孔和第二过孔连接所述接触电阻区。

Description

薄膜晶体管制作方法及阵列基板制作方法 技术领域
本发明的实施例涉及一种薄膜晶体管制作方法及阵列基板制作方法。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)具有体积小、功耗低、无辐射等特点，在当前的平板显示器市场中占据了主导地位。
金属氧化物TFT是最近几年新兴的技术，其开态电流大、迁移率高，均一性好，透明，制作工艺简单，可以更好地满足大尺寸液晶显示器和有源有机电致发光显示器的需求，备受人们的关注。金属氧化物TFT的开态电流是非晶硅TFT的50倍以上，关态电流一般在10-11A到10-12A之间。
为了降低液晶显示面板的功耗，需要在静态画面时采用低刷新频率。但是以目前的关态电流(也称：漏电流)在低频(如1Hz)下不能保持加在液晶显示像素的电压，所以必须降低关态电流，使关态电流在10-13以下。
发明内容
根据本发明的实施例，提供一种薄膜晶体管制作方法。该方法包括如下步骤：
在衬底基板上形成包括隔离层和金属氧化物半导体层的图形；
形成包括栅绝缘层及栅极的图形；
以所述栅极为遮挡对所述金属氧化物半导体层的非栅极对应区域进行掺杂，以形成接触电阻区；
形成包括第一绝缘间隔层及其中的第一过孔和第二过孔的图形，以暴露出源极和漏极与接触电阻区连接的区域；
形成包括源极和漏极的图形，所述源极和漏极经由所述第一过孔和第二过孔连接所述接触电阻区。
例如，所述掺杂的离子注入剂量为1015/cm2～1016/cm2。
例如，所述掺杂的离子能量为30keV～100keV。
例如，在进行掺杂之后，形成第一绝缘间隔层之前，所述方法还包括对所述接触电阻区进行退火工艺处理。
例如，所述退火工艺的退火温度为350℃～500℃。
例如，在形成所述第一过孔和第二过孔之后，形成源极和漏极之前，所述还包括：对所述第一过孔和第二过孔进行等离子体处理。
例如，采用N2O等离子体进行所述等离子体处理。
根据本发明的实施例，提供一种阵列基板制作方法。该方法包括如上所述的阵列基板制作方法。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是本发明实施例的薄膜晶体管制作方法中形成隔离层和金属氧化物半导体层的结构示意图；
图2是在图1的基础上形成栅绝缘层和栅极后的结构示意图；
图3是在图2的基础上对金属氧化物半导体层进行掺杂后的示意图；
图4是在图3的基础上形成第一绝缘间隔层及其上的过孔的示意图；
图5是在图4的基础上形成源极和漏极的结构示意图；
图6是在本发明实施例的阵列基板制作方法中形成第二绝缘间隔层及其上过孔的示意图；以及
图7是在图6的基础上形成像素电极的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的实施例提供一种薄膜晶体管的制作方法。如图1～6所示，该制作方法包括如下步骤：
步骤一，如图1所示，在衬底基板1上形成包括隔离层2和金属氧化物半导体层3的图形。
例如，在基板上通过PECVD方法连续沉积厚度为
Figure PCTCN2014088386-appb-000001
的隔离层2，隔离层2可以为氧化硅、氮化硅、氮氧化硅或它们的组合。在形成隔离层2时，氧化硅对应的反应气体为：N2O和SiH4；氮氧化硅对应的反应气体可以为：N2O、SiH4、NH3和N2；氮化硅对应的反应气体可以为SiH4、NH3和N2(或者SiH2Cl2、NH3和N2)。
然后，例如，在隔离层2上通过溅射或热蒸发的方法沉积厚度约为
Figure PCTCN2014088386-appb-000002
Figure PCTCN2014088386-appb-000003
的金属氧化物半导体层3。金属氧化物半导体层3可以是采用IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成。通过第一次构图工艺(包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺)形成金属氧化物半导体层3的图形。
步骤二，如图2所示，在完成步骤一的基板上形成包括栅绝缘层4及栅极13的图形。
例如，通过PECVD方法连续沉积厚度为
Figure PCTCN2014088386-appb-000004
的栅绝缘层4，栅绝缘层4可以为氧化硅、氮化硅、氮氧化硅或它们的组合。
例如，在栅绝缘层4上采用溅射或热蒸发的方法依积厚度约为
Figure PCTCN2014088386-appb-000005
Figure PCTCN2014088386-appb-000006
的栅金属层，栅金属可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金。栅金属层可以具有单层结构或多层结构。通过第二次构图工艺形成栅极13。例如，在形成栅极13的同时，还可以形成阵列基板的栅极线。
步骤三，如图3所示，以栅极13为遮挡对金属氧化物半导体层3的非栅极对应区域进行掺杂，以形成接触电阻区5。
由于离子注入是在栅绝缘层淀积之后，因此，需要进行高能量和高剂量注入，才能达到对源漏电极区进行掺杂的目的。例如，注入的剂量在1015/cm2～1016/cm2，离子能量在30～100keV左右。需要说明的是，离子注入的剂量和能量可以根据栅绝缘层的厚度等情况进行适当的调整。如果进行N－掺杂，例如可使用PH3。如果进行P+掺杂，例如可使用B2H6。
步骤四，如图4所示在完成步骤三的基板上形成包括第一绝缘间隔层6及其中的第一过孔71和第二过孔72的图形，以暴露出源极和漏极与接触电阻区5连接的区域。
例如，通过PECVD方法连续沉积厚度为
Figure PCTCN2014088386-appb-000007
的第一绝缘间隔层6，第一绝缘间隔层6可以为氧化硅、氮化硅、氮氧化硅或它们的组合。通过第三次构图工艺，分别形成第一过孔71和第二过孔72，经由第一过孔71和第二过孔72，源极和漏极连接到接触电阻区5。
步骤五，如图5～6所示，在完成步骤四的基板上形成包括源极8和漏极9的图形。
例如，先通过溅射或热蒸发的方法沉积厚度
Figure PCTCN2014088386-appb-000008
源/漏金属层，源/漏金属可以选用Cr、W、Ti、Ta、Mo、等金属或合金。源/漏金属层可以是单层也可以是多层。通过四次构图工艺形成源极8、漏极9。例如，在形成源极8、漏极9的同时，还可以形成阵列基板的数据扫描线(图中未示出)。源极8和漏极9分别通过第一过孔71和第二过孔72连接接触电阻区5(即连接有源层)。
根据本发明的实施例，还提供一种阵列基板的制作方法。该阵列基板的制作方法包括如上所述的薄膜晶体管的制作方法。例如，该阵列基板的制作方法除了包括上述步骤一至五之外，还包括如下步骤：
步骤六，如图6～7所示，在完成步骤五的基板上形成包括第二绝缘间隔层10和像素电极12的图形。
例如，采用PECVD方法连续沉积厚度为
Figure PCTCN2014088386-appb-000009
的第二保护层10，第二保护层可以为氧化硅、氮化硅、氮氧化硅或它们的组合。然后通过第五次构图工艺，形成第三过孔11，经由该第三过孔11，像素电极与漏极9连接。
最后，例如通过溅射或热蒸发的方法沉积厚度约为
Figure PCTCN2014088386-appb-000010
的透明导电层，透明导电层可以是ITO或者IZO，或者其他的透明金属氧化物。通过第六次构图工艺形成像素电极12，使像素电极12通过第三过孔11连接漏极9。
本实施例的薄膜晶体管制作方法和阵列基板制作方法中，利用栅电极作为遮挡，保护沟道的金属氧化物，通过掺杂形成接触电阻区，从而降低了薄膜晶体管(TFT)的关态电流，使得在低刷新频率下，TFT仍然能够保持加 在液晶显示像素的电压。
例如，为了提高金属氧化物的性能及掺杂离子的活性，可以在进行掺杂之后，形成第一绝缘间隔层6之前进行一次高温退火工艺，使掺杂的离子激活。例如，退火的温度可控制在350℃～500℃之间。高温退火除了提升掺杂离子的活性，使掺杂的离子移到晶格位置外，还可以减少半导体层的缺陷，以提升器件的稳定性。
例如，在形成所述第一过孔71和第二过孔72之后，形成源极8和漏极9之前还包括：对上述第一过孔71和第二过孔72进行等离子体处理，如进行N2O等离子体处理。由此，可以降低源极8、漏极9分别与接触电阻区5接触电阻，提升开态电流。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年6月25日递交的第201410295139.3号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (8)

  1. 一种薄膜晶体管制作方法，包括如下步骤：
    在衬底基板上形成包括隔离层和金属氧化物半导体层的图形；
    形成包括栅绝缘层及栅极的图形；
    以所述栅极为遮挡对所述金属氧化物半导体层的非栅极对应区域进行掺杂，以形成接触电阻区；
    形成包括第一绝缘间隔层及其中的第一过孔和第二过孔的图形，以暴露出源极和漏极与接触电阻区连接的区域；
    形成包括源极和漏极的图形，所述源极和漏极经由所述第一过孔和第二过孔连接所述接触电阻区。
  2. 如权利要求1所述的方法，其中所述掺杂的离子注入剂量为1015/cm2～1016/cm2。
  3. 如权利要求1或2所述的方法，其中所述掺杂的离子能量为30keV～100keV。
  4. 如权利要求1～3中任一项所述的方法，其中在进行掺杂之后，形成第一绝缘间隔层之前，所述方法还包括对所述接触电阻区进行退火工艺处理。
  5. 如权利要求4所述的方法，其中所述退火工艺的退火温度为350℃～500℃。
  6. 如权利要求1～5中任一项所述的方法，其中在形成所述第一过孔和第二过孔之后，形成源极和漏极之前，所述还包括：对所述第一过孔和第二过孔进行等离子体处理。
  7. 根据权利要求4所述的方法，其中采用N2O等离子体进行所述等离子体处理。
  8. 一种阵列基板制作方法，包括权利要求1～7任一项所述的薄膜晶体管制作方法。
PCT/CN2014/088386 2014-06-25 2014-10-11 薄膜晶体管制作方法及阵列基板制作方法 WO2015196627A1 (zh)

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