CN104600080A - 阵列基板、显示面板及阵列基板的制备方法 - Google Patents

阵列基板、显示面板及阵列基板的制备方法 Download PDF

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CN104600080A
CN104600080A CN201410849415.6A CN201410849415A CN104600080A CN 104600080 A CN104600080 A CN 104600080A CN 201410849415 A CN201410849415 A CN 201410849415A CN 104600080 A CN104600080 A CN 104600080A
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polycrystalline silicon
layer
temperature polycrystalline
low
silicon layer
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CN104600080B (zh
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王聪
杜鹏
陈黎暄
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201410849415.6A priority Critical patent/CN104600080B/zh
Priority to US14/435,468 priority patent/US9530800B2/en
Priority to JP2017534675A priority patent/JP6570640B2/ja
Priority to PCT/CN2015/071168 priority patent/WO2016106892A1/zh
Priority to GB1710274.0A priority patent/GB2548759B/en
Priority to KR1020177019782A priority patent/KR101999907B1/ko
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Abstract

本发明提供一种阵列基板、显示面板及阵列基板的制备方法。阵列基板包括呈矩阵分布的多个低温多晶硅薄膜晶体管，低温多晶硅薄膜晶体管包括：基板；设置在基板同一表面的低温多晶硅层、源极、漏极以及第一导电层，低温多晶硅层设置于基板的表面的中部，源极及漏极设置于低温多晶硅层的两侧，且源极的一端电连接低温多晶硅层的一端，漏极的一端电连接低温多晶硅层的另一端，漏极的另一端电连接第一导电层；绝缘层，绝缘层设置于低温多晶硅层、源极、漏极以及第一导电层上；栅极，栅极设置于绝缘层上且对应低温多晶硅层设置；钝化层，层叠设置于栅极上；以及第二导电层，第二导电层设置于钝化层上且对应第一导电层设置。

Description

阵列基板、显示面板及阵列基板的制备方法
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板、显示面板及阵列基板的制备方法。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。随着平面显示技术的发展，具有高分辨率、低能耗的液晶显示器的需求被提出。非晶硅的电子迁移率较低，而低温多晶硅(Low Temperature Ploy-silicon)可以在低温下制作，且拥有比非晶硅更高的电子迁移率。其次，低温多晶硅制作的CMOS器件可应用于使液晶显示器具有更高的分辨率和低能耗。因此，低温多晶硅得到了广泛地应用和研究。目前，包括低温多晶硅薄膜晶体管的阵列基板由于低温多晶硅中的光罩次数较多，一般而言，所述低温多晶硅薄膜晶体阵列基板的光罩次数为十次，从而造成低温多晶硅薄膜晶体管阵列基板的制备较为困难，且不利于产能的提高。
发明内容
本发明提供一种阵列基板，所述阵列基板包括呈矩阵分布的多个低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括：
基板；
设置在所述基板同一表面的低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端电连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
绝缘层，所述绝缘层设置于所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层上；
栅极，所述栅极设置于所述绝缘层上且对应所述低温多晶硅层设置；
钝化层，所述钝化层层叠设置于所述栅极上；以及
第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
其中，所述阵列基板还包括遮光层，所述遮光层设置于所述基板的表面，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述遮光层设置于所述基板的表面，且所述遮光层对应所述低温多晶硅层设置。
其中，所述阵列基板还包括缓冲层，所述缓冲层层叠设置于所述遮光层上，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层及所述遮光层设置于所述基板的表面上。
其中，所述阵列基板还包括第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层，所述第一欧姆接触层用于降低所述源极与所述低温多晶硅层之间的接触电阻。
其中，所述阵列基板还包括第二欧姆接触层，所述第二欧姆接触层连接所述漏极与所述低温多晶硅层，所述第二欧姆接触层用于降低所述漏极与所述低温多晶硅层之间的接触电阻。
另一方面本发明提供了一种显示面板，所述显示面板包括上述各个实施方式中任意一种实施方式的阵列基板。
另一方面，本发明还提供了阵列基板的制备方法，所述阵列基板的制备方法包括：
提供一基板；
在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
形成绝缘层，所述绝缘层形成在所述低温多晶硅层、所述源极、所述漏极及所述第一导电层上；
形成栅极，所述栅极设置在所述绝缘层上；
形成钝化层，所述钝化层设置在所述栅极上；
形成第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
其中，在所述步骤“提供一基板”以及所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之间，所述阵列基板的制备方法还包括：
在所述基板的表面上形成遮光层；
所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
在所述遮光层上设置所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层。
其中，在所述步骤“在所述基板的表面上形成遮光层”之后，在所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之前还包括：
在所述遮光层上形成缓冲层；
所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层设置在所述基板的表面上。
其中，所述阵列基板的制备方法还包括：
形成第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层；
形成第二欧姆接触层，所述第二欧姆接触层连接所述漏极及所述低温多晶硅层。
本发明的阵列基板及阵列基板的制备方法只需要七道光罩就能完成，从而减少了所述阵列基板的形成时所用到的光罩的数量，有利于所述阵列基板的产能的提高。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。
图2为本发明一较佳实施方式的显示面板的结构示意图。
图3为本发明一较佳实施方式的阵列基板的制备方法的流程图。
图4至图15为本发明阵列基板的制备方法中各个步骤对应的制程的剖面图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。所述阵列基板10包括基板101、低温多晶硅层104、源极107、漏极108、第一导电层112、绝缘层109、栅极110、钝化层111以及第二导电层113。所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的同一表面。所述低温多晶硅层104设置于所述基板101的表面的中部，所述源极107及所述漏极108设置于所述低温多晶硅层104的两侧，且所述源极107的一端电连接所述低温多晶硅层104的一端，所述漏极108的一端电连接所述低温多晶硅层104的另一端，所述漏极108的另一端电连接所述第一导电层112。所述绝缘层109设置于所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112上。所述栅极110设置于所述绝缘层109上且对应所述低温多晶硅层104设置。所述钝化层111设置于所述栅极110上。所述第二导电层113设置于所述钝化层111上且对应所述第一导电层112设置。其中，所述第一导电层112为像素电极，所述第二导电层113为公共电极。所述低温多晶硅层104、所述源极107、所述漏极108、所述绝缘层109及所述栅极110构成了低温多晶硅薄膜晶体管。
所述基板101包括第一表面a及与所述第一表面a相对设置的第二表面b。在本实施方式中，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第一表面a上。可以理解地，在其他实施方式中，低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第二表面b上。所述基板101可以为但不仅限于为玻璃基板。
所述阵列基板10还包括遮光层102，所述遮光层102设置于所述基板101的表面，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112通过所述遮光层102设置于所述基板101的表面，且所述遮光层102对应所述低温多晶硅层104设置。在本实施方式中，所述遮光层102设置于所述基板101的第一表面a上。所述遮光层102用于防止所述低温多晶硅薄膜晶体管对应像素朝向所述第二表面b漏光。
所述阵列基板10还包括缓冲层103，所述缓冲层103层叠设置于所述遮光层102上，所述低温多晶硅层104、所述源极107、所述漏极108以及所述第一导电层112通过所述缓冲层103及所述遮光层102设置于所述基板101的表面上。所述缓冲层103用于缓冲所述阵列基板10的制备过程中对所述基板101的损伤。
所述阵列基板10还包括第一欧姆接触层105，所述第一欧姆接触层105连接所述源极107与所述低温多晶硅层104，所述第一欧姆接触层105用于降低所述源极107与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第一欧姆接触层105包括第一重掺杂区域1051和第一轻掺杂区域1052。所述第一重掺杂区域1051一端与所述源极107相连，另一端与所述第一轻掺杂区域1052相连，所述第一轻掺杂区域1052的另一端与所述低温多晶硅层104的一端相连。所述第一重掺杂区域1051的一端与所述源极107部分层叠设置，以增加所述第一重掺杂区域1051与所述源极107的接触面积。所述第一重掺杂区域1051与所述第一轻掺杂区域1052掺杂的离子类型相同，比如可以同掺杂N型离子，所述第一重掺杂区域1051的掺杂浓度大于所述第一轻掺杂区域1052的掺杂浓度。本实施方式中的所述第一重掺杂区域1051及所述第一轻掺杂区域1052的设置既能够降低所述源极107与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
所述阵列基板10还包括第二欧姆接触层106，所述第二欧姆接触层106连接所述漏极108与所述低温多晶硅层104，所述第二欧姆接触层106用于降低所述漏极108与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第二欧姆接触层106包括第二重掺杂区域1061和第二轻掺杂区域1062。所述第二重掺杂区域1061一端与所述漏极108相连，另一端连接所述第二轻掺杂区域1062相连，所述第二轻掺杂区域1062的另一端与所述低温多晶硅层104的一端相连。所述第二重掺杂区域1061的一端与所述漏极108部分层叠设置，以增加所述第二重掺杂区域1061与所述漏极108的接触面积。所述第二重掺杂区域1061与所述第二轻掺杂区域1062掺杂的离子类型相同，比如可以同掺杂N型离子，所述第二重掺杂区域1061的掺杂浓度大于所述第二轻掺杂区域1062的掺杂浓度。本实施方式中的所述第二重掺杂区域1061及所述第二轻掺杂区域1062的设置既能够降低所述漏极108与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
下面结合图1对本发明的显示面板进行介绍。请参阅图2，图2为本发明一较佳实施方式的显示面板的结构示意图。所述显示面板1包括阵列基板10、彩色滤光基板20及液晶层30。所述阵列基板10与所述彩色滤光基板20相对设置，所述液晶层30设置在所述阵列基板10和所述彩色滤光基板20之间。所述阵列基板10包括基板101、低温多晶硅层104、源极107、漏极108、第一导电层112、绝缘层109、栅极110、钝化层111以及第二导电层113。所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的同一表面。所述低温多晶硅层104设置于所述基板101的表面的中部，所述源极107及所述漏极108设置于所述低温多晶硅层104的两侧，且所述源极107的一端电连接所述低温多晶硅层104的一端，所述漏极108的一端电连接所述低温多晶硅层104的另一端，所述漏极108的另一端电连接所述第一导电层112。所述绝缘层109设置于所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112上。所述栅极110设置于所述绝缘层109上且对应所述低温多晶硅侧呢过104设置。所述钝化层111设置于所述栅极110上。所述第二导电层113设置于所述钝化层111上且对应所述第一导电层112设置。其中，所述第一导电层112为像素电极，所述第二导电层113为公共电极。所述低温多晶硅层104、所述源极107、所述漏极108、所述绝缘层109及所述栅极110构成了低温多晶硅薄膜晶体管。
所述基板101包括第一表面a及与所述第一表面a相对设置的第二表面b。在本实施方式中，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第一表面a上。可以理解地，在其他实施方式中，低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第二表面b上。所述基板101可以为但不仅限于为玻璃基板。
所述阵列基板10还包括遮光层102，所述遮光层102设置于所述基板101的表面，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112通过所述这广场设置于所述基板101的表面，且所述遮光层102对应所述低温多晶硅层104设置。在本实施方式中，所述遮光层102设置于所述基板101的第一表面a上。所述遮光层102用于防止所述低温多晶硅薄膜晶体管对应像素朝向所述第二表面b漏光。
所述阵列基板10还包括缓冲层103，所述缓冲层103层叠设置于所述遮光层102上，所述低温多晶硅层104、所述源极107、所述漏极108以及所述第一导电层112通过所述缓冲层103及所述遮光层102设置于所述基板101的表面上。所述缓冲等103用于缓冲所述阵列基板10的制备过程中对所述基板101的损伤。
所述阵列基板10还包括第一欧姆接触层105，所述第一欧姆接触层105连接所述源极107与所述低温多晶硅层104，所述第一欧姆接触层105用于降低所述源极107与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第一欧姆接触层105包括第一重掺杂区域1051和第一轻掺杂区域1052。所述第一重掺杂区域1051一端与所述源极107相连，另一端与所述第一轻掺杂区域1052相连，所述第一轻掺杂区域1052的另一端与所述低温多晶硅层104的一端相连。所述第一重掺杂区域1051的一端与所述源极107部分层叠设置，以增加所述第一重掺杂区域1051与所述源极107的接触面积。所述第一重掺杂区域1051与所述第一轻掺杂区域1052掺杂的离子类型相同，比如可以同掺杂N型离子，所述第一重掺杂区域1051的掺杂浓度大于所述第一轻掺杂区域1052的掺杂浓度。本实施方式中的所述第一重掺杂区域1051及所述第一轻掺杂区域1052的设置既能够降低所述源极107与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
所述阵列基板10还包括第二欧姆接触层106，所述第二欧姆接触层106连接所述漏极108与所述低温多晶硅层104，所述第二欧姆接触层106用于降低所述漏极108与所述低温多晶硅层104之间的接触电阻。在本实施方式中，所述第二欧姆接触层106包括第二重掺杂区域1061和第二轻掺杂区域1062。所述第二重掺杂区域1061一端与所述漏极108相连，另一端连接所述第二轻掺杂区域1062相连，所述第二轻掺杂区域1062的另一端与所述低温多晶硅层104的一端相连。所述第二重掺杂区域1061的一端与所述漏极108部分层叠设置，以增加所述第二重掺杂区域1061与所述漏极108的接触面积。所述第二重掺杂区域1061与所述第二轻掺杂区域1062掺杂的离子类型相同，比如可以同掺杂N型离子，所述第二重掺杂区域1061的掺杂浓度大于所述第二轻掺杂区域1062的掺杂浓度。本实施方式中的所述第二重掺杂区域1061及所述第二轻掺杂区域1062的设置既能够降低所述漏极108与所述低温多晶硅层104之间的接触电阻，又能够减小所述低温多晶硅薄膜晶体管的泄露电流。
下面结合图1对本发明的阵列基板的制备方法进行介绍。请参阅图3，所述阵列基板的制备方法包括但不仅限于如下步骤。
步骤S101，提供一基板101。请参阅图4，所述基板101包括第一表面a及与所述第一表面a相对设置的第二表面b。在本实施方式中，所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第一表面a上。可以理解地，在其他实施方式中，低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112设置在所述基板101的第二表面b上。所述基板101可以为但不仅限于为玻璃基板。
步骤S102，在所述基板101的表面形成遮光层102。请参阅图5，在本实施方式中，在所述基板101的第一表面a的中部形成遮光层102。在其他实施方式中，也可以在所述基板101的第二表面b的中部形成遮光层102。所述遮光层102可以通过如下方式形成。首先，在所述基板101的第一表面a上形成一整层的遮光层，对所述一整层的遮光层进行曝光、显影、蚀刻为指定的图案，以作为所述遮光层102。在本实施方式中，用到一次光罩，为了方便描述，此步骤中用到的光罩成为第一次光罩。在本实施方式中，所述遮光层102设置于所述基板101的第一表面a上。所述遮光层102用于防止所述低温多晶硅薄膜晶体管对应像素朝向所述第二表面b漏光。
步骤S103，在所述遮光层102上形成缓冲层103。请参阅图6，在所述遮光层102上及所述基板101的未设置所述遮光层102的表面形成一整层的缓冲层103。所述缓冲层103用于缓冲所述阵列基板10的制备过程中对所述基板101的损伤。
步骤S104，形成低温多晶硅层104、源极107、漏极108以及第一导电层112，所述低温多晶硅层104对应所述基板101的表面的中部设置，所述源极107及所述漏极108设置于所述低温多晶硅层104的两侧，且所述源极107的一端电连接所述低温多晶硅层104的一端，所述漏极108的一端连接所述低温多晶硅层104的另一端，所述漏极108的另一端电连接所述第一导电层112。
请一并参阅图7，首先在所述缓冲层103上形成第一导电层112，所述第一导电层112设置在未覆盖所述遮光层102的缓冲层103上。所述缓冲层103的可以通过如下方式形成。首先，在所述缓冲层103上形成一整层的导电层，对所述一整层的导电层进行曝光、显影以及蚀刻成指定的图案，以形成所述第一导电层112。所述第一导电层112作为像素电极。在所述第一导电层112的形成过程中用到一次光罩，为了方便描述，所述第一导电层112形成时用到的光罩称为第二次光罩。
请一并参阅图8，在所述缓冲层103上形成源极107和漏极108。所述源极107及所述漏极108分别对应所述遮光层102的两端设置。所述源极107和所述漏极108的形成可以通过如下方式形成。首先，在所述缓冲层103上形成一整层的金属层，对所述一整层的金属层进行曝光、显影以及蚀刻成指定的图案，以形成所述源极107和所漏极108。在所述源极107和所述漏极108的形成过程中用到了一次光罩，为了方便描述，所述源极107及所述漏极108形成时用到的光罩称为第三次光罩。
请一并参阅图9，在所述缓冲层103上形成低温多晶硅层104，所述低温多晶硅层104设置于源极107和漏极108之间，且所述低温多晶硅层104的两端分别与所述源极107和所述漏极108相连。所述缓冲层104的形成可以通过如下方式形成。首先在所述缓冲层103上形成一整层的低温多晶硅，对所述一整层的低温多晶硅层进行曝光、显影以及蚀刻成指定的形状以形成所述低温多晶硅层104。在所述低温多晶硅层104的形成过程中用到了一次光罩，为了方便描述，所述低温多晶硅层104形成时用到的光罩称为第四次光罩。
步骤S105，形成绝缘层109，所述绝缘层109形成在所述低温多晶硅层104、所述源极107、所述漏极108及所述第一导电层112上。请一并参阅图10。
步骤S106，形成栅极110，所述栅极110设置在所述绝缘层109上。请一并参阅图11，所述栅极110可以通过如下方式形成。首先，在所述绝缘层109上设置一整层的金属层，对所述一整层的金属层进行曝光、显影以及蚀刻成指定的形状以形成所述栅极110。在所述栅极110的形成过程中用到了一次光罩，为了方便描述，形成所述栅极110时用到的光罩称为第五次光罩。
步骤S107，形成第一欧姆接触层105，所述第一欧姆接触层105连接所述源极107及所述低温多晶硅层104。请参阅图12，关于第一欧姆接触层105的形成请参阅前面的描述，在此不再赘述。
步骤S108，形成第二欧姆接触层106，所述第二欧姆接触层106连接所述漏极108及所述低温多晶硅层104。请参阅图13，关于第二欧姆接触层106的形成请参阅前面的描述，在此不再赘述。
步骤S109，形成钝化层111，所述钝化层111设置在所述栅极110上。请参阅图14，在所述钝化层111上形成贯孔1111，所述贯孔1111的也需要一道光罩，此光罩称为第六次光罩。
步骤S110，形成第二导电层113，所述第二导电层113设置于所述钝化层111上且对应所述第一导电层112设置，其中，所述第一到电层112为像素电极，所述第二导电层113为公共电极。请参阅图15，所述第二导电层113的形成可以通过如下方式形成。首先在所述钝化层111上形成一整层的导电层，对所述一整层的导电层进行曝光、显影以及蚀刻成指定的形状以形成所述第二导电层113。在所述第二导电层113的形成时需要一道光罩，为了方便描述，此次光罩称为第七次光罩。
通过对本发明阵列基板的制备方法的描述可见，本发明的阵列基板及阵列基板的制备方法只需要七道光罩就能完成，从而减少了所述阵列基板的形成时所用到的光罩的数量，有利于所述阵列基板的产能的提高。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

1.一种阵列基板，其特征在于，所述阵列基板包括呈矩阵分布的多个低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括：
基板；
设置在所述基板同一表面的低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端电连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
绝缘层，所述绝缘层设置于所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层上；
栅极，所述栅极设置于所述绝缘层上且对应所述低温多晶硅层设置；
钝化层，所述钝化层层叠设置于所述栅极上；以及
第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
2.如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括遮光层，所述遮光层设置于所述基板的表面，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述遮光层设置于所述基板的表面，且所述遮光层对应所述低温多晶硅层设置。
3.如权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括缓冲层，所述缓冲层层叠设置于所述遮光层上，所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层及所述遮光层设置于所述基板的表面上。
4.如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层，所述第一欧姆接触层用于降低所述源极与所述低温多晶硅层之间的接触电阻。
5.如权利要求4所述的阵列基板，其特征在于，所述阵列基板还包括第二欧姆接触层，所述第二欧姆接触层连接所述漏极与所述低温多晶硅层，所述第二欧姆接触层用于降低所述漏极与所述低温多晶硅层之间的接触电阻。
6.一种显示面板，其特征在于，所述显示面板包括如权利要求1-5任意一项所述的阵列基板。
7.一种阵列基板的制备方法，其特征在于，所述阵列基板的制备方法包括：
提供一基板；
在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层；
形成绝缘层，所述绝缘层形成在所述低温多晶硅层、所述源极、所述漏极及所述第一导电层上；
形成栅极，所述栅极设置在所述绝缘层上；
形成钝化层，所述钝化层设置在所述栅极上；
形成第二导电层，所述第二导电层设置于所述钝化层上且对应所述第一导电层设置，其中，所述第一导电层为像素电极，所述第二导电层为公共电极。
8.如权利要求7所述的阵列基板的制备方法，其特征在于，在所述步骤“提供一基板”以及所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之间，所述阵列基板的制备方法还包括：
在所述基板的表面上形成遮光层；
所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
在所述遮光层上设置所述低温多晶硅层、所述源极、所述漏极以及所述第一导电层。
9.如权利要求8所述的薄膜晶体管的制备方法，其特征在于，在所述步骤“在所述基板的表面上形成遮光层”之后，在所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”之前还包括：
在所述遮光层上形成缓冲层；
所述步骤“在所述基板的一个表面设置低温多晶硅层、源极、漏极以及第一导电层，所述低温多晶硅层设置于所述基板的表面的中部，所述源极及所述漏极设置于所述低温多晶硅层的两侧，且所述源极的一端电连接所述低温多晶硅层的一端，所述漏极的一端连接所述低温多晶硅层的另一端，所述漏极的另一端电连接所述第一导电层”为：
所述低温多晶硅层、所述源极、所述漏极及所述第一导电层通过所述缓冲层设置在所述基板的表面上。
10.如权利要求7所述的阵列基板的制备方法，其特征在于，所述阵列基板的制备方法还包括：
形成第一欧姆接触层，所述第一欧姆接触层连接所述源极及所述低温多晶硅层；
形成第二欧姆接触层，所述第二欧姆接触层连接所述漏极及所述低温多晶硅层。
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