CN106653695A - 一种低温多晶硅阵列基板及其制作方法 - Google Patents

一种低温多晶硅阵列基板及其制作方法 Download PDF

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CN106653695A
CN106653695A CN201611224492.8A CN201611224492A CN106653695A CN 106653695 A CN106653695 A CN 106653695A CN 201611224492 A CN201611224492 A CN 201611224492A CN 106653695 A CN106653695 A CN 106653695A
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CN106653695B (zh
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郭远
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供了一种低温多晶硅阵列基板及其制作方法，该方法包括：在玻璃基底上形成遮光层；在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案；对位于显示区域的所述U型多晶硅图案进行沟道掺杂处理；对位于显示区域的进行沟道掺杂处理之后的所述U型多晶硅图案进行N+重掺杂处理；在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极及轻掺杂区；对非显示区域的所述U型多晶硅图案进行P+重掺杂处理。本发明可以缩短阵列基板的制程。

Description

一种低温多晶硅阵列基板及其制作方法
技术领域
本发明属于阵列基板制作技术领域，具体地说，尤其涉及一种低温多晶硅阵列基板及其制作方法。
背景技术
近年来，LTPS(Low Temperature Poly-silicon，低温多晶硅)技术不断发展。采用LTPS工艺技术生产的液晶面板，有利于提高面板开口率，使显示器亮度提升、耗电降低，适用于生产更轻薄、低耗电、高分辨率的产品。
由于高分辨率及高性能需求，目前传统LTPS工艺相比薄膜晶体管液晶显示器需要高达12道工艺才能实现阵列基板的整体制程，制程过多会造成生产时间及生产成本的大幅升高，且工艺复杂化于制程中更易发生异常。
发明内容
为解决以上问题，本发明提供了一种低温多晶硅阵列基板及其制作方法，用以缩短阵列基板的制程。
根据本发明的一个方面，提供了一种用于制作低温多晶硅阵列基板的方法，包括：
在玻璃基底上形成遮光层，其中，所述遮光层包括阵列排布的遮光图案，沿列方向在每行间隔设置的遮光图案的两侧对称设置有一个延伸部，并且沿列方向的遮光图案形状相同；
在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，其中，所述U型多晶硅图案的两对边由行方向相邻的两个遮光图案进行遮光；
对位于显示区域的所述U型多晶硅图案进行沟道掺杂处理；
对位于显示区域的进行沟道掺杂处理之后的所述U型多晶硅图案进行N+重掺杂处理，用以形成N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区，其中，两个所述NMOS沟道各对应所述U型多晶硅图案的一个对边；
在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极及轻掺杂区，其中，所述N型双栅结构晶体管的源极通过所述第一过孔与对应的遮光图案连接；
对非显示区域的所述U型多晶硅图案进行P+重掺杂处理，以形成P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区，其中，两个所述PMOS沟道各对应所述U型多晶硅图案的一个对边。
根据本发明的一个实施例，在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，进一步包括以下步骤：
在所述遮光层及裸露的玻璃基底上沉积一层缓冲材料以形成缓冲层；
在所述缓冲层上沉积单晶硅材料并进行结晶处理以形成所述U型多晶硅图案。
根据本发明的一个实施例，在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极和漏极及轻掺杂区进一步包括以下步骤：
在所述N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上沉积一层绝缘材料以形成栅绝缘层；
在所述栅绝缘层上对应所述延伸部的位置蚀刻两个连通至对应遮光图案的延伸部的第一过孔；
在所述栅绝缘层上沉积金属材料并进行蚀刻处理以形成栅极线、所述N型双栅结构晶体管的源极和漏极，其中，所述N型双栅结构晶体管的源极通过一个所述第一过孔连接对应的遮光图案和NMOS沟道的源极区；
对所述N型双栅结构晶体管进行N-轻掺杂处理以形成位于NMOS沟道两侧的轻掺杂区。
根据本发明的一个实施例，所述栅极线沿沿行方向设置，并且将所述栅极线的宽度设置为等于所述NMOS沟道的长度。
根据本发明的一个实施例，所述N型双栅结构晶体管的源极通过对应的所述遮光图案及另一个所述第一过孔连接相邻列方向的所述N型双栅结构晶体管的源极。
根据本发明的一个实施例，所述遮光层采用金属材料制成。
根据本发明的一个实施例，所述延伸部设置为与所述N型双栅结构晶体管的源极的线宽相等。
根据本发明的一个实施例，所述U型多晶硅图案的开口方向设置为相同。
根据本发明的一个实施例，形成所述P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区之后还进一步包括：
在所述N型双栅结构晶体管及裸露的栅绝缘层上形成平坦层；
在所述平坦层上形成公共电极层；
在所述公共电极层上形成钝化层并蚀刻连通至所述N型双栅晶体管的漏极的第二过孔；
在所述钝化层上形成像素电极层，并通过第二过孔连接所述N型双栅晶体管的漏极区。
根据本发明的另一个方面，还提供了一种采用以上所述方法制作的低温多晶硅阵列基板。
本发明的有益效果：
本发明所述的方法在不改变薄膜晶体管结构，不降低产品分辨率、穿透率及性能的前提下，将整体制程缩短至10道，大大缩短了生产成本及生产时间。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是根据本发明的一个实施例的方法流程图；
图2a是根据本发明的一个实施例的遮光图案示意图；
图2b是根据本发明的一个实施例的U型多晶硅图案示意图；
图2c是根据本发明的一个实施例的形成源漏极之后的基板示意图；
图2d是根据本发明的一个实施例的低温多晶硅阵列基板示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
如图1所示为根据本发明的一个实施例的方法流程图，以下参考图1来对本发明进行详细说明。
首先，在步骤S101中，在玻璃基底上形成遮光层，其中，遮光层包括阵列排布的遮光图案，沿列方向在每行间隔设置的遮光图案的两侧对称设置有一个延伸部，并且沿列方向的遮光图案形状相同。
具体的，遮光层主要用于对阵列基板上显示区域的沟道区进行遮光，所以将遮光层的遮光图案设置于显示区域上，对于非显示区域可不需设置。在形成该遮光层时，通常先在玻璃基底上沉积一层金属材料，然后对该层金属材料再进行蚀刻处理以形成遮光层。如图2a所示，该遮光层设置为包括阵列排布的遮光图案11和遮光图案12，并且每行间隔设置的遮光图案11沿列方向两侧对称设置有一个延伸部111和112，每列遮光图案的形状相同。此处的行方向定义为面对阵列基板的水平方向。
接下来，在步骤S102中，在遮光层及裸露的玻璃基底上形成缓冲层，并在缓冲层上形成U型多晶硅图案，其中，U型多晶硅图案的两对边由行方向相邻的两个遮光图案进行遮光。
具体的，首先在遮光层及裸露的玻璃基底上沉积一层缓冲材料以形成缓冲层，用以屏蔽玻璃基底自身缺陷导致的器件不良，通常可采用PECVD工艺沉积SiO2材料形成缓冲层。接着，在缓冲层上沉积单晶硅材料，并进行结晶处理形成U型多晶硅图案。具体的，可采用ELA工艺形成U型多晶硅图案21。如图2b所示，U型多晶硅图案21的两对边211和212由行方向相邻的两个遮光图案进行遮光。
接下来，在步骤S103中，对位于显示区域的U型多晶硅图案进行沟道掺杂处理。具体的，采用硼离子对U型多晶硅图案进行轻掺杂处理，用于调整后续形成的N型沟道区的阈值电压，该掺杂处理过程可对整个显示区域的U型多晶硅图案21进行。
接下来，在步骤S104中，对位于显示区域的进行沟道掺杂处理之后的U型多晶硅图案进行N+重掺杂处理，用以形成N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区。其中，NMOS沟道由遮光图案进行遮光。具体的，如图2b所示，对应于遮光图案11形成一个NMOS沟道，对应于遮光图案12形成另一个NMOS沟道，源极区和漏极区对应U型多晶硅图案的两对边的末端。
接下来，在步骤S105中，在NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在栅绝缘层上形成栅极线、N型双栅结构晶体管的源极及轻掺杂区213，其中，源极通过第一过孔与对应的遮光图案连接。
具体的，首先，在NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上沉积一层绝缘材料以形成栅绝缘层GI。这样就在结束步骤S105之后的基板上一整面设置一层栅绝缘层。此处通常采用SiNx材料形成栅绝缘层。接着，在该栅绝缘层上对应延伸部的位置蚀刻连通至对应遮光图案延伸部111和112的第一过孔(未示出)，接着，在栅绝缘层上沉积金属材料并进行蚀刻处理以形成栅极线31和源极321，而对N型双栅结构晶体管的漏极区不做处理。其中，N型双栅结构晶体管的源极321通过一个第一过孔连接对应的遮光图案和NMOS沟道的源极区，通过同一遮光图案及另一个第一过孔连接相邻列方向的N型双栅结构晶体管的源极322。这样就可以采用遮光图案传输数据信号，而不需要额外设置数据线。
将栅极线31沿行方向设置，并与NMOS沟道重叠设置，使得NMOS沟道的长度等于栅极线的宽度。最后，对显示区域的U型多晶硅图案进行N-轻掺杂处理以形成沟道区两侧的轻掺杂区，用于减轻NMOS沟道的热载流子效应。
为设计方便，将延伸部111和112设置为与N型双栅结构晶体管源极的线宽相等，并且将所有的U型多晶硅图案的开口方向设置为相同，如图2b和图2c所示。
接下来，在步骤S106中，对非显示区域的U型多晶硅图案进行P+重掺杂处理以形成P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区，其中，两个PMOS沟道各对应U型多晶硅图案的一个对边。P型双栅结构晶体管的源极区和漏极区分别位于U型多晶硅图案两对边的末端处。
接下来，在步骤S107中，在N型双栅结构晶体管及裸露的栅绝缘层上形成平坦层。具体的，在N型双栅结构晶体管及裸露的栅绝缘层上沉积一层平坦化绝缘层材料形成平坦层。
接下来，在步骤S108中，在平坦层上形成公共电极层。具体的，在平坦层上沉积导电材料并进行处理形成公共电极图案。
接下来，在步骤S109中，在公共电极层上形成钝化层并蚀刻连通至N型双栅晶体管的漏极的第二过孔。具体的，如图2d所示，在公共电极层上沉积钝化材料形成钝化层，并在该层进行蚀刻处理形成连接连通至N型双栅晶体管的漏极的第二过孔41。
最后，在步骤S110中，在钝化层上形成像素电极层，并通过第二过孔41连接N型双栅晶体管的漏极区。具体的，在钝化层上沉积一层氧化铟锡材料并进行处理形成像素电极层，该像素电极层通过第二过孔41与N型双栅晶体管的漏极区连接。需注意的是，蚀刻第二过孔41时经过公共电极层，需对该第二过孔贯穿公共电极处进行处理，以防止像素电极与公共电极连接。
本发明所述的方法在不改变TFT结构，不降低产品分辨率，穿透率及性能的前提下，将整体制程缩短至10道，大大缩短了生产成本及生产时间。
根据本发明的另一个方面，还提供了一种低温多晶硅阵列基板，该阵列基板采用以上所述的方法制成，在不改变薄膜晶体管的结构，不降低产品分辨率，穿透率及性能的前提下，将整体制程缩短至10道，大大缩短了生产成本及生产时间。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

1.一种用于制作低温多晶硅阵列基板的方法，包括：
在玻璃基底上形成遮光层，其中，所述遮光层包括阵列排布的遮光图案，沿列方向在每行间隔设置的遮光图案的两侧对称设置有一个延伸部，并且沿列方向的遮光图案形状相同；
在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，其中，所述U型多晶硅图案的两对边由行方向相邻的两个遮光图案进行遮光；
对位于显示区域的所述U型多晶硅图案进行沟道掺杂处理；
对位于显示区域的进行沟道掺杂处理之后的所述U型多晶硅图案进行N+重掺杂处理，用以形成N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区，其中，两个所述NMOS沟道各对应所述U型多晶硅图案的一个对边；
在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极及轻掺杂区，其中，所述N型双栅结构晶体管的源极通过所述第一过孔与对应的遮光图案连接；
对非显示区域的所述U型多晶硅图案进行P+重掺杂处理，以形成P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区，其中，两个所述PMOS沟道各对应所述U型多晶硅图案的一个对边。
2.根据权利要求1所述的方法，其特征在于，在所述遮光层及裸露的玻璃基底上形成缓冲层，并在所述缓冲层上形成U型多晶硅图案，进一步包括以下步骤：
在所述遮光层及裸露的玻璃基底上沉积一层缓冲材料以形成缓冲层；
在所述缓冲层上沉积单晶硅材料并进行结晶处理以形成所述U型多晶硅图案。
3.根据权利要求2所述的方法，其特征在于，在所述NMOS沟道及对应的源极区和漏极区、裸露的缓冲层及非显示区域的所述U型多晶硅图案上形成栅绝缘层并蚀刻第一过孔后，在所述栅绝缘层上形成栅极线、所述N型双栅结构晶体管的源极和漏极及轻掺杂区进一步包括以下步骤：
在所述N型双栅结构晶体管的两个NMOS沟道及源极区和漏极区、裸露的缓冲层及非显示区域的U型多晶硅图案上沉积一层绝缘材料以形成栅绝缘层；
在所述栅绝缘层上对应所述延伸部的位置蚀刻两个连通至对应遮光图案的延伸部的第一过孔；
在所述栅绝缘层上沉积金属材料并进行蚀刻处理以形成栅极线、所述N型双栅结构晶体管的源极和漏极，其中，所述N型双栅结构晶体管的源极通过一个所述第一过孔连接对应的遮光图案和NMOS沟道的源极区；
对所述N型双栅结构晶体管进行N-轻掺杂处理以形成位于NMOS沟道两侧的轻掺杂区。
4.根据权利要求3所述的方法，其特征在于，所述栅极线沿沿行方向设置，并且将所述栅极线的宽度设置为等于所述NMOS沟道的长度。
5.根据权利要求3所述的方法，其特征在于，所述N型双栅结构晶体管的源极通过对应的所述遮光图案及另一个所述第一过孔连接相邻列方向的所述N型双栅结构晶体管的源极。
6.根据权利要求3所述的方法，其特征在于，所述遮光层采用金属材料制成。
7.根据权利要求3所述的方法，其特征在于，所述延伸部设置为与所述N型双栅结构晶体管的源极的线宽相等。
8.根据权利要求1所述的方法，其特征在于，所述U型多晶硅图案的开口方向设置为相同。
9.根据权利要求1所述的方法，其特征在于，形成所述P型双栅结构晶体管的两个PMOS沟道及源极区和漏极区之后还进一步包括：
在所述N型双栅结构晶体管及裸露的栅绝缘层上形成平坦层；
在所述平坦层上形成公共电极层；
在所述公共电极层上形成钝化层并蚀刻连通至所述N型双栅晶体管的漏极的第二过孔；
在所述钝化层上形成像素电极层，并通过第二过孔连接所述N型双栅晶体管的漏极区。
10.一种采用如权利要求1-9中任一项所述方法制作的低温多晶硅阵列基板。
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CN108447873A (zh) * 2018-03-19 2018-08-24 武汉华星光电技术有限公司 一种阵列基板及制备方法
CN109346482A (zh) * 2018-09-30 2019-02-15 武汉华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法、显示面板
CN109346482B (zh) * 2018-09-30 2024-01-05 武汉华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法、显示面板
CN112102739A (zh) * 2020-09-16 2020-12-18 武汉华星光电技术有限公司 一种电子设备

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