CN109346482A - 薄膜晶体管阵列基板及其制造方法、显示面板 - Google Patents

薄膜晶体管阵列基板及其制造方法、显示面板 Download PDF

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CN109346482A
CN109346482A CN201811154056.7A CN201811154056A CN109346482A CN 109346482 A CN109346482 A CN 109346482A CN 201811154056 A CN201811154056 A CN 201811154056A CN 109346482 A CN109346482 A CN 109346482A
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layer
interdigitation
grid
light shield
film transistor
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CN109346482B (zh
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王川
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开一种薄膜晶体管阵列基板及其制造方法、显示面板，通过叉指型栅极和叉指型遮光层之间电连接以及叉指型栅极设计的配合，以增加沟道的宽度，在保持单个薄膜晶体器件的沟道宽/长为W总/L不变时，增加的沟道宽度可以使沟道所占用的沟道层的宽度减小而保持单个薄膜晶体管总沟道宽度不变，使得单个薄膜晶体管器件所占面积减小，从而提高沟道层的利用率，降低生产成本。

Description

薄膜晶体管阵列基板及其制造方法、显示面板
技术领域
本发明涉及薄膜晶体管技术领域，尤其涉及一种薄膜晶体管阵列基板及其制造方法、显示面板。
背景技术
薄膜晶体管(Thin Film Transistor,TFT)器件是液晶显示器中十分重要的电子元器件，液晶显示器内部各种控制电路均由其构成。图1为现有液晶显示器中广泛使用的薄膜晶体管器件的截面结构，该薄膜晶体管存在所占器件面积太大，导致制造成本增加的问题。
因此，有必要提出一种技术方案以解决现有薄膜晶体管所占器件面积太大导致制造成本增加的问题。
发明内容
鉴于此，本发明的目的在于提供一种薄膜晶体管阵列基板及其制造方法、显示面板，以解决现有薄膜晶体管所占器件面积太大导致制造成本增加的问题。
为实现上述目的，技术方案如下。
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
叉指型遮光层，所述叉指型遮光层形成于衬底上；
缓冲层，所述缓冲层覆盖在所述叉指型遮光层和所述衬底上；
沟道层，所述沟道层形成于所述缓冲层上；
第一绝缘层，所述第一绝缘层覆盖在所述沟道层和所述缓冲层上；
叉指型栅极，所述叉指型栅极形成于所述第一绝缘层上且位于所述叉指型遮光层的上方；
第二绝缘层，所述第二绝缘层覆盖在所述叉指型栅极和所述第一绝缘层上；
至少一个第一电极及至少两个第二电极，所述第一电极和所述第二电极覆盖形成于所述第一绝缘层和所述第二绝缘层上的过孔以与所述沟道层连接，所述第二电极位于所述叉指型栅极的两侧，所述第二电极与所述第一电极间隔地设置；
其中，所述叉指型遮光层与所述叉指型栅极电连接。
在上述薄膜晶体管阵列基板中，所述叉指型栅极沿第一方向的投影与所述叉指型遮光层重叠，所述第一方向为垂直于所述衬底所在水平面且由所述叉指型栅极指向所述叉指型遮光层的方向。
在上述薄膜晶体管阵列基板中，所述叉指型遮光层与所述叉指型栅极通过导电层连接。
在上述薄膜晶体管阵列基板，所述导电层为从所述叉指型栅极上延伸出且覆盖所述缓冲层上过孔的栅极线。
在上述薄膜晶体管阵列基板，所述缓冲层包括依次覆盖在所述叉指型遮光层和所述衬底上的氮化硅层和氧化硅层，所述第一绝缘层包括依次覆盖在所述沟道层和所述缓冲层上的氧化硅层和氮化硅层。
一种薄膜晶体管阵列基板的制造方法，所述制造方法包括如下步骤：
于衬底上形成一叉指型遮光层；
形成覆盖所述叉指遮光层和所述衬底的缓冲层；
于所述缓冲层上形成沟道层；
形成覆盖所述沟道层和所述缓冲层的第一绝缘层；
于所述第一绝缘层上形成叉指型栅极，所述叉指型栅极位于所述叉指型遮光层的上方；
形成覆盖所述叉指型栅极和所述第一绝缘层的第二绝缘层；
形成至少一个第一电极及至少两个第二电极，所述第一电极和所述第二电极覆盖形成于所述第一绝缘层和所述第二绝缘层上的过孔以与所述沟道层连接，所述第二电极位于所述叉指型栅极的两侧，所述第二电极与所述第一电极间隔地设置；
其中，所述叉指型遮光层与所述叉指型栅极电连接。
在上述薄膜晶体管阵列基板的制造方法中，所述叉指型栅极沿第一方向的投影与所述叉指型遮光层重叠，所述第一方向为垂直于所述衬底所在水平面且由所述叉指型栅极指向所述叉指型遮光层的方向。
在上述薄膜晶体管阵列基板的制造方法中，所述叉指型遮光层与所述叉指型栅极通过导电层连接，所述导电层为从所述叉指型栅极上延伸出且覆盖所述缓冲层上过孔的栅极线。
在上述薄膜晶体管阵列基板的制造方法中，所述缓冲层包括依次覆盖在所述叉指型遮光层和所述衬底上的氮化硅层和氧化硅层，所述第一绝缘层包括依次覆盖在所述沟道层和所述缓冲层上的氧化硅层和氮化硅层。
一种显示面板，所述显示面板包括上述薄膜晶体管阵列基板。
有益效果：本发明通过叉指型栅极和叉指型遮光层之间电连接以及叉指型栅极设计的配合，以增加沟道的宽度，在保持单个薄膜晶体器件沟道的宽/长为W总/L不变时，增加的沟道宽度可以使沟道所占用的沟道层的宽度减小而保持单个薄膜晶体管总沟道宽度不变，使得单个薄膜晶体管器件所占面积减小，从而提高沟道层的利用率，降低生产成本。
附图说明
图1为现有技术中的薄膜晶体管器件的截面结构；
图2A-2H为本发明第一实施例薄膜晶体管阵列基板的形成过程中的结构示意图。
附图标注如下：
10、20衬底11遮光层21叉指型遮光层211遮光条12、22缓冲层
13、23沟道层14、24第一绝缘层15栅极25叉指型栅极251栅线
16、26第二绝缘层171、271源电极172、272漏电极
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图2A-2H所示，其为本发明的第一实施例的薄膜晶体管阵列基板的形成过程中的结构示意图，包括如下：
S11：如图2A所示，于衬底20上形成叉指型遮光层21；
衬底20可以为玻璃基板、塑料基板、可挠性基体或者柔性基板中的任意一种，本发明不作具体地限定。
叉指型遮光层21用于遮蔽背光，防止后续形成的沟道层受到背光影响而产生光载流子，导致薄膜晶体管的漏电流增大；叉指型遮光层21包括至少两遮光条211，遮光条211沿衬底20所在水平面的x方向平行地排列，遮光条211的一端连接在遮光主线上，遮光条211所在直线均与衬底20所在水平面的y方向平行，遮光主线所在直线与衬底所在平面的y方向垂直，衬底所在水平面的x方向和y方向相互垂直。具体在本实施例中，如图2B所示，其为叉指型遮光层在衬底20上的俯视示意图，衬底20上有多个像素区P以及位于像素区P一角的薄膜晶体管，叉指型遮光层21作为薄膜晶体管的组成部分，其也位于像素区P的一角且由两遮光条211和连接两遮光条211的遮光主线组成，两遮光条211为条形且沿衬底20所在水平面的x方向平行地排列，遮光主线所在的直线与衬底20所在水平面的x方向平行。叉指型遮光层21的制备材料为钼、铝、铜、钛或其组合；叉指型遮光层的厚度为500-2000埃。
本实施例通过一光罩制程Mask-1形成叉指型遮光层21。具体地，对衬底20进行清洗及烘干后，在衬底基板20上利用化学沉积的方法沉积一整面遮光层，接着在遮光层上涂布一整面光阻并对光阻进行预烘烤之后，然后采用掩膜版对整面的光阻进行曝光，再利用显影液进行显影处理，剩下未被显影液显影的光阻，再对未被光阻覆盖的遮光层进行蚀刻处理，最后去除未被显影液显影的光阻，制得叉指型遮光层21。
S12:如图2C所示，形成覆盖叉指型遮光层21和衬底20的缓冲层22。
缓冲层22起到防止衬底20中的杂质在后续工艺中向上扩散影响到沟道层性能或者隔绝热以保护衬底20的作用。缓冲层22为氧化硅层、氮化硅层或氧化硅和氧化硅的叠层，或者其他非导电层；缓冲层22的厚度为1000-5000埃；缓冲层22可采用化学气相沉积、等离子化学气相沉积、溅射沉积、真空蒸镀以及低压化学气相沉积中的任意一种制得。
S13:如图2D所示，于缓冲层22上形成沟道层23。
沟道层23用于在源电极和漏电极之间传导电流，通过调整沟道的组成可以控制电流。沟道层23为半导体材料，例如硅系半导体或金属氧化物半导体等。具体在本实施例中，沟道层23为多晶硅层，通过在缓冲层22上形成一整面的非晶硅层，接着对非晶硅层进行一光罩制程Mask-2处理以图案化非晶硅层，然后对图案化的非晶硅进行准分子激光退火(Excimer Laser annealing，ELA)处理得到沟道层23。其中，光罩制程Mask-2的过程与上述光罩制程Mask-1相同，此处不作详述。为了调整载流子在沟道中的迁移率，可以对沟道层进行离子掺杂，例如磷掺杂或者硼掺杂等。
S14:如图2E所示，形成覆盖沟道层23和缓冲层22的第一绝缘层24；
第一绝缘层24也称为栅极绝缘层，其作用为在沟道层和叉指型栅极之间起绝缘作用。通过采用化学气相沉积、等离子化学气相沉积、溅射沉积或真空蒸镀中任意一种以形成覆盖沟道层23和缓冲层22的一整面绝缘层而得到第一绝缘层24。第一绝缘层24的制备材料可以为氧化硅、氮化硅或氮氧化硅中的任意一种。该第一绝缘层的厚度为1000-3000埃。
S15:如图2F所示，于第一绝缘层24上形成叉指型栅极25，叉指型栅极25位于叉指型遮光层21的上方。
叉指型栅极25包括至少两条栅线251，栅线251沿衬底20所在水平面的x方向平行地排列，栅线251的一端均连接在主栅线上，栅线251所在直线均与衬底20所在水平面的y方向平行，主栅线与衬底20所在水平面的y方向垂直。具体在本实施例中，叉指型栅极25由两条状栅线251和连接两条状栅线251的主栅线252组成，两条状栅线251的宽度相同，两条状栅线251的长度不作具体的限定。叉指型栅极25与叉指型遮光层21电连接，为了便于理解，在图2F中用一导线表示叉指型栅极25与叉指型遮光层21之间的电连接关系。
本实施例通过一光罩制程Mask-3形成叉指型栅极25，光罩制程Mask-3的步骤与光罩制程Mask-1相同，此处不作详述。叉指型栅极25的制备材料可以为钼、铝、铜、钛或其组合；叉指型栅极的厚度为500-2000埃。
本实施例通过叉指型栅极和叉指型遮光层之间电连接以及叉指型栅极设计的配合，以增加沟道的宽度，在保持单个薄膜晶体器件沟道的宽/长比为W总/L不变时，增加的沟道宽度可以使沟道所占用沟道层的宽度减小而保持单个薄膜晶体管总沟道宽度不变，使得单个薄膜晶体管器件所占面积减小，从而提高沟道层的利用率，降低生产成本。
S16:如图2G所示，形成覆盖叉指型栅极25和第一绝缘层24的第二绝缘层26；
第二绝缘层26也称为层间绝缘层，通过采用化学气相沉积、等离子化学气相沉积、溅射沉积或真空蒸镀中的任意一种以形成覆盖叉指型栅极25和第一绝缘层24的一整面的绝缘层以得到第二绝缘层26；第二绝缘层26的制备材料可以为氧化硅、氮化硅或氮氧化硅中的任意一种；该第二绝缘层的厚度为1-4微米。
本实施例再通过一光罩制程Mask-4在第一绝缘层24和第二绝缘层26上形成至少三个过孔，三个过孔均暴露部分的沟道层，为后续形成间隔设置的源电极和漏电级且源级和漏级均与沟道层连接提供条件。光罩制程Mask-4的过程与上述光罩制程Mask-1相同，此处不作详述。
S17:如图2H所示，形成至少一个第一电极271及至少两个第二电极272，第一电极271和第二电极272覆盖形成于第一绝缘层24和第二绝缘层26上的过孔以与沟道层23连接，第二电极272位于叉指型栅极25的两侧，第二电极272与第一电极271间隔地设置。
在本实施例中，通过一光罩制程Mask-5在形成过孔的层间绝缘层上形成一个第一电极271和两个第二电极272，第一电极271为源电级，第二电极272为漏电极，第一电极271位于叉指型栅极25的两条栅线251之间，两个第二电极272分别位于叉指型栅极25的两侧且与第一电极271相对设置。第一电极271和第二电极272的制备材料包括但不限于铝、钼、钛、铬、铜、金属氧化物、金属合金或者其他导电材料，或者ITO(Indium tion oxide，氧化铟锡)，或者是两层ITO和位于两层ITO之间的银组成的叠层电极。光罩制程Mask-5的步骤与光罩制程Mask-1相同，此处不作详述。其中，一个源电极和一个漏电极之间的沟道层为沟道，沟道宽度与衬底20所在水平面的y方向平行，沟道长度与衬底20所在水平面的x方向平行。
本发明还提供上述过程制得的薄膜薄膜晶体管阵列基板，包括：
叉指型遮光层21，叉指型遮光层21形成于衬底20上；
缓冲层22，缓冲层22覆盖在叉指型遮光层21和衬底20上；
沟道层23，沟道层23形成于缓冲层22上；
第一绝缘层24，第一绝缘层24覆盖在沟道层23和缓冲层22上；
叉指型栅极25，叉指型栅极25形成于第一绝缘层24上且位于叉指型遮光层21的上方；
第二绝缘层26，第二绝缘层26覆盖在叉指型栅极25和第一绝缘层24上；
至少一个第一电极271及至少两个第二电极272，第一电极271和第二电极272覆盖形成于第一绝缘层24和第二绝缘层26上的过孔以与沟道层23连接，第二电极272位于叉指型栅极25的两侧，第二电极272与第一电极271间隔地设置；其中，叉指型遮光层21与叉指型栅极25电连接。
进一步地，叉指型栅极25沿第一方向的投影与叉指型遮光层21重叠，第一方向为垂直于衬底20所在水平面且由叉指型栅极25指向叉指型遮光层25的方向。叉指型栅极25的图案与叉指型遮光层21的图案相同且相对设置，有利于提高器件的可靠性，避免出现漏电极电场过大导致器件产生击穿失效以及漏电流和寄生电容偏大的问题。
进一步地，叉指型遮光层21与叉指型栅极25通过导电层连接，导电层可以是导电材料，导电层也可以为从叉指型栅极25上延伸出且覆盖缓冲层22上过孔的栅极线。在制备叉指型栅极25时，在缓冲层22上形成过孔并在过孔中覆盖栅极层以得到连接叉指型栅极25和叉指型遮光层21的栅极线。
进一步地，缓冲层22包括依次覆盖在叉指型遮光层21和衬底上20的氮化硅层和氧化硅层，第一绝缘层24包括依次覆盖在沟道层23和缓冲层22上的氧化硅层和氮化硅层。此种缓冲层22和第一绝缘层24的组成能保证本发明薄膜晶体管阵列基板上的TFT的开启电压与现有TFT的开启电压相同。此外，缓冲层22先沉积氮化硅再沉积氧化硅也可以更好地阻止衬底20中的杂质在后续工艺中进入其他各个膜层从而影响TFT器件的电学性能，各个膜层之间的结合力也会比较好，不容易相互分离。
本发明还提供一种显示面板，该显示面板包括上述薄膜晶体管阵列基板。
以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (10)

1.一种薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板包括：
叉指型遮光层，所述叉指型遮光层形成于衬底上；
缓冲层，所述缓冲层覆盖在所述叉指型遮光层和所述衬底上；
沟道层，所述沟道层形成于所述缓冲层上；
第一绝缘层，所述第一绝缘层覆盖在所述沟道层和所述缓冲层上；
叉指型栅极，所述叉指型栅极形成于所述第一绝缘层上且位于所述叉指型遮光层的上方；
第二绝缘层，所述第二绝缘层覆盖在所述叉指型栅极和所述第一绝缘层上；
至少一个第一电极及至少两个第二电极，所述第一电极和所述第二电极覆盖形成于所述第一绝缘层和所述第二绝缘层上的过孔以与所述沟道层连接，所述第二电极位于所述叉指型栅极的两侧，所述第二电极与所述第一电极间隔地设置；
其中，所述叉指型遮光层与所述叉指型栅极电连接。
2.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述叉指型栅极沿第一方向的投影与所述叉指型遮光层重叠，所述第一方向为垂直于所述衬底所在水平面且由所述叉指型栅极指向所述叉指型遮光层的方向。
3.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述叉指型遮光层与所述叉指型栅极通过导电层连接。
4.根据权利要求3所述的薄膜晶体管阵列基板，其特征在于，所述导电层为从所述叉指型栅极上延伸出且覆盖所述缓冲层上过孔的栅极线。
5.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述缓冲层包括依次覆盖在所述叉指型遮光层和所述衬底上的氮化硅层和氧化硅层，所述第一绝缘层包括依次覆盖在所述沟道层和所述缓冲层上的氧化硅层和氮化硅层。
6.一种薄膜晶体管阵列基板的制造方法，其特征在于，所述制造方法包括如下步骤：
于衬底上形成一叉指型遮光层；
形成覆盖所述叉指遮光层和所述衬底的缓冲层；
于所述缓冲层上形成沟道层；
形成覆盖所述沟道层和所述缓冲层的第一绝缘层；
于所述第一绝缘层上形成叉指型栅极，所述叉指型栅极位于所述叉指型遮光层的上方；
形成覆盖所述叉指型栅极和所述第一绝缘层的第二绝缘层；
形成至少一个第一电极及至少两个第二电极，所述第一电极和所述第二电极覆盖形成于所述第一绝缘层和所述第二绝缘层上的过孔以与所述沟道层连接，所述第二电极位于所述叉指型栅极的两侧，所述第二电极与所述第一电极间隔地设置；
其中，所述叉指型遮光层与所述叉指型栅极电连接。
7.根据权利要求6所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述叉指型栅极沿第一方向的投影与所述叉指型遮光层重叠，所述第一方向为垂直于所述衬底所在水平面且由所述叉指型栅极指向所述叉指型遮光层的方向。
8.根据权利要求6所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述叉指型遮光层与所述叉指型栅极通过导电层连接，所述导电层为从所述叉指型栅极上延伸出且覆盖所述缓冲层上过孔的栅极线。
9.根据权利要求6所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述缓冲层包括依次覆盖在所述叉指型遮光层和所述衬底上的氮化硅层和氧化硅层，所述第一绝缘层包括依次覆盖在所述沟道层和所述缓冲层上的氧化硅层和氮化硅层。
10.一种显示面板，其特征在于，所述显示面板包括权利要求1-5任一项所述的薄膜晶体管阵列基板。
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