CN110109306A - 阵列基板及其制造方法、显示面板 - Google Patents

阵列基板及其制造方法、显示面板 Download PDF

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CN110109306A
CN110109306A CN201910337921.XA CN201910337921A CN110109306A CN 110109306 A CN110109306 A CN 110109306A CN 201910337921 A CN201910337921 A CN 201910337921A CN 110109306 A CN110109306 A CN 110109306A
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light
scan line
shielding conductive
controlling grid
grid scan
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CN110109306B (zh
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聂晓辉
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本申请提供一种阵列基板及其制造方法、显示面板，通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线的阻抗减小，从而使得显示面板的驱动功耗减小，提高像素充放电的相应速度。

Description

阵列基板及其制造方法、显示面板
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示面板。
背景技术
低温多晶硅薄膜晶体管(Low Temperature Poly Silicon Thin FilmTransistor，LTPS-TFT)具有制备温度低、载流子迁移率高以及器件尺寸小等突出优点，是发展低功耗以及高集成度显示面板的关键技术。基于矩阵显示逐行扫描的原理，当逐行扫描的栅极扫描线电压低于TFT的阈值电压时，TFT的导电沟道处于截断状态，此时像素电路处于关态；当逐行扫描的栅极扫描线电压高于TFT阈值电压时，TFT导电沟道处于导通状态，由源极接入的信息电压将加载到像素(漏极)电容和存储电容上，像素电路处于开态；扫描完成后像素行TFT全部关闭，已经写入的信息电压保持不变，直到下一帧扫描到时再重新写入信息。栅极扫描线金属阻抗决定了驱动电路的功耗大小和像素充放电响应速度。在实际生产过程中，为保证液晶显示面板(Liquid Crystal Display，LCD)的开口率，栅极扫描线金属线宽一般设计较小，导致金属阻抗较大，LCD驱动功耗的显著增加。
因此，有必要提出一种技术方案以解决扫描金属线的阻抗较大导致LCD的驱动功耗增加的问题。
发明内容
本申请的目的在于提供一种阵列基板及其制造方法、显示面板，该阵列基板的栅极扫描线和遮光导电层电性连接，使得阵列基板具有高开口率的同时，显示面板工作时驱动功耗减小。
为实现上述目的，技术方案如下：
一种阵列基板，所述阵列基板包括：
一衬底；
形成于所述衬底上的遮光导电层；
覆盖所述衬底和所述遮光导电层的缓冲层；
形成于所述缓冲层上的沟道层；
覆盖所述缓冲层和所述沟道层的第一绝缘层；
形成于所述第一绝缘层上且位于所述遮光导电层正上方的多条栅极扫描线；
其中，所述栅极扫描线和所述遮光导电层电性连接。
在上述阵列基板中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
在上述阵列基板中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
在上述阵列基板中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
在上述阵列基板中，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
一种阵列基板的制造方法，所述制造方法包括如下步骤：
提供一衬底；
于所述衬底上形成遮光导电层；
形成覆盖所述衬底和所述遮光导电层的缓冲层；
于所述缓冲层上形成沟道层；
形成覆盖所述缓冲层和所述沟道层的第一绝缘层；
于所述第一绝缘层上形成多个栅极扫描线，多条所述栅极扫描线位于所述遮光导电层的正上方；
其中，所述栅极扫描线和所述遮光导电层电性连接。
在上述阵列基板的制造方法中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
在上述阵列基板的制造方法中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
在上述阵列基板的制造方法中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
一种显示面板，所述显示面板包括上述阵列基板。
有益效果：本申请提供一种阵列基板及其制造方法、显示面板，通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
附图说明
图1为本申请第一实施例阵列基板的平面示意图；
图2为沿图1所示阵列基板A-A切线的截面示意图；
图3为本申请第二实施例阵列基板的平面示意图；
图4为沿图3所示阵列基板A-A切线的截面示意图；
图5为本申请第一实施例阵列基板的制造方法的流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1和图2，图1为本申请第一实施例阵列基板的平面示意图，图2为沿图1所示阵列基板A-A切线的截面示意图。阵列基板100为薄膜晶体管阵列基板，即多个薄膜晶体管(未示出)阵列分布地设置于衬底10上。阵列基板100包括衬底10、遮光导电层11、缓冲层12、沟道层13、第一绝缘层14、栅极扫描线15以及过孔16。
衬底10可以玻璃基板，也可以为柔性基板。
遮光导电层11一方面用于避免背光照射至沟道层13的沟道1311上，从而避免沟道1311出现光生漏电流的问题。遮光导电层11形成于衬底10上，遮光导电层11包括多条遮光导电线111，多条遮光导电线111平行排列。每条遮光导电线111的宽度D1比沟道层13中每个叉指半导体构件131的沟道1311的宽度d大以避免背光照射到沟道1311上。栅极扫描线15和遮光导电层11电性连接，以使遮光导电层11还用于传导扫描电信号。具体，每条遮光导电线111与每条栅极扫描线15一对一地通过贯穿缓冲层12和第一绝缘层14的至少两个过孔16电性连接。遮光导电层11的制备材料为钼、铝、钛以及铜中的至少一种。遮光导电层11的制备材料11和栅极扫描线15的制备材料相同。
缓冲层12用于防止衬底10中的金属离子(铝、钡以及钠等)在热工艺中扩散到沟道层13中的沟道1311中而影响薄膜晶体管的电性能。缓冲层12覆盖衬底10和遮光导电层11。缓冲层12为覆盖遮光导电层11和衬底10的氧化硅层和氮化硅层，氮化硅层位于靠近衬底10的一侧。缓冲层12的厚度为3000埃-4000埃。缓冲层12是通过化学气相沉积制备得到。
沟道层13形成于缓冲层12上。沟道层13包括多个阵列排布的叉指半导体构件131。多个叉指半导体构件131位于多条遮光导电线111的上方。多个叉指半导体构件131分为多行排列，每个叉指半导体构件131为叉指型，每个叉指半导体构件131具有同行的两个沟道1311，以降低薄膜晶体管处于关态时的漏电流。每个叉指半导体构件131具有一个源极接触区和一个漏极接触区，以分别用于与源电极(未示出)和漏电极(未示出)电性接触。沟道层13的制备材料为多晶硅。沟道层13的制备材料也可以为金属氧化物半导体或单晶硅中的一种。沟道层13是利用化学气相沉积形成整面的非晶硅，再通过准分子激光退火工艺使非晶硅转化为多晶硅，再经过黄光制程以使得多晶硅图案化以形成多个阵列排布的叉指半导体构件。
第一绝缘层14为栅极绝缘层。第一绝缘层14覆盖缓冲层12和沟道层13。第一绝缘层14为氮化硅层。可以理解的是，第一绝缘层14也可以为氧化硅层或氧化硅和氮化硅的叠层。第一绝缘层14的厚度为1000埃-1500埃。第一绝缘层14是通过化学气相沉积制备得到。
栅极扫描线15用于传输扫描电信号以控制薄膜晶体管的工作状态。栅极扫描线15形成于第一绝缘层14上且位于遮光导电层11正上方。栅极扫描线15也形成于过孔16中以使第一绝缘层14上的栅极扫描线和遮光导电层11电性连接。栅极扫描线15包括多条平行的金属线。每条栅极扫描线15的宽度等于沟道1311的宽度d，即每条栅极扫描线15的宽度d小于每个导电遮光线111的宽度D1。具体地，每条栅极扫描线15的宽度为3±0.1微米。栅极扫描线15与遮光导电层11电性连接，使得相对于传统技术中栅极扫描线15的宽度基本不变时，用于传输扫描电信号的导线(包括栅极扫描线15和导电遮光层11)的有效面积增大，显著地降低用于传输扫描电信号的导线的电阻，降低扫描驱动电路的功耗，提高像素(未示出)充放电响应的速度。
过孔16用于使栅极扫描线15和遮光导电层11电性连接。过孔16贯穿缓冲层12和第一绝缘层14。每个叉指半导体构件131相对的两侧均分别设置有至少一过孔16，以提高每条遮光导电线111和对应栅极扫描线15的电性连接的良率，而且多个过孔16能减小连接栅极扫描线15和遮光导电层11之间的导线(位于过孔16中的栅极扫描线)的整体阻值。具体地，每个叉指半导体构件131相对的两侧设置均分别设置有一个过孔16，同一行叉指半导体构件131中，相邻两个叉指半导体构件131之间设置有一个过孔16，使得过孔16周期性地分布。过孔16通过形成第一绝缘层14后，通过于第一绝缘层14上形成整面光阻，再利用光罩曝光部分光阻，刻蚀未被光阻覆盖的第一绝缘层14以及缓冲层12以形成过孔16。过孔16沿第一方向的尺寸D2大于栅极扫描线的宽度D1，第一方向为垂直于栅极扫描线15(栅极扫描线延伸方向)的方向，第一方向与衬底10设置有栅极扫描线的平面平行，以使每个过孔16中的栅极扫描线15与遮光导电层11充分接触，从而降低形成于过孔16中的栅极扫描线15的阻抗。过孔16可以为圆形，过孔16的半径大于栅极扫描线15的宽度。过孔16也可以为正方形，过孔16的边长大于栅极扫描线15的宽度。
请参阅图3和图4，图3为本申请第二实施例阵列基板的平面示意图，图4为沿图3所示阵列基板A-A切线的截面示意图。图3所示阵列基板100与图1所示阵列基板100基本相似，不同之处在于，每条栅极扫描线15在衬底10上的正投影和对应与栅极扫描线10电性连接的每条遮光导电线111在衬底10上的正投影重合，即每条栅极扫描线15和与栅极扫描线15电性连接的每条遮光导电线111相同(包括栅极扫描线15的宽度d以及遮光导电线111的宽度D1相同)，以保证遮光导电线111起到遮光作用的同时，进一步地提高阵列基板制成的显示面板的开口率。另外，每个过孔16包括贯穿缓冲层12的第一连接孔121和贯穿第一绝缘层14的第二连接孔141，第一连接孔121与第二连接孔141连通，第二连接孔141在衬底10上的正投影位于第一连接孔121在衬底10的正投影内，即第一连接孔121的尺寸大于第二连接孔141的尺寸，以保证形成的第二连接孔141能与第一连接孔121连通。第一连接孔121是形成缓冲层12后，采用黄光制程处理缓冲层12形成。第二连接孔141是形成第一绝缘层14后，采用黄光制程处理第一绝缘层14形成。第二连接孔141沿第一方向的尺寸大于每条栅极扫描线15的宽度，第一方向为垂直于栅极扫描线15的方向。
本申请阵列基板通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线的阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
请参阅图5，其为本申请第一实施例阵列基板的制造方法的流程图。阵列基板的制造方法包括如下步骤：
S10:提供一衬底；
S11:于衬底上形成遮光导电层；
S12:形成覆盖衬底和遮光导电层的缓冲层；
S13:于缓冲层上形成沟道层；
S14:形成覆盖缓冲层和沟道层的第一绝缘层；
S15:于第一绝缘层上形成多个栅极扫描线，多条栅极扫描线位于遮光导电层的正上方，栅极扫描线和遮光导电层电性连接。
本申请阵列基板的制造方法通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
在本实施例中，遮光导电层包括多条遮光导电线，每条遮光导电线与每条栅极扫描线一对一地通过贯穿缓冲层和第一绝缘层的至少两个过孔电性连接。
在本实施例中，每条栅极扫描线在衬底上的正投影和对应与栅极扫描线电性连接的每条遮光导电线在衬底上的正投影重合，以保证遮光导电线起到遮光作用的同时，进一步地提高阵列基板制成的显示面板的开口率。
在本实施例中，过孔沿第一方向的尺寸大于栅极扫描线的宽度，第一方向为垂直于栅极扫描线的方向，以使每个过孔中的栅极扫描线与遮光导电层充分接触，从而降低形成于过孔中的栅极扫描线的阻抗。
本申请还提供一种显示面板，该显示面板为液晶显示面板或有机发光二极管显示面板。显示面板可以为液晶显示面板或有机发光二极管显示面板。显示面板包括上述阵列基板。
本申请显示面板通过使阵列基板的栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线的阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (10)

1.一种阵列基板，其特征在于，所述阵列基板包括：
一衬底；
形成于所述衬底上的遮光导电层；
覆盖所述衬底和所述遮光导电层的缓冲层；
形成于所述缓冲层上的沟道层；
覆盖所述缓冲层和所述沟道层的第一绝缘层；
形成于所述第一绝缘层上且位于所述遮光导电层正上方的多条栅极扫描线；
其中，所述栅极扫描线和所述遮光导电层电性连接。
2.根据权利要求1所述阵列基板，其特征在于，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
3.根据权利要求2所述的阵列基板，其特征在于，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
4.根据权利要求2所述的阵列基板，其特征在于，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
5.根据权利要求2所述的阵列基板，其特征在于，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
6.一种阵列基板的制造方法，其特征在于，所述制造方法包括如下步骤：
提供一衬底；
于所述衬底上形成遮光导电层；
形成覆盖所述衬底和所述遮光导电层的缓冲层；
于所述缓冲层上形成沟道层；
形成覆盖所述缓冲层和所述沟道层的第一绝缘层；
于所述第一绝缘层上形成多个栅极扫描线，多条所述栅极扫描线位于所述遮光导电层的正上方；
其中，所述栅极扫描线和所述遮光导电层电性连接。
7.根据权利要求6所述的阵列基板的制造方法，其特征在于，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
8.根据权利要求7所述的阵列基板的制造方法，其特征在于，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
9.根据权利要求7所述的阵列基板的制造方法，其特征在于，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
10.一种显示面板，其特征在于，所述显示面板包括权利要求1-5任一项所述的阵列基板。
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