WO2023108811A1 - 阵列基板、显示面板及阵列基板的制作方法 - Google Patents

阵列基板、显示面板及阵列基板的制作方法 Download PDF

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Publication number
WO2023108811A1
WO2023108811A1 PCT/CN2021/141568 CN2021141568W WO2023108811A1 WO 2023108811 A1 WO2023108811 A1 WO 2023108811A1 CN 2021141568 W CN2021141568 W CN 2021141568W WO 2023108811 A1 WO2023108811 A1 WO 2023108811A1
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layer
gate
source
drain
active layer
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PCT/CN2021/141568
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English (en)
French (fr)
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戴晨
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/624,033 priority Critical patent/US20230197738A1/en
Publication of WO2023108811A1 publication Critical patent/WO2023108811A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the display field, in particular to an array substrate, a display panel and a method for manufacturing the array substrate.
  • TFT Thin Film Transistor
  • thin film transistors are divided into amorphous silicon (a-Si) TFT, low temperature polysilicon (Low Temperature Poly-silicon, LTPS) TFT and metal oxide (Metal Oxide) TFT.
  • a-Si amorphous silicon
  • LTPS Low Temperature Poly-silicon
  • Metal Oxide Metal Oxide
  • different types of thin film transistors have their unique advantages, and the display effect of the display panel can be effectively improved by forming multiple types of thin film transistors into a hybrid TFT structure.
  • the manufacturing process of the array substrate with the hybrid thin film transistor structure is relatively complicated, which makes the production efficiency of the array substrate low and the production cost too high.
  • Embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate, which can solve the problem of low production efficiency caused by the complicated manufacturing process of the existing array substrate.
  • An embodiment of the present application provides an array substrate, including:
  • the thin film transistor layer is arranged on the base substrate; the thin film transistor layer includes a first thin film transistor, and the first thin film transistor includes a first active layer and a first gate stacked on the base substrate. electrode insulating layer and a first source-drain layer, the first gate insulating layer is located between the first active layer and the first source-drain layer, and the first source-drain layer includes the The first source and the first drain electrically connected to the first active layer; the first thin film transistor also includes a first gate, and the first gate is located on the first gate insulating layer, so The first gate is arranged in the same layer as the first source-drain layer.
  • the first active layer, the first gate insulating layer and the first source-drain layer are sequentially arranged along a direction away from the base substrate.
  • there is a gap between the first gate, the first source and the first drain, and the first gate insulating layer corresponds to the The position of the gap is provided with a first opening.
  • the array substrate includes a planar layer, the planar layer is disposed on the first source-drain layer and the first gate, and the planar layer fills the The gap and the first opening.
  • the first thin film transistor further includes a second gate and an interlayer dielectric layer, and the second gate is located in the first active layer close to the substrate On one side of the substrate, the interlayer dielectric layer is located between the first active layer and the second gate.
  • the array substrate includes a second thin film transistor, and the second thin film transistor is arranged on the base substrate in parallel with the first thin film transistor;
  • the thin film transistor includes a second active layer stacked on the base substrate, the first gate insulating layer and a second source-drain layer, and the first gate insulating layer is located on the second active layer.
  • layer and the second source and drain layer, the second source and drain layer includes a second source and a second drain electrically connected to the second active layer; the second source and drain layer is set in the same layer as the first source-drain layer and the first gate.
  • the second active layer, the first gate insulating layer and the second source-drain layer are sequentially arranged along a direction away from the base substrate.
  • a second opening is opened on the first gate insulating layer at a position corresponding to the first source, and the second opening leaks the second active A source layer, the first source is electrically connected to the second active layer through the second opening.
  • the second thin film transistor includes a third gate and a second gate insulating layer, and the third gate is arranged corresponding to the second active layer, so The second gate insulating layer is located between the third gate and the second active layer;
  • the third gate is located on a side of the second active layer away from the base substrate; or,
  • the third gate is located on a side of the second active layer close to the base substrate.
  • the array substrate further includes a light-shielding metal layer, and the light-shielding metal layer is located on a side of the second active layer close to the base substrate.
  • the third gate is arranged on the same layer as the second gate; or,
  • the third gate is set in the same layer as the first source-drain layer.
  • the second thin film transistor further includes a fourth gate and a third gate insulating layer, and the third gate insulating layer is located between the third gate and the third gate. Between the fourth gates, the fourth gates are arranged correspondingly to the second active layer.
  • the third gate and the fourth gate are located on a side of the second active layer away from the base substrate; or,
  • At least one of the third gate and the fourth gate is located on a side of the second active layer close to the base substrate.
  • the material of the first active layer includes one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide; the second active layer The material includes low temperature polysilicon.
  • an embodiment of the present application further provides a display panel, which includes the array substrate described in any one of the above.
  • the embodiment of the present application also provides a method for manufacturing an array substrate, the method including:
  • the first active layer, the first gate insulating layer, the first gate, the first source and the first drain form a first thin film transistor.
  • the sequentially forming the first active layer and the first gate insulating layer on the base substrate includes:
  • a first gate insulating layer is formed on the first active layer.
  • the forming the first gate, the first source and the first drain on the first gate insulating layer includes:
  • a first gate, a first source, a first drain, a second source, and a second drain are formed on the first gate insulating layer, so that the first source and the first drain Electrically connected to the first active layer, the first source, the second source and the second drain are electrically connected to the second active layer; the second active layer, The second gate insulating layer, the third gate, the first gate insulating layer, the first source and the first drain form a second thin film transistor.
  • the method further includes:
  • a flat layer is formed on the first gate, the first source, the first drain, the second source and the second drain.
  • a buffer layer is formed on the light-shielding metal layer.
  • the array substrate includes a base substrate and a thin film transistor layer
  • the thin film transistor layer includes a first thin film transistor
  • the first thin film transistor includes a first active layer, a first gate insulating layer, a first source and drain layer
  • the first gate wherein the first source and drain layer includes a first source and a first drain electrically connected to the first active layer, and the first gate and the first source and drain layer are arranged in the same layer.
  • FIG. 1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for manufacturing an array substrate provided in an embodiment of the present application
  • FIG. 4 is a flowchart of step S200 in FIG. 3 provided by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of step S200 in FIG. 3 provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of step S300 in FIG. 3 provided by an embodiment of the present application.
  • Embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • the embodiment of the present application provides an array substrate. As shown in FIG. 1, FIG. 5 and FIG. other film layer structures on the substrate 100 to keep the array substrate 100 relatively stable.
  • the base substrate 110 used may be a glass substrate or a rigid substrate or a flexible substrate made of other materials, which is not limited here.
  • the array substrate 100 includes a thin film transistor layer 120, and the thin film transistor layer 120 is arranged on the base substrate 110.
  • the thin film transistor layer 120 is used as a switch control structure on the array substrate 100, and is used to control other functional layer structures arranged on the array substrate 100. control to meet different application requirements.
  • the thin film transistor layer 120 includes a first thin film transistor 121
  • the first thin film transistor 121 includes a first active layer 1211, a first gate insulating layer 1212, and a first source and drain layer 1213 stacked on the base substrate 110.
  • the first gate insulating layer 1212 is located between the first active layer 1211 and the first source-drain layer 1213, and is used to separate the first active layer 1211 from the first source-drain layer 1213, so as to facilitate the The design of the connection method between the first source-drain layer 1213 and the first active layer 1211 .
  • the first active layer 1211, the first gate insulating layer 1212, and the first source-drain layer 1213 are sequentially arranged along the direction away from the base substrate 110, or the first source-drain layer 1213, the first The gate insulating layer 1212 and the first active layer 1211 are sequentially arranged along the direction away from the base substrate 110, that is, the positions of the first active layer 1211 and the first source-drain layer 1213 relative to the base substrate 110 can be exchanged.
  • the specific setting method can be adjusted accordingly according to actual design requirements.
  • the first source-drain layer 1213 includes a first source 1213a and a first drain 1213b electrically connected to the first active layer 1211, by connecting the first source 1213a and the first drain 1213b with the first active Layer 1211 is electrically connected, and the control of the driving voltage on the first source 1213a and the first drain 1213b can realize the conduction of the first active layer 1211 connected between the first source 1213a and the first drain 1213b. On and off, so as to realize the control of other functional layer structures disposed on the array substrate 100 .
  • the first thin film transistor 121 further includes a first gate 1214, the first gate 1214 is located on the first gate insulating layer 1212, and the first gate 1214 is used as a switch structure of the first thin film transistor 121, by regulating the first gate 1214 A driving voltage at the input end of the gate 1214 can control the first thin film transistor 121 to be turned on or off, so as to realize the regulation and control of other functional structures by the first thin film transistor 121 .
  • the first gate 1214 and the first source-drain layer 1213 are arranged in the same layer, that is, the first gate 1214 and the first source-drain layer 1213 belong to the same metal layer, that is, the first gate 1214 and the first source
  • the pole 1213a and the first drain 1213b are arranged in the same layer, and this structural arrangement enables the first source 1213a and the first drain 1213b in the first gate 1214 and the first source-drain layer 1213 to adopt The same photomask is manufactured at the same time, thereby saving one photomask, simplifying the manufacturing process of the array substrate 100, improving the production efficiency of the array substrate 100, and reducing the production cost.
  • the array substrate 100 includes a base substrate 110 and a thin film transistor layer 120
  • the thin film transistor layer 120 includes a first thin film transistor 121
  • the first thin film transistor 121 includes a first active layer 1211, a first gate insulating layer 1212 , a first source-drain layer 1213 and a first gate 1214
  • the first source-drain layer 1213 includes a first source 1213a and a first drain 1213b electrically connected to the first active layer 1211
  • the first gate The electrode 1214 is set in the same layer as the first source-drain layer 1213 .
  • the first gate 1214 and the first source-drain layer 1213 can be fabricated simultaneously using the same photomask during the fabrication process, Therefore, the manufacturing process of the array substrate 100 is simplified, the production efficiency of the array substrate 100 is improved, and the production cost is reduced.
  • the first gate 1214 is spaced apart from the first source 1213a and the first drain 1213b to avoid Mutual interference occurs among the first gate 1214 , the first source 1213 a and the first drain 1213 b, thereby affecting the normal turn-on and turn-off of the first thin film transistor 121 .
  • a first opening 1212a is opened on the first gate insulating layer 1212 at a position corresponding to the gap 1215, so as to ensure that the first gate 1214 is completely separated from the first source 1213a and the first drain 1213b, so as to avoid gaps in the array substrate.
  • the etching is incomplete due to etching precision or etching depth, etc., which causes interference between the first gate 1214, the first source 1213a and the first drain 1213b, thereby ensuring the stability of the first thin film transistor 121. structural stability.
  • the array substrate 100 includes a planar layer 123, the planar layer 123 is disposed on the first source-drain layer 1213 and the first gate 1214, and the planar layer 123 fills the first gate 1214 and the first source 1213a and the first The gap 1215 between the drain electrodes 1213b and the first opening 1212a on the first gate insulating layer 1212 .
  • the planar layer 123 By setting the planar layer 123, the surface of the array substrate 100 can be planarized to facilitate the connection between the array substrate 100 and the subsequent functional layer structure, and the connection between the first gate 1214 and the first source 1213a and the first drain 1213b can also be improved. The electrical insulation between them can avoid mutual interference and improve the structural stability of the first thin film transistor 121 .
  • the first thin film transistor 121 further includes a second gate 1216 and an interlayer dielectric layer 1217, the second gate 1216 is located on the side of the first active layer 1211 close to the substrate 110, and the interlayer dielectric layer 1217 is Located between the first active layer 1211 and the second gate 1216, to separate the second gate 1216 from the first active layer 1211, to avoid direct contact between the second gate 1216 and the first active layer 1211, thereby It affects the control of turning on and off of the first thin film transistor 121 .
  • the second gate 1216 is provided on the side of the first active layer 1211 close to the base substrate 110, so that the second gate 1216 and the first gate 1214 form a double gate structure, and the second gate 1216 can be An effective electrostatic shielding effect is played between a gate and the first drain 1213b, so that the feedback capacitance between the first gate 1214 and the first drain 1213b is greatly reduced, and the load of the first thin film transistor 121 is increased. Flow rate.
  • the second grid 1216 is arranged correspondingly to the first active layer 1211, and the second grid 1216 can also function as the light-shielding metal layer 124 to shield the external ambient light and prevent the external ambient light from irradiating the first active layer.
  • the source layer 1211 affects the structure of the first active layer 1211 , further improving the overall structural stability of the first thin film transistor 121 .
  • the second gate 1216 can also be arranged on the side of the first active layer 1211 away from the substrate 110, that is, the second gate 1216 and the first gate 1214 are located on the same side of the first active layer 1211.
  • the second gate 1216 and the first gate 1214 can also form a double gate structure, so as to improve the carrier mobility of the first thin film transistor 121 .
  • a layer of light-shielding metal layer 124 can be formed on the base substrate 110 corresponding to the position of the first active layer 1211, so as to ensure that the first thin film transistor 121 overall structural stability.
  • the array substrate 100 includes a second thin film transistor 122 , and the second thin film transistor 122 and the first thin film transistor 121 are arranged in parallel on the base substrate 110 .
  • the diversity of drive control of the array substrate 100 can be improved, so as to meet different control requirements for other functional layer structures disposed on the array substrate 100 .
  • the second thin film transistor 122 includes a second active layer 1221, a first gate insulating layer 1212 and a second source-drain layer 1226 stacked on the base substrate 110, and the first gate insulating layer 1212 is located on the second Between the second active layer 1221 and the second source-drain layer 1226, it is used to separate the second active layer 1221 from the second source-drain layer 1226, so as to separate the second source-drain layer 1226 from the second active layer 1226.
  • the design of the connection mode between the source layers 1221 is used to separate the second active layer 1221 from the second source-drain layer 1226, so as to separate the second source-drain layer 1226 from the second active layer 1226.
  • the second active layer 1221, the first gate insulating layer 1212 and the second source-drain layer 1226 are sequentially arranged along the direction away from the base substrate 110, or the second source-drain layer 1226, the first The gate insulating layer 1212 and the second active layer 1221 are sequentially arranged along the direction away from the base substrate 110, that is, the positions of the second active layer 1221 and the second source-drain layer 1226 relative to the base substrate 110 can be exchanged, and the The specific setting method can be adjusted accordingly according to actual design requirements.
  • the second source-drain layer 1226 includes a second source 1226a and a second drain 1226b electrically connected to the second active layer 1221, by connecting the second source 1226a and the second drain 1226b with the second active Layer 1221 is electrically connected, and the control of the driving voltage on the second source 1226a and the second drain 1226b can realize the conduction of the second active layer 1221 connected between the second source 1226a and the second drain 1226b. On and off, so as to realize the control of other functional layer structures disposed on the array substrate 100 .
  • the second source-drain layer 1226 is set in the same layer as the first source-drain layer 1213 and the first gate 1214, that is, the second source-drain layer 1226, the first source-drain layer 1213 and the first gate 1214 are arranged in the same layer, that is, the second source 1226a, the second drain 1226b, the first source 1213a, the first drain 1213b and the first gate 1214 are arranged in the same layer.
  • This structural arrangement enables the second source electrode 1226a, the second drain electrode 1226b, the first source electrode 1213a, the first drain electrode 1213b and the first gate electrode 1214 to be fabricated simultaneously using the same photomask during the fabrication process of the array substrate 100. , so as to simplify the manufacturing process of the array substrate 100, improve the production efficiency, and reduce the production cost.
  • a second opening 1212b is opened on the first gate insulating layer 1212 corresponding to the first source 1213a, the second opening 1212b leaks out of the second active layer 1221, and the first source 1213a passes through the second The opening 1212b is electrically connected to the second active layer 1221; at the same time, a third opening 1212c is opened on the first gate insulating layer 1212 corresponding to the first source 1213a and the first drain 1213b, and the first source 1213a and the first drain 1213b are electrically connected to the first active layer 1211 through the third opening 1212c; the position corresponding to the second source 1226a and the second drain 1226b on the first gate insulating layer 1212 is also provided with a fourth The opening 1212d, the second source 1226a and the second drain 1226b are electrically connected to the second active layer 1221 through the fourth opening 1212d, so as to realize the electrical connection between the first thin film transistor 121 and the second thin film transistor 122 , so as to coordinate and regulate
  • the second thin film transistor 122 includes a third gate 1223 and a second gate insulating layer 1222, wherein the third gate 1223 is arranged corresponding to the second active layer 1221, and the second gate insulating layer 1222 is located Between the third grid 1223 and the second active layer 1221, to separate the third grid 1223 from the second active layer 1221, avoiding the third grid 1223 from being in direct contact with the second active layer 1221, thereby affecting Controlling the turn-on and turn-off of the second thin film transistor 122 .
  • the third gate 1223 is located on the side of the second active layer 1221 away from the base substrate 110. By adjusting the driving voltage at the input end of the third gate 1223, the second source 1226a and the The second drain 1226b is controlled to be turned on or off, so as to control the second thin film transistor 122 to be turned on or off.
  • the third gate 1223 is located on the side of the second active layer 1221 away from the base substrate 110, external ambient light may irradiate the second active layer 1221 through the base substrate 110, causing damage to the structure of the second active layer 1221. Therefore, it is necessary to arrange a layer of light-shielding metal layer 124 on the side of the second active layer 1221 close to the base substrate 110, so as to prevent the second active layer 1221 from undergoing structural changes due to the irradiation of external ambient light, thereby ensuring the second The structural stability of the thin film transistor 122.
  • the third gate 1223 is located on the side of the second active layer 1221 close to the base substrate 110. At this time, the third gate 1223 can connect the second source 1226a and the second drain 1226b In addition to regulating the conduction or disconnection between them, the third gate 1223 can also serve as the light-shielding metal layer 124 to protect the second active layer 1221 and ensure the structural stability of the second thin film transistor 122 .
  • the third gate 1223 can be arranged on the same layer as the second gate 1216, that is, the third gate 1223 and the second gate 1216 belong to the same metal layer.
  • This structural arrangement makes the third gate 1223 and the second gate 1216
  • the second grid 1216 can be fabricated simultaneously with the same photomask during the fabrication of the array substrate 100 , thereby simplifying the fabrication process of the array substrate 100 , improving production efficiency, and reducing production costs.
  • the third gate 1223 can also be set in the same layer as the first source-drain layer 1213, that is, the third gate 1223, the second source 1226a, the second drain 1226b, the first source 1213a, Both the first drain electrode 1213b and the first gate electrode 1214 belong to the same metal layer, thereby further simplifying the manufacturing process of the array substrate 100, improving production efficiency, and reducing production cost.
  • the second thin film transistor 122 further includes a fourth gate 1225 and a third gate insulating layer 1224, the third gate insulating layer 1224 is located between the third gate 1223 and the fourth gate 1225, the fourth gate
  • the electrode 1225 is arranged corresponding to the second active layer 1221 , and the arrangement of the fourth gate 1225 enables a double gate structure to be formed in the second thin film transistor 122 , thereby improving the carrier mobility of the second thin film transistor 122 .
  • the third gate 1223 and the fourth gate 1225 are located on the side of the second active layer 1221 away from the base substrate 110, it is necessary to set the second active layer 1221 on the side close to the base substrate 110
  • a light-shielding metal layer 124 is used to ensure the structural stability of the array substrate 100 .
  • the gate can also serve as the light-shielding metal layer 124, so that the light-shielding can be omitted.
  • the metal layer 124 is provided to simplify the overall structure of the array substrate 100 .
  • the material of the first active layer 1211 includes one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide
  • the material of the second active layer 1221 includes low-temperature polysilicon
  • the first thin film transistor 121 is a metal oxide (Metal Oxide) thin film transistor
  • the second thin film transistor 122 is a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) thin film transistor.
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility, small size, fast charging, and fast switching speed, and has a good effect when used for gate driving; the metal oxide thin film transistor has good uniformity and low leakage current. Advantages, can be used for display pixel drive. Therefore, by forming a low-temperature polysilicon thin film transistor and a metal oxide thin film transistor into a mixed thin film transistor structure, the driving current in the gate drive circuit of the display device can be increased, and the leakage current when the display pixel of the display device is driven can be reduced, thereby Improve the applicability of the array substrate 100 .
  • the embodiment of the present application also provides a display panel, which includes an array substrate.
  • a display panel which includes an array substrate.
  • the specific structure of the array substrate refer to the above-mentioned embodiments. Since this display panel adopts all the technical solutions of all the above-mentioned embodiments, it has at least the above-mentioned All the beneficial effects brought by the technical solutions of the embodiments will not be repeated here.
  • FIG. 2 is a schematic structural view of a display panel provided by an embodiment of the present application.
  • the display panel 10 includes an array substrate 100 , a light emitting device 200 and a package assembly 300 , wherein the light emitting device 200 is disposed on the array substrate 100 , the package assembly 300 is disposed on the light emitting device 200 .
  • the light emitting device 200 includes a plurality of light emitting pixels
  • the array substrate 100 includes a plurality of first thin film transistors 121 and a plurality of second thin film transistors 122
  • the light emitting pixels are electrically connected to corresponding first thin film transistors 121 and second thin film transistors 122
  • the connection mode between the light-emitting pixel and the first thin film transistor 121 and the second thin film transistor 122, and the regulation of the first thin film transistor 121 and the second thin film transistor 122 on or off it is possible to realize the control of multiple light emitting devices.
  • the control of the light emitting mode of the pixels realizes different display requirements of the display panel 10 and improves the display effect of the display panel 10 .
  • the display panel 10 in the embodiment of the present application has a wide range of applications, including various display and lighting display devices such as televisions, computers, mobile phones, foldable and rollable display screens, and wearable devices such as Smart bracelets and smart watches, etc., are all within the scope of the application field to which the display panel 10 in the embodiment of the present application belongs.
  • the embodiment of the present application also provides a method for manufacturing an array substrate.
  • the method for manufacturing an array substrate includes the following steps:
  • the base substrate 110 is used as a support structure in the array substrate 100 for supporting other film structures on the array substrate 100 to keep the array substrate 100 relatively stable.
  • the base substrate 110 used may be a glass substrate or a rigid substrate or a flexible substrate made of other materials, which is not limited here.
  • a first active layer 1211 is deposited on the base substrate 110 and etched according to design requirements to form a target pattern.
  • the material used for the first active layer 1211 includes one or more of indium gallium zinc oxide, indium tin oxide or indium zinc oxide, that is, the first active layer 1211 is a metal oxide semiconductor.
  • the thickness of the first active layer 1211 is greater than or equal to 400 angstroms and less than or equal to 1000 angstroms. If the thickness of the first active layer 1211 is too small, it may affect the carrier mobility of the first active layer 1211, thereby affecting the overall performance of the array substrate 100; if the thickness of the first active layer 1211 is too large, then This will cause the overall thickness of the array substrate 100 to be too large, which is not conducive to the structural design of the array substrate 100 .
  • the thickness of the first active layer 1211 is set to 400 angstroms, 600 angstroms, 800 angstroms or 1000 angstroms, etc., and the specific thickness value can be adjusted accordingly according to the actual design requirements, and there is no special limitation here.
  • a first gate insulating layer 1212 needs to be formed on its surface, and the first gate insulating layer 1212 covers the first active layer 1211 and the base substrate 110 .
  • the first gate insulating layer 1212 can separate the first active layer 1211, so as to facilitate the design of the connection method between subsequent film layers and the first active layer 1211; on the other hand, the first gate insulating layer 1212 can The surface of the first active layer 1211 is planarized to facilitate the effective fabrication of subsequent film layers.
  • the material used for the first gate insulating layer 1212 includes one or more of silicon oxide, silicon nitride or silicon oxynitride.
  • the thickness of the first gate insulating layer 1212 is greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms, while ensuring that the first gate insulating layer 1212 has sufficient physical insulation and electrical insulation, avoiding the first gate insulating layer 1212 from being too thick.
  • the thickness causes the overall thickness of the array substrate 100 to be too large, so as to facilitate the overall structural design of the array substrate 100 .
  • the first gate 1214, the first source 1213a and the first drain 1213b are all conductive structures, when the materials used are the same, the first gate 1214, the first source 1213a and the first drain 1213b can be manufactured simultaneously by using the same photomask.
  • the first gate electrode 1214, the first source electrode 1213a and the first drain electrode 1213b are in the same film layer, which is beneficial to simplify the manufacturing process of the array substrate 100 and improve the performance of the array substrate 100.
  • the first active layer 1211, the first gate insulating layer 1212, the first gate 1214, the first source 1213a and the first drain 1213b jointly form the first thin film transistor 121, because the first active layer 1211 uses
  • the material includes one or more of indium gallium zinc oxide, indium tin oxide or indium zinc oxide, so the type of the first thin film transistor 121 is a metal oxide thin film transistor.
  • a third opening 1212c is opened on the first gate insulating layer 1212 at a position corresponding to the first active layer 1211 by etching.
  • the hole 1212c leaks part of the first active layer 1211, and when the first source 1213a and the first drain 1213b are formed, the first source 1213a and the first drain 1213b will respectively fill the corresponding third opening 1212c, thereby The electrical connection between the first source electrode 1213a and the first drain electrode 1213b and the first active layer 1211 is realized.
  • the manufacturing method of the array substrate 100 in the embodiment of the present application includes sequentially forming the first active layer 1211 and the first gate insulating layer 1212 on the base substrate 110, and then forming the first gate on the first gate insulating layer 1212. 1214 , the first source 1213a and the first drain 1213b , and electrically connect the first source 1213a and the first drain 1213b to the first active layer 1211 .
  • the film layer can omit a photomask for separately manufacturing the first grid 1214 , thereby simplifying the manufacturing process of the array substrate 100 , improving production efficiency, and reducing production cost.
  • step S200 the first active layer 1211 and the first gate insulating layer 1212 are sequentially formed on the base substrate 110, mainly including the following steps:
  • a second active layer 1221 is firstly deposited on the base substrate 110 and etched according to design requirements to form a target pattern.
  • the material used for the second active layer 1221 includes low-temperature polysilicon, that is, the second active layer 1221 is a low-temperature polysilicon semiconductor.
  • a second gate insulating layer 1222 After forming the second active layer 1221 , a second gate insulating layer 1222 needs to be formed on its surface, and the second gate insulating layer 1222 covers the second active layer 1221 and the base substrate 110 .
  • the second gate insulating layer 1222 can separate the second active layer 1221, so as to facilitate the design of the connection method between the subsequent film layer and the second active layer 1221; on the other hand, the second gate insulating layer 1222 can The surface of the second active layer 1221 is planarized to facilitate the effective fabrication of subsequent film layers.
  • the material used for the second gate insulating layer 1222 includes one or more of silicon oxide, silicon nitride or silicon oxynitride.
  • the thickness of the second gate insulating layer 1222 is greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms, while ensuring that the second gate insulating layer 1222 has sufficient physical insulation and electrical insulation, the second gate insulating layer 1222 is prevented from being too thick.
  • the thickness causes the overall thickness of the array substrate 100 to be too large, so as to facilitate the overall structural design of the array substrate 100 .
  • a metal layer is deposited on the second gate insulating layer 1222, and then the metal layer is etched according to design requirements, so that the metal layer corresponds to the second active layer 1221.
  • the third gate 1223 is formed at the position, so as to facilitate the structure design of the thin film transistor corresponding to the second active layer 1221 .
  • a second gate 1216 is formed on the second gate insulating layer 1222, wherein the second gate 1216 corresponds to another thin film transistor, and its specific setting position can be determined according to the thickness of the thin film transistor.
  • the setting requirements should be adjusted accordingly, only need to ensure that the second grid 1216 and the third grid 1223 are of the same metal layer, so that the second grid 1216 and the third grid 1223 can be formed under one photomask at the same time to simplify the array
  • the manufacturing process of the substrate 100 improves the production efficiency and reduces the production cost.
  • an interlayer dielectric layer 1217 needs to be deposited on the second gate 1216 and the third gate 1223, and the interlayer dielectric layer 1217 covers the second gate. pole 1216, the third gate 1223 and the second gate insulating layer 1222.
  • the interlayer dielectric layer 1217 can separate the second gate 1216 and the third gate 1223, so as to facilitate the design of the connection mode between the subsequent film layer and the second gate 1216 and the third gate 1223; on the other hand, The interlayer dielectric layer 1217 can planarize the surfaces of the second gate 1216 and the third gate 1223 to facilitate the effective fabrication of subsequent film layers.
  • the material used for the interlayer dielectric layer 1217 includes one or more of silicon oxide, silicon nitride or silicon oxynitride.
  • the thickness of the interlayer dielectric layer 1217 is greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms. While ensuring that the interlayer dielectric layer 1217 has sufficient physical insulation and electrical insulation, it is also possible to prevent the interlayer dielectric layer 1217 from being too thick and causing the entire array substrate 100 The thickness is too large to facilitate the overall structural design of the array substrate 100 .
  • a first active layer 1211 is deposited on the interlayer dielectric layer 1217, and then the first active layer 1211 is etched to form a target pattern, and the first active layer 1211 Corresponding to the second gate 1216 .
  • the first active layer 1211 and the second gate 1216 correspond to the same thin film transistor, and setting the first active layer 1211 and the second gate 1216 correspondingly is beneficial to the structural design of the thin film transistor.
  • a first gate insulating layer 1212 needs to be formed on its surface, so that the first gate insulating layer 1212 covers the first active layer 1211 and the interlayer dielectric layer 1217 .
  • the first gate insulating layer 1212 can separate the first active layer 1211, so as to facilitate the design of the connection method between subsequent film layers and the first active layer 1211; on the other hand, the first gate insulating layer 1212 can The surface of the first active layer 1211 is planarized to facilitate the effective fabrication of subsequent film layers.
  • step S300 forming the first gate 1214, the first source 1213a and the first drain 1213b on the first gate insulating layer 1212 in step S300 includes:
  • first gate 1214 Form the first gate 1214, the first source 1213a, the first drain 1213b, the second source 1226a and the second drain 1226b on the first gate insulating layer 1212, so that the first source 1213a and the first drain
  • the pole 1213b is electrically connected to the first active layer 1211
  • the first source 1213a , the second source 1226a and the second drain 1226b are electrically connected to the second active layer 1221 .
  • the second active layer 1221 , the second gate insulating layer 1222 , the third gate 1223 , the first gate insulating layer 1212 , the first source 1213 a and the first drain 1213 b form the second thin film transistor 122 .
  • the second active layer 1221 is made of low temperature polysilicon
  • the type of the second thin film transistor 122 is a low temperature polysilicon thin film transistor.
  • a third opening 1212c is opened on the first gate insulating layer 1212 at a position corresponding to the first active layer 1211 by etching.
  • the hole 1212c leaks part of the first active layer 1211, so as to facilitate the electrical connection between the first source electrode 1213a and the first drain electrode 1213b and the first active layer 1211; the first gate insulating layer 1212 corresponds to the second active layer 1221
  • the position of the fourth opening 1212d is opened by etching, and the fourth opening 1212d leaks part of the second active layer 1221, so that the second source 1226a and the second drain 1226b are electrically connected to the second active layer 1221. connect.
  • the position corresponding to the second active layer 1221 on the first gate insulating layer 1212 is also provided with a second opening 1212b by etching, and the first source 1213a is electrically connected to the second active layer 1221 through the second opening 1212b.
  • connection that is, the first source electrode 1213a is electrically connected to the first active layer 1211 and the second active layer 1221 at the same time, so as to realize the electrical connection between the first thin film transistor 121 and the second thin film transistor 122, so as to facilitate the connection between the Coordinated regulation of other functional layer structures on the array substrate 100 .
  • the first gate 1214 when forming the first gate 1214, the first source 1213a, the first drain 1213b, the second source 1226a and the second drain 1226b on the first gate insulating layer 1212, the first gate A metal layer is deposited on the insulating layer 1212, and then the metal layer is etched according to the target pattern design requirements, so as to simultaneously form the first gate 1214, the first source 1213a, the first gate insulating layer 1212 on the first gate insulating layer 1212
  • the first drain 1213b, the second source 1226a and the second drain 1226b can omit unnecessary photomask process, simplify the manufacturing process of the array substrate 100, and improve the production efficiency.
  • the first gate 1214, the first source 1213a and the first drain 1213b all belong to the first thin film transistor 121 and are located relatively close to each other, in order to ensure that the first gate 1214 and the first source 1213a and The first drain electrodes 1213b are completely separated, and when the metal layer is etched, a gap 1215 is formed between the first gate electrode 1214, the first source electrode 1213a, and the first drain electrode 1213b.
  • the first gate insulating layer 1212 is etched to form a first opening 1212a at the position corresponding to the gap 1215 on the first gate insulating layer 1212, so as to ensure that the first gate 1214 is connected with the first source 1213a and the first
  • the drain 1213b is completely separated to avoid incomplete etching due to etching precision or etching depth during the fabrication of the array substrate 100, so that the gap between the first gate 1214 and the first source 1213a and the first drain 1213b The disturbance occurs, thereby ensuring the structural stability of the first thin film transistor 121 .
  • the manufacturing method of the array substrate 100 in the embodiment of the present application further includes: forming A flat layer 123 .
  • the flat layer 123 covers the first gate insulating layer 1212 and fills the gap 1215 between the first gate 1214 and the first source 1213a and the first drain 1213b and the first opening on the first gate insulating layer 1212. hole 1212a.
  • the planar layer 123 the surface of the array substrate 100 can be planarized to facilitate the connection between the array substrate 100 and the subsequent functional layer structure, and the connection between the first gate 1214 and the first source 1213a and the first drain 1213b can also be improved. The electrical insulation between them can avoid mutual interference and improve the structural stability of the first thin film transistor 121 .
  • a layer of light-shielding metal layer 124 is directly formed on the surface of the array substrate 100, and then A buffer layer 125 is formed on the light-shielding metal layer 124 .
  • the disposition position of the light-shielding metal layer 124 can be correspondingly adjusted according to the target disposition position of the corresponding thin film transistor, only needing to make the light-shielding metal layer 124 correspond to the corresponding first active layer 1211 and second active layer 1221 .
  • a layer of light-shielding metal layer 124 on the base substrate 110, it is possible to prevent external ambient light from irradiating the first active layer 1211 and the second active layer 1221 through the base substrate 110, thereby ensuring that the first active layer 1211 and the second active layer 1221 The structural stability of the second active layer 1221.
  • the buffer layer 125 can separate the light-shielding metal layer 124 from subsequent film layers to avoid mutual interference; at the same time, the buffer layer 125 can also planarize the surface of the light-shielding metal layer 124 to facilitate the effective formation of subsequent film layers.
  • each metal film layer in the embodiment of the present application includes the first gate 1214, the second gate 1216, and the first source 1213a in the first thin film transistor 121 and the first drain 1213b, as well as the third gate 1223, the fourth gate 1225, the second source 1226a and the second drain 1226b in the second thin film transistor 122, if the manufacturing process is feasible, they can cooperate with each other
  • the manufacturing method of the same layer is adopted to save the number of photomasks to the greatest extent, simplify the manufacturing process of the array substrate 100 , and improve the production efficiency.
  • both the first thin film transistor 121 and the second thin film transistor 122 can have a bottom gate structure or a top gate structure, and according to actual structure design requirements, the positions of their corresponding gates can be adjusted.
  • the first gate When the relative positions of 1214, the second grid 1216, the third grid 1223 and the fourth grid 1225 are changed, the corresponding manufacturing process can also be changed accordingly, and a gate structure arranged on the same layer is adopted with a photomask It can also be adjusted accordingly, as long as the number of photomasks is saved, the manufacturing process of the array substrate 100 is simplified, the production efficiency of the array substrate 100 is improved, and the production cost is reduced while meeting the structural design requirements of the array substrate 100 .

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Abstract

本申请实施例公开了一种阵列基板、显示面板及阵列基板的制作方法。阵列基板包括衬底基板和薄膜晶体管层；薄膜晶体管层包括第一薄膜晶体管，第一薄膜晶体管包括第一有源层、第一栅极绝缘层、第一源漏极层及与第一源漏极层同层设置的第一栅极。通过将第一栅极与第一源漏极层同层设置，能够简化制程工序。

Description

阵列基板、显示面板及阵列基板的制作方法 技术领域
本申请涉及显示领域，具体涉及一种阵列基板、显示面板及阵列基板的制作方法。
背景技术
随着显示技术的发展，具有高画质、省电、机身薄及应用范围广等优点的显示面板逐渐成为显示装置中的主流。薄膜晶体管(Thin Film Transistor，TFT)是显示面板中的主要驱动元件，直接关系到高性能显示面板的发展方向。
依据有源层材料的不同，薄膜晶体管分为非晶硅(a-Si)TFT、低温多晶硅(Low Temperature Poly-silicon，LTPS)TFT及金属氧化物(Metal Oxide)TFT。其中，不同类型的薄膜晶体管具有其独特的优势，通过将多种类型的薄膜晶体管形成混合TFT结构能够有效改善显示面板的显示效果。但在现有技术中，具有该混合薄膜晶体管结构的阵列基板的制程较复杂，使得阵列基板的生产效率较低且生产成本过高。
技术问题
本申请实施例提供一种阵列基板、显示面板及阵列基板的制作方法，可以解决现有阵列基板制程较复杂导致生产效率较低的问题。
技术解决方案
本申请实施例提供一种阵列基板，包括：
衬底基板；
薄膜晶体管层，设置在所述衬底基板上；所述薄膜晶体管层包括第一薄膜晶体管，所述第一薄膜晶体管包括层叠设置在所述衬底基板上的第一有源层、第一栅极绝缘层和第一源漏极层，所述第一栅极绝 缘层位于所述第一有源层和所述第一源漏极层之间，所述第一源漏极层包括与所述第一有源层电连接的第一源极和第一漏极；所述第一薄膜晶体管还包括第一栅极，所述第一栅极位于所述第一栅极绝缘层上，所述第一栅极与所述第一源漏极层同层设置。
可选的，在本申请的一些实施例中，所述第一有源层、所述第一栅极绝缘层和所述第一源漏极层沿远离所述衬底基板的方向依次设置。
可选的，在本申请的一些实施例中，所述第一栅极与所述第一源极和所述第一漏极之间具有间隙，所述第一栅极绝缘层上对应所述间隙的位置开设有第一开孔。
可选的，在本申请的一些实施例中，所述阵列基板包括平坦层，所述平坦层设置在所述第一源漏极层和所述第一栅极上，所述平坦层填充所述间隙和所述第一开孔。
可选的，在本申请的一些实施例中，所述第一薄膜晶体管还包括第二栅极和层间介质层，所述第二栅极位于所述第一有源层靠近所述衬底基板的一侧，所述层间介质层位于所述第一有源层和所述第二栅极之间。
可选的，在本申请的一些实施例中，所述阵列基板包括第二薄膜晶体管，所述第二薄膜晶体管与所述第一薄膜晶体管并列设置在所述衬底基板上；所述第二薄膜晶体管包括层叠设置在所述衬底基板上的第二有源层、所述第一栅极绝缘层和第二源漏极层，所述第一栅极绝缘层位于所述第二有源层和所述第二源漏极层之间，所述第二源漏极层包括与所述第二有源层电连接的第二源极和第二漏极；所述第二源漏极层与所述第一源漏极层和所述第一栅极同层设置。
可选的，在本申请的一些实施例中，所述第二有源层、所述第一栅极绝缘层和所述第二源漏极层沿远离所述衬底基板的方向依次设置。
可选的，在本申请的一些实施例中，所述第一栅极绝缘层上对应所述第一源极的位置开设有第二开孔，所述第二开孔漏出所述第二有 源层，所述第一源极通过所述第二开孔与所述第二有源层电连接。
可选的，在本申请的一些实施例中，所述第二薄膜晶体管包括第三栅极和第二栅极绝缘层，所述第三栅极与所述第二有源层对应设置，所述第二栅极绝缘层位于所述第三栅极和所述第二有源层之间；
所述第三栅极位于所述第二有源层背离所述衬底基板的一侧；或，
所述第三栅极位于所述第二有源层靠近所述衬底基板的一侧。
可选的，在本申请的一些实施例中，所述阵列基板还包括遮光金属层，所述遮光金属层位于所述第二有源层靠近所述衬底基板的一侧。
可选的，在本申请的一些实施例中，所述第三栅极与所述第二栅极同层设置；或，
所述第三栅极与所述第一源漏极层同层设置。
可选的，在本申请的一些实施例中，所述第二薄膜晶体管还包括第四栅极和第三栅极绝缘层，所述第三栅极绝缘层位于所述第三栅极和所述第四栅极之间，所述第四栅极与所述第二有源层对应设置。
可选的，在本申请的一些实施例中，所述第三栅极和所述第四栅极位于所述第二有源层背离所述衬底基板的一侧；或，
所述第三栅极和所述第四栅极中至少一个位于所述第二有源层靠近所述衬底基板的一侧。
可选的，在本申请的一些实施例中，所述第一有源层的材质包括氧化铟镓锌、氧化铟锡或氧化铟锌中的一种或多种；所述第二有源层的材质包括低温多晶硅。
相应的，本申请实施例还提供一种显示面板，所述显示面板包括上述任一项所述的阵列基板。
相应的，本申请实施例还提供一种阵列基板的制作方法，所述方法包括：
提供一衬底基板；
在所述衬底基板上依次形成第一有源层和第一栅极绝缘层；
在所述第一栅极绝缘层上形成第一栅极、第一源极和第一漏极，使所述第一源极和所述第一漏极与所述第一有源层电连接；所述第一 有源层、所述第一栅极绝缘层、所述第一栅极、所述第一源极和所述第一漏极形成第一薄膜晶体管。
可选的，在本申请的一些实施例中，所述在所述衬底基板上依次形成第一有源层和第一栅极绝缘层，包括：
在所述衬底基板上依次形成第二有源层和第二栅极绝缘层；
在所述第二栅极绝缘层上形成第二栅极和第三栅极，使所述第三栅极与所述第二有源层对应设置；
在所述第二栅极和所述第三栅极上形成层间介质层；
在所述层间介质层上对应所述第二栅极的位置形成第一有源层；
在所述第一有源层上形成第一栅极绝缘层。
可选的，在本申请的一些实施例中，所述在所述第一栅极绝缘层上形成第一栅极、第一源极和第一漏极，包括：
在所述第一栅极绝缘层上形成第一栅极、第一源极、第一漏极、第二源极和第二漏极，使所述第一源极和所述第一漏极与所述第一有源层电连接，所述第一源极、所述第二源极和所述第二漏极与所述第二有源层电连接；所述第二有源层、所述第二栅极绝缘层、所述第三栅极、所述第一栅极绝缘层、所述第一源极和所述第一漏极形成第二薄膜晶体管。
可选的，在本申请的一些实施例中，所述方法还包括：
在所述第一栅极、所述第一源极、所述第一漏极、所述第二源极和所述第二漏极上形成一层平坦层。
可选的，在本申请的一些实施例中，所述在所述衬底基板上依次形成第二有源层和第二栅极绝缘层之前，还包括：
在所述衬底基板上形成一层遮光金属层；
在所述遮光金属层上形成一层缓冲层。
有益效果
本申请实施例中阵列基板包括衬底基板和薄膜晶体管层，薄膜晶 体管层包括第一薄膜晶体管，第一薄膜晶体管包括第一有源层、第一栅极绝缘层、第一源漏极层和第一栅极，其中，第一源漏极层包括与第一有源层电连接的第一源极和第一漏极，第一栅极与第一源漏极层同层设置。通过将第一栅极与第一源漏极层同层设置，使得第一栅极、第一源极和第一漏极在制作过程中能够采用同一道光罩同时制成，从而简化阵列基板的制程工序，提高阵列基板的生产效率，降低生产成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种阵列基板的结构示意图；
图2是本申请实施例提供的一种显示面板的结构示意图；
图3是本申请实施例提供的一种阵列基板的制作方法的流程图；
图4是本申请实施例提供的图3中步骤S200的流程图；
图5是本申请实施例提供的图3中步骤S200的结构示意图；
图6是本申请实施例提供的图3中步骤S300的结构示意图。
附图标记说明：
Figure PCTCN2021141568-appb-000001
Figure PCTCN2021141568-appb-000002
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种阵列基板、显示面板及阵列基板的制作方法。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
首先，本申请实施例提供一种阵列基板，如图1、图5和图6所示，阵列基板100包括衬底基板110，衬底基板110作为阵列基板100中的支撑结构，用于支撑阵列基板100上的其他膜层结构，以保持阵列基板100的相对稳定。其中，所用衬底基板110可以是玻璃基板或其他材质的硬性基板或柔性基板，此处不做限制。
阵列基板100包括薄膜晶体管层120，薄膜晶体管层120设置在衬底基板110上，薄膜晶体管层120作为阵列基板100上的开关控制结构，用于对设置在阵列基板100上的其他功能层结构进行控制，以满足不同的应用需求。
其中，薄膜晶体管层120包括第一薄膜晶体管121，第一薄膜晶体管121包括层叠设置在衬底基板110上的第一有源层1211、第一栅极绝缘层1212和第一源漏极层1213，且第一栅极绝缘层1212位于第一有源层1211和第一源漏极层1213之间，用于将第一有源层1211和第一源漏极层1213隔开，以便于对第一源漏极层1213与第一有源层1211之间连接方式的设计。
需要说明的是，第一有源层1211、第一栅极绝缘层1212和第一源漏极层1213沿远离衬底基板110的方向依次设置，或者，第一源漏极层1213、第一栅极绝缘层1212和第一有源层1211沿远离衬底基板110的方向依次设置，即第一有源层1211和第一源漏极层1213相对衬底基板110的位置能够进行调换，其具体设置方式能够根据实际设计需求进行相应调整。
其中，第一源漏极层1213包括与第一有源层1211电连接的第一源极1213a和第一漏极1213b，通过将第一源极1213a和第一漏极1213b与第一有源层1211电连接，并对第一源极1213a和第一漏极1213b上驱动电压的调控，能够实现连接在第一源极1213a和第一漏极1213b之间的第一有源层1211的导通与断开，从而实现对设置在阵列基板100上的其他功能层结构的控制。
可选的，第一薄膜晶体管121还包括第一栅极1214，第一栅极1214位于第一栅极绝缘层1212上，第一栅极1214作为第一薄膜晶体管121的开关结构，通过调控第一栅极1214输入端的驱动电压，能够控制第一薄膜晶体管121导通或断开，从而实现第一薄膜晶体管121对其他功能结构的调控。
其中，第一栅极1214与第一源漏极层1213同层设置，即第一栅极1214与第一源漏极层1213属于同一层金属层，也即第一栅极1214 与第一源极1213a和第一漏极1213b同层设置，此种结构设置方式使得第一栅极1214和第一源漏极层1213中的第一源极1213a和第一漏极1213b在制作过程中能够采用同一道光罩同时制成，从而节省一道光罩，简化阵列基板100的制程工序，提高阵列基板100的生产效率，降低生产成本。
本申请实施例中阵列基板100包括衬底基板110和薄膜晶体管层120，薄膜晶体管层120包括第一薄膜晶体管121，第一薄膜晶体管121包括第一有源层1211、第一栅极绝缘层1212、第一源漏极层1213和第一栅极1214，其中，第一源漏极层1213包括与第一有源层1211电连接的第一源极1213a和第一漏极1213b，第一栅极1214与第一源漏极层1213同层设置。通过将第一栅极1214与第一源漏极层1213同层设置，使得第一栅极1214、第一源极1213a和第一漏极1213b在制作过程中能够采用同一道光罩同时制成，从而简化阵列基板100的制程工序，提高阵列基板100的生产效率，降低生产成本。
可选的，第一栅极1214与第一源极1213a和第一漏极1213b之间具有间隙1215，即第一栅极1214与第一源极1213a和第一漏极1213b间隔设置，以避免第一栅极1214、第一源极1213a和第一漏极1213b之间出现相互干扰，从而影响第一薄膜晶体管121的正常导通与断开。
其中，第一栅极绝缘层1212上对应间隙1215的位置开设有第一开孔1212a，以保证第一栅极1214与第一源极1213a和第一漏极1213b完全隔开，避免在阵列基板100制作过程中因刻蚀精度或刻蚀深度等导致刻蚀不完全，使第一栅极1214与第一源极1213a和第一漏极1213b之间出现干扰，从而保证第一薄膜晶体管121的结构稳定性。
可选的，阵列基板100包括平坦层123，平坦层123设置在第一源漏极层1213和第一栅极1214上，平坦层123填充第一栅极1214与第一源极1213a和第一漏极1213b之间的间隙1215以及第一栅极绝缘层1212上的第一开孔1212a。通过设置平坦层123，既能对阵列基板100表面进行平坦化，以便于阵列基板100与后续功能层结构的 连接，还能提高第一栅极1214与第一源极1213a和第一漏极1213b之间的电绝缘性，避免出现相互干扰，提高第一薄膜晶体管121的结构稳定性。
可选的，第一薄膜晶体管121还包括第二栅极1216和层间介质层1217，第二栅极1216位于第一有源层1211靠近衬底基板110的一侧，层间介质层1217则位于第一有源层1211和第二栅极1216之间，以将第二栅极1216与第一有源层1211隔开，避免第二栅极1216与第一有源层1211直接接触，从而影响对第一薄膜晶体管121导通和断开的控制。
其中，在第一有源层1211靠近衬底基板110的一侧设置第二栅极1216，使得第二栅极1216与第一栅极1214形成双栅极结构，第二栅极1216可在第一个栅极和第一漏极1213b之间起到有效的静电屏蔽作用，从而使得第一栅极1214与第一漏极1213b之间的反馈电容大大减小，提升第一薄膜晶体管121的载流子迁移率。
此外，第二栅极1216与第一有源层1211对应设置，第二栅极1216同时可以起到遮光金属层124的作用，以对外部环境光线进行遮挡，避免外部环境光线照射至第一有源层1211上而对第一有源层1211的结构产生影响，进一步提高第一薄膜晶体管121的整体结构稳定性。
需要说明的是，第二栅极1216也能够设置在第一有源层1211背离衬底基板110的一侧，即第二栅极1216和第一栅极1214位于第一有源层1211的同一侧，第二栅极1216和第一栅极1214同样能够形成双栅极结构，以提升第一薄膜晶体管121的载流子迁移率。此时，为避免外部环境光线对第一有源层1211结构的影响，可以在衬底基板110上对应第一有源层1211的位置形成一层遮光金属层124，以确保第一薄膜晶体管121的整体结构稳定性。
可选的，阵列基板100包括第二薄膜晶体管122，第二薄膜晶体管122与第一薄膜晶体管121并列设置在衬底基板110上。通过对多个薄膜晶体管之间相互配合的设计，能够提高阵列基板100驱动控制 的多样性，从而满足对设置在阵列基板100上的其他功能层结构的不同控制需求。
其中，第二薄膜晶体管122包括层叠设置在衬底基板110上的第二有源层1221、第一栅极绝缘层1212和第二源漏极层1226，且第一栅极绝缘层1212位于第二有源层1221和第二源漏极层1226之间，用于将第二有源层1221和第二源漏极层1226隔开，以便于对第二源漏极层1226与第二有源层1221之间连接方式的设计。
需要说明的是，第二有源层1221、第一栅极绝缘层1212和第二源漏极层1226沿远离衬底基板110的方向依次设置，或者，第二源漏极层1226、第一栅极绝缘层1212和第二有源层1221沿远离衬底基板110的方向依次设置，即第二有源层1221和第二源漏极层1226相对衬底基板110的位置能够进行调换，其具体设置方式能够根据实际设计需求进行相应调整。
其中，第二源漏极层1226包括与第二有源层1221电连接的第二源极1226a和第二漏极1226b，通过将第二源极1226a和第二漏极1226b与第二有源层1221电连接，并对第二源极1226a和第二漏极1226b上驱动电压的调控，能够实现连接在第二源极1226a和第二漏极1226b之间的第二有源层1221的导通与断开，从而实现对设置在阵列基板100上的其他功能层结构的控制。
可选的，第二源漏极层1226与第一源漏极层1213和第一栅极1214同层设置，即第二源漏极层1226、第一源漏极层1213和第一栅极1214同层设置，也即第二源极1226a、第二漏极1226b、第一源极1213a、第一漏极1213b和第一栅极1214同层设置。此种结构设置方式使得第二源极1226a、第二漏极1226b、第一源极1213a、第一漏极1213b和第一栅极1214在阵列基板100制作过程中能够采用同一道光罩同时制成，从而简化阵列基板100的制程工序，提高生产效率，降低生产成本。
可选的，第一栅极绝缘层1212上对应第一源极1213a的位置开设有第二开孔1212b，第二开孔1212b漏出第二有源层1221，第一源 极1213a则通过第二开孔1212b与第二有源层1221电连接；同时，第一栅极绝缘层1212上对应第一源极1213a和第一漏极1213b的位置开设有第三开孔1212c，第一源极1213a和第一漏极1213b则通过第三开孔1212c与第一有源层1211电连接；第一栅极绝缘层1212上对应第二源极1226a和第二漏极1226b的位置还开设有第四开孔1212d，第二源极1226a和第二漏极1226b则通过第四开孔1212d与第二有源层1221电连接，从而实现第一薄膜晶体管121与第二薄膜晶体管122之间的电连接，以便于对设置在阵列基板100上的其他功能层结构的配合调控。
可选的，第二薄膜晶体管122包括第三栅极1223和第二栅极绝缘层1222，其中，第三栅极1223与第二有源层1221对应设置，第二栅极绝缘层1222则位于第三栅极1223和第二有源层1221之间，以将第三栅极1223与第二有源层1221隔开，避免第三栅极1223与第二有源层1221直接接触，从而影响对第二薄膜晶体管122导通和断开的控制。
在一些实施例中，第三栅极1223位于第二有源层1221背离衬底基板110的一侧，通过对第三栅极1223输入端驱动电压的调控，能够实现对第二源极1226a和第二漏极1226b之间导通或断开的调控，从而实现对第二薄膜晶体管122导通或断开的控制。
由于第三栅极1223位于第二有源层1221背离衬底基板110的一侧，外部环境光线可能通过衬底基板110照射至第二有源层1221，对第二有源层1221的结构造成影响，故需要在第二有源层1221靠近衬底基板110的一侧设置一层遮光金属层124，以避免第二有源层1221受外部环境光线的照射而发生结构变化，从而保证第二薄膜晶体管122的结构稳定性。
在另一些实施例中，第三栅极1223位于第二有源层1221靠近衬底基板110的一侧，此时，第三栅极1223除能够对第二源极1226a和第二漏极1226b之间的导通或断开进行调控外，第三栅极1223还同时能够作为遮光金属层124，以对第二有源层1221形成保护，保 证第二薄膜晶体管122的结构稳定性。
可选的，第三栅极1223能够与第二栅极1216同层设置，即第三栅极1223与第二栅极1216属于同一层金属层，此种结构设置方式使得第三栅极1223和第二栅极1216在阵列基板100制作过程中能够采用同一道光罩同时制成，从而简化阵列基板100的制程工序，提高生产效率，降低生产成本。
在一些实施例中，第三栅极1223还能够与第一源漏极层1213同层设置，即第三栅极1223、第二源极1226a、第二漏极1226b、第一源极1213a、第一漏极1213b和第一栅极1214均属于同一金属层，从而进一步简化阵列基板100的制程工序，提高生产效率，降低生产成本。
可选的，第二薄膜晶体管122还包括第四栅极1225和第三栅极绝缘层1224，第三栅极绝缘层1224位于第三栅极1223和第四栅极1225之间，第四栅极1225与第二有源层1221对应设置，第四栅极1225的设置使得第二薄膜晶体管122中形成双栅结构，从而提升第二薄膜晶体管122的载流子迁移率。
其中，当第三栅极1223和第四栅极1225均位于第二有源层1221背离衬底基板110的一侧时，则需要在第二有源层1221靠近衬底基板110的一侧设置一层遮光金属层124，以保证阵列基板100的结构稳定性。当第三栅极1223和第四栅极1225中至少一个位于第二有源层1221靠近衬底基板110的一侧时，该栅极能够同时兼具遮光金属层124的作用，从而能够省略遮光金属层124的设置，以简化阵列基板100的整体结构。
可选的，本申请实施例中第一有源层1211的材质包括氧化铟镓锌、氧化铟锡或氧化铟锌中的一种或多种，第二有源层1221的材质则包括低温多晶硅，即第一薄膜晶体管121为金属氧化物(Metal Oxide)薄膜晶体管，第二薄膜晶体管122为低温多晶硅(Low Temperature Poly-silicon，LTPS)薄膜晶体管。
其中，低温多晶硅薄膜晶体管具有迁移率高、尺寸小、充电快、 开关速度快等优点，用于栅极驱动时具有很好的效果；金属氧化物薄膜晶体管则具有均一性良好及漏电流低的优点，可用于显示像素驱动。因此，通过将低温多晶硅薄膜晶体管和金属氧化物薄膜晶体管形成混合薄膜晶体管结构，既能提高显示装置的栅极驱动电路中的驱动电流，又能降低显示装置的显示像素驱动时的漏电流，从而提高阵列基板100的适用性。
其次，本申请实施例还提供一种显示面板，该显示面板包括阵列基板，该阵列基板的具体结构参照上述实施例，由于本显示面板采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
图2是本申请实施例提供的一种显示面板的结构示意图，如图2所示，显示面板10包括阵列基板100、发光器件200和封装组件300，其中，发光器件200设置于阵列基板100上，封装组件300设置于发光器件200上。
其中，发光器件200包括多个发光像素，阵列基板100包括多个第一薄膜晶体管121和多个第二薄膜晶体管122，发光像素与对应的第一薄膜晶体管121和第二薄膜晶体管122电连接，通过对发光像素与第一薄膜晶体管121和第二薄膜晶体管122的连接方式的设计，以及对第一薄膜晶体管121和第二薄膜晶体管122导通或断开方式的调控，能够实现对多个发光像素发光方式的控制，从而实现显示面板10不同的显示需求，提升显示面板10的显示效果。
需要说明的是，本申请实施例中显示面板10应用范围十分广泛，包括电视机、电脑、移动电话、可折叠以及可卷曲显示屏等各种显示及照明的显示装置中，以及可穿戴设备如智能手环和智能手表等，均在本申请实施例中的显示面板10所属应用领域范围内。
最后，本申请实施例还提供一种阵列基板的制作方法，如图3所示，阵列基板的制作方法包括以下步骤：
S100、提供一衬底基板110。衬底基板110作为阵列基板100中的支撑结构，用于支撑阵列基板100上的其他膜层结构，以保持阵列 基板100的相对稳定。其中，所用衬底基板110可以是玻璃基板或其他材质的硬性基板或柔性基板，此处不做限制。
S200、在衬底基板110上依次形成第一有源层1211和第一栅极绝缘层1212。
如图5所示，将衬底基板110清洗干净后，先在衬底基板110上沉积一层第一有源层1211，并根据设计需求对其进行刻蚀，以形成目标图案。第一有源层1211所用材质包括氧化铟镓锌、氧化铟锡或氧化铟锌中的一种或多种，即第一有源层1211为金属氧化物半导体。
其中，第一有源层1211的厚度大于或等于400埃且小于或等于1000埃。若第一有源层1211的厚度过小，则可能影响第一有源层1211的载流子迁移率，从而影响阵列基板100的整体性能；若第一有源层1211的厚度过大，则会导致阵列基板100的整体厚度过大，不利于阵列基板100的结构设计。
在实际制作过程中，将第一有源层1211的厚度设置为400埃、600埃、800埃或1000埃等，其具体厚度值能够根据实际设计需求进行相应调整，此处不做特殊限制。
制作形成第一有源层1211后，需要在其表面形成一层第一栅极绝缘层1212，第一栅极绝缘层1212覆盖第一有源层1211和衬底基板110。一方面，第一栅极绝缘层1212能够将第一有源层1211隔开，以便于后续膜层与第一有源层1211连接方式的设计；另一方面，第一栅极绝缘层1212能够对第一有源层1211表面进行平坦化，以便于后续膜层的有效制作。
其中，第一栅极绝缘层1212所用材料包括氧化硅、氮化硅或氮氧化硅中的一种或多种。第一栅极绝缘层1212的厚度大于或等于1000埃且小于或等于5000埃，在保证第一栅极绝缘层1212具有足够的物理绝缘和电气绝缘的同时，避免第一栅极绝缘层1212过厚导致阵列基板100整体厚度过大，以便于阵列基板100整体的结构设计。
S300、在第一栅极绝缘层1212上形成第一栅极1214、第一源极1213a和第一漏极1213b，使第一源极1213a和第一漏极1213b与第 一有源层1211电连接。
如图6所示，利用第一栅极绝缘层1212将第一有源层1211隔开后，需要在第一栅极绝缘层1212上形成第一栅极1214、第一源极1213a和第一漏极1213b，由于第一栅极1214、第一源极1213a和第一漏极1213b均为导电结构，当其所用材料相同时，第一栅极1214、第一源极1213a和第一漏极1213b能够采用同一道光罩同时制成，此时，第一栅极1214、第一源极1213a和第一漏极1213b处于同一膜层，有利于简化阵列基板100的制程工艺，提高阵列基板100的生产效率。
其中，第一有源层1211、第一栅极绝缘层1212、第一栅极1214、第一源极1213a和第一漏极1213b共同形成第一薄膜晶体管121，由于第一有源层1211所用材质包括氧化铟镓锌、氧化铟锡或氧化铟锌中的一种或多种，故第一薄膜晶体管121类型为金属氧化物薄膜晶体管。
需要说明的是，在形成第一栅极绝缘层1212的过程中，通过刻蚀在第一栅极绝缘层1212上对应第一有源层1211的位置开设有第三开孔1212c，第三开孔1212c漏出部分第一有源层1211，在形成第一源极1213a和第一漏极1213b时，第一源极1213a和第一漏极1213b则会分别填充对应的第三开孔1212c，从而实现第一源极1213a和第一漏极1213b与第一有源层1211的电连接。
本申请实施例中阵列基板100的制作方法包括在衬底基板110上依次形成第一有源层1211和第一栅极绝缘层1212，然后在第一栅极绝缘层1212上形成第一栅极1214、第一源极1213a和第一漏极1213b，并使第一源极1213a和第一漏极1213b与第一有源层1211电连接。通过在第一栅极绝缘层1212上同时形成第一栅极1214、第一源极1213a和第一漏极1213b，使得第一栅极1214、第一源极1213a和第一漏极1213b处于同一膜层，能够省略一道单独制作第一栅极1214的光罩，从而简化阵列基板100的制程工艺，提高生产效率，降低生产成本。
可选的，如图4所示，步骤S200中在衬底基板110上依次形成第一有源层1211和第一栅极绝缘层1212，主要包括以下步骤：
S210、在衬底基板110上依次形成第二有源层1221和第二栅极绝缘层1222。
将衬底基板110清洗干净后，先在衬底基板110上沉积一层第二有源层1221，并根据设计需求对其进行刻蚀，以形成目标图案。第二有源层1221所用材质包括低温多晶硅，即第二有源层1221为低温多晶硅半导体。
制作形成第二有源层1221后，需要在其表面形成一层第二栅极绝缘层1222，第二栅极绝缘层1222覆盖第二有源层1221和衬底基板110。一方面，第二栅极绝缘层1222能够将第二有源层1221隔开，以便于后续膜层与第二有源层1221连接方式的设计；另一方面，第二栅极绝缘层1222能够对第二有源层1221表面进行平坦化，以便于后续膜层的有效制作。
其中，第二栅极绝缘层1222所用材料包括氧化硅、氮化硅或氮氧化硅中的一种或多种。第二栅极绝缘层1222的厚度大于或等于1000埃且小于或等于5000埃，在保证第二栅极绝缘层1222具有足够的物理绝缘和电气绝缘的同时，避免第二栅极绝缘层1222过厚导致阵列基板100整体厚度过大，以便于阵列基板100整体的结构设计。
S220、在第二栅极绝缘层1222上形成第二栅极1216和第三栅极1223，使第三栅极1223与第二有源层1221对应设置。
形成第二栅极绝缘层1222后，在第二栅极绝缘层1222上沉积一层金属层，然后根据设计需求对该金属层进行刻蚀，使该金属层在对应第二有源层1221的位置形成第三栅极1223，以便于第二有源层1221对应的薄膜晶体管的结构设计。
在对该金属层进行刻蚀的同时，在第二栅极绝缘层1222上形成第二栅极1216，其中，第二栅极1216与另一个薄膜晶体管对应，其具体设置位置能够根据薄膜晶体管的设置要求进行相应调整，只需保证第二栅极1216与第三栅极1223为同一金属层，从而使得第二栅极 1216和第三栅极1223能够在一道光罩下同时形成，以简化阵列基板100的制程工序，提高生产效率，降低生产成本。
S230、在第二栅极1216和第三栅极1223上形成层间介质层1217。
通过图案刻蚀形成第二栅极1216和第三栅极1223后，需要在第二栅极1216和第三栅极1223上沉积一层层间介质层1217，层间介质层1217覆盖第二栅极1216、第三栅极1223和第二栅极绝缘层1222。一方面，层间介质层1217能够将第二栅极1216和第三栅极1223隔开，以便于后续膜层与第二栅极1216和第三栅极1223连接方式的设计；另一方面，层间介质层1217能够对第二栅极1216和第三栅极1223的表面进行平坦化，以便于后续膜层的有效制作。
其中，层间介质层1217所用材料包括氧化硅、氮化硅或氮氧化硅中的一种或多种。层间介质层1217的厚度大于或等于1000埃且小于或等于5000埃，在保证层间介质层1217具有足够的物理绝缘和电气绝缘的同时，避免层间介质层1217过厚导致阵列基板100整体厚度过大，以便于阵列基板100整体的结构设计。
S240、在层间介质层1217上对应第二栅极1216的位置形成第一有源层1211。
形成层间介质层1217后，在层间介质层1217上沉积一层第一有源层1211，然后对第一有源层1211进行刻蚀，以形成目标图案，并使第一有源层1211与第二栅极1216对应。其中，第一有源层1211和第二栅极1216对应于同一个薄膜晶体管，将第一有源层1211与第二栅极1216对应设置，有利于该薄膜晶体管的结构设计。
S250、在第一有源层1211上形成第一栅极绝缘层1212。
通过图案刻蚀形成第一有源层1211后，需要在其表面形成一层第一栅极绝缘层1212，以使第一栅极绝缘层1212覆盖第一有源层1211和层间介质层1217。一方面，第一栅极绝缘层1212能够将第一有源层1211隔开，以便于后续膜层与第一有源层1211连接方式的设计；另一方面，第一栅极绝缘层1212能够对第一有源层1211表面进行平坦化，以便于后续膜层的有效制作。
可选的，步骤S300中在第一栅极绝缘层1212上形成第一栅极1214、第一源极1213a和第一漏极1213b包括：
在第一栅极绝缘层1212上形成第一栅极1214、第一源极1213a、第一漏极1213b、第二源极1226a和第二漏极1226b，使第一源极1213a和第一漏极1213b与第一有源层1211电连接，第一源极1213a、第二源极1226a和第二漏极1226b与第二有源层1221电连接。
其中，第二有源层1221、第二栅极绝缘层1222、第三栅极1223、第一栅极绝缘层1212、第一源极1213a和第一漏极1213b形成第二薄膜晶体管122。由于第二有源层1221所用材质包括低温多晶硅，故第二薄膜晶体管122的类型为低温多晶硅薄膜晶体管。
需要说明的是，在形成第一栅极绝缘层1212的过程中，通过刻蚀在第一栅极绝缘层1212上对应第一有源层1211的位置开设有第三开孔1212c，第三开孔1212c漏出部分第一有源层1211，以便于第一源极1213a和第一漏极1213b与第一有源层1211的电连接；第一栅极绝缘层1212上对应第二有源层1221的位置则通过刻蚀开设有第四开孔1212d，第四开孔1212d漏出部分第二有源层1221，以便于第二源极1226a和第二漏极1226b与第二有源层1221的电连接。
此外，第一栅极绝缘层1212上对应第二有源层1221的位置还通过刻蚀开设有第二开孔1212b，第一源极1213a通过第二开孔1212b与第二有源层1221电连接，即第一源极1213a同时与第一有源层1211和第二有源层1221电连接，以实现第一薄膜晶体管121和第二薄膜晶体管122之间的电连接，以便于对设置在阵列基板100上的其他功能层结构的配合调控。
具体的，在第一栅极绝缘层1212上形成第一栅极1214、第一源极1213a、第一漏极1213b、第二源极1226a和第二漏极1226b时，先在第一栅极绝缘层1212上沉积一层金属层，然后根据目标图案设计需求，对该金属层进行刻蚀，以在第一栅极绝缘层1212上同时形成第一栅极1214、第一源极1213a、第一漏极1213b、第二源极1226a和第二漏极1226b，从而能够省略不必要的光罩过程，简化阵列基板 100的制程工序，提高生产效率。
其中，由于第一栅极1214、第一源极1213a和第一漏极1213b同属于第一薄膜晶体管121，且所处位置相对较近，为保证第一栅极1214与第一源极1213a和第一漏极1213b之间完全隔开，在对该金属层进行刻蚀时，在第一栅极1214与第一源极1213a和第一漏极1213b之间形成间隙1215的同时，会进一步对第一栅极绝缘层1212进行刻蚀，以在第一栅极绝缘层1212上对应该间隙1215的位置形成第一开孔1212a，以保证第一栅极1214与第一源极1213a和第一漏极1213b完全隔开，避免在阵列基板100制作过程中因刻蚀精度或刻蚀深度等导致刻蚀不完全，使第一栅极1214与第一源极1213a和第一漏极1213b之间出现干扰，从而保证第一薄膜晶体管121的结构稳定性。
可选的，本申请实施例中阵列基板100的制作方法还包括：在第一栅极1214、第一源极1213a、第一漏极1213b、第二源极1226a和第二漏极1226b上形成一层平坦层123。其中，平坦层123覆盖第一栅极绝缘层1212并填充第一栅极1214与第一源极1213a和第一漏极1213b之间的间隙1215以及第一栅极绝缘层1212上的第一开孔1212a。通过设置平坦层123，既能对阵列基板100表面进行平坦化，以便于阵列基板100与后续功能层结构的连接，还能提高第一栅极1214与第一源极1213a和第一漏极1213b之间的电绝缘性，避免出现相互干扰，提高第一薄膜晶体管121的结构稳定性。
可选的，在制作阵列基板100的过程中，为进一步提高阵列基板100的结构稳定性，在将衬底基板110清洗干净后，先直接在阵列基板100表面形成一层遮光金属层124，然后在遮光金属层124上形成一层缓冲层125。
其中，遮光金属层124的设置位置能够根据对应薄膜晶体管的目标设置位置进行相应调整，只需使遮光金属层124与对应的第一有源层1211和第二有源层1221对应即可。通过在衬底基板110上形成一层遮光金属层124，能够避免外部环境光线通过衬底基板110照射至 第一有源层1211和第二有源层1221，从而保证第一有源层1211和第二有源层1221的结构稳定性。
缓冲层125的设置则能够将遮光金属层124与后续膜层隔开，以免出现相互干扰；同时，缓冲层125还能够对遮光金属层124表面进行平坦化，以便于后续膜层的有效形成。
需要说明的是，在阵列基板100的制作过程中，本申请实施例中的各金属膜层，包括第一薄膜晶体管121中的第一栅极1214、第二栅极1216、第一源极1213a和第一漏极1213b，以及第二薄膜晶体管122中的第三栅极1223、第四栅极1225、第二源极1226a和第二漏极1226b，在制作工艺可行的情况下，可以相互配合采用同层制作的方式，以最大限度上节省光罩次数，简化阵列基板100的制程工序，提高生产效率。
其中，第一薄膜晶体管121和第二薄膜晶体管122均可以为底栅结构或者顶栅结构，根据实际结构的设计需求，能够对其相应的栅极所处的位置进行调整，当第一栅极1214、第二栅极1216、第三栅极1223和第四栅极1225的相对位置发生改变时，其对应的制作流程也能够随之进行改变，采用一道光罩进行同层设置的栅极结构也能够随之进行调整，只需保证在满足阵列基板100结构设计需求的情况下节省光罩次数，简化阵列基板100的制程工序，提高阵列基板100的生产效率，降低生产成本即可。
以上对本申请实施例所提供的一种阵列基板、显示面板及阵列基板的制作方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    衬底基板；
    薄膜晶体管层，设置在所述衬底基板上；所述薄膜晶体管层包括第一薄膜晶体管，所述第一薄膜晶体管包括层叠设置在所述衬底基板上的第一有源层、第一栅极绝缘层和第一源漏极层，所述第一栅极绝缘层位于所述第一有源层和所述第一源漏极层之间，所述第一源漏极层包括与所述第一有源层电连接的第一源极和第一漏极；所述第一薄膜晶体管还包括第一栅极，所述第一栅极位于所述第一栅极绝缘层上，所述第一栅极与所述第一源漏极层同层设置。
  2. 根据权利要求1所述的阵列基板，其中，所述第一有源层、所述第一栅极绝缘层和所述第一源漏极层沿远离所述衬底基板的方向依次设置。
  3. 根据权利要求1所述的阵列基板，其中，所述第一栅极与所述第一源极和所述第一漏极之间具有间隙，所述第一栅极绝缘层上对应所述间隙的位置开设有第一开孔。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板包括平坦层，所述平坦层设置在所述第一源漏极层和所述第一栅极上，所述平坦层填充所述间隙和所述第一开孔。
  5. 根据权利要求1所述的阵列基板，其中，所述第一薄膜晶体管还包括第二栅极和层间介质层，所述第二栅极位于所述第一有源层靠近所述衬底基板的一侧，所述层间介质层位于所述第一有源层和所述第二栅极之间。
  6. 根据权利要求5所述的阵列基板，其中，所述阵列基板包括第二薄膜晶体管，所述第二薄膜晶体管与所述第一薄膜晶体管并列设置在所述衬底基板上；所述第二薄膜晶体管包括层叠设置在所述衬底基板上的第二有源层、所述第一栅极绝缘层和第二源漏极层，所述第一栅极绝缘层位于所述第二有源层和所述第二源漏极层之间，所述第 二源漏极层包括与所述第二有源层电连接的第二源极和第二漏极；所述第二源漏极层与所述第一源漏极层和所述第一栅极同层设置。
  7. 根据权利哟求6所述的阵列基板，其中，所述第二有源层、所述第一栅极绝缘层和所述第二源漏极层沿远离所述衬底基板的方向依次设置。
  8. 根据权利要求6所述的阵列基板，其中，所述第一栅极绝缘层上对应所述第一源极的位置开设有第二开孔，所述第二开孔漏出所述第二有源层，所述第一源极通过所述第二开孔与所述第二有源层电连接。
  9. 根据权利要求6所述的阵列基板，其中，所述第二薄膜晶体管包括第三栅极和第二栅极绝缘层，所述第三栅极与所述第二有源层对应设置，所述第二栅极绝缘层位于所述第三栅极和所述第二有源层之间；
    所述第三栅极位于所述第二有源层背离所述衬底基板的一侧；或，
    所述第三栅极位于所述第二有源层靠近所述衬底基板的一侧。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括遮光金属层，所述遮光金属层位于所述第二有源层靠近所述衬底基板的一侧。
  11. 根据权利要求9所述的阵列基板，其中，所述第三栅极与所述第二栅极同层设置；或，
    所述第三栅极与所述第一源漏极层同层设置。
  12. 根据权利要求9所述的阵列基板，其中，所述第二薄膜晶体管还包括第四栅极和第三栅极绝缘层，所述第三栅极绝缘层位于所述第三栅极和所述第四栅极之间，所述第四栅极与所述第二有源层对应设置。
  13. 根据权利要求12所述的阵列基板，其中，所述第三栅极和所述第四栅极位于所述第二有源层背离所述衬底基板的一侧；或，
    所述第三栅极和所述第四栅极中至少一个位于所述第二有源层靠近所述衬底基板的一侧。
  14. 根据权利要求6所述的阵列基板，其中，所述第一有源层的材质包括氧化铟镓锌、氧化铟锡或氧化铟锌中的一种或多种；所述第二有源层的材质包括低温多晶硅。
  15. 一种显示面板，其中，所述显示面板包括权利要求1所述的阵列基板。
  16. 一种阵列基板的制作方法，其中，所述方法包括：
    提供一衬底基板；
    在所述衬底基板上依次形成第一有源层和第一栅极绝缘层；
    在所述第一栅极绝缘层上形成第一栅极、第一源极和第一漏极，使所述第一源极和所述第一漏极与所述第一有源层电连接；所述第一有源层、所述第一栅极绝缘层、所述第一栅极、所述第一源极和所述第一漏极形成第一薄膜晶体管。
  17. 根据权利要求16所述的阵列基板的制作方法，其中，所述在所述衬底基板上依次形成第一有源层和第一栅极绝缘层，包括：
    在所述衬底基板上依次形成第二有源层和第二栅极绝缘层；
    在所述第二栅极绝缘层上形成第二栅极和第三栅极，使所述第三栅极与所述第二有源层对应设置；
    在所述第二栅极和所述第三栅极上形成层间介质层；
    在所述层间介质层上对应所述第二栅极的位置形成第一有源层；
    在所述第一有源层上形成第一栅极绝缘层。
  18. 根据权利要求17所述的阵列基板的制作方法，其中，所述在所述第一栅极绝缘层上形成第一栅极、第一源极和第一漏极，包括：
    在所述第一栅极绝缘层上形成第一栅极、第一源极、第一漏极、第二源极和第二漏极，使所述第一源极和所述第一漏极与所述第一有源层电连接，所述第一源极、所述第二源极和所述第二漏极与所述第二有源层电连接；所述第二有源层、所述第二栅极绝缘层、所述第三栅极、所述第一栅极绝缘层、所述第一源极和所述第一漏极形成第二薄膜晶体管。
  19. 根据权利要求18所述的阵列基板的制作方法，其中，所述方 法还包括：
    在所述第一栅极、所述第一源极、所述第一漏极、所述第二源极和所述第二漏极上形成一层平坦层。
  20. 根据权利要求17所述的阵列基板的制作方法，其中，所述在所述衬底基板上依次形成第二有源层和第二栅极绝缘层之前，还包括：
    在所述衬底基板上形成一层遮光金属层；
    在所述遮光金属层上形成一层缓冲层。
PCT/CN2021/141568 2021-12-17 2021-12-27 阵列基板、显示面板及阵列基板的制作方法 WO2023108811A1 (zh)

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