WO2022257183A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2022257183A1
WO2022257183A1 PCT/CN2021/101402 CN2021101402W WO2022257183A1 WO 2022257183 A1 WO2022257183 A1 WO 2022257183A1 CN 2021101402 W CN2021101402 W CN 2021101402W WO 2022257183 A1 WO2022257183 A1 WO 2022257183A1
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Prior art keywords
drain
source
semiconductor layer
semiconductor device
insulating layer
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PCT/CN2021/101402
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English (en)
French (fr)
Inventor
胡道兵
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Publication of WO2022257183A1 publication Critical patent/WO2022257183A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • the present application relates to the technical field of display panel manufacturing, in particular to a semiconductor device and a method for manufacturing the semiconductor device.
  • an array substrate is generally included.
  • the array substrate includes thin film transistors.
  • Commonly used thin film transistors include a top-gate self-aligned structure type thin film transistor, and the top-gate self-aligned structure type thin film transistor includes an active layer, wherein the active layer can be divided into a high-resistance region corresponding to the gate electrode and a region connected to the source and drain electrodes.
  • the corresponding low-resistance area because the gate electrode and the low-resistance area in the active layer do not overlap, there is a small parasitic capacitance between the gate electrode and the active layer, which can reduce the resistance of the active layer, thereby reducing Signal delay improves the display effect, and is widely used in high-resolution and large-size display panels.
  • problems in the currently prepared thin film transistors such as low mobility and poor stability, and when preparing thin film transistors, the array substrate is limited by the complicated preparation process, resulting in high production costs and difficult Meet larger size needs.
  • the semiconductor devices obtained in the existing manufacturing technology cannot meet the requirements of large-sized panels, and when the thin film transistors in the semiconductor devices work normally, the electron mobility of the device is small, which cannot meet the requirements of high refresh rate display.
  • an embodiment of the present application provides a semiconductor device and a method for manufacturing the semiconductor device.
  • a vertical channel thin film transistor is formed, which effectively improves the performance of the device. Carrier mobility, and ultimately improve the performance of semiconductor devices.
  • the first aspect of the embodiments of the present application provides a semiconductor device, including:
  • the main body portion of the source electrode and the main body portion of the drain electrode are arranged on different surfaces, the semiconductor layer is arranged on one side of the main body portion of the source electrode, and at least part of the semiconductor layer covers the source electrode
  • the main body part, the gate is arranged on the non-body part of the source, and the drain is grid-shaped.
  • the semiconductor layer includes a main body and an extension, the main body of the semiconductor layer is disposed on the source, and the extension of the semiconductor layer is disposed on the surface of the substrate.
  • one end of the drain is disposed on the semiconductor layer, and the other end of the drain is disposed on the surface of the substrate.
  • the projection of the gate on the substrate is outside the range of the projection of the drain on the substrate.
  • the semiconductor device further includes an insulating layer, one end of the insulating layer is disposed on the source, and the other end of the insulating layer is disposed on the main body portion of the drain.
  • the insulating layer includes a bent portion disposed between one end of the insulating layer and the other end of the insulating layer, the bent portion is connected to one side of the semiconductor layer and the The drain electrode is in contact with one side surface of the drain electrode, and the gate electrode is disposed on the insulating layer corresponding to the non-body portion of the source electrode and is in contact with the bent portion.
  • the source is in a grid shape.
  • the semiconductor device further includes a first contact electrode and a second contact electrode, the first contact electrode is disposed on one side of the drain, and the second contact electrode is disposed on the source pole side.
  • a second aspect of the embodiments of the present application provides a semiconductor device, including:
  • the main body portion of the source electrode and the main body portion of the drain electrode are arranged on different surfaces, the semiconductor layer is arranged on one side of the main body portion of the source electrode, and at least part of the semiconductor layer covers the source electrode the main part of the source, the gate is disposed on the non-body part of the source.
  • the semiconductor layer includes a main body and an extension, the main body of the semiconductor layer is disposed on the source, and the extension of the semiconductor layer is disposed on the surface of the substrate.
  • one end of the drain is disposed on the semiconductor layer, and the other end of the drain is disposed on the surface of the substrate.
  • the projection of the gate on the substrate is outside the range of the projection of the drain on the substrate.
  • the semiconductor device further includes an insulating layer, one end of the insulating layer is disposed on the source, and the other end of the insulating layer is disposed on the main body portion of the drain.
  • the insulating layer includes a bent portion disposed between one end of the insulating layer and the other end of the insulating layer, the bent portion is connected to one side of the semiconductor layer and the The drain electrode is in contact with one side surface of the drain electrode, and the gate electrode is disposed on the insulating layer corresponding to the non-body portion of the source electrode and is in contact with the bent portion.
  • the source or the drain is grid-like.
  • the semiconductor device further includes a first contact electrode and a second contact electrode, the first contact electrode is disposed on one side of the drain, and the second contact electrode is disposed on the source pole side.
  • a method for manufacturing a thin film transistor including the following steps:
  • B100 preparing a first insulating layer on the substrate
  • B101 preparing a source on the first insulating layer
  • B102 Prepare a semiconductor layer on one side of the source, and at least part of the semiconductor layer covers the main body of the source;
  • B103 Prepare a drain on the semiconductor layer, wherein at least part of the projection of the drain on the main body of the source overlaps with the main body of the source;
  • B104 Prepare a second insulating layer on the source electrode, wherein the second insulating layer is in contact with one side of the semiconductor layer and at least a part of the drain electrode;
  • B105 preparing a gate on the second insulating layer.
  • the step B102 includes: processing the semiconductor layer by a blue laser annealing process.
  • the drain when preparing and forming the drain, is arranged in a grid shape.
  • one end of the drain is disposed on the semiconductor layer, and the other end of the drain is disposed on the surface of the substrate.
  • the embodiment of the present application provides a semiconductor device and a method for manufacturing the semiconductor device.
  • the semiconductor layer is arranged on the source of the thin film transistor, and the drain is arranged on the semiconductor layer.
  • the gate of the thin film transistor is arranged at the corresponding positions on both sides of the semiconductor layer, thereby forming a vertical channel type thin film transistor, thereby improving the mobility of carriers in the thin film transistor, when the current is transmitted in the vertical channel , even if operations such as bending are performed on it, the performance of the device will not be affected, thereby effectively improving the performance of the thin film transistor.
  • FIG. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a bending structure of a semiconductor device provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the film layer structure of another semiconductor device provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of the film layer structure of the semiconductor device provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of a semiconductor device manufacturing process flow provided by an embodiment of the present application.
  • FIGS. 8A-8D are schematic diagrams of film layer structures corresponding to the semiconductor device manufacturing process provided in the embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • the semiconductor device includes a substrate 100 , a source 101 , a semiconductor layer 104 , a drain 105 , an insulating layer 102 and a gate 103 .
  • the source electrode 101 is arranged on the substrate 100, the semiconductor layer 104 is arranged on the source electrode 101, and the drain electrode 105 is arranged on the semiconductor layer 104, and at the same time, the drain electrode 105 is arranged on the substrate
  • the projection on 100 overlaps with the projection of source 101 on the substrate, and may overlap completely or partially.
  • the gate 103 is disposed on the insulating layer 102 .
  • the source electrode 101 includes a body portion 1011 and a non-body portion 1012 disposed on one side of the body portion 1011 .
  • the drain electrode 105 includes a drain body portion 1051 and a drain extension portion 1052
  • the semiconductor layer 104 includes a semiconductor layer body portion 1041 and a semiconductor layer extension portion 1042, wherein the source electrode 101 body portion 1011 and the drain electrode body portion 1051 are
  • the main body portion 1041 of the semiconductor layer is disposed on the source 101
  • the extension portion 1042 of the semiconductor layer extends to the surface of the substrate and is in contact with the substrate.
  • the thin film transistor inside the semiconductor device provided by the embodiment of the present application is a vertical channel type thin film transistor.
  • the vertical channel type thin film transistor is applied in a flexible panel, since the channel is vertically arranged, the panel is processed When bending, the channel can effectively avoid the effect of bending stress.
  • the semiconductor layer 104 When setting, the semiconductor layer 104 is arranged on one side of the source electrode 101, and the semiconductor layer 104 is at least partly correspondingly arranged on the source electrode 101, as shown in FIG.
  • the portion 1041 is provided on the body portion 1011 of the source electrode 101 .
  • at least the main body portion 1041 covers the main body portion 1011 of the source electrode 101 .
  • another part of the semiconductor layer 104 that is, the extension portion 1042 of the semiconductor layer 104 extends to the surface of the substrate 100 and is in contact with the surface of the substrate 100 .
  • the semiconductor layer 104 forms an inverted "L"-like structure. Therefore, different devices can be closely matched, thereby effectively improving the stability and reliability of the devices during use.
  • the drain 105 is correspondingly disposed on the semiconductor layer 104, and at the same time the drain 105 is extended to the bottom of the substrate 100. surface, at this time, both the semiconductor layer 104 and the drain electrode 105 are in contact with the surface of the substrate 100 .
  • the end of one side of the drain 105 is flush with the end of one side of the semiconductor layer 104 , so as to ensure consistency among different devices and improve the stability of the thin film transistor. Moreover, since the drain 105 completely covers the semiconductor layer 104 , there is a larger contact area between the drain 105 and the semiconductor layer 104 , ensuring the charge transfer effect in the thin film transistor, thereby improving the performance of the thin film transistor.
  • the insulating layer 102 is disposed on the source electrode 101 . Specifically, one end of the insulating layer 102 is disposed on the non-main portion 1012 of the source 101, and the other end of the insulating layer 102 is disposed on the main portion 1011 of the drain 105.
  • the insulating layer 102 also includes one end disposed on the insulating layer 102 and The bent portion 1021 between the other ends. Wherein, the bent portion 1021 is in contact with the side surfaces of the semiconductor layer 104 and the drain electrode 105 .
  • the insulating layer 102 can effectively block part of the source 101 , the semiconductor layer 104 and the drain 105 , and at the same time, the gate 103 is disposed on the insulating layer 102 corresponding to the non-body portion 1012 of the source 101 .
  • the grid 103 may be in contact with the bent portion 1021 , or a certain gap may be reserved between the grid 103 and the bent portion 1021 . Therefore, the performance of the thin film transistor is guaranteed.
  • the drain 105 of the thin film transistor in the embodiment of the present application is arranged on the source 101, and the semiconductor layer 104 is arranged between the drain 105 and the source 101, Therefore, the channel region of the thin film transistor is a vertical channel, and when the carriers in the thin film transistor are transported, they will be transported in the vertical channel region.
  • FIG. 2 is a schematic diagram of a bending structure of a semiconductor device provided by an embodiment of the present application.
  • the semiconductor device in the embodiment of the present application is applied to a flexible panel, since the thin film transistor inside the semiconductor device is a vertical channel type thin film transistor, a longitudinal crack 200 will appear during the bending process, and the longitudinal crack caused by 200 will not affect the charge transfer in the vertical direction, and the charge can still be transferred vertically from the drain 105 to the source 101 normally. Therefore, the bending process has little influence on the channel current, thereby effectively improving the bending resistance of the backplane.
  • FIG. 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • the semiconductor device includes a substrate 100 , a source 101 , a semiconductor layer 104 , a drain 105 , an insulating layer 102 and a gate 103 .
  • the source electrode 101 is arranged on the substrate 100, and the semiconductor layer 104 is arranged on the source electrode 101.
  • the semiconductor layer 104 in the embodiment of the present application is completely arranged on the source electrode 101. , and the semiconductor layer 104 is not in contact with the substrate.
  • the drain 105 is disposed on the semiconductor layer 104 .
  • One end of the insulating layer 102 is disposed on the source 101 , the other end of the insulating layer 102 extends to the drain 105 , and the insulating layer 102 is in contact with the semiconductor layer 104 and the corresponding sides of the drain 105 at the same time.
  • the gate 103 is disposed on the insulating layer 102, and when the gate 103 is disposed, the gate 103 is disposed on one side of the semiconductor layer 104, and when the gate 103 is disposed on one side of the semiconductor layer 104, the gate A capacitor structure can be formed between the electrode 103 and the source 101, so as to ensure the normal operation of the thin film transistor. Further, when setting the gate 103 , ensure that the projection of the gate 103 on the substrate 100 does not overlap with the projection of the drain 105 on the substrate 100 .
  • FIG. 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • the semiconductor device includes a substrate 100 , a source 101 , a semiconductor layer 104 , a drain 105 , an insulating layer 102 and a gate 103 .
  • the source 101 is disposed on the substrate 100
  • the semiconductor layer 104 is disposed on the source 101
  • the semiconductor layer 104 is disposed on one side of the source 101
  • the drain 105 is arranged on the semiconductor layer 104
  • the insulating layer 102 is arranged on the source 101
  • one end of the insulating layer 102 is arranged on the source 101
  • the insulating layer 102 covers the drain 105, meanwhile, the insulating layer 102
  • the other end extends onto the substrate 100 and is in contact with the surface of the substrate 100 .
  • the insulating layer 102 is in contact with the side surfaces of the two ends of the semiconductor layer 104 and the drain electrode 105 .
  • the semiconductor layer 104 and the drain electrode 105 are completely covered by the insulating layer 102 .
  • the thin film transistor works normally, the carriers are transported from the drain 105 to the source 101. Since the thin film transistor in the embodiment of the present application is a vertical channel type thin film transistor, even if the thin film transistor is bent, it will not affect the thin film transistor. affect the performance of the transistor.
  • the thickness of the semiconductor layer 104 is the same as the channel length of the TFT, and at the same time, the gate 103 is disposed on the insulating layer 102 , and the gate 103 is disposed on the insulating layer 102 corresponding to the source 101 .
  • a connection electrode can be provided on one side of the source 101 and the drain 105, or a connection electrode can be provided between the source 101 and the drain 105.
  • Corresponding vias are provided on one side of the drain 105, and the source 101 and the drain 105 are electrically connected to other film layers through the vias, thereby realizing the function of a thin film transistor.
  • the arrangement area and area of the insulating layer 102 are larger, so that the insulating layer 102 can block the semiconductor layer 104 and the drain 105 as much as possible, thereby preventing different devices from There are problems such as mutual interference between them, and various performances of thin film transistors are improved.
  • the gate 103 is arranged on one side of the insulating layer 102, and the gate 103 is arranged on the corresponding source 101.
  • a storage capacitor structure can be formed between the gate 103 and the corresponding source 101 .
  • the material of the source 101 and the drain 105 can be selected from, for example, metal, conductive material, metal alloy, etc., wherein the conductive material can be selected from indium tin oxide, etc., and the material of the source 101 and the drain 105 Can be the same.
  • the material of the semiconductor layer 104 can be InOx, IGZO, or ZnO
  • the material of the insulating layer 102 can be an insulating material such as alumina to ensure the insulating effect of the insulating layer 102 .
  • FIG. 5 is a schematic diagram of a film layer structure of another semiconductor device provided by an embodiment of the present application.
  • the semiconductor device includes a substrate 100 , a source 101 , a semiconductor layer 104 , a drain 105 , an insulating layer 102 and a gate 103 .
  • the source 101 is disposed on the substrate 100
  • the semiconductor layer 104 is disposed on the source 101
  • one side of the semiconductor layer 104 is disposed on the semiconductor layer 104
  • the other end of the semiconductor layer 104 extends to the substrate 100, And contact with the surface of the substrate 100 , so as to realize the conduction between the semiconductor layer 104 and the source 101 .
  • the drain 105 is disposed on the semiconductor layer 104 , and the projected area of the drain 105 on the semiconductor layer 104 is smaller than the area of the upper surface of the semiconductor layer 104 , that is, the drain 105 is completely disposed on the semiconductor layer 104 .
  • the insulating layer 102 is disposed on the source 101, specifically, one end of the insulating layer 102 is disposed on the substrate 100, the insulating layer 102 is in contact with the side of one end of the semiconductor layer 104 and the side of one end of the drain 105, and at the same time , the other end of the insulating layer 102 is disposed on the drain electrode 105, so as to realize the function of barrier between different film layers.
  • the gate 103 is arranged on one side of the insulating layer 102, and the projection of the gate 103 on the substrate 100 does not coincide with the projection of the drain 105 on the substrate 100, that is, the gate 103 is on the substrate 100.
  • the projection on is located outside the range of the projection of the drain electrode 105 on the substrate 100 .
  • the gate 103 and the source 101 can form a capacitor structure, and at the same time, the source 101 , the semiconductor layer 104 and the drain 105 form a vertical thin film transistor.
  • the thin film transistor is bent, since it is a vertical thin film transistor, bending in the longitudinal direction will not affect the performance of the thin film transistor, thereby effectively improving the performance of the thin film transistor.
  • the drain 105 or the source 101 in the embodiment of the present application can also be set as a grid structure, and the source 101 and the drain 105 of the grid structure are in the When bent, the internal bending stress is small, thereby effectively improving the performance of the thin film transistor.
  • FIG. 6 is a schematic diagram of the film layer structure of the semiconductor device provided by the embodiment of the present application.
  • the semiconductor device includes a substrate 100 , a source 101 , a semiconductor layer 104 , a drain 105 , an insulating layer 102 and a gate 103 .
  • the source electrode 101 is arranged on the substrate 100, one end of the semiconductor layer 104 is arranged on the source electrode 101, and one end of the semiconductor layer 104 is arranged on one side of the source electrode 101, and the other end of the semiconductor layer 104 extends to the substrate 100 and is in contact with the surface of the substrate 100.
  • the drain electrode 105 is arranged on the semiconductor layer 104, and the projection of the drain electrode 105 on the substrate 100 is located in the projection area of the semiconductor layer 104 on the substrate 100, and at the same time, one end of the drain electrode 105 is level with one end of the semiconductor layer 104 together.
  • One end of the insulating layer 102 is disposed on the source 101 , the other end of the insulating layer 102 is disposed on the drain 105 , and the insulating layer 102 is in contact with the side surfaces of the semiconductor layer 104 and one end of the drain 105 at the same time. Meanwhile, the gate 103 is disposed on the insulating layer 102 , and it is ensured that the projection of the gate 103 on the substrate 100 does not coincide with the projection of the drain 105 on the substrate 100 .
  • the semiconductor device further includes a first contact electrode 1053 and a second contact electrode 1054, the second contact electrode 1054 is disposed on the semiconductor layer 104, the first contact electrode 1053 is disposed on the drain 105, specifically, the second contact electrode 1054 is disposed on one side of the semiconductor layer 104 , and the first contact electrode 1053 is disposed on one side of the drain 105 . Therefore, the electrical connection with other film layers can be realized through the first contact electrode 1053 and the second contact electrode 1054 .
  • the drain 105 is arranged opposite to the source 101 to form a vertical channel thin film transistor.
  • the length of the thin film transistor channel is the thickness of the semiconductor layer 104, and the thickness can be determined according to the actual situation. Precise control is required, and the mobility of electrons in the semiconductor layer 104 is greater than that in the channel of a general thin film transistor, and the performance of the thin film transistor in the embodiment of the present application is more stable. Because it is a vertical channel thin film transistor, the size of the thin film transistor can be further reduced, thereby significantly reducing the area of the pixel, and on the other hand, significantly improving the electrical properties of the thin film transistor.
  • FIG. 7 is a schematic flow chart of the manufacturing process of the thin film transistor provided in the embodiment of the present application.
  • 8A-8D are schematic diagrams of film layer structures corresponding to the manufacturing process of the semiconductor device provided in the embodiment of the present application.
  • the preparation process includes the following steps:
  • B100 preparing a first insulating layer on the substrate
  • B101 preparing a source on the first insulating layer
  • a substrate 100 is provided.
  • the substrate 100 in the embodiment of the present application may include a multi-layer structure, for example, the substrate 100 includes a first substrate and a first insulating layer disposed on the first substrate.
  • the first substrate may include a glass substrate or a film material such as polyimide, and the first insulating layer may include an insulating film material such as silicon dioxide or silicon nitride.
  • a source 101 is prepared on the substrate 100.
  • the source 101 can be arranged on one side of the substrate 100, and one end of the source 101 can be connected to the substrate 100. one end is even.
  • B102 Prepare a semiconductor layer on one side of the source, and at least part of the semiconductor layer covers the main body of the source;
  • B103 Prepare a drain on the semiconductor layer, wherein at least part of the projection of the drain on the main body of the source overlaps with the main body of the source;
  • B104 Prepare a second insulating layer on the source electrode, wherein the second insulating layer is in contact with one side of the semiconductor layer and at least a part of the drain electrode;
  • a semiconductor layer 104 is prepared on the source electrode 101 , wherein, when the semiconductor layer 104 is prepared, the semiconductor layer 104 is disposed on one side of the source electrode 101 . Part of the semiconductor layer 104 is disposed on one side of the source 101 , and another part of the semiconductor layer 104 extends to the substrate 100 and is in contact with the surface of the substrate 100 . In this way, the semiconductor layer 104 is firmly fixed in the device.
  • the semiconductor layer 104 After the semiconductor layer 104 is prepared, continue to prepare the drain 105 on the semiconductor layer 104, wherein one end of the drain 105 is flush with one end of the semiconductor layer 104, and the other end of the drain 105 can extend to the surface of the substrate 100, and In contact with the surface of the substrate 100 , at least part of the projection of the drain electrode 105 on the body portion 1011 of the source electrode 101 overlaps with the body portion 1011 of the source electrode 101 . And the drain 105 completely covers the semiconductor layer 104 , and at least part of the projection of the drain 105 on the main body 1011 of the source 101 overlaps with the main body 1011 of the source 101 .
  • the semiconductor layer 104 when preparing the semiconductor layer 104, it also includes the step of: processing the semiconductor layer 104 through a blue laser annealing process.
  • the energy of the laser can be selected according to the thickness of the actual film. The specific value can be Choose according to different product needs.
  • the moving and scanning speed of the laser on the semiconductor layer 104 is controlled to ensure that the semiconductor layer can be completely annealed, to obtain thin film transistors with different crystallization properties, and finally achieve the purpose of improving device performance.
  • the drain 105 when preparing the drain 105, only a part of the drain 105 can also be provided, that is, the drain 105 is only provided in the corresponding region on the semiconductor layer 104, so as to simplify the structure in the thin film transistor and reduce the size of the thin film transistor. the goal of.
  • the insulating layer 102 is continued to be prepared, and the insulating layer 102 is the second insulating layer.
  • one end of the insulating layer 102 is disposed on the source 101 , and the other end of the insulating layer 102 extends to the surface of the drain 105 and is in contact with the drain 105 .
  • the insulating layer 102 further includes a bent portion 1021 , and the bent portion 1021 is in contact with the side surfaces of the semiconductor layer 104 and one end of the drain electrode 105 .
  • the insulating layer 102 forms a stepped structure, so as to realize the effect of blocking and insulating between different film layers.
  • B105 preparing a gate on the second insulating layer.
  • the gate 103 of the thin film transistor is prepared.
  • the gate 103 is disposed on the insulating layer 102, and the gate 103 is disposed on the insulating layer 102 corresponding to the first region 700 of the source 101. In this way, the gate 103 and the source 101 can form a capacitive structure, thereby realizing charge storage.
  • the projection of the gate 103 on the substrate 100 does not coincide with the projection of the drain 105 on the substrate 100 .
  • the thin film transistor is a vertical channel thin film transistor.
  • the length of the channel is the thickness of the semiconductor layer 104 disposed between the drain 105 and the source 101 .
  • the embodiment of the present application also provides a light emitting device, the light emitting device includes the thin film transistor provided in the embodiment of the present application, the thin film transistor is a vertical channel type thin film transistor, when the light emitting device is bent, the device still has better luminescence properties.

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Abstract

本申请提供一种半导体器件及其制备方法，半导体器件包括衬底、源极、半导体层、漏极、绝缘层以及栅极，源极的主体部与漏极的主体部异面设置，半导体层设置在源极与漏极之间，且栅极设置在半导体层的一侧，从而形成垂直沟道型薄膜晶体管。有效的提高了薄膜晶体管内载流子的迁移率，以及半导体器件的性能。

Description

半导体器件及其制备方法 技术领域
本申请涉及显示面板制造技术领域，特别是涉及一种半导体器件及半导体器件的制备方法。
 背景技术
随着显示技术的不断提升，新型显示产品对显示技术的要求也越来越高，特别是在大尺寸8K可卷曲型高端显示产品中，对显示背板的驱动能力也提出了更高的要求。
在显示面板等半导体器件中，一般包括阵列基板。其中，阵列基板包括薄膜晶体管。常用的薄膜晶体管包括顶栅自对准结构型薄膜晶体管，该顶栅自对准结构型薄膜晶体管包括有源层，其中有源层可分为与栅电极对应的高电阻区以及与源漏极对应的低电阻区，因栅电极和有源层中低电阻区没有交叠，使栅电极与有源层之间具有较小的寄生电容，可减小有源层的电阻，从而可减小信号延迟，提高显示效果，而被广泛的应用于高分辨率、大尺寸的显示面板中。但是，目前制备得到的薄膜晶体管还存在一定的问题，如迁移率较低以及稳定性差，并且，在制备薄膜晶体管时，阵列基板受限于复杂的制备工艺，从而造成生产成本较高，进而难以满足较大尺寸的需求。
因此需要对现有技术中的问题提出解决方法。
 技术问题
现有制备技术中得到的半导体器件还无法满足较大尺寸的面板需求，并且，半导体器件内的薄膜晶体管在正常工作时，器件电子迁移率较小，无法满足高刷新率显示的需求。
 技术解决方案
为解决上述问题，本申请实施例提供一种半导体器件及其半导体器件的制备方法，通过对半导体器件内的薄膜晶体管的结构进行改进，进而形成一种垂直沟道型薄膜晶体管，有效的提高器件载流子的迁移率，并最终提高半导体器件的性能。
为解决上述技术问题，本申请实施例提供的技术方法如下：
本申请实施例的第一方面，提供了一种半导体器件，包括：
衬底、源极、漏极、半导体层以及栅极；
其中，所述源极的主体部与所述漏极的主体部异面设置，所述半导体层设置在所述源极的主体部的一侧，且至少部分所述半导体层覆盖所述源极的主体部，所述栅极设置在所述源极的非主体部上，且所述漏极为网格状。
根据本申请一实施例，所述半导体层包括主体部和延伸部，所述半导体层的主体部设置在所述源极上，所述半导体层的延伸部设置于所述衬底的表面。
根据本申请一实施例，所述漏极的一端设置在所述半导体层上，所述漏极的另一端设置于所述衬底的表面。
根据本申请一实施例，所述栅极在所述衬底上的投影位于所述漏极在所述衬底上的投影的范围外。
根据本申请一实施例，所述半导体器件还包括绝缘层，所述绝缘层的一端设置在所述源极上，所述绝缘层的另一端设置于所述漏极的所述主体部上。
根据本申请一实施例，所述绝缘层包括设置在所述绝缘层的一端和所述绝缘层的另一端之间的弯折部，所述弯折部与所述半导体层的一侧面以及所述漏极的一侧面相接触，且所述栅极设置在所述源极的非主体部对应的所述绝缘层上并与所述弯折部相接触。
根据本申请一实施例，所述源极为网格状。
根据本申请一实施例，所述半导体器件还包括第一接触电极和第二接触电极，所述第一接触电极设置在所述漏极的一侧，所述第二接触电极设置在所述源极的一侧。
本申请实施例的第二方面，提供了一种半导体器件，包括：
衬底、源极、漏极、半导体层以及栅极；
其中，所述源极的主体部与所述漏极的主体部异面设置，所述半导体层设置在所述源极的主体部的一侧，且至少部分所述半导体层覆盖所述源极的主体部，所述栅极设置在所述源极的非主体部上。
根据本申请一实施例，所述半导体层包括主体部和延伸部，所述半导体层的主体部设置在所述源极上，所述半导体层的延伸部设置于所述衬底的表面。
根据本申请一实施例，所述漏极的一端设置在所述半导体层上，所述漏极的另一端设置于所述衬底的表面。
根据本申请一实施例，所述栅极在所述衬底上的投影位于所述漏极在所述衬底上的投影的范围外。
根据本申请一实施例，所述半导体器件还包括绝缘层，所述绝缘层的一端设置在所述源极上，所述绝缘层的另一端设置于所述漏极的所述主体部上。
根据本申请一实施例，所述绝缘层包括设置在所述绝缘层的一端和所述绝缘层的另一端之间的弯折部，所述弯折部与所述半导体层的一侧面以及所述漏极的一侧面相接触，且所述栅极设置在所述源极的非主体部对应的所述绝缘层上并与所述弯折部相接触。
根据本申请一实施例，所述源极或所述漏极为网格状。
根据本申请一实施例，所述半导体器件还包括第一接触电极和第二接触电极，所述第一接触电极设置在所述漏极的一侧，所述第二接触电极设置在所述源极的一侧。
根据本申请实施例的第二方面，还提供一种薄膜晶体管的制备方法，包括如下步骤：
B100：在衬底上制备第一绝缘层；
B101：在所述第一绝缘层上制备源极；
B102：在所述源极的一侧制备半导体层，且至少部分所述半导体层覆盖所述源极的主体部；
B103：在所述半导体层上制备漏极，其中，至少部分所述漏极在所述源极的主体部上的投影与所述源极的主体部重叠；
B104：在所述源极上制备第二绝缘层，其中，所述第二绝缘层与所述半导体层的一侧面以及所述漏极的至少一部分相接触；
B105：在所述第二绝缘层上制备栅极。
根据本申请一实施例，所述步骤B102包括：通过蓝色激光退火工艺对所述半导体层进行处理。
根据本申请一实施例，其中在制备形成所述漏极时，所述漏极设置为网格状。
根据本申请一实施例，其中所述漏极的一端设置在所述半导体层上，所述漏极的另一端设置在所述衬底的表面。
 有益效果
综上所述，本申请实施例的有益效果为：
本申请实施例提供一种半导体器件及半导体器件的制备方法，通过对半导体器件内的薄膜晶体管的结构进行改进，将半导体层设置在薄膜晶体管的源极上，并将漏极设置在半导体层，同时将薄膜晶体管的栅极设置在半导体层的两侧对应位置处，从而形成一种垂直沟道型薄膜晶体管，进而提高薄膜晶体管内载流子的迁移率，当电流在垂直型沟道内传输时，即使对其进行弯折等操作，也不会对器件的性能造成影响，进而有效的提高薄膜晶体管的性能。
 附图说明
图1为本申请实施例提供的一种半导体器件的结构示意图；
图2为本申请实施例提供的半导体器件的弯折结构示意图；
图3为本申请实施例提供的又一半导体器件的结构示意图；
图4为本申请实施例提供的另一半导体器件的结构示意图；
图5为本申请实施例提供的另一半导体器件的膜层结构示意图；
图6为本申请实施例提供的半导体器件的膜层结构示意图；
图7为本申请实施例提供的半导体器件制备工艺流程示意图；
图8A-图8D为本申请实施例提供的半导体器件制备工艺对应的膜层结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
随着显示面板制备技术的不断发展，人们希望制备并获得到质量及性能最佳的面板。但是，显示面板中的半导体器件在显示过程中，内部的薄膜晶体管的性能在很大程度上影响到器件的显示性能，因此，制备并获得具有较高迁移率等特点的薄膜晶体管对器件的显示性能具有重要的作用。
如图1所示，图1为本申请实施例提供的一种半导体器件的结构示意图。半导体器件包括衬底100、源极101、半导体层104、漏极105、绝缘层102以及栅极103。
具体的，在设置上述各膜层时，源极101设置在衬底100上，半导体层104设置在源极101上，同时漏极105设置在半导体层104上，同时，漏极105在衬底100上的投影与源极101在衬底上的投影重叠，可完全重叠或者部分重叠。栅极103设置在绝缘层102上。
优选的，如图1所示，源极101包括主体部1011和设置在主体部1011一侧的非主体部1012。漏极105包括漏极主体部1051和漏极延伸部1052，半导体层104包括半导体层的主体部1041和半导体层的延伸部1042，其中，源极101的主体部1011与漏极主体部1051为异面设置，半导体层的主体部1041设置在源极101上，半导体层的延伸部1042延伸至衬底表面，并与衬底相接触。
本申请实施例提供的半导体器件内部的薄膜晶体管为垂直沟道型薄膜晶体管，当将该垂直沟道型薄膜晶体管应用在可弯曲面板内时，由于沟道为垂直设置，因此，在对面板进行弯曲时，沟道可有效的避开弯曲应力的作用。
在设置时，半导体层104设置在源极101的一侧，并且半导体层104至少部分对应的设置在源极101上，如图1中所示，半导体层104的一部分，即半导体层104的主体部1041设置在源极101的主体部1011上。其中，至少主体部1041覆盖源极101的主体部1011。同时，半导体层104的另一部分，即半导体层104的延伸部1042延伸至衬底100的表面，并与衬底100的表面相接触。这样，半导体层104形成一类似倒“L”型结构。从而使得不同器件之间能紧密的相配合，进而有效的提高了器件在使用过程中的稳定性和可靠性能。
优选的，由于部分半导体层104设置在源极101上，因此，在设置漏极105时，将漏极105对应的设置在该半导体层104上，并且同时将漏极105延伸至衬底100的表面，此时半导体层104与漏极105的均与衬底100的表面相接触。
其中，漏极105的一侧的端部与半导体层104的一侧的端部相平齐，从而保证不同器件之间的一致性设置，以提高薄膜晶体管的稳定性。并且，由于漏极105完全覆盖半导体层104，因此，使得漏极105与半导体层104之间具有较大的接触面积，保证了薄膜晶体管内电荷的传输效果，从而提高了薄膜晶体管的性能。
本申请实施例中，绝缘层102设置在源极101上。具体的，绝缘层102的一端设置在源极101的非主体部1012上，绝缘层102的另一端设置在漏极105的主体部1011上，绝缘层102还包括设置在绝缘层102的一端与另一端之间的弯折部1021。其中，弯折部1021与半导体层104、漏极105的侧面相接触。这样，绝缘层102可有效地将部分源极101、半导体层104以及漏极105阻隔，同时，将栅极103设置在源极101的非主体部1012对应的绝缘层102上。本申请实施例中，栅极103可与弯折部1021接触，或者栅极103与弯折部1021之间预留一定的间隙。从而保证薄膜晶体管的性能。当对本申请实施例中的薄膜晶体管施加控制信号时，由于本申请实施例中的薄膜晶体管的漏极105设置在源极101上，并且半导体层104设置在漏极105与源极101之间，因此，薄膜晶体管的沟道区就为一垂直型沟道，当薄膜晶体管内的载流子在进行传输时，会在该垂直型的沟道区内传输。
进一步的，如图2所示，图2为本申请实施例提供的半导体器件弯折结构示意图。当将本申请实施例中的半导体器件应用在柔性面板中时，由于半导体器件内部的薄膜晶体管为垂直沟道型薄膜晶体管，在弯折的过程中，会出现纵向裂缝200，而造成的纵向裂缝200并不会对垂直方向上的电荷传输造成影响，电荷仍能正常的从漏极105垂直的传输到源极101上。因此，弯折过程对沟道电流影响较小，进而有效的提升背板耐弯折性。
如图3所示，图3为本申请实施例提供的又一半导体器件的结构示意图。具体的，半导体器件包括衬底100、源极101、半导体层104、漏极105、绝缘层102以及栅极103。
其中，源极101设置在衬底100上，半导体层104设置在源极101上，与图1中的薄膜晶体管的结构进行比较，本申请实施例中的半导体层104完全设置在源极101上，并且该半导体层104不与衬底相接触。进一步的，漏极105设置在半导体层104上。绝缘层102的一端设置在源极101上，绝缘层102的另一端延伸至漏极105上，并且绝缘层102同时与半导体层104以及漏极105对应的侧面相接触。
最后，再将栅极103设置在绝缘层102上，并且在设置栅极103时，将栅极103设置在半导体层104的一侧，当栅极103设置在半导体层104的一侧时，栅极103可与源极101之间形成电容结构，从而保证薄膜晶体管的正常工作。进一步的，在设置栅极103时，保证栅极103在衬底100上的投影与漏极105在衬底100上的投影不重叠。
结合图1以及图2中的结构，可知，图3中对薄膜晶体管左侧的结构进一步改进，使得薄膜晶体管的尺寸进一步减小，但是并未对薄膜晶体管的性能造成影响。当对薄膜晶体管进行弯折时，垂直沟道型薄膜晶体管仍具有较好的性能，从而有效提供器件的使用性能。
如图4所示，图4为本申请实施例提供的另一半导体器件的结构示意图。半导体器件包括衬底100、源极101、半导体层104、漏极105、绝缘层102以及栅极103。
具体的，源极101设置在衬底100上，半导体层104设置在源极101上，在本实施例中，半导体层104设置在源极101的一侧上。同时，漏极105设置在半导体层104上，绝缘层102设置在源极101上，并且，绝缘层102的一端设置在源极101上，绝缘层102覆盖漏极105，同时，绝缘层102的另一端延伸至衬底100上并与衬底100的表面相接触。进一步的，绝缘层102对应的与半导体层104和漏极105的两端的侧面相接触。此时，半导体层104和漏极105完全被绝缘层102所覆盖。当薄膜晶体管正常工作时，载流子从漏极105传输至源极101内，由于本申请实施例中的薄膜晶体管为垂直沟道型薄膜晶体管，即使薄膜晶体管被弯折，也不会对薄膜晶体管的性能造成影响。
具体的，半导体层104的厚度与薄膜晶体管的沟道长度相同，同时，将栅极103设置在绝缘层102上，并且将栅极103设置在源极101对应的绝缘层102上。
本申请实施例中，为了保证薄膜晶体管的源极101以及漏极105与其他膜层相连接，优选的，可在源极101和漏极105的一侧设置连接电极，或者在源极101和漏极105的一侧设置相应的过孔，并通过过孔使源极101和漏极105与其他膜层相电连接，进而实现薄膜晶体管的功能。
与图3中的薄膜晶体管相比，本申请实施例中，绝缘层102的布置面积及区域更大，这样，绝缘层102可尽可能的将半导体层104和漏极105阻隔，进而防止不同器件之间的出现相互干涉等问题，并提高薄膜晶体管的各项性能。
当薄膜晶体管设置为图3中所示的垂直沟道型薄膜晶体管的结构时，栅极103设置在绝缘层102的一侧上，并且，栅极103设置在对应的源极101上，这样，栅极103才能与相对应的源极101之间形成存储电容的结构。
本申请实施例中，源极101与漏极105的材质例如可选自金属、导电材料、金属合金等，其中导电材料可选择为铟锡氧化物等，且源极101与漏极105的材料可相同。进一步的，半导体层104的材料可为InOx、IGZO、或ZnO，同时，绝缘层102的材料可为氧化铝等绝缘材料以保证绝缘层102的绝缘效果。
如图5所示，图5为本申请实施例提供的另一半导体器件的膜层结构示意图。半导体器件包括衬底100、源极101、半导体层104、漏极105、绝缘层102以及栅极103。
具体的，源极101设置在衬底100上，半导体层104设置在源极101上，且半导体层104的一侧设置在半导体层104上，半导体层104的另一端延伸至衬底100上，并与衬底100的表面相接触，从而实现半导体层104与源极101之间的导通。
同时，漏极105设置在半导体层104上，且漏极105在半导体层104上的投影面积小于半导体层104的上表面的面积，即漏极105完全设置在半导体层104上。
进一步的，绝缘层102设置在源极101上，具体的，绝缘层102的一端设置在衬底100上，绝缘层102与半导体层104一端的侧面以及漏极105的一端的侧面相接触，同时，绝缘层102的另一端设置在漏极105上，从而实现对不同膜层之间的阻隔的作用。
优选的，栅极103设置在绝缘层102的一侧上，并且，栅极103在衬底100上的投影与漏极105在衬底100上的投影不重合，即栅极103在衬底100上的投影位于漏极105在衬底100上的投影的范围外。这样，栅极103与源极101可形成电容结构，同时，源极101、半导体层104以及漏极105形成一垂直结构型薄膜晶体管。当该薄膜晶体管被弯折时，由于为垂直型薄膜晶体管，在纵向的弯折并不会对薄膜晶体管的性能造成影响，从而有效的提高薄膜晶体管的性能。
选用的，为了进一步的提高半导体器件的弯折性能，本申请实施例中的就漏极105或源极101还可设置为网格状结构，网格状结构的源极101和漏极105在被弯折时，内部的弯折应力较小，从而有效的提高薄膜晶体管的性能。
如图6所示，图6为本申请实施例提供的半导体器件的膜层结构示意图。半导体器件包括衬底100、源极101、半导体层104、漏极105、绝缘层102以及栅极103。
进一步的，源极101设置在衬底100上，半导体层104的一端设置在源极101上，且半导体层104的一端设置在源极101的一侧，半导体层104的另一端延伸至衬底100的表面，并与衬底100的表面相接触。
漏极105设置在半导体层104上，且漏极105在衬底100上的投影位于半导体层104在衬底100上的投影区域内，同时，漏极105的一端与半导体层104的一端相平齐。
绝缘层102的一端设置在源极101上，绝缘层102的另一端设置在漏极105上，并且，绝缘层102同时与半导体层104、漏极105的一端的侧面相接触。同时，栅极103设置在绝缘层102上，并保证栅极103在衬底100上的投影与漏极105在衬底100上的投影不相重合。
优选的，半导体器件还包括第一接触电极1053和第二接触电极1054，第二接触电极1054设置在半导体层104上，第一接触电极1053设置在漏极105上，具体的，第二接触电极1054设置在半导体层104的一侧，第一接触电极1053设置在漏极105的一侧。因此，通过第一接触电极1053与第二接触电极1054可实现与其他膜层之间的电连接。
并且，本申请实施例中，漏极105相对设置在源极101上而形成垂直沟道型薄膜晶体管，此时，薄膜晶体管沟道的长度即为半导体层104的厚度，而该厚度可根据实际需要进行精确调控，且半导体层104中的电子迁移率比一般薄膜晶体管沟道内的迁移率大，并且，本申请实施例中的薄膜晶体管的性能更加稳定。由于为垂直沟道型薄膜晶体管，因此，薄膜晶体管的尺寸可进一步缩小，从而显著减小像素的面积，并且在另一方面，显著提高薄膜晶体管的电性。
进一步的，本申请实施例还提供一种薄膜晶体管的制备方法。如图7所示，图7为本申请实施例提供的薄膜晶体管制备工艺流程示意图。图8A-图8D为本申请实施例提供的半导体器件的制备工艺对应的膜层结构示意图。
具体的，制备工艺包括如下步骤：
B100：在衬底上制备第一绝缘层；
B101：在所述第一绝缘层上制备源极；
如图8A所示，提供衬底100，本申请实施例中的衬底100可包括多层结构，如衬底100包括第一基板以及设置在第一基板上的第一绝缘层。第一基板可包括玻璃基板或者聚酰亚胺等膜层材料，第一绝缘层可包括二氧化硅、氮化硅等绝缘膜层材料。
衬底100制备完成后，再在衬底100上制备一源极101，在制备源极101时，源极101可设置在衬底100的一侧，其源极101的一端可与衬底100的一端相平齐。
B102：在所述源极的一侧制备半导体层，且至少部分所述半导体层覆盖所述源极的主体部；
B103：在所述半导体层上制备漏极，其中，至少部分所述漏极在所述源极的主体部上的投影与所述源极的主体部重叠；
B104：在所述源极上制备第二绝缘层，其中，所述第二绝缘层与所述半导体层的一侧面以及所述漏极的至少一部分相接触；
如图8B所示，源极101制备完成后，在源极101上制备半导体层104，其中，在制备半导体层104时，半导体层104设置在源极101的一侧位置。部分半导体层104设置在源极101的一侧，同时，半导体层104的另一部分延伸至衬底100上，并与衬底100的表面相接触。这样，半导体层104便牢固的固定在器件内。
半导体层104制备完成后，继续在半导体层104上制备漏极105，其中，漏极105的一端与半导体层104的一端平齐，漏极105的另一端可延伸至衬底100的表面，并与衬底100的表面相接触，至少部分漏极105在源极101的主体部1011上的投影与源极101的主体部1011重叠。且漏极105将半导体层104完全覆盖，且至少部分漏极105在源极101的主体部1011上的投影与源极101的主体部1011相重叠。
进一步的，在制备半导体层104时，还包括步骤：通过蓝色激光退火工艺对所述半导体层104进行处理，在进行激光退火处理时，可根据实际薄膜的厚度选取激光的能量，具体值可根据不同的产品需要进行选取。同时，在激光退火时，控制激光在半导体层104上的移动扫描速度，以保证半导体层能完全退火，得到不同结晶性能的薄膜晶体管，并最终达到提高器件性能的目的。
优选的，在制备漏极105时，还可只设置部分漏极105，即漏极105只设置在半导体层104上对应的区域内，以简化薄膜晶体管内的结构，并达到减小薄膜晶体管尺寸的目的。
如图8C所示，漏极105制备完成后，继续制备绝缘层102，绝缘层102即为第二绝缘层。其中，绝缘层102的一端设置在源极101上，绝缘层102的另一端延伸至漏极105的表面，并与漏极105相接触。绝缘层102还包括弯折部1021，弯折部1021与半导体层104和漏极105的一端的侧面相接触。绝缘层102制备完成后，绝缘层102形成一阶梯状结构，从而实现对不同膜层之间的阻隔和绝缘效果。
B105：在所述第二绝缘层上制备栅极。
如图8D所示，绝缘层102制备完成后，制备薄膜晶体管的栅极103。栅极103设置在绝缘层102上，并且将栅极103设置在源极101的第一区域700对应的绝缘层102上，这样，栅极103与源极101可形成电容结构，从而实现对电荷的存储。
本申请实施例中，栅极103在衬底100上的投影与漏极105在衬底100上的投影不重合。同时，由于漏极105设置在源极101上，因此，薄膜晶体管为垂直沟道型薄膜晶体管。沟道的长度即为设置在漏极105与源极101之间的半导体层104的厚度。当薄膜晶体管被弯折后，由于为垂直沟道型薄膜晶体管，载流子仍能正常的在对应的沟道内传输，从而有效的保证了薄膜晶体管的性能。
进一步的，本申请实施例还提供一种发光装置，发光装置包括本申请实施例提供的薄膜晶体管，该薄膜晶体管为垂直沟道型薄膜晶体管，当发光装置被弯折后，器件仍具有较好的发光性能。
以上对本申请实施例所提供的一种半导体器件及半导体器件的制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种半导体器件，包括：
    衬底、源极、漏极、半导体层以及栅极；
    其中，所述源极的主体部与所述漏极的主体部异面设置，所述半导体层设置在所述源极的主体部的一侧，且至少部分所述半导体层覆盖所述源极的主体部，所述栅极设置在所述源极的非主体部上，且所述漏极为网格状。
  2. 根据权利要求1所述的半导体器件，其中所述半导体层包括主体部和延伸部，所述半导体层的主体部设置在所述源极上，所述半导体层的延伸部设置于所述衬底的表面。
  3. 根据权利要求2所述的半导体器件，其中所述漏极的一端设置在所述半导体层上，所述漏极的另一端设置于所述衬底的表面。
  4. 根据权利要求1所述的半导体器件，其中所述栅极在所述衬底上的投影位于所述漏极在所述衬底上的投影的范围外。
  5. 根据权利要求4所述的半导体器件，其中所述半导体器件还包括绝缘层，所述绝缘层的一端设置在所述源极上，所述绝缘层的另一端设置于所述漏极的所述主体部上。
  6. 根据权利要求5所述的半导体器件，其中所述绝缘层包括设置在所述绝缘层的一端和所述绝缘层的另一端之间的弯折部，所述弯折部与所述半导体层的一侧面以及所述漏极的一侧面相接触，且所述栅极设置在所述源极的非主体部对应的所述绝缘层上并与所述弯折部相接触。
  7. 根据权利要求1所述的半导体器件，其中所述源极为网格状。
  8. 根据权利要求1所述的半导体器件，其中所述半导体器件还包括第一接触电极和第二接触电极，所述第一接触电极设置在所述漏极的一侧，所述第二接触电极设置在所述源极的一侧。
  9. 一种半导体器件，包括：
    衬底、源极、漏极、半导体层以及栅极；
    其中，所述源极的主体部与所述漏极的主体部异面设置，所述半导体层设置在所述源极的主体部的一侧，且至少部分所述半导体层覆盖所述源极的主体部，所述栅极设置在所述源极的非主体部上。
  10. 根据权利要求9所述的半导体器件，其中所述半导体层包括主体部和延伸部，所述半导体层的主体部设置在所述源极上，所述半导体层的延伸部设置于所述衬底的表面。
  11. 根据权利要求10所述的半导体器件，其中所述漏极的一端设置在所述半导体层上，所述漏极的另一端设置于所述衬底的表面。
  12. 根据权利要求9所述的半导体器件，其中所述栅极在所述衬底上的投影位于所述漏极在所述衬底上的投影的范围外。
  13. 根据权利要求12所述的半导体器件，其中所述半导体器件还包括绝缘层，所述绝缘层的一端设置在所述源极上，所述绝缘层的另一端设置于所述漏极的所述主体部上。
  14. 根据权利要求13所述的半导体器件，其中所述绝缘层包括设置在所述绝缘层的一端和所述绝缘层的另一端之间的弯折部，所述弯折部与所述半导体层的一侧面以及所述漏极的一侧面相接触，且所述栅极设置在所述源极的非主体部对应的所述绝缘层上并与所述弯折部相接触。
  15. 根据权利要求9所述的半导体器件，其中所述源极为网格状。
  16. 根据权利要求9所述的半导体器件，其中所述半导体器件还包括第一接触电极和第二接触电极，所述第一接触电极设置在所述漏极的一侧，所述第二接触电极设置在所述源极的一侧。
  17. 一种半导体器件的制备方法，包括如下步骤：
    B100：在衬底上制备第一绝缘层；
    B101：在所述第一绝缘层上制备源极；
    B102：在所述源极的一侧制备半导体层，且至少部分所述半导体层覆盖所述源极的主体部；
    B103：在所述半导体层上制备漏极，其中，至少部分所述漏极在所述源极的主体部上的投影与所述源极的主体部重叠；
    B104：在所述源极上制备第二绝缘层，其中，所述第二绝缘层与所述半导体层的一侧面以及所述漏极的至少一部分相接触；
    B105：在所述第二绝缘层上制备栅极。
  18. 根据权利要求17所述的半导体器件的制备方法，其中所述步骤B102包括：通过蓝色激光退火工艺对所述半导体层进行处理。
  19. 根据权利要求17所述的半导体器件的制备方法，其中在制备形成所述漏极时，将所述漏极设置为网格状。
  20. 根据权利要求18所述的半导体器件的制备方法，其中所述漏极的一端设置在所述半导体层上，所述漏极的另一端设置在所述衬底的表面。
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