CN106373967A - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

Info

Publication number
CN106373967A
CN106373967A CN201610968576.6A CN201610968576A CN106373967A CN 106373967 A CN106373967 A CN 106373967A CN 201610968576 A CN201610968576 A CN 201610968576A CN 106373967 A CN106373967 A CN 106373967A
Authority
CN
China
Prior art keywords
contact structures
pixel electrode
film layer
layer
array base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610968576.6A
Other languages
English (en)
Other versions
CN106373967B (zh
Inventor
牛菁
孙双
张方振
米东灿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201610968576.6A priority Critical patent/CN106373967B/zh
Publication of CN106373967A publication Critical patent/CN106373967A/zh
Priority to US15/707,827 priority patent/US10217851B2/en
Application granted granted Critical
Publication of CN106373967B publication Critical patent/CN106373967B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441Deposition of conductive or insulating materials for electrodes
    • H01L21/443Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明属于显示技术领域,具体涉及一种阵列基板的制备方法、阵列基板和显示装置。该阵列基板的制备方法包括:在衬底上依次形成有源膜层、第一绝缘膜层、栅极膜层,通过一次构图工艺形成包括有源层、第一绝缘层和栅极的图形;形成栅绝缘层,通过一次构图工艺在所述第一绝缘层和所述栅绝缘层中分别形成第一接触孔和第二接触孔;形成像素电极膜层,在所述像素电极膜层中形成第一接触结构和第二接触结构;形成源漏膜层,通过一次构图工艺,形成包括像素电极、源极和漏极的图形,所述源极和所述漏极分别位于所述第一接触结构和所述第二接触结构的上方。该阵列基板的制备方法简化了生产过程,减少了由于对位不准引起的产品不良。

Description

阵列基板及其制备方法、显示装置
技术领域
本发明属于显示技术领域,具体涉及一种阵列基板的制备方法、阵列基板和显示装置。
背景技术
在液晶显示领域中,薄膜晶体管(Thin Film Transistor,简称TFT)的有源层一直使用稳定性能、加工性能等优异的硅系材料(包括非晶硅和多晶硅),其中非晶硅迁移率很低,而多晶硅虽然有较高的迁移率,但用其制造的薄膜晶体管均匀性较差、良率低、单价高。近年来,将透明的氧化物半导体膜用于沟道形成区来制造薄膜晶体管,并应用于电子器件及光器件的技术受到广泛关注。
现有的一种顶栅结构的氧化物薄膜晶体管的阵列基板结构中,衬底上方依次为有源层、第一绝缘层、栅极、栅绝缘层、源极和漏极、钝化层和像素电极;源极和漏极均由电阻较小的金属材料组成,直接设置在栅绝缘层上方,通过过孔与有源层连接;像素电极设置在钝化层上方,钝化层中开设过孔,像素电极通过过孔与漏极相连。而且,由于像素电极与漏极间隔钝化层设置,为保证两者的连接,需在钝化层上设置多个过孔,工艺难度大。而若采用先形成像素电极,然后在其上直接形成漏极以使两者直接连接的方式以省去钝化层过孔,则后续形成像素电极的湿刻工艺的刻蚀液会对有源层产生不良影响。
同时,现有的氧化物薄膜晶体管的阵列基板的工艺需进行六次构图工艺,分别为有源层、栅极、栅绝缘层以及第一绝缘层的过孔、数据线以及源极和漏极、钝化层和像素电极,多次掩模曝光构图加大阵列基板制备工艺的难度,而且容易出现由于对位精度不足引起的不良,产品良率下降。
发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不足,提供一种阵列基板的制备方法、阵列基板和显示装置,该阵列基板的制备方法至少部分解决氧化物薄膜晶体管的阵列基板的工艺繁多复杂,容易出现由于对位精度不足引起的不良的问题。
解决本发明技术问题所采用的技术方案是该阵列基板的制备方法,包括步骤:
在衬底上依次形成有源膜层、第一绝缘膜层、栅极膜层,通过一次构图工艺形成包括有源层、第一绝缘层和栅极的图形,所述有源层在所述衬底上的正投影面积大于所述栅极的正投影面积;
形成栅绝缘层,通过一次构图工艺在所述第一绝缘层和所述栅绝缘层中分别形成第一接触孔和第二接触孔,以裸露出所述有源层,所述第一接触孔和所述第二接触孔在所述衬底上的正投影位于所述有源层在所述衬底上的正投影内;
形成像素电极膜层,在所述像素电极膜层中形成第一接触结构和第二接触结构,所述第一接触结构和所述第二接触结构在所述衬底上的正投影至少分别包括所述第一接触孔和所述第二接触孔在所述衬底上的正投影;
形成源漏膜层,通过一次构图工艺,形成包括像素电极、源极和漏极的图形,所述源极和所述漏极分别位于所述第一接触结构和所述第二接触结构的上方。
优选的是,,所述像素电极膜层采用透明的金属氧化物形成,在所述像素电极膜层中形成第一接触结构和第二接触结构的步骤包括:
在所述像素电极膜层的上方形成光敏感绝缘膜层,通过一次构图工艺去除至少对应着所述第一接触孔和所述第二接触孔部分的所述光敏感绝缘膜层;
将至少对应着所述第一接触孔和所述第二接触孔部分的所述像素电极膜层的金属氧化物还原处理为金属,从而在所述像素电极膜层对应着所述第一接触孔的上方形成所述第一接触结构,对应着所述第二接触孔的上方形成所述第二接触结构。
优选的是,形成所述像素电极膜层的金属氧化物为氧化铟锡,采用还原气体处理工艺将氧化铟锡还原为金属铟。
优选的是,还原气体包括H2、NH3。
优选的是,所述第一绝缘层和所述栅绝缘层采用相同的材料形成。
一种阵列基板,包括依次层叠设置的有源层、第一绝缘层、栅极、栅绝缘层、像素电极、同层设置的源极和漏极,所述源极和所述漏极的区域下方分别包括与所述像素电极同层设置的第一接触结构和第二接触结构,所述源极通过所述第一接触结构与所述有源层电连接,所述漏极通过所述第二接触结构与所述有源层电连接。
优选的是,所述像素电极为透明的金属氧化物,所述第一接触结构和所述第二接触结构为金属;且所述像素电极中的金属氧化物具有与所述第一接触结构和所述第二接触结构中相同的金属成分。
优选的是,形成所述像素电极的透明的金属氧化物为氧化铟锡,形成所述第一接触结构和所述第二接触结构的金属为铟。
优选的是,所述第一绝缘层设置于所述栅极与所述有源层之间,且仅设置于对应着所述有源层的上方,所述第一绝缘层在所述衬底上的正投影面积大于所述栅极的正投影面积而小于所述有源层的正投影面积。
一种显示装置,包括上述的阵列基板。
本发明的有益效果是:该阵列基板的制备方法总共经历了四次掩模曝光工艺,相较于原有技术中的六次掩模曝光工艺,大大缩减了工艺段,降低了工艺的复杂度和难度,简化了生产过程,同时减少了由于对位不准引起的产品不良;
相应的,该阵列基板其中的有源层采用金属氧化物形成,其有源层性能佳,保证了薄膜晶体管的性能,进而保证了阵列基板的性能。
附图说明
图1为本发明实施例1中阵列基板的制备方法的流程图;
图2A-图2H为对应图1中阵列基板的工艺结构示意图;
图3为本发明实施例1中阵列基板的结构示意图;
附图标记中:
1-衬底;2-有源层;3-第一绝缘层;4-栅极;40-栅极膜层;5-栅绝缘层;5a-第一接触孔;5b-第二接触孔;6-源极;7-漏极;70-源漏金属膜层;8-像素电极;80-像素电极膜层;8a-第一接触结构;8b-第二接触结构;100-光刻胶层。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明阵列基板的制备方法、阵列基板和显示装置作进一步详细描述。
实施例1:
本实施例提供一种阵列基板的制备方法,该阵列基板的制备方法能解决现有技术中阵列基板中薄膜晶体管的漏极与像素电极的连接中,要么工艺难度大要么会对有源层造成影响的问题,极大的简化漏极与像素电极的连接,保证良好的层间接触性;同时还减少了阵列基板整体的制备步骤,降低了工艺的复杂度。
该阵列基板的制备方法,包括步骤:
步骤S1):在衬底上依次形成有源膜层、第一绝缘膜层、栅极膜层,通过一次构图工艺形成包括有源层、第一绝缘层和栅极的图形,有源层在衬底上的正投影面积大于栅极的正投影面积。
在该步骤中,首先在透明衬底1上依次沉积有源膜层、第一绝缘膜层、栅极膜层40;然后涂覆光刻胶层100,对光刻胶层100进行半曝光、显影工艺后进行栅极膜层40湿刻、第一绝缘膜层干刻、有源膜层湿刻,得到如图2A所示的阵列基板的结构,此时形成包括有源层2(由有源膜层形成)、第一绝缘层3(由第一绝缘膜层形成)的图形;随后灰化光刻胶层100,裸露出部分栅极膜层40,然后进行第二次栅极膜层40湿刻,形成包括栅极4的图形,得到如图2B所示的阵列基板的结构。图2A和图2B中,第一绝缘层3与有源层2的正投影面积相同。
在形成包括有源层2、第一绝缘层3和栅极4的图形的掩模板中,对应着形成栅极4的图形部分为光刻胶全保留区,对应着形成除栅极4部分以外的有源层2的区域为光刻胶半保留区域,其他区域为光刻胶全去除区域。在图2B中,以第一绝缘层3在衬底1上的正投影面积与有源层2的正投影面积相等作为示例。
其中,有源膜层采用铟镓锌氧化物(Indium Gallium Zinc Oxide,简称IGZO)等氧化物金属材料形成。利用以铟、镓、锌、氧为构成元素的非晶质In-Ga-Zn-O系材料(a-IGZO)的场效应型薄膜晶体管因其具有较高迁移率,较大开关比,因此能获得较好的性能。
步骤S2):形成栅绝缘层,通过一次构图工艺在第一绝缘层和栅绝缘层中分别形成第一接触孔和第二接触孔,以裸露出有源层,第一接触孔和第二接触孔位于有源层在衬底上的正投影内。
在该步骤中,在阵列基板上沉积栅绝缘层5,通过第二次掩模曝光工艺在第一绝缘层3和栅绝缘层5分别形成第一接触孔5a和第二接触孔5b。如图2C所示,位于有源层2上方的栅绝缘层5部分的正投影面积与第一绝缘层3在衬底1上的正投影面积相等。第一接触孔5a和第二接触孔5b分别位于有源层2的上方,并分别处于第一绝缘层3的两侧,栅极4完全处于位于有源层2上方的栅绝缘层5的包裹中,此时位于有源层2上方部分的栅绝缘层5对栅极4起到了良好的隔离作用。
其中,第一接触孔5a和第二接触孔5b位于有源层2在衬底1上的正投影内,即第一接触孔5a和第二接触孔5b在衬底1上的正投影与栅极4在衬底1上的正投影不重合,且第一绝缘层3在衬底1上的正投影面积大于栅极4的正投影面积而小于有源层2的正投影面积。
其中,图2C以将第一接触孔5a和第二接触孔5b形成在第一绝缘层3的两侧边缘作为示例,因此在将图2B与图2C相比时第一绝缘层3的面积有所缩小。容易理解的是,第一接触孔5a和第二接触孔5b也可以形成在第一绝缘层3的非边缘,而是在第一接触孔5a和第二接触孔5b远离栅极4的一侧还保留一部分与两侧的栅绝缘层5相接。相应的,在步骤S1)中,也可以通过掩模板图形的设计,使得第一绝缘层3在衬底1上的正投影面积介于栅极4的正投影面积与有源层2的正投影面积之间即可,这里不做限定。
优选的是,第一绝缘膜层和栅绝缘层采用相同的材料形成,便于在构图工艺中一次性形成贯穿第一绝缘层3和栅绝缘层5的第一接触孔5a和第二接触孔5b。
步骤S3):形成像素电极膜层,在像素电极膜层中形成第一接触结构和第二接触结构,第一接触结构和第二接触结构在衬底上的正投影分别对应至少分别包括第一接触孔和第二接触孔的在衬底上的正投影。
在该步骤中,像素电极膜层80对应着有源层2在衬底1上的正投影面积大于第一绝缘层3的正投影面积部分形成第一接触结构8a和第二接触结构8b,即在栅极4的两侧分别形成第一接触结构8a和第二接触结构8b,第一接触结构8a在衬底1上的正投影完全覆盖第一接触孔5a的正投影,第二接触结构8b在衬底1上的正投影完全覆盖第二接触孔8b的正投影。其中,像素电极膜层80采用透明的金属氧化物形成。
在像素电极膜层80中形成第一接触结构8a和第二接触结构8b的步骤具体包括:
在像素电极膜层80的上方形成光敏感绝缘膜层,通过一次构图工艺去除至少对应着第一接触孔5a和第二接触孔5b部分的光敏感绝缘膜层,例如这里的光敏感绝缘膜层为光刻胶层100,如图2D所示;
将至少对应着第一接触孔5a和第二接触孔5b部分的像素电极膜层80的金属氧化物还原处理为金属,从而在像素电极膜层80对应着第一接触孔5a的上方形成第一接触结构8a,对应着第二接触孔5b的上方形成第二接触结构8b,如图2E所示。从图2E中可见,第一接触结构8a和第二接触结构8b与像素电极8是同层连续设置的,只是由于还原反应而在像素电极层8中部分形成了第一接触结构8a和第二接触结构8b。
优选的是,形成像素电极膜层80的采用透明的金属氧化物,例如为氧化铟锡或者具有使其能保持透明状态的一定厚度范围内的其他金属氧化物。这些金属氧化物优选具有容易还原氧化的金属材料,例如氧化铟成分,此时即可采用还原气体处理工艺将氧化铟锡还原为金属铟;其中,还原气体包括H2、NH3。光敏感绝缘膜层可以为包括光刻胶在内的既对光敏感、又不存在导电性质的多种材料形成,本实施例中以光刻胶层100作为示例进行说明。
该步骤在完成栅绝缘层5的图形后,直接沉积透明的像素电极膜层80和光刻胶层100,通过第三次曝光、显影工艺后得到如图2D所示的光刻胶层100的结构,此时光刻胶层100在栅绝缘层5中的接触孔以及源极6和漏极7对应区域开口;接着对接触孔里覆盖的金属氧化物以及将形成源极和漏极对应区域的金属氧化物,采用还原性气体(H2、NH3等)进行还原气体处理,将这些区域的金属氧化物还原得到低电阻的金属铟,而且不需要进行刻蚀工艺,直接剥离光刻胶层100即可得到如图2E所示的具有第一接触结构8a和第二接触结构8b的阵列基板结构。
步骤S4):形成源漏膜层,通过一次构图工艺,形成包括像素电极、源极和漏极的图形,源极和漏极分别位于第一接触结构和第二接触结构的上方。
其中,在形成包括像素电极8、源极6和漏极7的图形的掩模板中,对应着形成源极6和漏极7的图形部分为光刻胶全保留区,对应着形成像素电极8的区域为光刻胶半保留区域,其他区域为光刻胶全去除区域。此时,源极6和漏极7分别对应形成在第一接触结构8a和第二接触结构8b的上方,利用第一接触结构8a和第二接触结构8b的低电阻性,使得有源层2与源极6和漏极7具有更好的接触效果,保证薄膜晶体管在导通时的沟道效果。
在该步骤中,通过溅射工艺形成源漏金属膜层70后,通过第四次曝光、显影工艺,得到如图2F所示的阵列基板结构。经过对源漏金属膜层70湿刻和对像素电极膜层80湿刻;接着灰化光刻胶层100得到如图2G所示的阵列基板结构,图2G中的阵列基板已经形成独立的源极6的图形、部分像素电极的图形和部分漏极的图形;进而,对源漏金属膜层70再进行第二次湿刻后形成包括漏极7和像素电极8的图形,如图2H所示,从而完成整个阵列基板的制备工艺。
在步骤S4)中,源极6、漏极7和像素电极8的图形通过一次掩模曝光工艺完成,像素电极8通过金属铟与漏极7直接连接,避免了现有技术中在钝化层中设置众多过孔的复杂工艺;同时,源极6和漏极7也通过低电阻金属铟与有源层2直接连接,保证良好的接触效果。这种结构既可以实现漏极7与像素电极8直接电连接,也避免了先制备像素电极8时刻蚀液对有源层2中氧化物金属材料的侵蚀,保证了有源层2性能的稳定性。
容易理解的是,在步骤S4)中形成包括像素电极8、源极6和漏极7的图形的同时,还包括使源漏膜层形成包括数据线的图形(图2H中未示出),从而保证数据线对薄膜晶体管的源极数据信号的传输效果。
上述工艺过程,在完成栅绝缘层5的图形后直接沉积像素电极膜层80,并对接触孔里覆盖的、与源极6和漏极7对应区域的像素电极膜层80的材料进行还原气体plasma处理,得到低电阻的金属铟;然后直接沉积源漏金属膜层70,通过一次构图工艺,同时得到源极6、漏极7和像素电极8的图形,极大的简化了工艺步骤。
本实施例的包含顶栅型薄膜晶体管的阵列基板的制备方法,1)采用半曝光工艺,使有源层2、第一绝缘层3以及栅极4通过一次掩模曝光工艺制备完成;2)采用半曝光工艺,使源极6、漏极7和像素电极8通过一次掩模曝光工艺制备完成,减少了两次掩模曝光工艺。像素电极8在对应着位于源极6和漏极7下方的部分,经过还原处理转变为低电阻的金属铟,保证了源极6、漏极7与有源层2之间良好的欧姆接触。
本实施例中的阵列基板的制备方法总共经历了四次掩模曝光工艺,相较于原有技术中的六次掩模曝光工艺,大大缩减了工艺段,降低了工艺的复杂度和难度,简化了生产过程,同时减少了由于对位不准引起的产品不良。
相应的,本实施例还提供一种阵列基板,该阵列基板结构简单,层间接触性能好。
图3为本实施例中阵列基板的局部剖面图。如图3所示,该阵列基板包括在透明的衬底1上方依次层叠设置的有源层2、第一绝缘层3、栅极4、栅绝缘层5、像素电极8、同层设置的源极6和漏极7,源极6和漏极7的区域下方分别包括与像素电极8同层设置第一接触结构8a和第二接触结构8b(像素电极8、第一接触结构8a和第二接触结构8b一体形成),即第一接触结构8a和第二接触结构8b与像素电极8同层连续设置,源极6通过第一接触结构8a与有源层2电连接,漏极7通过第二接触结构8b与有源层2电连接。该阵列基板结构简单,并且降低了工艺的复杂度,减少了由于接触孔造成层间对位不准引起的产品不良。
优选的是,像素电极8为透明的金属氧化物,第一接触结构8a和第二接触结构8b为金属;且像素电极8中的金属氧化物具有与第一接触结构8a和第二接触结构8b中相同的金属成分。进一步优选的是,形成像素电极8的透明的金属氧化物为氧化铟锡,形成第一接触结构8a和第二接触结构8b的金属为铟。当然,形成像素电极8的透明的金属氧化物也可以为具有使其能保持透明状态的一定厚度范围内的其他金属氧化物。这些金属氧化物优选具有容易还原氧化的金属材料,例如氧化铟成分,此时即可采用还原气体处理工艺将氧化铟锡还原为金属铟。
优选的是,第一绝缘层3设置于栅极4与有源层2之间,且仅设置于对应着有源层2的上方,第一绝缘层3在衬底1上的正投影面积大于栅极4的正投影面积而小于有源层2的正投影面积,使得第一绝缘层3部分覆盖于有源层2的上方,以便于有源层2与位于第一绝缘层3上方的源极6和漏极7的接触。与现有技术阵列基板中的薄膜晶体管相比,第一绝缘层3并未覆盖衬底1的全部区域,仅仅设置在对应着有源层2区域的上方,同时源极6和漏极7下方全部有金属铟存在,且源极6和漏极7通过金属铟分别与有源层2和像素电极8连接,保证有源层2与源极6、漏极7的接触效果。
本实施例中的包含顶栅型薄膜晶体管的阵列基板,其中的有源层采用金属氧化物形成,其有源层性能佳,保证了薄膜晶体管的性能,进而保证了阵列基板的性能。
实施例2:
本实施例提供一种显示装置,该显示装置包括实施例1中的阵列基板及其相应的制备方法形成。
该显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
该显示装置具有较佳的显示性能。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种阵列基板的制备方法,其特征在于,包括步骤:
在衬底上依次形成有源膜层、第一绝缘膜层、栅极膜层,通过一次构图工艺形成包括有源层、第一绝缘层和栅极的图形,所述有源层在所述衬底上的正投影面积大于所述栅极的正投影面积;
形成栅绝缘层,通过一次构图工艺在所述第一绝缘层和所述栅绝缘层中分别形成第一接触孔和第二接触孔,以裸露出所述有源层,所述第一接触孔和所述第二接触孔在所述衬底上的正投影位于所述有源层在所述衬底上的正投影内;
形成像素电极膜层,在所述像素电极膜层中形成第一接触结构和第二接触结构,所述第一接触结构和所述第二接触结构在所述衬底上的正投影至少分别包括所述第一接触孔和所述第二接触孔在所述衬底上的正投影;
形成源漏膜层,通过一次构图工艺,形成包括像素电极、源极和漏极的图形,所述源极和所述漏极分别位于所述第一接触结构和所述第二接触结构的上方。
2.根据权利要求1所述的阵列基板的制备方法,其特征在于,所述像素电极膜层采用透明的金属氧化物形成,在所述像素电极膜层中形成第一接触结构和第二接触结构的步骤包括:
在所述像素电极膜层的上方形成光敏感绝缘膜层,通过一次构图工艺去除至少对应着所述第一接触孔和所述第二接触孔部分的所述光敏感绝缘膜层;
将至少对应着所述第一接触孔和所述第二接触孔部分的所述像素电极膜层的金属氧化物还原处理为金属,从而在所述像素电极膜层对应着所述第一接触孔的上方形成所述第一接触结构,对应着所述第二接触孔的上方形成所述第二接触结构。
3.根据权利要求2所述的阵列基板的制备方法,其特征在于,形成所述像素电极膜层的金属氧化物为氧化铟锡,采用还原气体处理工艺将氧化铟锡还原为金属铟。
4.根据权利要求3所述的阵列基板的制备方法,其特征在于,还原气体包括H2、NH3
5.根据权利要求1-4任一项所述的阵列基板的制备方法,其特征在于,所述第一绝缘层和所述栅绝缘层采用相同的材料形成。
6.一种阵列基板,其特征在于,包括依次层叠设置的有源层、第一绝缘层、栅极、栅绝缘层、像素电极、同层设置的源极和漏极,所述源极和所述漏极的区域下方分别包括与所述像素电极同层设置的第一接触结构和第二接触结构,所述源极通过所述第一接触结构与所述有源层电连接,所述漏极通过所述第二接触结构与所述有源层电连接。
7.根据权利要求6所述的阵列基板,其特征在于,所述像素电极为透明的金属氧化物,所述第一接触结构和所述第二接触结构为金属;且所述像素电极中的金属氧化物具有与所述第一接触结构和所述第二接触结构中相同的金属成分。
8.根据权利要求7所述的阵列基板,其特征在于,形成所述像素电极的金属氧化物为氧化铟锡,形成所述第一接触结构和所述第二接触结构的金属为铟。
9.根据权利要求6-8任一项所述的阵列基板,其特征在于,所述第一绝缘层设置于所述栅极与所述有源层之间,且仅设置于对应着所述有源层的上方,所述第一绝缘层在所述衬底上的正投影面积大于所述栅极的正投影面积而小于所述有源层的正投影面积。
10.一种显示装置,其特征在于,包括权利要求6-9任一项所述的阵列基板。
CN201610968576.6A 2016-10-27 2016-10-27 阵列基板及其制备方法、显示装置 Active CN106373967B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201610968576.6A CN106373967B (zh) 2016-10-27 2016-10-27 阵列基板及其制备方法、显示装置
US15/707,827 US10217851B2 (en) 2016-10-27 2017-09-18 Array substrate and method of manufacturing the same, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610968576.6A CN106373967B (zh) 2016-10-27 2016-10-27 阵列基板及其制备方法、显示装置

Publications (2)

Publication Number Publication Date
CN106373967A true CN106373967A (zh) 2017-02-01
CN106373967B CN106373967B (zh) 2017-12-22

Family

ID=57892851

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610968576.6A Active CN106373967B (zh) 2016-10-27 2016-10-27 阵列基板及其制备方法、显示装置

Country Status (2)

Country Link
US (1) US10217851B2 (zh)
CN (1) CN106373967B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911458A (zh) * 2019-11-13 2020-03-24 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN113838758A (zh) * 2021-11-30 2021-12-24 晶芯成(北京)科技有限公司 一种半导体器件及其制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107464776B (zh) * 2017-08-30 2020-05-26 京东方科技集团股份有限公司 一种显示面板、其制作方法及显示装置
CN107910300B (zh) * 2017-11-20 2020-04-21 合肥京东方光电科技有限公司 一种阵列基板的制作方法、阵列基板及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579227A (zh) * 2012-08-10 2014-02-12 三星显示有限公司 薄膜晶体管基板及其制造方法
CN103715094A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN106024706A (zh) * 2016-06-22 2016-10-12 深圳市华星光电技术有限公司 阵列基板及其制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101151799B1 (ko) * 2005-11-09 2012-06-01 엘지디스플레이 주식회사 액정표시장치용 어레이기판과 그 제조방법
KR100964227B1 (ko) * 2008-05-06 2010-06-17 삼성모바일디스플레이주식회사 평판 표시 장치용 박막 트랜지스터 어레이 기판, 이를포함하는 유기 발광 표시 장치, 및 이들의 제조 방법
CN102543860B (zh) * 2010-12-29 2014-12-03 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制造方法
KR101876819B1 (ko) * 2011-02-01 2018-08-10 삼성디스플레이 주식회사 박막트랜지스터 기판 및 그의 제조방법
KR20130007902A (ko) * 2011-07-11 2013-01-21 삼성디스플레이 주식회사 유기발광표시장치 및 이의 제조방법
CN102800630A (zh) * 2012-07-26 2012-11-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
WO2014046068A1 (ja) * 2012-09-24 2014-03-27 シャープ株式会社 アクティブマトリックス基板、表示装置、及び、その製造方法
CN103646966B (zh) * 2013-12-02 2016-08-31 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制备方法、显示装置
US9929279B2 (en) * 2014-02-05 2018-03-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579227A (zh) * 2012-08-10 2014-02-12 三星显示有限公司 薄膜晶体管基板及其制造方法
CN103715094A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN106024706A (zh) * 2016-06-22 2016-10-12 深圳市华星光电技术有限公司 阵列基板及其制作方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911458A (zh) * 2019-11-13 2020-03-24 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN113838758A (zh) * 2021-11-30 2021-12-24 晶芯成(北京)科技有限公司 一种半导体器件及其制造方法
CN113838758B (zh) * 2021-11-30 2022-02-11 晶芯成(北京)科技有限公司 一种半导体器件及其制造方法

Also Published As

Publication number Publication date
US10217851B2 (en) 2019-02-26
US20180122924A1 (en) 2018-05-03
CN106373967B (zh) 2017-12-22

Similar Documents

Publication Publication Date Title
CN106935659B (zh) 薄膜晶体管及其制造方法、阵列基板以及显示装置
CN102842587B (zh) 阵列基板及其制作方法、显示装置
CN106531692A (zh) 阵列基板的制备方法、阵列基板及显示装置
CN107994066B (zh) Tft、制作方法、阵列基板、显示面板及装置
CN103247531B (zh) 薄膜晶体管及其制作方法及显示器
CN105428243B (zh) 一种薄膜晶体管及制作方法、阵列基板和显示装置
WO2017173712A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN103500730B (zh) 一种阵列基板及其制作方法、显示装置
CN106783737A (zh) 阵列基板及其制造方法、显示面板、显示装置
CN106373967B (zh) 阵列基板及其制备方法、显示装置
WO2016206206A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
CN106847830A (zh) 阵列基板及其制作方法、显示面板
WO2014117443A1 (zh) 氧化物薄膜晶体管阵列基板及其制作方法、显示面板
WO2015067068A1 (zh) 低温多晶硅薄膜晶体管阵列基板及其制作方法、显示装置
WO2022267554A1 (zh) 薄膜晶体管的制备方法及薄膜晶体管
CN105977205B (zh) 薄膜晶体管、阵列基板的制备方法、阵列基板及显示装置
CN110148601A (zh) 一种阵列基板、其制作方法及显示装置
CN105870169A (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN109686794A (zh) 薄膜晶体管及其制造方法、显示装置
CN106449653B (zh) 一种显示基板及其制备方法、显示面板、显示装置
CN110190028A (zh) 薄膜晶体管阵列基板制备方法
CN105489618B (zh) 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
CN105514173A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN109712993A (zh) 阵列基板及制造方法及显示装置
CN106449521B (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant