WO2019200834A1 - Tft阵列基板的制作方法及tft阵列基板 - Google Patents

Tft阵列基板的制作方法及tft阵列基板 Download PDF

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WO2019200834A1
WO2019200834A1 PCT/CN2018/106327 CN2018106327W WO2019200834A1 WO 2019200834 A1 WO2019200834 A1 WO 2019200834A1 CN 2018106327 W CN2018106327 W CN 2018106327W WO 2019200834 A1 WO2019200834 A1 WO 2019200834A1
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layer
material layer
electrode
photoresist pattern
amorphous silicon
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PCT/CN2018/106327
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English (en)
French (fr)
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刘广辉
何鹏
许勇
艾飞
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武汉华星光电技术有限公司
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Priority to US16/097,279 priority Critical patent/US10971530B2/en
Publication of WO2019200834A1 publication Critical patent/WO2019200834A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT array substrate and a TFT array substrate.
  • a flat panel display device such as a liquid crystal display (LCD) has gradually replaced a cathode ray tube (CRT) display device.
  • the liquid crystal display device has many advantages such as thin body, power saving, no radiation, and the like, and has been widely used.
  • the liquid crystal display panel comprises a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • an amorphous silicon (a-Si) material or a low temperature poly-silicon (LTPS) material is often used as the material of the active layer of the TFT device.
  • a TFT array substrate made of a low-temperature polysilicon material a TFT array substrate made of an amorphous silicon material has low resolution and high power consumption, but at the same time has a short manufacturing cycle, and thus a TFT made of an amorphous silicon material.
  • the TFT array substrate fabricated by the array substrate and the low-temperature polysilicon material has a certain market share in the existing market.
  • a gate electrode is generally formed on a substrate, and a gate insulating layer and an amorphous silicon layer are formed over the gate electrode, and then respectively disposed at both ends of the amorphous silicon layer.
  • the source and drain of the connected metal, the TFT array substrate of the structure is directly in contact with the amorphous silicon layer due to the source and the drain, and the contact resistance between the amorphous silicon layer and the source and drain is large, affecting The quality of the product.
  • An object of the present invention is to provide a method for fabricating a TFT array substrate, which can reduce contact resistance between a source/drain and an active layer, and improve product quality.
  • Another object of the present invention is to provide a TFT array substrate capable of reducing contact resistance between a source/drain and an active layer, and having high product quality.
  • the present invention first provides a method for fabricating a TFT array substrate, comprising the following steps:
  • Step S1 providing a substrate, forming a gate and a gate insulating layer covering the gate on the substrate;
  • Step S2 forming an active layer on the gate insulating layer
  • Step S3 sequentially depositing an electrode material layer and a metal material layer on the gate insulating layer and the active layer; forming a photoresist pattern on the metal material layer, the photoresist pattern including the spaced first and second light blocks a blocking block, the projection of the portion of the first photoresist block in the vertical direction overlaps with one end of the active layer, and the projection of the portion of the second photoresist block in the vertical direction overlaps with the other end of the active layer;
  • the thickness of the photoresist block is greater than the thickness of the second photoresist block;
  • Step S4 etching the metal material layer and the electrode material layer by blocking the photoresist pattern, removing the portion of the metal material layer and the electrode material layer that is not blocked by the photoresist pattern, and graying the photoresist pattern to the second photoresist
  • the block is removed, and the metal material layer is etched by ashing the photoresist pattern to remove the portion of the metal material layer that is not blocked by the ashing photoresist pattern, and the contact electrodes respectively connected to the two ends of the active layer are formed.
  • a pixel electrode and a source/drain on the contact electrode are formed by blocking the photoresist pattern, removing the portion of the metal material layer and the electrode material layer that is not blocked by the photoresist pattern, and graying the photoresist pattern to the second photoresist The block is removed, and the metal material layer is etched by ashing the photoresist pattern to remove the portion of the metal material layer that is not blocked by the ashing photoresist pattern, and the contact
  • the step S4 further includes the step of removing the ashed photoresist pattern.
  • the method for fabricating the TFT array substrate further includes: step S5, depositing a passivation layer on the gate insulating layer, the active layer, the pixel electrode, and the source/drain; forming a common electrode on the passivation layer.
  • a specific process of forming a gate on the substrate is: depositing a gate metal layer on the substrate, and performing an exposure and development process on the gate metal layer to form a gate;
  • the step S2 includes:
  • Step S21 depositing an amorphous silicon material on the gate insulating layer, and performing an exposure and development process on the amorphous silicon material to form an amorphous silicon island;
  • Step S22 performing ion doping on the amorphous silicon island to form an active layer;
  • the active layer includes an amorphous silicon material layer and a doped amorphous silicon layer on the amorphous silicon material layer;
  • a specific process of forming a photoresist pattern on the metal material layer is: forming a photoresist material layer on the metal material layer, and patterning the photoresist material layer by using a halftone mask to obtain a photoresist pattern.
  • the metal material layer and the electrode material layer are etched by using the photoresist pattern as a occlusion, and when the metal material layer and the electrode material layer are not blocked by the photoresist pattern, the amorphous silicon layer is also doped.
  • the portion not blocked by the photoresist pattern is removed to form a first contact layer and a second contact layer respectively located on both ends of the amorphous silicon material layer, the contact electrode being connected to the first contact layer, the pixel electrode and the second electrode Contact layer connection.
  • the metal material layer is dry etched by blocking the photoresist pattern to remove the portion of the metal material layer that is not blocked by the photoresist pattern, and the photoresist pattern is used as the shielding electrode material layer and the doped amorphous silicon.
  • the layer is subjected to wet etching to remove the electrode material layer and the portion of the doped amorphous silicon layer that is not blocked by the photoresist pattern;
  • the metal material layer is dry etched by using the ashed photoresist pattern as a occlusion, and the portion of the metal material layer that is not ashed by the photoresist pattern is removed.
  • the material of the gate is Mo
  • the material of the gate insulating layer is SiNx;
  • the material of the electrode material layer is indium tin oxide.
  • the amorphous silicon island is doped with N-type ions.
  • the amorphous silicon island is doped with N-type ions by using phosphorus ions.
  • the present invention also provides a TFT array substrate comprising a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the substrate and the gate, and a gate insulating layer disposed above the gate electrode An active layer, a contact electrode and a pixel electrode respectively connected to both ends of the active layer, and a source/drain located on the contact electrode.
  • a method for fabricating a TFT array substrate provided by the present invention after forming an active layer above a gate electrode, sequentially depositing an electrode material layer and a metal material layer on a gate insulating layer and an active layer, And forming a photoresist pattern on the metal material layer, the photoresist pattern comprises first and second photoresist blocks having different thicknesses, and the metal material layer and the electrode material layer are etched by the photoresist pattern to form respectively and the active layer
  • the contact electrode and the pixel electrode connected at the end and the source/drain on the contact electrode have a simple manufacturing process, can effectively reduce the contact resistance between the source/drain and the active layer, and improve the quality of the product.
  • the TFT array substrate provided by the invention can reduce the contact resistance between the source/drain and the active layer, and has high product quality.
  • FIG. 1 is a flow chart showing a method of fabricating a TFT array substrate of the present invention
  • FIG. 2 is a schematic view showing a step S1 of a method of fabricating a TFT array substrate of the present invention
  • FIG. 3 and FIG. 4 are schematic diagrams showing the step S2 of the method for fabricating the TFT array substrate of the present invention.
  • FIG. 5 is a schematic diagram of step S3 of the method for fabricating the TFT array substrate of the present invention.
  • FIG. 6 to FIG. 8 are schematic diagrams showing a step S4 of the method for fabricating the TFT array substrate of the present invention.
  • FIG. 9 is a schematic view showing a step S5 of the method for fabricating the TFT array substrate of the present invention and a schematic structural view of the TFT array substrate of the present invention.
  • the present invention provides a method for fabricating a TFT array substrate, including the following steps:
  • Step S1 Referring to FIG. 2, a substrate 10 is provided on which a gate electrode 20 and a gate insulating layer 30 covering the gate electrode 20 are formed.
  • a specific process of forming the gate electrode 20 on the substrate 10 is: depositing a gate metal layer on the substrate 10, and performing an exposure and development process on the gate metal layer to form a gate. Extreme 20.
  • the material of the gate electrode 20 may be molybdenum (Mo).
  • the material of the gate insulating layer 30 may be silicon nitride (SiNx).
  • Step S2 referring to FIG. 4, an active layer 40 is formed over the gate insulating layer 30.
  • the step S2 includes:
  • Step S21 referring to FIG. 3, an amorphous silicon material is deposited on the gate insulating layer 30, and the amorphous silicon material is subjected to an exposure and development process to form an amorphous silicon island 49.
  • the amorphous silicon island 49 is ion doped to form the active layer 40.
  • the active layer 40 includes an amorphous silicon material layer 41 and a doped amorphous silicon layer 42 on the amorphous silicon material layer 41.
  • the amorphous silicon island 49 is doped with N-type ions.
  • the amorphous silicon island 49 is doped with N-type ions by using phosphorus ions.
  • Step S3 referring to FIG. 5, the electrode material layer 50 and the metal material layer 60 are sequentially deposited on the gate insulating layer 30 and the active layer 40.
  • a photoresist pattern 70 is formed on the metal material layer 60, and the photoresist pattern 70 includes spaced first and second light blocking blocks 71 and 72, and a portion of the first light blocking block 71 is projected in a vertical direction.
  • One end of the active layer 40 is overlapped, and a projection of a portion of the second photoresist block 72 in the vertical direction overlaps with the other end of the active layer 40.
  • the thickness of the first photoresist block 71 is greater than the thickness of the second photoresist block 72.
  • the material of the electrode material layer 50 is preferably indium tin oxide (ITO).
  • a specific process of forming the photoresist pattern 70 on the metal material layer 60 is: forming a photoresist material layer on the metal material layer 60, and patterning the photoresist material layer by using a halftone mask (HTM). A photoresist pattern 70 is obtained.
  • HTM halftone mask
  • Step S4 referring to FIG. 6, the metal material layer 60 and the electrode material layer 50 are etched by using the photoresist pattern 70 as a mask to remove the portion of the metal material layer 60 and the electrode material layer 50 that is not blocked by the photoresist pattern 70.
  • ashing the photoresist pattern 70 removes the second photoresist block 72 while thinning the thickness of the first photoresist block 71.
  • the etched photoresist pattern 70 is used as an occlusion to etch the metal material layer 60 , and the portion of the metal material layer 60 that is not ashed by the photoresist pattern 70 is removed to form an active layer.
  • the contact electrode 51 and the pixel electrode 52 connected to each other at 40 and the source/drain 61 located on the contact electrode 51.
  • step S4 the metal material layer 60 and the electrode material layer 50 are etched by using the photoresist pattern 70 as a mask, and the metal material layer 60 and the electrode material layer 50 are not blocked by the photoresist pattern.
  • the portion of the occlusion is 70
  • the portion of the doped amorphous silicon layer 42 that is not blocked by the photoresist pattern 70 is removed, and the first contact layer 421 and the second contact layer 422 are respectively formed on both ends of the amorphous silicon material layer 41.
  • the contact electrode 51 is connected to the first contact layer 421
  • the pixel electrode 52 is connected to the second contact layer 422 .
  • the metal material layer 60 is dry etched by using the photoresist pattern 70 as a occlusion, and the portion of the metal material layer 60 that is not blocked by the photoresist pattern 70 is removed, and then the photoresist pattern 70 is used as an occlusion pair.
  • the electrode material layer 50 and the doped amorphous silicon layer 42 are wet-etched to remove portions of the electrode material layer 50 and the doped amorphous silicon layer 42 that are not blocked by the photoresist pattern 70.
  • the metal material layer 60 is dry etched by using the ashed photoresist pattern 70 as an occlusion, and the portion of the metal material layer 60 that is not blocked by the ash-formed photoresist pattern 70 is removed.
  • the step S4 further includes the step of removing the grayed photoresist pattern 70.
  • Step S5 referring to FIG. 9, a passivation layer 80 is deposited on the gate insulating layer 30, the active layer 40, the pixel electrode 52, and the source/drain electrodes 61.
  • a common electrode 90 is formed on the passivation layer 80.
  • the material of the common electrode 90 is preferably indium tin oxide.
  • the method for fabricating the TFT array substrate of the present invention sequentially deposits the electrode material layer 50 and the metal material layer on the gate insulating layer 30 and the active layer 40 after forming the active layer 40 over the gate electrode 20. 60, and a photoresist pattern 70 is formed on the metal material layer 60.
  • the photoresist pattern 70 includes first and second photoresist blocks 71 and 72 having different thicknesses, and the metal material layer 60 and the electrode material layer 50 are formed by the photoresist pattern 70.
  • Etching is performed to form the connection electrode 51 and the pixel electrode 52 respectively connected to both ends of the active layer 40, and the source/drain electrodes 61 are formed on the connection electrode 51, compared with the amorphous silicon layer directly and the source in the prior art.
  • the level and drain connections enable the present invention to effectively reduce the contact resistance between the source/drain and the active layer, thereby effectively improving the quality of the product.
  • the present invention forms the active layer 40 by forming an amorphous silicon island 49 on the gate insulating layer 30 and ion doping the amorphous silicon island 49, so that the active layer 40 has amorphous silicon disposed in order.
  • the portion is etched to form a first contact layer 421 and a second contact layer 422 respectively located on opposite ends of the amorphous silicon material layer 41.
  • the contact electrode 51 is connected to the first contact layer 421, and the pixel electrode 52 is
  • the second contact layer 422 is connected to further reduce the contact resistance between the source/drain and the active layer, and the present invention can complete the first process without modifying the active layer film forming apparatus compared to the prior art.
  • the fabrication of the contact layer 421 and the second contact layer 422 is simple in process and low in equipment cost.
  • the fabrication method of the TFT array substrate of the present invention can be realized by using the existing production line of the TFT array substrate using the LTPS material.
  • the present invention further provides a TFT array substrate obtained by the above method for fabricating a TFT array substrate, the TFT array substrate comprising a substrate 10 and a gate electrode 20 disposed on the substrate 10 .
  • a gate insulating layer 30 disposed on the substrate 10 and the gate 20, an active layer 40 disposed on the gate insulating layer 30 and above the gate electrode 20, and contact electrodes respectively connected to both ends of the active layer 40 51 and the pixel electrode 52 and the source/drain 61 on the contact electrode 51.
  • the TFT array substrate further includes a passivation layer 80 disposed on the gate insulating layer 30 , the pixel electrode 52 , the active layer 40 , and the source/drain electrodes 61 , and is disposed on the passivation layer 80 .
  • the common electrode 90 disposed on the gate insulating layer 30 , the pixel electrode 52 , the active layer 40 , and the source/drain electrodes 61 , and is disposed on the passivation layer 80 .
  • the common electrode 90 is disposed on the gate insulating layer 30 , the pixel electrode 52 , the active layer 40 , and the source/drain electrodes 61 .
  • the active layer 40 includes an amorphous silicon material layer 41 and a doped amorphous silicon layer 42 on the amorphous silicon material layer 41.
  • the doped amorphous silicon layer 42 includes respectively The first contact layer 421 and the second contact layer 422 are located on both ends of the amorphous silicon material layer 41.
  • the contact electrode 51 is connected to the first contact layer 421, and the pixel electrode 52 is connected to the second contact layer 422.
  • the material of the gate electrode 20 may be molybdenum.
  • the material of the gate insulating layer 30 may be silicon nitride.
  • the material of the contact electrode 51, the pixel electrode 52, and the common electrode 90 is preferably indium tin oxide.
  • the TFT array substrate of the present invention is provided with the contact electrode 51 and the pixel electrode 52 respectively connected to both ends of the active layer 40, and the source/drain 61 disposed on the contact electrode 51 is provided, compared with the prior art.
  • the medium amorphous silicon layer is directly connected to the source and the drain, and the invention can effectively reduce the contact resistance between the source/drain and the active layer, thereby effectively improving the quality of the product.
  • the active layer 40 of the present invention includes an amorphous silicon material layer 41 and a doped amorphous silicon layer 42.
  • the doped amorphous silicon layer 42 includes first contact layers respectively located on opposite ends of the amorphous silicon material layer 41. 421 and a second contact layer 422, the contact electrode 51 is connected to the first contact layer 421, and the pixel electrode 52 is connected to the second contact layer 422, thereby further reducing contact between the source/drain and the active layer. resistance.
  • the TFT array substrate of the present invention is formed by sequentially depositing an electrode material layer and a metal material layer on the gate insulating layer and the active layer after forming an active layer above the gate electrode, and in the metal material.
  • a photoresist pattern is formed on the layer, the photoresist pattern includes first and second photoresist blocks having different thicknesses, and the metal material layer and the electrode material layer are etched by the photoresist pattern to form contacts respectively connected to the two ends of the active layer.
  • the electrode and the pixel electrode and the source/drain on the contact electrode have a simple process, and can effectively reduce the contact resistance between the source/drain and the active layer, thereby improving the quality of the product.
  • the TFT array substrate of the present invention can reduce the contact resistance between the source/drain and the active layer, and has high product quality.

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Abstract

本发明提供一种TFT阵列基板的制作方法及TFT阵列基板。该TFT阵列基板的制作方法在形成位于栅极上方的有源层后，在栅极绝缘层与有源层上依次沉积电极材料层与金属材料层，并在金属材料层上制作光阻图案，光阻图案包括厚度不同的第一、第二光阻块，利用光阻图案对金属材料层、电极材料层进行刻蚀，形成分别与有源层两端连接的接触电极及像素电极以及位于接触电极上的源/漏极，制程简单，能够有效降低源/漏极与有源层间的接触电阻，提升产品的品质。

Description

TFT阵列基板的制作方法及TFT阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板的制作方法及TFT阵列基板。
背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(Color Filter，CF)基板、薄膜晶体管(Thin Film Transistor，TFT)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal，LC)及密封胶框(Sealant)组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
现有的液晶显示装置的TFT阵列基板中，TFT器件的有源层的材料常使用非晶硅(a-Si)材料或低温多晶硅(Low Temperature Poly-silicon，LTPS)材料。相较于采用低温多晶硅材料制作的TFT阵列基板，采用非晶硅材料制作的TFT阵列基板的分辨率低、功耗高，但其同时具有制作周期短的特点，因此非晶硅材料制作的TFT阵列基板及低温多晶硅材料制作的TFT阵列基板在现有的市场中均具有一定的市场占有率。
在采用非晶硅材料制作的TFT阵列基板中，一般是在衬底基板上制作栅极，并在栅极上方制作栅极绝缘层及非晶硅层，而后设置分别与非晶硅层两端连接的金属的源级及漏极，该种结构的TFT阵列基板由于源级与漏极直接与非晶硅层接触，非晶硅层与源级及漏极之间的接触电阻较大，影响了产品的品质。
发明内容
本发明的目的在于提供一种TFT阵列基板的制作方法，能够降低源/漏极与有源层之间的接触电阻，提升产品的品质。
本发明的另一目的在于提供一种TFT阵列基板，能够降低源/漏极与有源层之间的接触电阻，产品品质高。
为实现上述目的，本发明首先提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、提供衬底，在所述衬底上形成栅极及覆盖栅极的栅极绝缘层；
步骤S2、形成位于栅极绝缘层之上的有源层；
步骤S3、在栅极绝缘层与有源层上依次沉积电极材料层及金属材料层；在金属材料层上形成光阻图案，所述光阻图案包括间隔的第一光阻块与第二光阻块，第一光阻块的部分在竖直方向的投影与有源层的一端重叠，第二光阻块的部分在竖直方向的投影与有源层的另一端重叠；所述第一光阻块的厚度大于第二光阻块的厚度；
步骤S4、以光阻图案为遮挡对金属材料层、电极材料层进行刻蚀，去除金属材料层、电极材料层未被光阻图案遮挡的部分，对光阻图案进行灰化将第二光阻块去除，以灰化后的光阻图案为遮挡对金属材料层进行刻蚀，去除金属材料层未被灰化后的光阻图案遮挡的部分，形成分别与有源层两端连接的接触电极及像素电极以及位于接触电极上的源/漏极。
所述步骤S4还包括将灰化后的光阻图案进行去除的步骤。
所述TFT阵列基板的制作方法还包括：步骤S5、在栅极绝缘层、有源层、像素电极及源/漏极上沉积钝化层；在钝化层上形成公共电极。
所述步骤S1中，在所述衬底上形成栅极的具体过程为：在衬底上沉积栅极金属层，对所述栅极金属层进行曝光显影制程，形成栅极；
所述步骤S2包括：
步骤S21、在栅极绝缘层上沉积非晶硅材料，对所述非晶硅材料进行曝光显影制程，形成非晶硅岛；
步骤S22、对所述非晶硅岛进行离子掺杂，形成有源层；所述有源层包括非晶硅材料层及位于非晶硅材料层上的掺杂非晶硅层；
所述步骤S3中，在金属材料层上形成光阻图案的具体过程为：在金属材料层上形成光阻材料层，利用一半色调光罩对光阻材料层进行图案化，得到光阻图案。
所述步骤S4中，以光阻图案为遮挡对金属材料层、电极材料层进行刻蚀，去除金属材料层、电极材料层未被光阻图案遮挡的部分时，还将掺杂非晶硅层未被光阻图案遮挡的部分去除，形成分别位于非晶硅材料层两端上的第一接触层及第二接触层，所述接触电极与第一接触层连接，所述像素电极与第二接触层连接。
所述步骤S4中，以光阻图案为遮挡对金属材料层进行干刻蚀，去除金属材料层未被光阻图案遮挡的部分，以光阻图案为遮挡对电极材料层及掺杂非晶硅层进行湿刻蚀，去除电极材料层及掺杂非晶硅层未被光阻图案遮挡的部分；
所述步骤S4中，以灰化后的光阻图案为遮挡对金属材料层进行干刻蚀，去除金属材料层未被灰化后的光阻图案遮挡的部分。
所述栅极的材料为Mo；
所述栅极绝缘层的材料为SiNx；
所述电极材料层的材料为氧化铟锡。
所述步骤S22中，对所述非晶硅岛进行N型离子掺杂。
所述步骤S22中，利用磷离子对所述非晶硅岛进行N型离子掺杂。
本发明还提供一种TFT阵列基板，包括衬底、设于衬底上的栅极、设于衬底及栅极上的栅极绝缘层、设于栅极绝缘层上且位于栅极上方的有源层、分别与有源层两端连接的接触电极及像素电极以及位于接触电极上的源/漏极。
本发明的有益效果：本发明提供的一种TFT阵列基板的制作方法在形成位于栅极上方的有源层后，在栅极绝缘层与有源层上依次沉积电极材料层与金属材料层，并在金属材料层上制作光阻图案，光阻图案包括厚度不同的第一、第二光阻块，利用光阻图案对金属材料层、电极材料层进行刻蚀，形成分别与有源层两端连接的接触电极及像素电极以及位于接触电极上的源/漏极，制程简单，能够有效降低源/漏极与有源层间的接触电阻，提升产品的品质。本发明提供的一种TFT阵列基板能够降低源/漏极与有源层之间的接触电阻，产品品质高。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的TFT阵列基板的制作方法的流程图；
图2为本发明的TFT阵列基板的制作方法的步骤S1的示意图；
图3及图4为本发明的TFT阵列基板的制作方法的步骤S2的示意图；
图5为本发明的TFT阵列基板的制作方法的步骤S3的示意图；
图6至图8为本发明的TFT阵列基板的制作方法的步骤S4的示意图；
图9为本发明的TFT阵列基板的制作方法的步骤S5的示意图暨本发明的TFT阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、请参阅图2，提供衬底10，在所述衬底10上形成栅极20及覆盖栅极20的栅极绝缘层30。
具体地，所述步骤S1中，在所述衬底10上形成栅极20的具体过程为：在衬底10上沉积栅极金属层，对所述栅极金属层进行曝光显影制程，形成栅极20。
具体地，所述栅极20的材料可以为钼(Mo)。
具体地，所述栅极绝缘层30的材料可以为氮化硅(SiNx)。
步骤S2、请参阅图4，形成位于栅极绝缘层30之上的有源层40。
具体地，所述步骤S2包括：
步骤S21，请参阅图3，在栅极绝缘层30上沉积非晶硅材料，对所述非晶硅材料进行曝光显影制程，形成非晶硅岛49。
步骤S22，请参阅图4，对所述非晶硅岛49进行离子掺杂，形成有源层40。所述有源层40包括非晶硅材料层41及位于非晶硅材料层41上的掺杂非晶硅层42。
具体地，所述步骤S22中，对所述非晶硅岛49进行N型离子掺杂。
优选地，所述步骤S22中，利用磷离子对所述非晶硅岛49进行N型离子掺杂。
步骤S3、请参阅图5，在栅极绝缘层30与有源层40上依次沉积电极材料层50及金属材料层60。在金属材料层60上形成光阻图案70，所述光阻图案70包括间隔的第一光阻块71与第二光阻块72，第一光阻块71的部分在竖直方向的投影与有源层40的一端重叠，第二光阻块72的部分在竖直方向的投影与有源层40的另一端重叠。所述第一光阻块71的厚度大于第二光阻块72的厚度。
具体地，所述电极材料层50材料优选为氧化铟锡(ITO)。
所述步骤S3中，在金属材料层60上形成光阻图案70的具体过程为：在金属材料层60上形成光阻材料层，利用一半色调光罩(HTM)对光阻材 料层进行图案化，得到光阻图案70。
步骤S4、请参阅图6，以光阻图案70为遮挡对金属材料层60、电极材料层50进行刻蚀，去除金属材料层60、电极材料层50未被光阻图案70遮挡的部分。请参阅图7，对光阻图案70进行灰化将第二光阻块72去除，同时减薄第一光阻块71的厚度。请参阅图8，以灰化后的光阻图案70为遮挡对金属材料层60进行刻蚀，去除金属材料层60未被灰化后的光阻图案70遮挡的部分，形成分别与有源层40两端连接的接触电极51及像素电极52以及位于接触电极51上的源/漏极61。
具体地，请参阅图6，所述步骤S4中，以光阻图案70为遮挡对金属材料层60、电极材料层50进行刻蚀，去除金属材料层60、电极材料层50未被光阻图案70遮挡的部分时，还将掺杂非晶硅层42未被光阻图案70遮挡的部分去除，形成分别位于非晶硅材料层41两端上的第一接触层421及第二接触层422，所述接触电极51与第一接触层421连接，所述像素电极52与第二接触层422连接。
进一步地，所述步骤S4中，以光阻图案70为遮挡对金属材料层60进行干刻蚀，去除金属材料层60未被光阻图案70遮挡的部分，之后以光阻图案70为遮挡对电极材料层50及掺杂非晶硅层42进行湿刻蚀，去除电极材料层50及掺杂非晶硅层42未被光阻图案70遮挡的部分。所述步骤S4中，以灰化后的光阻图案70为遮挡对金属材料层60进行干刻蚀，去除金属材料层60未被灰化后的光阻图案70遮挡的部分。
具体地，所述步骤S4还包括将灰化后的光阻图案70进行去除的步骤。
步骤S5、请参阅图9，在栅极绝缘层30、有源层40、像素电极52及源/漏极61上沉积钝化层80。在钝化层80上形成公共电极90。
具体地，所述公共电极90的材料优选为氧化铟锡。
需要说明的是，本发明的TFT阵列基板的制作方法在形成位于栅极20上方的有源层40之后，在栅极绝缘层30与有源层40上依次沉积电极材料层50与金属材料层60，并在金属材料层60上制作光阻图案70，光阻图案70包括厚度不同的第一、第二光阻块71、72，利用光阻图案70对金属材料层60及电极材料层50进行刻蚀而形成分别与有源层40两端连接的连接电极51及像素电极52，并在连接电极51上形成源/漏极61，相比与现有技术中非晶硅层直接与源级和漏极连接，本发明能够有效降低源/漏极与有源层之间的接触电阻，有效地提升了产品的品质。进一步地，本发明通过在栅极绝缘层30上形成非晶硅岛49，并对非晶硅岛49进行离子掺杂而形成有源层40，使有源层40具有依次设置的非晶硅材料层41及掺杂非晶硅层 42，并且在利用光阻图案70对金属材料层60及电极材料层50进行刻蚀的同时还对掺杂非晶硅层42未被光阻图案70遮挡的部分进行刻蚀，形成分别位于非晶硅材料层41两端上的第一接触层421及第二接触层422，所述接触电极51与第一接触层421连接，所述像素电极52与第二接触层422连接，从而进一步的降低源/漏极与有源层之间的接触电阻，同时相比于现有技术，本发明无需对有源层成膜设备进行改造即可完成第一接触层421及第二接触层422的制作，制程简单，设备成本较低，利用现有的采用LTPS材料的TFT阵列基板的产线即可实现本发明的TFT阵列基板的制作方法。
请参阅图9，基于同一发明构思，本发明还提供一种采用上述的TFT阵列基板制作方法制得的TFT阵列基板，该TFT阵列基板包括衬底10、设于衬底10上的栅极20、设于衬底10及栅极20上的栅极绝缘层30、设于栅极绝缘层30上且位于栅极20上方的有源层40、分别与有源层40两端连接的接触电极51及像素电极52以及位于接触电极51上的源/漏极61。
具体地，请参阅图9，所述TFT阵列基板还包括设于栅极绝缘层30、像素电极52、有源层40及源/漏极61上的钝化层80以及位于钝化层80上的公共电极90。
具体地，请参阅图9，所述有源层40包括非晶硅材料层41及位于非晶硅材料层41上的掺杂非晶硅层42，所述掺杂非晶硅层42包括分别位于非晶硅材料层41两端上的第一接触层421及第二接触层422，所述接触电极51与第一接触层421连接，所述像素电极52与第二接触层422连接。
具体地，所述栅极20的材料可以为钼。
具体地，所述栅极绝缘层30的材料可以为氮化硅。
具体地，所述接触电极51、像素电极52、公共电极90的材料优选为氧化铟锡。
需要说明的是，本发明的TFT阵列基板设置分别与有源层40两端连接的接触电极51及像素电极52，并设置位于接触电极51上的源/漏极61，相比与现有技术中非晶硅层直接与源级和漏极连接，本发明能够有效降低源/漏极与有源层之间的接触电阻，有效地提升了产品的品质。进一步地，本发明设置有源层40包括非晶硅材料层41及掺杂非晶硅层42，掺杂非晶硅层42包括分别位于非晶硅材料层41两端上的第一接触层421及第二接触层422，所述接触电极51与第一接触层421连接，所述像素电极52与第二接触层422连接，从而进一步的降低源/漏极与有源层之间的接触电阻。
综上所述，本发明的TFT阵列基板的制作方法在形成位于栅极上方的有源层后，在栅极绝缘层与有源层上依次沉积电极材料层与金属材料层， 并在金属材料层上制作光阻图案，光阻图案包括厚度不同的第一、第二光阻块，利用光阻图案对金属材料层、电极材料层进行刻蚀，形成分别与有源层两端连接的接触电极及像素电极以及位于接触电极上的源/漏极，制程简单，能够有效降低源/漏极与有源层间的接触电阻，提升产品的品质。本发明的TFT阵列基板能够降低源/漏极与有源层之间的接触电阻，产品品质高。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤S1、提供衬底，在所述衬底上形成栅极及覆盖栅极的栅极绝缘层；
    步骤S2、形成位于栅极绝缘层之上的有源层；
    步骤S3、在栅极绝缘层与有源层上依次沉积电极材料层及金属材料层；在金属材料层上形成光阻图案，所述光阻图案包括间隔的第一光阻块与第二光阻块，第一光阻块的部分在竖直方向的投影与有源层的一端重叠，第二光阻块的部分在竖直方向的投影与有源层的另一端重叠；所述第一光阻块的厚度大于第二光阻块的厚度；
    步骤S4、以光阻图案为遮挡对金属材料层、电极材料层进行刻蚀，去除金属材料层、电极材料层未被光阻图案遮挡的部分，对光阻图案进行灰化将第二光阻块去除，以灰化后的光阻图案为遮挡对金属材料层进行刻蚀，去除金属材料层未被灰化后的光阻图案遮挡的部分，形成分别与有源层两端连接的接触电极及像素电极以及位于接触电极上的源/漏极。
  2. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述步骤S4还包括将灰化后的光阻图案进行去除的步骤。
  3. 如权利要求2所述的TFT阵列基板的制作方法，还包括：步骤S5、在栅极绝缘层、有源层、像素电极及源/漏极上沉积钝化层；在钝化层上形成公共电极。
  4. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述步骤S1中，在所述衬底上形成栅极的具体过程为：在衬底上沉积栅极金属层，对所述栅极金属层进行曝光显影制程，形成栅极；
    所述步骤S2包括：
    步骤S21、在栅极绝缘层上沉积非晶硅材料，对所述非晶硅材料进行曝光显影制程，形成非晶硅岛；
    步骤S22、对所述非晶硅岛进行离子掺杂，形成有源层；所述有源层包括非晶硅材料层及位于非晶硅材料层上的掺杂非晶硅层；
    所述步骤S3中，在金属材料层上形成光阻图案的具体过程为：在金属材料层上形成光阻材料层，利用一半色调光罩对光阻材料层进行图案化，得到光阻图案。
  5. 如权利要求4所述的TFT阵列基板的制作方法，其中，所述步骤S4中，以光阻图案为遮挡对金属材料层、电极材料层进行刻蚀，去除金属 材料层、电极材料层未被光阻图案遮挡的部分时，还将掺杂非晶硅层未被光阻图案遮挡的部分去除，形成分别位于非晶硅材料层两端上的第一接触层及第二接触层，所述接触电极与第一接触层连接，所述像素电极与第二接触层连接。
  6. 如权利要求5所述的TFT阵列基板的制作方法，其中，所述步骤S4中，以光阻图案为遮挡对金属材料层进行干刻蚀，去除金属材料层未被光阻图案遮挡的部分，以光阻图案为遮挡对电极材料层及掺杂非晶硅层进行湿刻蚀，去除电极材料层及掺杂非晶硅层未被光阻图案遮挡的部分；所述步骤S4中，以灰化后的光阻图案为遮挡对金属材料层进行干刻蚀，去除金属材料层未被灰化后的光阻图案遮挡的部分。
  7. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述栅极的材料为Mo；
    所述栅极绝缘层的材料为SiNx；
    所述电极材料层的材料为氧化铟锡。
  8. 如权利要求4所述的TFT阵列基板的制作方法，其中，所述步骤S22中，对所述非晶硅岛进行N型离子掺杂。
  9. 如权利要求4所述的TFT阵列基板的制作方法，其中，所述步骤S22中，利用磷离子对所述非晶硅岛进行N型离子掺杂。
  10. 一种TFT阵列基板，包括衬底、设于衬底上的栅极、设于衬底及栅极上的栅极绝缘层、设于栅极绝缘层上且位于栅极上方的有源层、分别与有源层两端连接的接触电极及像素电极以及位于接触电极上的源/漏极。
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