WO2020082501A1 - 阵列基板的制作方法、阵列基板及显示装置 - Google Patents

阵列基板的制作方法、阵列基板及显示装置 Download PDF

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Publication number
WO2020082501A1
WO2020082501A1 PCT/CN2018/118055 CN2018118055W WO2020082501A1 WO 2020082501 A1 WO2020082501 A1 WO 2020082501A1 CN 2018118055 W CN2018118055 W CN 2018118055W WO 2020082501 A1 WO2020082501 A1 WO 2020082501A1
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layer
array substrate
source
amorphous silicon
manufacturing
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PCT/CN2018/118055
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English (en)
French (fr)
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葛邦同
付婷婷
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惠科股份有限公司
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Priority to US16/313,022 priority Critical patent/US10727256B2/en
Publication of WO2020082501A1 publication Critical patent/WO2020082501A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate manufacturing method, an array substrate, and a display device.
  • the liquid crystal display panel (LCD, Liquid Crystal) is an important part of the liquid crystal display, which usually includes a relatively set color filter substrate (Color Filter Substrate, CF substrate) and a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array substrate), and a liquid crystal layer (Liquid Crystal) disposed between the two substrates.
  • the array substrate is provided with scanning lines and data lines that cross each other to define a plurality of pixel units.
  • the TFT is turned on or off according to the scanning line signals to transmit the data line signals to the pixel units.
  • the liquid crystal molecules of the liquid crystal layer are based on different data voltages.
  • the signal rotates to transmit or block light to refract the light provided by the backlight module to form an image corresponding to the data signal.
  • the gate, gate insulating layer, active layer, and source-drain layer all include a photolithography process.
  • a method currently proposed to save the process is to form a source-drain and active layer through a half-tone lithography process.
  • the source-drain metal layer is wet-etched using a wet etching method using the photosensitive material layer as a mask, and then The photosensitive material layer is used as a mask to dry etch the active layer under the source and drain metal layers.
  • the lateral etching length of the source and drain metal layers is close to the vertical etching depth, causing the source
  • the drain metal layer is retracted from the photosensitive material layer by a distance, and the length of the active layer after dry etching is substantially the same as the length of the photosensitive material layer.
  • the active layer protrudes from the source drain metal layer by a distance, called The active layer has a tail. Due to the band tail, the active layer cannot be blocked by the gate for a distance from the backlight direction and cannot be blocked by the source and drain for a distance from the positive light direction. The light from the backlight and the light reflected by the liquid crystal layer impinge on the active layer to generate light leakage current.
  • An object of the present application is to provide a method for manufacturing an array substrate, including but not limited to solving the technical problem of light leakage current caused by excessive tailing of the active layer.
  • a method for manufacturing an array substrate including:
  • a semiconductor material layer and a source-drain metal layer are sequentially formed on the gate insulating layer, and an island-shaped photoresist pattern is formed on the source-drain metal layer, the island-shaped photoresist pattern includes a first portion and A second portion on both sides of a portion, the height of the second portion is greater than the height of the first portion; using the island-shaped photoresist pattern as a mask to perform the first wet etching of the source-drain metal layer to obtain Source-drain metal segment;
  • the island-shaped photoresist pattern after the first ashing is ashed a second time, and the first part is removed to obtain a third part arranged at intervals, and the height of the third part is smaller than the height of the first part;
  • the source and drain metal segments are subjected to a second wet etching to obtain source and drain electrodes.
  • the semiconductor material layer includes an amorphous silicon layer and a doped layer formed on the amorphous silicon layer; the active segment portion includes an amorphous silicon segment and a doped segment provided on the amorphous silicon segment.
  • the doped layer is an amorphous silicon layer doped with n-type elements.
  • the thickness of the amorphous silicon layer is 1000-4000 angstroms, and the thickness of the doped layer is 300-1000 angstroms.
  • the method further includes performing a second dry etching on the doped section to obtain an ohmic contact layer located on both sides of the amorphous silicon section.
  • the amorphous silicon layer is deposited on the gate insulating layer by a chemical vapor deposition method, and the doped layer is deposited on the gate insulating layer by a chemical vapor deposition method.
  • the first dry etching also includes a method of increasing the ratio of the vertical etching to the lateral etching.
  • the method for increasing the ratio of the longitudinal etching to the lateral etching includes at least one of the following:
  • the first ashing uses a mixed gas of oxygen and fluorine-containing gas; the fluorine-containing gas includes at least one of NF3, CF4, C2F6, C4F8, CHF3, and SF6.
  • the second ashing uses a mixed gas of oxygen and fluorine-containing gas; the fluorine-containing gas includes at least one of NF3, CF4, C2F6, C4F8, CHF3, and SF6.
  • the material of the source-drain metal layer is at least one of chromium, molybdenum, copper, titanium, aluminum, or molybdenum nitride.
  • the source-drain metal layer is a Mo / Al / Mo layer, a MoN / Al / Mo layer or a Mo / Al / MoN layer.
  • the thickness of the upper Mo or MoN layer is 100-500 angstroms
  • the thickness of the middle Al layer is 2000-5500 angstroms
  • the thickness of the lower Mo or MoN layer is 100-300 angstroms.
  • the time of the second wet etching does not exceed 150 seconds.
  • the distance of the edge of the source-drain metal segment with respect to the edge of the island-shaped photoresist pattern shrinks inwards by 0.5-1.5 microns.
  • the obtained distance between the source electrode and the drain electrode inwardly with respect to the edge of the third portion is 0.5-1.5 microns.
  • Another object of the present application is to provide an array substrate including an amorphous silicon segment, and the length of the amorphous silicon tail of the amorphous silicon segment is between 1 and 1.6 microns.
  • the array substrate further includes an ohmic contact layer disposed above both sides of the amorphous silicon segment and between the source electrode and the drain electrode, the ohmic contact layer protruding relative to the edges of the source electrode and the drain electrode
  • the length is between 0.1 and 0.4 microns.
  • Still another object of the present application is to provide a display device including an array substrate including an amorphous silicon segment and source and drain electrodes provided on both sides of the amorphous silicon segment, the amorphous
  • the length of the amorphous silicon tail of the silicon segment is between 1 and 1.6 microns
  • the source and drain are Mo / Al / Mo layer, MoN / Al / Mo layer or Mo / Al / MoN layer
  • the upper layer is Mo or MoN
  • the thickness of the layer is 100-500 angstroms
  • the thickness of the intermediate layer Al layer is 2000-5500 angstroms
  • the thickness of the lower Mo or MoN layer is 100-300 angstroms.
  • the array substrate further includes an ohmic contact layer disposed above both sides of the amorphous silicon segment and between the source electrode and the drain electrode, the ohmic contact layer protruding relative to the edges of the source electrode and the drain electrode
  • the length is between 0.1 and 0.4 microns.
  • the manufacturing method of the array substrate adds the first ashing process to the photoresist patterns with different height portions after the first wet etching of the source-drain metal layer with a halftone mask,
  • the edge of the photoresist pattern is aligned with the edge of the source-drain metal layer after wet etching, so that the edge of the semiconductor material layer can be aligned with the source during the first dry etching of the semiconductor material layer under the source-drain metal layer
  • the edges of the drain metal layer are close to or even aligned, reducing the tail length of the active layer, preventing both sides of the active layer from being irradiated by light from the backlight direction or light reflected from one side of the liquid crystal layer to generate light leakage current ,
  • the length of the amorphous silicon band tail of the array substrate and the display device is reduced, thereby reducing the light leakage current, ensuring the stability of the pixel voltage and the stability of
  • FIG. 1 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present application
  • step a of the method for manufacturing an array substrate provided by an embodiment of the present application
  • 3 and 4 are schematic diagrams of step b of the method for manufacturing an array substrate provided by an embodiment of the present application.
  • step c of the method for manufacturing an array substrate provided by an embodiment of the present application
  • step d is a schematic diagram of step d of the method for manufacturing an array substrate provided by an embodiment of the present application.
  • step e of the method for manufacturing an array substrate provided by an embodiment of the present application.
  • step f of the method for manufacturing an array substrate provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 11 is another schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIGS. 1 to 7 the present application provides a method for manufacturing an array substrate, including:
  • step a as shown in FIG. 2, a substrate base layer 1 is provided, a gate 2 is formed on the substrate base layer 1, and a gate insulating layer 3 is formed on the gate 2 and the substrate base layer 1.
  • the substrate base layer 1 is a transparent base layer, such as a glass plate, a transparent plastic plate, and the like.
  • a first metal material layer (not shown) is deposited on the substrate base layer 1 by sputter coating, etc., a first photoresist layer is formed on the first metal material layer, and the first mask plate (not shown) The first photoresist layer is exposed.
  • the mask plate has a hollow pattern area (not shown) corresponding to a plurality of scanning lines and the grid 2. The ultraviolet light exposes the photosensitive material through the hollow pattern area, and after development, the corresponding scanning line on the first photoresist layer The area with the gate 2 remains, other areas are removed, and then the first metal material layer is wet-etched using the hollow pattern area of the first photoresist layer as a mask to obtain the scan line (not shown) and the gate Pole 2.
  • the first metal material layer may be chromium (Cr), molybdenum (Mo), copper (Cu), titanium (Ti), molybdenum / aluminum (Mo / Al) composite layer or molybdenum / aluminum / molybdenum (Mo / Al / Mo)
  • the thickness of the first metal material layer is 2000-8000 angstroms.
  • the gate insulating layer 3 is formed on the gate 2 and the scanning line by chemical vapor deposition.
  • the material of the gate insulating layer 3 is at least one of silicon oxide (SiOx) and silicon nitride (SiNx), and the thickness of the gate insulating layer 3 is 1000-5000 angstroms.
  • Step b as shown in FIGS. 3 and 4, an amorphous silicon layer 14, a doped layer 15 and a source-drain metal layer 17 are sequentially formed on the gate insulating layer 3, and an island shape is formed on the source-drain metal layer 17
  • a photoresist pattern 19 the island-shaped photoresist pattern 19 includes a first portion 191 and second portions 192 located on both sides of the first portion 191, the height of the second portion 192 is greater than the height of the first portion 191, and then the island-shaped photoresist
  • the pattern 19 is a mask for the first wet etching of the source-drain metal layer 17.
  • the amorphous silicon layer 14 is deposited on the gate insulating layer 3 by a chemical vapor deposition method, and the doped layer 15 is deposited on the amorphous silicon layer 14 by a chemical vapor deposition method.
  • the amorphous silicon layer 14 and the doped layer 15 together serve as the semiconductor material layer 16.
  • the semiconductor material layer 16 may also be formed by depositing an amorphous silicon layer 14 and ion-doping the amorphous silicon layer 14, the lower half of the pure amorphous silicon layer 14 is not ion-doped, the upper half Partially doped with ions, it has good conductivity and will not be repeated here.
  • the doped layer 15 is an N + doped layer 15, for example, the amorphous silicon layer 14 is doped with n-type elements such as B (boron), P (phosphorus), or As (arsenic).
  • n-type elements such as B (boron), P (phosphorus), or As (arsenic).
  • the thickness of the amorphous silicon layer 14 is 1000-4000 angstroms, and the thickness of the doped layer 15 is 300-1000 angstroms.
  • the material of the source-drain metal layer 17 may be at least one of chromium (Cr), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), or molybdenum nitride (MoN).
  • the source-drain metal layer 17 is a Mo / Al / Mo layer, MoN / Al / Mo or Mo / Al / MoN layer, and the thickness of the upper Mo layer or MoN layer (away from the semiconductor material layer 6) is 100 -500 angstroms, the thickness of the intermediate layer Al layer is 2000-5500 angstroms, and the thickness of the lower Mo layer or MoN layer (near the semiconductor material layer 6) is 100-300 angstroms.
  • Al has the advantages of good conductivity and low cost, and the Mo material can effectively prevent the diffusion of Al atoms to the amorphous silicon layer 14, further prevent the generation of light leakage current, improve the electrical characteristics of the TFT, and prevent Al from ITO (Indium Tin Oxide) diffusion of the transparent conductive layer to prevent affecting the performance of the transparent conductive layer.
  • ITO Indium Tin Oxide
  • the specific formation method of the island-shaped photoresist pattern 19 is to coat the second photoresist layer 18 on the source-drain metal layer 17 to provide a half-tone mask 10 with a fully light-transmitting region 103, In the semi-transmissive area 102 and the opaque area 101, after exposure and development, the portion of the second photoresist layer 18 corresponding to the fully transparent area 103 remains to form the first portion 191, and the portion corresponding to the opaque area 101 is removed. The portion corresponding to the semi-transmissive area 102 forms the second portion 192.
  • the source-drain metal layer 17 is etched to obtain the source-drain metal segment 171 under the island-shaped photoresist pattern 19, and the edge of the source-drain metal segment 171 is opposite to the island-shaped photoresist pattern 19
  • the edge of the indented inward, the indented distance is about 0.5-1.5 microns.
  • step c as shown in FIG. 5, the island-shaped photoresist pattern 19 is first ashed to align the edge of the island-shaped photoresist pattern 19 with the edge of the source-drain metal segment 171.
  • the first ashing uses a mixed gas of oxygen and a fluorine-containing gas
  • the fluorine-containing gas includes at least one of NF 3 , CF 4 , C 2 F 6 , C 4 F 8 , CHF 3 , and SF 6 .
  • the mixed gas is ionized into a plasma by an RF power source such as a high-pressure discharge, and the island-shaped photoresist pattern 19 is etched with the plasma.
  • the edge of the photoresist pattern 19 is indented inwards by a distance of about 0.5-1.5 microns.
  • the heights of the first portion 191 and the second portion 192 both decrease.
  • Step d using the island-shaped photoresist pattern 19 after the first ashing as a mask, perform the first dry etching on the amorphous silicon layer 14 and the doped layer 15 to obtain the source and drain
  • the active segment portion 161 aligned with the edge of the polar metal segment 171 includes the amorphous silicon segment 141 aligned with the edge of the source-drain metal segment 171 and the doped segment 151 aligned with the edge of the amorphous segment .
  • Dry etching uses vacuum gas to generate a gas plasma under the action of a high-voltage power supply.
  • the gas plasma only affects the non-metallic film layer, and does not etch the metal layer, ensuring that the source-drain metal segment 171 is not affected.
  • the gas plasma bombards the surface of the layer to be etched, which is shown as vertical etching, and the gas plasma reacts with the layer to be etched to generate volatile substances, which is shown as horizontal etching.
  • the vertical depth increases, the lateral etching ability gradually decreases. Therefore, dry etching will form an arc-shaped depression on the surface of the layer to be etched, causing a small inclination at the edges of the amorphous silicon section 141 and the doped section 151 (not shown) Show).
  • “alignment” here does not necessarily mean vertical alignment from top to bottom, but means that the edge of the amorphous silicon segment 141 and the edge of the doped segment 151 have consistency formed by dry etching based on the same mask.
  • the ratio of the vertical etching to the lateral etching in the first dry etching which specifically includes: reducing the etching reaction gas flow ratio, such as when used
  • the mixed plasma of oxygen and SF 6 can reduce the flow rate of SF 6 and increase the vertical etching rate; increase the etching power, that is, increase the ability of attracting electrons between the two plates of the etching chamber, so that the electrons hit the to-be-etched at a faster rate Layer to increase the longitudinal etching rate; reduce the etching gas pressure and reduce the concentration of the reaction gas in the etching chamber, so that the lateral etching rate of the reaction gas becomes slower.
  • the edge of the active segment portion 161 is aligned with the edge of the island-shaped photoresist pattern 19 after the first ashing, reducing the width of the active segment portion 161, thereby reducing the
  • the tail length reduces the length to which both sides of the active segment portion 161 may be irradiated by light, thereby reducing the light leakage current.
  • Step e as shown in FIG. 7, the second ashing is performed on the photoresist pattern after the first ashing to obtain a third portion 193 disposed at intervals, and the active segment portion 161 is exposed between the third portions 193 In the middle.
  • the second ashing uses a mixed gas of oxygen and a fluorine-containing gas
  • the fluorine-containing gas includes at least one of NF 3 , CF 4 , C 2 F 6 , C 4 F 8 , CHF 3 , and SF 6 .
  • the mixed gas is ionized into a plasma by an RF power source such as a high-pressure discharge, and the island-shaped photoresist pattern 19 after the first ashing is etched by the plasma, and the second portion 192 with a small thickness is completely etched away
  • the first portion 191 with a larger thickness is partially removed to form a third portion 193, the thickness of the third portion 193 is smaller than the thickness of the first portion 191, and the length of the third portion 193 is smaller than the length of the first portion 191.
  • the third part 193 exposes the middle and both ends of the active segment part 161.
  • Step f as shown in FIGS. 8 and 9, using the third portion 193 as a mask, perform a second wet etching on the source-drain metal segment 171 to obtain a position below the third portion 193 and relative to the third portion 193
  • the source 172 and the drain 173 whose edges are inwardly retracted are about 0.5-1.5 microns, and at the same time, the source 172 and the drain 173 are also retracted inward and retracted relative to the edge of the active segment portion 161 The distance is about 0.5-1.5 microns.
  • the distance in which the source electrode 172 and the drain electrode 173 retract inward relative to the edge of the active segment portion 161 by adjusting the etching time, that is, the source electrode 172 and the drain electrode 173 The smaller the distance inwardly retracted from the edge of the active segment portion 161, the shorter the tailed length of the two sides of the active segment portion 161 relative to the source electrode 172 and the drain electrode 173, that is, the amorphous silicon segment
  • the tail of 141 and the tail of the ohmic contact layer 152 are smaller, so that the amorphous silicon segment 141 and the ohmic contact layer 152 can have a larger portion blocked by the source 172 and the drain 173, reducing the light generated by light irradiation Leakage current.
  • the time of the second wet etching does not exceed 150 seconds, which can avoid the source-drain metal segment 171 Be over-etched.
  • the second dry etching is performed on the upper doped segment 151 in the active segment portion 161 to obtain an ohmic contact layer 152 corresponding to two third portions 193, an amorphous silicon segment
  • Both sides of the 141 are in contact with the ohmic contact layer 152, which can improve the electrical contact resistance between the amorphous silicon segment 141 and the source and drain 173, thereby improving the electrical characteristics of the TFT.
  • the portion of the amorphous silicon segment 141 exposed between the ohmic contact layers 152 serves as a channel region.
  • the gate electrode 2, the gate insulating layer 3, the amorphous silicon segment 141, the ohmic contact layer 152, and the source electrode 172 and the drain electrode 173 form a TFT.
  • the amorphous silicon segment 141 and the ohmic contact layer 152 are the active layer 20 of the TFT.
  • the portion where the edge of the amorphous silicon segment 141 protrudes relative to the edge of the source 172 and the drain 173 is called an amorphous silicon tail
  • the portion where the ohmic contact layer 152 protrudes to the edge of the source 172 and the drain 173 is called doping Layer tail
  • the length of the doped layer tail is less than the amorphous silicon band tail, specifically, the length of the amorphous silicon band tail is between 1 and 1.6 microns
  • the length of the doped layer band tail is between 0.1 and 0.4 microns between.
  • the length of the amorphous silicon tail obtained by the manufacturing method of the array substrate of the present application is between 1 and 1.6 microns, which can significantly reduce the light leakage current.
  • the manufacturing method of the array substrate provided by the present application further includes stripping the two third portions 193, depositing and forming a passivation layer 6 on the TFT, forming a flat layer 7 on the passivation layer 6, and forming pixels on the flat layer 7
  • the electrode layer 9 and the pixel electrode layer 9 are connected to the drain electrode 173 through the through holes in the passivation layer 6 and the flat layer 7 to obtain the array substrate 100, as shown in FIG.
  • a color resist layer 8 is formed on the passivation layer 6, a flat layer 7 is formed on the color resist layer 8, a pixel electrode layer 9 is formed on the flat layer 7, the pixel electrode layer 9 includes a plurality of sub-pixel electrodes 90, each The sub-pixel electrode layer 9 is connected to the drain electrode 173 through the through holes in the passivation layer 6, the color resist layer 8 and the flat layer 7, to obtain a COA (Color On Array) type array substrate 100, as shown in FIG.
  • COA Color On Array
  • the color The color resist layer 8 includes a red color resist block 81, a green color resist block 82, and a blue color resist block 83, corresponding to a sub-pixel electrode 90, respectively, forming a red sub-pixel 11, a green sub-pixel 12, and a blue sub-pixel 13.
  • a-Si tails with different lengths can be obtained according to different process conditions in the manufacturing process and
  • the doped layer has a tail (N + tail).
  • This application tested the light leakage current caused by the backlight fully turned on under several conditions. It can be seen that the manufacturing method of the array substrate provided by the embodiment of the present application can reduce the tail length of the amorphous silicon segment 141 by about 0.7 microns, and the light leakage current is as low as 6% of the conventional structure, thereby effectively ensuring the pixel voltage Stability and stability of display quality.
  • the present application also provides an array substrate 100, which is manufactured by using the manufacturing method of the array substrate described in the above embodiment, as shown in FIGS. 10 and 11.
  • the array substrate 100 is manufactured by the method for manufacturing an array substrate described in the above embodiments, and includes a substrate base layer 1, a gate electrode 2 provided on the substrate base layer 1, a substrate electrode provided on the substrate base layer 1 and the gate electrode 2 Gate insulating layer 3, amorphous silicon segment 141 provided on the gate insulating layer 3, ohmic contact layer 152 provided on both sides of the amorphous silicon segment 141, source electrode 172 and drain electrode provided corresponding to the ohmic contact layer 152 173, and the pixel electrode 90 connected to the drain electrode 173.
  • the portion where the edge of the amorphous silicon segment 141 protrudes relative to the edge of the source 172 and the drain 173 is called an amorphous silicon tail, and the portion where the ohmic contact layer 152 protrudes relative to the edge of the source 172 and the drain 173 is called a doped
  • the tail length of the doped layer, the length of the tail of the doped layer is smaller than that of the amorphous silicon, specifically, the length of the tail of the amorphous silicon is between 1 and 1.6 micrometers, which can be reduced to about 1 micrometer under the optimal condition 5
  • the length of the tail of the doped layer is between 0.1 and 0.4 microns, and under optimal conditions, 5 can be reduced to about 0.1 microns.
  • Both the amorphous silicon tail (a-Si tail) and the doped layer tail (N + tail) of the array substrate 100 provided by the embodiments of the present application are reduced, thereby reducing the light leakage current and ensuring the stability of the pixel voltage And the stability of the display.
  • the source electrode 172 and the drain electrode 173 have a stack structure of Mo / Al / Mo layer, MoN / Al / Mo or Mo / Al / MoN layer, and the thickness of the upper Mo or MoN layer (away from the amorphous silicon segment 141) is 100- 500 angstroms, the thickness of the middle Al layer is 2000-5500 angstroms, and the thickness of the lower Mo or MoN layer (near the amorphous silicon segment 141) is 100-300 angstroms.
  • Al has the advantages of good conductivity and low cost, and the Mo material can effectively prevent the diffusion of Al atoms to the amorphous silicon segment 141, further prevent the generation of light leakage current, improve the electrical characteristics of the TFT, and prevent Al from going to the pixel
  • the diffusion of the electrode 90 prevents affecting the performance of the transparent conductive layer.
  • the present application also provides a display device 500, as shown in FIG. 12, which includes a liquid crystal display panel and a backlight module 400.
  • the liquid crystal display panel is composed of the array substrate 100 (see FIG. 11) and the array substrate described in the above embodiment.
  • a counter substrate 200 oppositely disposed at 100 and a liquid crystal layer 300 interposed between the array substrate 100 and the counter substrate 200 are formed.
  • the backlight module 400 is disposed on the side of the array substrate 100 to provide light to the liquid crystal layer 300.
  • the display device 500 of the present application includes the array substrate 100 described in the above embodiments, and both the amorphous silicon tail (a-Si tail) and the doped layer tail (N + tail) are reduced, thereby reducing the light leakage current , To ensure the stability of the pixel voltage and the stability of the display screen.
  • a-Si tail amorphous silicon tail
  • N + tail doped layer tail

Abstract

一种阵列基板的制作方法，在源漏极金属层(17)的湿蚀刻工艺后对导状光阻图案(19)进行第一次灰化，使岛状光阻图案(19)的边缘与源漏极金属段(171)的边缘对齐。

Description

阵列基板的制作方法、阵列基板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板的制作方法、阵列基板及显示装置。
背景技术
液晶显示面板(LCD，Liquid Crystal Display)是液晶显示器的重要组成部分，其通常包括相对设置的彩色滤光片基板(Color Filter Substrate，CF基板)和薄膜晶体管阵列基板(Thin Film Transistor Array Substrate,TFT阵列基板)，以及配置于该两基板之间的液晶层(Liquid Crystal Layer)构成。阵列基板上设有相互交叉以限定多个像素单元的扫描线和数据线，TFT根据扫描线的信号打开或关闭，以将数据线的信号传递至像素单元，液晶层的液晶分子根据不同数据电压信号旋转，以透光或遮光，将背光模组所提供的光线折射出来以形成对应数据信号的图像。
底栅型的薄膜晶体管(TFT)的制作中，栅极、栅极绝缘层、有源层和源漏极层均包括一道光刻制程。目前提出的一种节省制程的方法是通过一道半色调光刻工艺形成源漏极和有源层，先采用湿蚀刻法以感光材料层为掩模对源漏极金属层进行湿蚀刻，然后以感光材料层为掩模对源漏极金属层下方的有源层进行干蚀刻，由于湿蚀刻具有各向同性的特点，所以对源漏极金属层的横向蚀刻长度接近于垂直蚀刻深度，造成源漏极金属层相对于感光材料层缩进一段距 离，而干蚀刻后的有源层与感光材料层的长度基本一致，如此，造成有源层相对于源漏极金属层突出一段距离，称为有源层带尾(tail)。由于该带尾，使得有源层从背光方向上有一段距离无法被栅极遮挡，从正光方向上有一段距离无法被源漏极遮挡。来自背光源的光线和被液晶层一侧反射的光线照射到有源层上，产生光漏电流，带尾的长度越大，光漏电流越大，进而造成像素电压的变化并使最佳伽马公共电压(Best Vcom,Best gamma common voltage)不稳定，导致画面发生闪烁现象和残影(Image Sticking)的发生，最终降低画面显示质量。
申请内容
本申请一目的在于提供一种阵列基板的制作方法，包括但不限于解决有源层带尾过大导致光漏电流的技术问题。
为解决上述技术问题，本申请实施例采用的技术方案是：一种阵列基板的制作方法，包括：
提供衬底基层，在所述衬底基层上形成栅极，并在所述栅极和所述衬底基层上形成栅极绝缘层；
在栅极绝缘层上依次形成半导体材料层和源漏极金属层，并在所述源漏极金属层上形成岛状光阻图案，所述岛状光阻图案包括第一部分和位于所述第一部分两侧的第二部分，所述第二部分的高度大于所述第一部分的高度；以所述岛状光阻图案为掩模对所述源漏极金属层进行第一次湿蚀刻，得到源漏极金属段；
对所述岛状光阻图案进行第一次灰化，使所述岛状光阻图案的边缘与所述源漏极金属段的边缘对齐；
以经第一次灰化后的岛状光阻图案为掩模，对所述半导体材料层层进行第 一次干蚀刻，得到有源段部分；
对经第一次灰化后的岛状光阻图案进行第二次灰化，去除第一部分，得到间隔设置的第三部分，所述第三部分的高度小于第一部分的高度；
以所述第三部分为掩模，对所述源漏极金属段进行第二次湿蚀刻，得到源极和漏极。
所述半导体材料层包括非晶硅层以及形成于所述非晶硅层上的掺杂层；所述有源段部分包括非晶硅段以及设于非晶硅段上的掺杂段。
所述掺杂层为掺杂n型元素的非晶硅层。
所述非晶硅层的厚度为1000-4000埃，所述掺杂层的厚度为300-1000埃。
在得到所述源极和漏极之后，还包括对所述掺杂段进行第二次干蚀刻，得到位于所述非晶硅段两侧上方的欧姆接触层。
所述非晶硅层通过化学气相沉积法沉积于所述栅极绝缘层上，所述掺杂层通过化学气相沉积法沉积于所述栅极绝缘层上。
所述第一次干蚀刻还包括增加纵向蚀刻与横向蚀刻的速率之比的方法。
所述增加纵向蚀刻与横向蚀刻的速率之比的方法包括下列至少之一：
减小蚀刻反应气体流量比率；
提高蚀刻功率；以及
减小蚀刻气体压力，降低蚀刻腔内反应气体浓度。
所述第一次灰化采用氧气和含氟气体的混合气体；所述含氟气体包括NF3、CF4、C2F6、C4F8、CHF3、SF6中的至少一种。
所述第二次灰化采用氧气和含氟气体的混合气体；所述含氟气体包括NF3、CF4、C2F6、C4F8、CHF3、SF6中的至少一种。
所述源漏极金属层的材料为铬、钼、铜、钛、铝或氮化钼中的至少一种。
所述源漏极金属层为Mo/Al/Mo层、MoN/Al/Mo层或Mo/Al/MoN层。
上层Mo或MoN层的厚度为100-500埃，中间层Al层的厚度为2000-5500埃，下层Mo或MoN层的厚度为100-300埃。
所述第二次湿蚀刻的时间不超过150秒。
所述第一次湿蚀刻后，所述源漏极金属段的边缘相对于所述岛状光阻图案的边缘向内缩进的距离为0.5-1.5微米。
所述第二次湿蚀刻后，得到的所述源极和漏极相对于所述第三部分的边缘向内缩进的距离为0.5-1.5微米。
本申请的另一目的在于提供一种阵列基板，所述阵列基板包括非晶硅段，所述非晶硅段的非晶硅带尾的长度在1至1.6微米之间。
所述阵列基板还包括设于所述非晶硅段的两侧上方与所述源极和漏极之间的欧姆接触层，所述欧姆接触层相对于所述源极和漏极的边缘突出的长度在0.1至0.4微米之间。
本申请的再一目的在于提供一种显示装置，包括阵列基板，所述阵列基板包括非晶硅段以及设于所述非晶硅段的两侧上方的源极和漏极，所述非晶硅段的非晶硅带尾的长度在1至1.6微米之间，所述源极和漏极为Mo/Al/Mo层、MoN/Al/Mo层或Mo/Al/MoN层，上层Mo或MoN层的厚度为100-500埃，中间层Al层的厚度为2000-5500埃，下层Mo或MoN层的厚度为100-300埃。
所述阵列基板还包括设于所述非晶硅段的两侧上方与所述源极和漏极之间的欧姆接触层，所述欧姆接触层相对于所述源极和漏极的边缘突出的长度在0.1至0.4微米之间。
本申请实施例提供的阵列基板的制作方法，通过在以半色调掩模对源漏极金属层的第一次湿蚀刻后，对具有不同高度部分的光阻图案增加第一次灰化工 艺，使光阻图案的边缘与湿蚀刻后的源漏极金属层的边缘对齐，从而在对源漏极金属层下方的半导体材料层进行第一次干蚀刻时，能够使半导体材料层的边缘与源漏极金属层的边缘接近甚至对齐，降低了有源层的带尾长度，防止有源层的两侧被来自背光方向的光线或被液晶层一侧反射来的光线照射到而产生光漏电流，保证了像素电压的稳定以及画面显示的质量。阵列基板及显示装置的非晶硅带尾的长度降低，从而降低了光漏电流，保证了像素电压的稳定性和显示画面的稳定性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请实施例提供的阵列基板的制作方法的流程图；
图2是本申请实施例提供的阵列基板的制作方法的步骤a的示意图；
图3和4是本申请实施例提供的阵列基板的制作方法的步骤b的示意图；
图5是本申请实施例提供的阵列基板的制作方法的步骤c的示意图；
图6是本申请实施例提供的阵列基板的制作方法的步骤d的示意图；
图7是本申请实施例提供的阵列基板的制作方法的步骤e的示意图；
图8和图9是本申请实施例提供的阵列基板的制作方法的步骤f的示意图；
图10是本申请实施例提供的阵列基板的一种结构示意图；
图11是本申请实施例提供的阵列基板的另一种结构示意图；
图12是本申请实施例提供的显示装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。请参阅图1至7，本申请提供一种阵列基板的制作方法，包括：
步骤a，如图2所示，提供衬底基层1，在衬底基层1上形成栅极2，并在栅极2和衬底基层1上形成栅极绝缘层3。
具体地，衬底基层1为透明基层，如玻璃板、透明塑料板等。
在衬底基层1上通过溅射镀膜等方式沉积第一金属材料层(未图示)，在第一金属材料层上形成第一光阻层，通过第一掩模板(未图示)对该第一光阻层进行曝光。该掩模板上具有对应多条扫描线以及栅极2的镂空图案区(未图示)，紫外光通过该镂空图案区对该感光材料进行曝光，显影后，第一光阻层上对应 扫描线和栅极2的区域保留，其他区域被去除，然后，以该第一光阻层的镂空图案区作为掩模对第一金属材料层进行湿蚀刻，同时得到扫描线(未图示)和栅极2。
第一金属材料层可以为铬(Cr)、钼(Mo)、铜(Cu)、钛(Ti)、钼/铝(Mo/Al)复合层或钼/铝/钼(Mo/Al/Mo)等两种以上金属的复合层等，第一金属材料层的厚度为2000-8000埃。
在栅极2和扫描线上通过化学气相沉积法沉积形成栅极绝缘层3。栅极绝缘层3的材料为氧化硅(SiOx)和氮化硅(SiNx)的至少一种，栅极绝缘层3的厚度为1000-5000埃。
步骤b，如图3和图4所示，在栅极绝缘层3上依次形成非晶硅层14、掺杂层15和源漏极金属层17，在源漏极金属层17上形成岛状光阻图案19，该岛状光阻图案19包括第一部分191和位于第一部分191两侧的第二部分192，第二部分192的高度大于第一部分191的高度，然后，以该岛状光阻图案19为掩模对源漏极金属层17进行第一次湿蚀刻。
具体地，通过化学气相沉积法在栅极绝缘层3上沉积形成非晶硅层14，通过化学气相沉积法在非晶硅层14上沉积形成掺杂层15。非晶硅层14和掺杂层15共同作为半导体材料层16。
在其他实施例中，半导体材料层16还可以由沉积非晶硅层14并对非晶硅层14进行离子掺杂形成，下半部分纯净的非晶硅层14未被离子掺杂，上半部分被离子掺杂，具有良好的导电性，在此不再赘述。
具体地，在本实施例中，掺杂层15为N+掺杂层15，如由非晶硅层14掺杂B(硼)、P(磷)或As(砷)等n型元素形成。
非晶硅层14的厚度为1000-4000埃，掺杂层15的厚度为300-1000埃。
源漏极金属层17的材料可以为铬(Cr)、钼(Mo)、铜(Cu)、钛(Ti)、铝(Al)或氮化钼(MoN)中的至少一种。在本实施例中，源漏极金属层17为Mo/Al/Mo层、MoN/Al/Mo或Mo/Al/MoN层，上层Mo层或MoN层(远离半导体材料层6)的厚度为100-500埃，中间层Al层的厚度为2000-5500埃，下层Mo层或MoN层(靠近半导体材料层6)的厚度为100-300埃。一方面，Al具有良好的导电性和低成本优点，而Mo材料能够有效防止Al原子向非晶硅层14的扩散，进一步防止产生光漏电流，改善TFT的电学特性，还能防止Al向ITO(氧化铟锡)透明导电层的扩散，防止影响透明导电层的性能。
岛状光阻图案19的具体形成方法为，在源漏极金属层17上涂布第二光阻层18，提供一半色调光罩10，该半色调光罩10上具有全透光区103、半透光区102以及不透光区101，曝光并显影后，第二光阻层18上对应全透光区103的部分保留，形成第一部分191，对应不透光区101的部分被去掉，对应半透光区102的部分形成第二部分192。
经过该步骤b后，源漏极金属层17被蚀刻，得到位于该岛状光阻图案19下方的源漏极金属段171，该源漏极金属段171的边缘相对于岛状光阻图案19的边缘向内缩进，缩进距离约为0.5-1.5微米。
步骤c，如图5所示，对岛状光阻图案19进行第一次灰化，使岛状光阻图案19的边缘与源漏极金属段171的边缘对齐。
具体来说，第一次灰化采用氧气和含氟气体的混合气体，含氟气体包括NF 3、CF 4、C 2F 6、C 4F 8、CHF 3、SF 6中的至少一种。将该混合气体通过射频功率源如高压放电形式电离为等离子体，以该等离子体对岛状光阻图案19进行蚀刻。
岛状光阻图案19经第一次灰化后，其边缘向内缩进，缩进距离大约0.5-1.5 微米。同时，第一部分191和第二部分192的高度均减小。
步骤d，如图6所示，以经第一次灰化后的岛状光阻图案19为掩模，对非晶硅层14和掺杂层15进行第一次干蚀刻，得到与源漏极金属段171的边缘对齐的有源段部分161，该有源段部分161包括与源漏极金属段171的边缘对齐的非晶硅段141和与非晶段的边缘对齐的掺杂段151。
干蚀刻是利用真空气体在高压电源的作用下产生气体等离子体，气体等离子体只对非金属膜层产生作用，对金属层不产生蚀刻，保证了源漏极金属段171不被影响。
干蚀刻过程中，气体等离子体轰击待蚀刻层表面，表现为纵向蚀刻，气体等离子体与待蚀刻层反应生成挥发性物质，表现为横向蚀刻。随着纵向深度的增加，横向蚀刻能力逐渐降低，因此，干蚀刻会在待蚀刻层表面形成弧形的凹陷，在非晶硅段141和掺杂段151的边缘造成一小的倾角(未图示)。应当理解的是，这里的“对齐”并不一定指上下垂直对准，而是指非晶硅段141的边缘和掺杂段151的边缘具有基于同一掩模经干蚀刻形成的一致性。
在该步骤d中，为了使得有源段部分161的边缘尽可能垂直形成，需要提高第一次干蚀刻中纵向蚀刻与横向蚀刻的比率，具体包括：减小蚀刻反应气体流量比率，如当采用氧气与SF 6的混合等离子体时，可以降低SF 6的流量，提高纵向蚀刻速率；提高蚀刻功率，即提高蚀刻腔体的两极板间吸引电子的能力，使电子以更快的速率撞击待蚀刻层，提高纵向蚀刻速率；减小蚀刻气体压力，降低蚀刻腔内反应气体浓度，使反应气体的横向蚀刻速率变慢。
经过该步骤d后，有源段部分161的边缘与第一次灰化后的岛状光阻图案19的边缘对齐，降低了有源段部分161的宽度，从而降低了有源段部分161的带尾长度并降低了有源段部分161的两侧可能被光线照射到的长度，从而降 低了光漏电流。
步骤e，如图7所示，对经第一次灰化后的光阻图案进行第二次灰化，得到间隔设置的第三部分193，第三部分193之间暴露出有源段部分161的中部。
具体来说，第二次灰化采用氧气和含氟气体的混合气体，含氟气体包括NF 3、CF 4、C 2F 6、C 4F 8、CHF 3、SF 6中的至少一种。将该混合气体通过射频功率源如高压放电形式电离为等离子体，以该等离子体对第一次灰化后的岛状光阻图案19进行蚀刻，厚度较小的第二部分192被完全蚀刻去除，厚度较大的第一部分191被部分去除，形成第三部分193，第三部分193的厚度小于第一部分191的厚度，且第三部分193的长度小于第一部分191的长度。第三部分193将有源段部分161的中部以及两端暴露出。
步骤f，如图8和图9所示，以第三部分193为掩模，对源漏极金属段171进行第二次湿蚀刻，得到位于第三部分193下方且相对于第三部分193的边缘向内缩进的源极172和漏极173，缩进距离大约为0.5-1.5微米，同时，源极172和漏极173相对于有源段部分161的边缘也向内缩进，缩进距离大约为0.5-1.5微米。在该第二次湿蚀刻中，还可以通过调整蚀刻时间，来调整源极172和漏极173相对于有源段部分161的边缘向内缩进的距离，即，源极172和漏极173相对于有源段部分161的边缘向内缩进的距离越小，则有源段部分161的两侧相对于源极172和漏极173突出的带尾的长度更小，即非晶硅段141的带尾和欧姆接触层152的带尾更小，从而非晶硅段141和欧姆接触层152能够有更大的部分被源极172和漏极173遮挡，降低由光线照射而产生的光漏电流。
具体地，对于Mo/Al/Mo、MoN/Al/Mo或Mo/Al/MoN结构的源漏极金属层17，第二次湿蚀刻的时间不超过150秒，能够避免源漏极金属段171被过 度蚀刻。
然后，以第三部分193为掩模，对有源段部分161中位于上层的掺杂段151进行第二次干蚀刻，得到对应两个第三部分193的欧姆接触层152，非晶硅段141的两侧与欧姆接触层152相接，能够改善非晶硅段141与源漏极173之间的电学接触电阻，从而提高TFT的电学特性。非晶硅段141暴露于欧姆接触层152之间的部分作为沟道区。
栅极2、栅极绝缘层3、非晶硅段141、欧姆接触层152以及源极172和漏极173形成一个TFT，非晶硅段141及欧姆接触层152为TFT的有源层20。
非晶硅段141的边缘相对于源极172和漏极173的边缘突出的部分称为非晶硅带尾，欧姆接触层152对于源极172和漏极173的边缘突出的部分称为掺杂层带尾，掺杂层带尾的长度小于非晶硅带尾，具体来说，非晶硅带尾的长度在1至1.6微米之间，掺杂层带尾的长度在0.1至0.4微米之间。经本申请的阵列基板的制作方法得到的非晶硅带尾的长度在1至1.6微米之间，能够显著降低光漏电流。
本申请提供的阵列基板的制作方法，还包括将两个第三部分193剥离，在TFT上沉积形成钝化层6，并在钝化层6上形成平坦层7，在平坦层7上形成像素电极层9，像素电极层9通过贯穿钝化层6和平坦层7上的过孔与漏极173连接，得到阵列基板100，如图10所示；或者包括在TFT上沉积形成钝化层6，在钝化层6上形成彩色色阻层8，在彩色色阻层8上形成平坦层7，在平坦层7上形成像素电极层9，像素电极层9包括多个子像素电极90，每一子像素电极层9通过贯穿钝化层6、彩色色阻层8以及平坦层7上的过孔与漏极173连接，得到COA(Color on Array)型阵列基板100，如图11所示，彩色色阻层8包括红色色阻块81、绿色色阻块82和蓝色色阻块83，分别对应一子像素电 极90，形成红色子像素11、绿色子像素12和蓝色子像素13。
请参阅下表1，通过本申请实施例提供的阵列基板的制作方法所制作的阵列基板中，对应制作过程中不同工艺条件可得到具有不同长度的非晶硅带尾(a-Si tail)和掺杂层带尾(N+tail)，本申请测试了几种条件下在背光全开的情况下所导致产生的光漏电流。由此可知，本申请实施例提供的阵列基板的制作方法能够将非晶硅段141的带尾长度降低约0.7微米，使光漏电流低至常规结构的6％，从而有效保证了像素电压的稳定性和显示质量的稳定性。
表1不同长度的非晶硅段带尾和掺杂层带尾的光漏电流测试结果
Figure PCTCN2018118055-appb-000001
其中，E为科学计数法符号。
本申请还提供一种阵列基板100，采用上述实施例所说的阵列基板的制作方法所制作得到，如图10和11所示。该阵列基板100采用上述实施例所说的阵列基板的制作方法所制作得到，包括衬底基层1、设于衬底基层1上的栅极2、设于衬底基层1和栅极2上的栅极绝缘层3、设于栅极绝缘层3上的非晶硅段141、对应非晶硅段141的两侧设置的欧姆接触层152、对应欧姆接触层152设置的源极172和漏极173，以及连接于漏极173的像素电极90。
非晶硅段141的边缘相对于源极172和漏极173的边缘突出的部分称为非 晶硅带尾，欧姆接触层152相对于源极172和漏极173的边缘突出的部分称为掺杂层带尾，掺杂层带尾的长度小于非晶硅带尾，具体来说，非晶硅带尾的长度在1至1.6微米之间，最佳条件5下可以降到约1微米，掺杂层带尾的长度在0.1至0.4微米之间，最佳条件下5可以降到约0.1微米。本申请实施例提供的阵列基板100的非晶硅带尾(a-Si tail)和掺杂层带尾(N+tail)均得以降低，从而降低了光漏电流，保证了像素电压的稳定性和显示画面的稳定性。源极172和漏极173为Mo/Al/Mo层、MoN/Al/Mo或Mo/Al/MoN层的叠层结构，上层Mo或MoN层(远离非晶硅段141)的厚度为100-500埃，中间层Al层的厚度为2000-5500埃，下层Mo或MoN层(靠近非晶硅段141)的厚度为100-300埃。一方面，Al具有良好的导电性和低成本优点，而Mo材料能够有效防止Al原子向非晶硅段141的扩散，进一步防止产生光漏电流，改善TFT的电学特性，还能防止Al向像素电极90的扩散，防止影响透明导电层的性能。
本申请还提供一种显示装置500，如图12所示，包括液晶显示面板和背光模组400，液晶显示面板由上述实施例所说的阵列基板100(参见图11所示)、与阵列基板100相对设置的对置基板200以及夹设于阵列基板100和对置基板200之间的液晶层300形成，背光模组400设于阵列基板100一侧，以向液晶层300提供光线。本申请的显示装置500包括上述实施例所说的阵列基板100，其非晶硅带尾(a-Si tail)和掺杂层带尾(N+tail)均得以降低，从而降低了光漏电流，保证了像素电压的稳定性和显示画面的稳定性。
以上仅为本申请的可选实施例而已，并不用于限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (20)

  1. 一种阵列基板的制作方法，包括：
    提供衬底基层，在所述衬底基层上形成栅极，并在所述栅极和所述衬底基层上形成栅极绝缘层；
    在栅极绝缘层上依次形成半导体材料层和源漏极金属层，并在所述源漏极金属层上形成岛状光阻图案，所述岛状光阻图案包括第一部分和位于所述第一部分两侧的第二部分，所述第二部分的高度大于所述第一部分的高度；以所述岛状光阻图案为掩模对所述源漏极金属层进行第一次湿蚀刻，得到源漏极金属段；
    对所述岛状光阻图案进行第一次灰化，使所述岛状光阻图案的边缘与所述源漏极金属段的边缘对齐；
    以经第一次灰化后的岛状光阻图案为掩模，对所述半导体材料层层进行第一次干蚀刻，得到有源段部分；
    对经第一次灰化后的岛状光阻图案进行第二次灰化，去除第一部分，得到间隔设置的第三部分，所述第三部分的高度小于第一部分的高度；以及
    以所述第三部分为掩模，对所述源漏极金属段进行第二次湿蚀刻，得到源极和漏极。
  2. 根据权利要求1所述的阵列基板的制作方法，其中，所述半导体材料层包括非晶硅层以及形成于所述非晶硅层上的掺杂层；所述有源段部分包括非晶硅段以及设于非晶硅段上的掺杂段。
  3. 根据权利要求2所述的阵列基板的制作方法，其中，所述掺杂层为掺杂n型元素的非晶硅层。
  4. 如权利要求2所述的阵列基板的制作方法，其中所述非晶硅层的厚度为1000-4000埃，所述掺杂层的厚度为300-1000埃。
  5. 如权利要求2所述的阵列基板的制作方法，其中，在得到所述源极和漏极之后，还包括对所述掺杂段进行第二次干蚀刻，得到位于所述非晶硅段两侧上方的欧姆接触层。
  6. 如权利要求2所述的阵列基板的制作方法，其中，所述非晶硅层通过化学气相沉积法沉积于所述栅极绝缘层上，所述掺杂层通过化学气相沉积法沉积于所述栅极绝缘层上。
  7. 如权利要求1所述的阵列基板的制作方法，其中，所述第一次干蚀刻还包括增加纵向蚀刻与横向蚀刻的速率之比的方法。
  8. 如权利要求7所述的阵列基板的制作方法，其中，所述增加纵向蚀刻与横向蚀刻的速率之比的方法包括下列至少之一：
    减小蚀刻反应气体流量比率；
    提高蚀刻功率；以及
    减小蚀刻气体压力，降低蚀刻腔内反应气体浓度。
  9. 如权利要求1所述的阵列基板的制作方法，其中，所述第一次灰化采用氧气和含氟气体的混合气体；所述含氟气体包括NF3、CF4、C2F6、C4F8、CHF3、SF6中的至少一种。
  10. 如权利要求1所述的阵列基板的制作方法，其中，所述第二次灰化采用氧气和含氟气体的混合气体；所述含氟气体包括NF3、CF4、C2F6、C4F8、CHF3、SF6中的至少一种。
  11. 如权利要求1所述的阵列基板的制作方法，其中，所述源漏极金属层的材料为铬、钼、铜、钛、铝或氮化钼中的至少一种。
  12. 如权利要求11所述的阵列基板的制作方法，其中，所述源漏极金属层为Mo/Al/Mo层、MoN/Al/Mo层或Mo/Al/MoN层。
  13. 如权利要求12所述的阵列基板的制作方法，其中，上层Mo或MoN层的厚度为100-500埃，中间层Al层的厚度为2000-5500埃，下层Mo或MoN层的厚度为100-300埃。
  14. 如权利要求13所述的阵列基板的制作方法，其中，所述第二次湿蚀刻的时间不超过150秒。
  15. 如权利要求1所述的阵列基板的制作方法，其中，所述第一次湿蚀刻后，所述源漏极金属段的边缘相对于所述岛状光阻图案的边缘向内缩进的距离为0.5-1.5微米。
  16. 如权利要求1所述的阵列基板的制作方法，其中，所述第二次湿蚀刻后，得到的所述源极和漏极相对于所述第三部分的边缘向内缩进的距离为0.5-1.5微米。
  17. 一种阵列基板，所述阵列基板包括非晶硅段，所述非晶硅段的非晶硅带尾的长度在1至1.6微米之间。
  18. 如权利要求17所述的阵列基板，其中，所述阵列基板还包括设于所述非晶硅段的两侧上方与所述源极和漏极之间的欧姆接触层，所述欧姆接触层相对于所述源极和漏极的边缘突出的长度在0.1至0.4微米之间。
  19. 一种显示装置，包括阵列基板，所述阵列基板包括非晶硅段以及设于所述非晶硅段的两侧上方的源极和漏极，所述非晶硅段的非晶硅带尾的长度在1至1.6微米之间，所述源极和漏极为Mo/Al/Mo层、MoN/Al/Mo层或Mo/Al/MoN层，上层Mo或MoN层的厚度为100-500埃，中间层Al层的厚度为2000-5500埃，下层Mo或MoN层的厚度为100-300埃。
  20. 如权利要求19所述的显示装置，其中，所述阵列基板还包括设于所述非晶硅段的两侧上方与所述源极和漏极之间的欧姆接触层，所述欧姆接触层相对于所述源极和漏极的边缘突出的长度在0.1至0.4微米之间。
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