WO2020177597A1 - 阵列基板及其制备方法、显示面板和显示装置 - Google Patents

阵列基板及其制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2020177597A1
WO2020177597A1 PCT/CN2020/076814 CN2020076814W WO2020177597A1 WO 2020177597 A1 WO2020177597 A1 WO 2020177597A1 CN 2020076814 W CN2020076814 W CN 2020076814W WO 2020177597 A1 WO2020177597 A1 WO 2020177597A1
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Prior art keywords
light
shielding pattern
substrate
pattern
barrier layer
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PCT/CN2020/076814
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English (en)
French (fr)
Inventor
刘军
闫梁臣
周斌
刘宁
李广耀
李伟
郝朝威
张晓东
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2020177597A1 publication Critical patent/WO2020177597A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Definitions

  • the present disclosure relates to an array substrate and a preparation method thereof, a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • Organic Light Emitting Diode Organic Light Emitting Diode
  • an array substrate includes a substrate; a first light-shielding pattern provided on one side of the substrate; and a barrier layer provided on a side of the first light-shielding pattern away from the substrate, the barrier layer covering at least a part of the first light-shielding pattern.
  • the array substrate further includes: a second light-shielding pattern disposed on a side of the first light-shielding pattern away from the substrate, the second light-shielding pattern covers a part of the first light-shielding pattern; the barrier layer at least covers the first light-shielding pattern The part of the pattern that is not covered by the second shading pattern.
  • the distance of at least part of the edge of the orthographic projection of the barrier layer on the substrate beyond the edge of the orthographic projection of the portion of the first shading pattern not covered by the second shading pattern on the substrate is less than or equal to 2 ⁇ m.
  • the material of the barrier layer includes hardened photoresist.
  • the size of the barrier layer in a direction perpendicular to the substrate is greater than or equal to 0.1 ⁇ m.
  • the material of the first light shielding pattern includes at least one of aluminum or aluminum neodymium alloy; the material of the second light shielding pattern includes at least one of molybdenum, molybdenum tungsten alloy, or molybdenum-niobium alloy.
  • the thickness of the first light-shielding pattern ranges from 0.1 ⁇ m to 0.15 ⁇ m, and the thickness of the second light-shielding pattern ranges from 0.05 ⁇ m to 0.08 ⁇ m.
  • the array substrate further includes: a thin film transistor disposed on the side of the barrier layer and the second light-shielding pattern away from the substrate.
  • the thin film transistor includes a gate and an active layer, and the gate is located far from the active layer.
  • the orthographic projection of the active layer on the substrate is within a range of the orthographic projection of the first light shielding pattern on the substrate.
  • the orthographic projection of the barrier layer on the substrate and the orthographic projection of the active layer on the substrate at least partially overlap.
  • the array substrate further includes: a buffer layer disposed between the barrier layer, the second light-shielding pattern, and the active layer.
  • the display panel includes: the array substrate as described in any of the above embodiments.
  • a display device in another aspect, includes: the display panel as described in any of the above embodiments.
  • a method for manufacturing an array substrate includes: providing a substrate; forming a first light-shielding pattern on one side of the substrate; and forming a barrier layer on a side of the first light-shielding pattern away from the substrate, and the barrier layer covers at least a part of the first light-shielding pattern.
  • the preparation method further includes: forming a second light-shielding pattern on a side of the first light-shielding pattern away from the substrate, the second light-shielding pattern covers a portion of the first light-shielding pattern; the barrier layer at least covers the first light-shielding pattern The part not covered by the second shading pattern.
  • forming the first shading pattern on one side of the substrate and forming the second shading pattern on the side of the first shading pattern away from the substrate includes: sequentially forming the first shading pattern on one side of the substrate Layer and the second light-shielding layer, the etching selection ratio of the second light-shielding layer is greater than the etching selection ratio of the first light-shielding layer; the second light-shielding layer is coated with photoresist on the side away from the substrate; the second light-shielding layer is formed by one patterning process A shading pattern, a second shading pattern, and a photoresist pattern covering the first shading pattern and the second shading pattern, the edge of the orthographic projection of the photoresist pattern on the substrate exceeds the orthographic projection of the first shading pattern on the substrate the edge of.
  • the photoresist pattern includes a first part and a second part that are connected to each other, the orthographic projection of the first part on the substrate is within the range of the orthographic projection of the second shading pattern on the substrate, and the second part At least a part of the edge of the orthographic projection on the substrate exceeds the edge of the orthographic projection of the portion of the first light shielding pattern that is not covered by the second light shielding pattern on the substrate.
  • the thickness of the first part is less than or equal to the thickness of the second part.
  • forming the barrier layer on the side of the first light-shielding pattern away from the substrate includes: heating the photoresist pattern so that the portion of the photoresist pattern beyond the edge of the second light-shielding pattern collapses to cover the second light-shielding pattern. A part of the light shielding pattern not covered by the second light shielding pattern; the first part of the photoresist pattern is ashed and removed.
  • the preparation method further includes: hardening the remaining photoresist to form a barrier layer.
  • FIG. 1 is a structural diagram of an array substrate according to the related art
  • Fig. 2 is a structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 3 is a structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate according to some embodiments of the present disclosure
  • FIG. 5 is a flowchart of another method for manufacturing an array substrate according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of forming a first light-shielding layer, a second light-shielding layer, and photoresist on a substrate according to some embodiments of the present disclosure
  • FIG. 7 is a structural diagram of forming a photoresist pattern through a halftone mask on the basis of FIG. 6 according to some embodiments of the present disclosure
  • FIG. 8 is a diagram of etching the first light-shielding layer and the second light-shielding layer under the mask of the photoresist pattern on the basis of some embodiments of the present disclosure to form the first light-shielding pattern and the second light-shielding pattern. Structure diagram
  • FIG. 9 shows heating of the photoresist pattern on the basis of FIG. 8 according to some embodiments of the present disclosure so that the portion of the photoresist pattern that extends beyond the edge of the second light shielding pattern collapses, covering the first light shielding pattern but not the second light shielding pattern Structure diagram of the covered part;
  • FIG. 10 is a structural diagram of performing ashing treatment on the semi-retained portion of the photoresist on the basis of FIG. 9 and hardening the remaining photoresist to form a barrier layer according to some embodiments of the present disclosure
  • FIG. 11 is a structural diagram of forming a buffer layer and an active layer on the basis of FIG. 10 according to some embodiments of the present disclosure
  • FIG. 12 is a structural diagram of forming a gate insulating layer, a gate electrode, and an interlayer insulating layer on the basis of FIG. 11 according to some embodiments of the present disclosure
  • FIG. 13 is a structural diagram of forming a source and drain pattern and a passivation layer on the basis of FIG. 12 according to some embodiments of the present disclosure
  • FIG. 14 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • top-gate TFT Thin Film Transistor
  • OLED panels such as large-size OLED panels such as TVs and advertising screens
  • top-gate TFT Thin Film Transistor
  • the OLED panel 00 includes a substrate 01 and a top-gate TFT 03 provided on the substrate 01.
  • a top-gate TFT refers to a TFT whose gate, source and drain are located on the same side of its active layer, such as the gate 031 and source 032 of the top gate TFT 03 in Figure 1 and the drain 033 They are all located on the side of the active layer 034 away from the substrate 01.
  • the OLED panel 00 in the related art further includes a light-shielding layer 02 disposed between the substrate 01 and the active layer 034.
  • the light-shielding layer 02 can shield the active layer 034 from light to prevent active Layer 034 is illuminated by light.
  • the light-shielding layer 02 is made of metal aluminum material, which will cause abnormalities and form bumps under heating and other conditions (for example, in subsequent film etching and annealing processes, metal aluminum will occur due to heating in these processes. Electromigration to form bumps), it is easy to pierce the active layer 034 in the top-gate TFT 03, and a short-circuit phenomenon may occur, which is not conducive to improving the yield.
  • the array substrate 10 includes a substrate 1, a first light-shielding pattern 21 provided on the side of the substrate 1, and a barrier layer 3 provided on the side of the first light-shielding pattern 21 away from the substrate 1.
  • the barrier layer 3 covers at least a part of the first light shielding pattern 21.
  • the barrier layer 3 can be used to A part of the light shielding pattern 21 that may produce protrusions is blocked, so that when the array substrate 10 also includes a top-gate TFT, the active layer of the top-gate TFT is prevented from being pierced by the protrusions, so that the array substrate 10 Short circuit is unlikely to occur in the medium, and the yield of the array substrate 10 is improved.
  • the material of the first light shielding pattern 21 includes at least one of aluminum or aluminum neodymium alloy.
  • the material of the first light shielding pattern 21 may be aluminum, or aluminum neodymium alloy, etc., or the first The material of the light shielding pattern 21 may also include aluminum and aluminum neodymium alloys and the like.
  • the first light-shielding pattern 21 can block light from reaching the active layer of the TFT in the array substrate (the active layer 51 of the top-gate TFT 5 in FIG. 2), thereby preventing the threshold voltage of the TFT from drifting. Improve the working stability of TFT.
  • selecting at least one material of aluminum or aluminum neodymium alloy to make the first light-shielding pattern 21 is also conducive to reducing the manufacturing cost of the array substrate 10, and the economy is high.
  • the planar shape of the first shading pattern 21 (that is, the shape of the orthographic projection of the first shading pattern 21 on the substrate 1) is not limited in the embodiments of the present disclosure, as long as it satisfies the first shading pattern 21 It suffices that light is blocked from being directed to the active layer 51.
  • the planar shape of the first light shielding pattern 21 may be a strip shape or other irregular shapes.
  • the first light shielding pattern 21 is configured such that the orthographic projection of the active layer 51 on the substrate 1 falls within the range of the orthographic projection of the first light shielding pattern 21 on the substrate 1.
  • the barrier layer 3 there are many ways to arrange the barrier layer 3, in some examples, as shown in FIG. 2, the barrier layer 3 completely covers the first light shielding pattern 21, and the barrier layer 3 can block any of the first light shielding patterns 21.
  • the protrusions generated at the positions can prevent the protrusions generated at any position of the first light shielding pattern 21 from piercing the active layer 51.
  • the barrier layer 3 only covers a part of the first light shielding pattern 21.
  • the barrier layer 3 may only cover the edge portion of the first light shielding pattern 21.
  • the array substrate 10 further includes a second light-shielding pattern 22 disposed on a side of the first light-shielding pattern 21 away from the substrate 1, and the second light-shielding pattern 21
  • the pattern 22 covers a portion of the first light shielding pattern 21, and the barrier layer 3 covers at least a portion of the first light shielding pattern 21 that is not covered by the second light shielding pattern 22.
  • the second light shielding pattern 22 covers the middle part of the first light shielding pattern 21, and the barrier layer 3 covers at least the edge part of the first light shielding pattern 21 except the middle part.
  • the second light-shielding pattern 22 and the blocking layer 3 can jointly block the positions on the first light-shielding pattern 21 where protrusions may occur, so as to prevent the first light-shielding pattern 21 from piercing the active
  • the layer 51 prevents short circuits in the array substrate 10 and improves the yield of the array substrate 10.
  • the material of the second light-shielding pattern 22 includes at least one of molybdenum, molybdenum-tungsten alloy, or molybdenum-niobium alloy, and the second light-shielding pattern 22 may serve as an electromigration blocking layer of the first light-shielding pattern 21, such as the
  • the array substrate 10 adopts an aluminum/molybdenum (Al/Mo, Mo can be used as an electromigration barrier layer of Al) structure, that is, the material of the first light shielding pattern 21 is aluminum, and the material of the second light shielding pattern 22 is molybdenum.
  • the thickness of the first shading pattern 21 is in the range of 0.1 ⁇ m to 0.15 ⁇ m
  • the thickness of the second shading pattern 22 is in the range of 0.05 ⁇ m to 0.08 ⁇ m.
  • At least a part of the edge of the orthographic projection of the barrier layer 3 on the substrate 1 exceeds the part of the first light shielding pattern 21 that is not covered by the second light shielding pattern 22 on the substrate 1.
  • the distance of the edge of the orthographic projection is less than or equal to 2 ⁇ m, for example, 1 ⁇ m to 2 ⁇ m.
  • the part of the first light-shielding pattern 21 prone to abnormal protrusions can be completely blocked by the blocking layer 3, which can better prevent the active layer of the TFT from being pierced due to protrusions on the first light-shielding pattern 21.
  • the material of the barrier layer 3 includes hardened photoresist.
  • the hardened photoresist may be a product obtained by baking and carbonizing the photoresist.
  • the photoresist can be directly processed to form the barrier layer 3. In this way, not only can the barrier layer 3 be used to shield the second A light-shielding pattern 21 is prone to abnormally protruding parts, and has high economic efficiency.
  • the material of the barrier layer 3 is not limited to the hardened photoresist, and any material that can block the abnormal protrusions of the first light shielding pattern 21 can be used to make the barrier layer 3, for example, the barrier layer 3.
  • the material of may also include at least one of molybdenum, molybdenum-tungsten alloy, or molybdenum-niobium alloy.
  • the size of the barrier layer 3 in the direction perpendicular to the substrate is greater than or equal to 0.1 ⁇ m, so that the barrier layer 3 can effectively block the protrusions formed on the first light shielding pattern 21, thereby preventing The source layer is pierced.
  • the array substrate 10 further includes a thin film transistor 5 (that is, a top-gate TFT) disposed on the side of the barrier layer 3 and the second light shielding pattern 22 away from the substrate 1.
  • the thin film transistor 5 includes a gate 52 and an active layer 51, and the gate 52 is located on the side of the active layer 51 away from the substrate 1.
  • the orthographic projection of the active layer 51 on the substrate 1 is within the range of the orthographic projection of the first light shielding pattern 21 on the substrate 1.
  • the orthographic projection of the barrier layer 3 on the substrate 1 and the orthographic projection of the active layer 51 on the substrate 1 at least partially overlap.
  • the first light-shielding pattern 21 and the second light-shielding pattern 22 can not only block the light from being directed to the active layer 51, prevent negative drift of the threshold voltage of the thin film transistor, and improve the stability of the thin film transistor.
  • the second light shielding pattern 22 and the blocking layer 3 can also be used to shield the part of the first light shielding pattern 21 that is prone to abnormal protrusions, so as to prevent the active layer 51 from being pierced by the protrusions.
  • the array substrate 10 further includes a buffer layer 4 disposed between the barrier layer, the second light shielding pattern, and the active layer.
  • the active layer 51 of the thin film transistor 5 can be made flat, and at the same time, the active layer 51 can be better prevented from being pierced by the protrusions formed on the first light shielding pattern, thereby improving reliability.
  • Some embodiments of the present disclosure provide a manufacturing method of an array substrate. Referring to FIG. 3 and FIG. 4, the manufacturing method includes the following steps:
  • a substrate 1 is provided.
  • a first light shielding pattern 21 is formed on one side of the substrate 1.
  • a barrier layer 3 is formed on a side of the first light shielding pattern 21 away from the substrate 1, and the barrier layer 3 covers at least a part of the first light shielding pattern 21.
  • the barrier layer 3 is formed on the side of the first light shielding pattern 21 away from the substrate 1, and the barrier layer 3 covers at least a part of the first light shielding pattern 21. Therefore, the barrier layer 3 can be used to A part of the light shielding pattern 21 that may have abnormal protrusions is blocked, thereby preventing short circuits from occurring and improving the yield.
  • the preparation method includes:
  • a second shading pattern 22 is formed on the side of the first shading pattern 21 away from the substrate 1.
  • the second shading pattern 22 is formed on the side of the first shading pattern 21 away from the substrate 1, and
  • the second light shielding pattern 22 covers a part of the first light shielding pattern 21, and the barrier layer 3 covers at least an area of the first light shielding pattern 21 not covered by the second light shielding pattern 22.
  • the second light shielding pattern 22 covers the middle part of the first light shielding pattern 21, and the barrier layer 3 covers at least the edge part of the first light shielding pattern 21 except the middle part.
  • the second light-shielding pattern 22 and the blocking layer 3 can jointly block the position where protrusions may occur on the first light-shielding pattern 21, so as to prevent the active layer from being pierced due to the protrusions on the first light-shielding pattern 21. This prevents short circuits in the array substrate 10 and improves the yield of the array substrate 10.
  • the foregoing S2 to S4 include:
  • a first light-shielding layer 100 and a second light-shielding layer 200 are sequentially formed on one side of the substrate 1.
  • the etching selection ratio of the second light-shielding layer 200 is greater than the etching selection ratio of the first light-shielding layer 100, such as the first
  • the material of the light shielding layer 100 may be aluminum, and the material of the second light shielding layer 200 may be molybdenum.
  • the thickness of the first light shielding layer 100 may be 0.1 ⁇ m to 0.15 ⁇ m
  • the thickness of the second light shielding layer 200 may be 0.05 ⁇ m to 0.08 ⁇ m.
  • the first light-shielding pattern 21, the second light-shielding pattern 22, and the photoresist pattern 301 covering the first light-shielding pattern 21 and the second light-shielding pattern 22 are formed by one patterning process.
  • the edge of the orthographic projection of the photoresist pattern 301 on the substrate 1 exceeds the edge of the orthographic projection of the first light shielding pattern 21 on the substrate 1.
  • the photoresist pattern 301 is on the substrate 1.
  • the distance between the edge of the orthographic projection of the first light shielding pattern 21 and the edge of the orthographic projection of the first light shielding pattern 21 on the substrate 1 is less than or equal to 2 ⁇ m, for example, the distance is 1 ⁇ m to 2 ⁇ m, so that after the shielding layer 3 is formed, the barrier layer 3
  • the distance of at least part of the edge of the orthographic projection on the substrate 1 beyond the edge of the orthographic projection of the portion of the first light shielding pattern 21 not covered by the second light shielding pattern 22 on the substrate 1 is less than or equal to 2 ⁇ m.
  • the photoresist pattern 301 may be formed on the first light-shielding pattern 21 and the second light-shielding pattern 22 to be formed through processes such as exposure and development, so that the photoresist pattern 301 is orthographically projected on the substrate 1
  • the distance between the edge of the first light-shielding pattern 21 and the orthographic projection of the first light-shielding pattern 21 on the substrate 1 is less than or equal to 2 ⁇ m, for example, the distance is 1 ⁇ m to 2 ⁇ m.
  • the first light-shielding layer 100 and The second light-shielding layer 200 is etched.
  • nitric acid, phosphoric acid or acetic acid can be used for etching.
  • the obtained second The light shielding pattern 22 is indented relative to the first light shielding pattern 21, that is, as shown in FIG. 8, the second light shielding pattern 22 covers the middle of the first light shielding pattern 21.
  • the photoresist pattern 103 can be prepared by using a common mask, or can be prepared by using a halftone mask.
  • the thickness of the photoresist pattern at different positions is the same, and the finally formed barrier layer 3 can completely cover the first shading pattern 21 and the second shading pattern. Pattern 22.
  • the thickness of the photoresist pattern 103 located in different regions can be controlled, so as to reduce the coverage on the first light shielding pattern 21 as much as possible.
  • the photoresist pattern can prevent the hardened photoresist from containing a large amount of hydrogen to affect the channel layer of the TFT and cause the threshold voltage to drift.
  • the photoresist pattern 103 includes a first portion A 1 and a second portion A 2 connected to each other.
  • the orthographic projection of the first portion A 1 on the substrate 1 is located on the second light-shielding pattern 22 on the substrate 1 Within the range of the orthographic projection on the substrate 1, the orthographic projection of the portion of the first shading pattern 21 that is not covered by the second shading pattern 22 on the substrate 1 is within the scope of the orthographic projection of the second portion A 2 on the substrate 1. .
  • the first portion A 1 in the orthogonal projection on the substrate 1 in the range of 22 orthogonal projection on the substrate 1, a second light-shielding pattern, the second portion A 2 has two, two a 2 second portions located on opposite sides of a first part a 1 and respectively connected to the first portion a 1.
  • first portion of the thickness D A 1 1 is equal to or less than the second portion of the thickness D A 2 2.
  • a halftone mask 400 may be used to expose and develop the photoresist 300 to form the photoresist pattern 301 described above.
  • the first portion A 1 of the photoresist pattern 301 is a semi-reserved portion of photoresist
  • the second portion A 2 of the photoresist pattern 301 is a completely reserved portion of photoresist.
  • the rest of the photoresist part is completely removed, thereby forming a photoresist fully retained part (that is, the second part A 2 ) and the photoresist semi-retained part (that is, the first part A 1 ) as shown in FIG. 8 Photoresist pattern 301.
  • the first portion of the thickness D A 1 1 is 1.2 ⁇ m ⁇ 1.3 ⁇ m
  • a thickness of the second portion A 2 D 2 was 1 ⁇ m. In this way, the protrusions generated on the first folded Anu pattern 21 can be effectively blocked after the barrier layer is formed on the photoresist pattern 301.
  • the halftone mask 400 includes a completely transparent portion 403, a completely opaque portion 402, and a semi-transparent portion 401. If the photoresist 300 is a positive photoresist, as shown in FIG. 7, the completely transparent portion 403 of the halftone mask 400 corresponds to the completely removed portion of the photoresist, and the completely opaque portion 402 is completely The remaining portion corresponds to the second portion A 2 , and the semi-transmissive portion 401 corresponds to the semi-retained photoresist portion (ie, the first portion A 1 ).
  • the completely transparent part of the halftone mask 400 corresponds to the completely reserved part of the photoresist (that is, the second part A 2 ), and the completely opaque part and the photoresist are completely
  • the removed part corresponds to the semi-transparent part and the photoresist semi-retained part (ie, the first part A 1 ).
  • the above S2 to S4 further include:
  • the heating temperature is 130°C to 180°C, and the time is 2min to 4min. Since the photoresist pattern 301 is not baked during the masking process, the photoresist pattern 301 contains more solvent. At this time, the photoresist pattern 301 is covered on the first light shielding pattern 21 and the second light shielding pattern 22. The photoresist pattern 301 is heated to volatilize the solvent in the photoresist pattern 301, so that the portion of the photoresist pattern 301 beyond the edge of the second shading pattern 22 can be cured and collapsed to the first shading pattern under the action of heating and baking. The portion 21 that is not covered by the second light-shielding pattern 22, that is, after the second light-shielding pattern 22 is retracted, the exposed first light-shielding pattern 21 is covered by the photoresist pattern 301.
  • the photoresist patterns covered on the first light-shielding pattern 21 can be reduced as much as possible, so as to prevent the hardened photoresist from containing a large amount of hydrogen to affect the channel layer of the TFT and cause threshold voltage drift.
  • the preparation method may further include:
  • an ion implantation method may be used to harden the remaining photoresist.
  • phosphorane or borane can be used for ion implantation, and the photoresist can be ion doped to achieve hardening treatment.
  • the first light-shielding pattern 21 and the second light-shielding pattern 22 can be formed through a single patterning process, and the barrier layer 3 can be prepared by the photoresist 300 used in this patterning process.
  • the preparation of the barrier layer 3 is completed without increasing the number of masks.
  • the edge of the orthographic projection of the second portion A 2 of the photoresist pattern 302 on the substrate 1 exceeds the first light-shielding pattern, the second light-shielding pattern is not
  • the edge of the orthographic projection of the part covered by 22 on the substrate 1 (for example, exceeding 1 ⁇ m to 2 ⁇ m) can make the part of the first light shielding pattern 21 not covered by the second light shielding pattern 22 completely covered by the denatured photoresist , Which can improve process reliability.
  • the halftone mask 400 is used to mask the photoresist 300, and finally the half-retained part of the photoresist covering the second area is ashed and removed, which can minimize the barrier layer 3 in the second area.
  • a covering area on the light-shielding pattern 21 can prevent the hardened photoresist from containing a large amount of hydrogen which will affect the channel layer of the TFT and cause the threshold voltage to shift.
  • the preparation method may further include:
  • the buffer layer 4 is continuously deposited on the substrate 1 on which the barrier layer 3 is prepared.
  • the material of the buffer layer 4 may be silicon oxide, and the thickness may be 0.3 ⁇ m to 0.5 ⁇ m.
  • a semiconductor layer is continuously deposited on the buffer layer 4, and the active layer 51 is formed through a patterning process.
  • the material of the semiconductor layer may be indium tin oxide, and the thickness may be 0.05 ⁇ m to 0.1 ⁇ m. Due to shading requirements, the edge of the orthographic projection of the shading structure (such as the first shading pattern 21 and/or the second shading pattern 22) on the substrate 1 exceeds the edge of the orthographic projection of the active layer 51 on the substrate by 2 ⁇ m ⁇ 4 ⁇ m.
  • a gate insulating layer 53 is continuously deposited on the substrate 1 on which the active layer 51 is formed.
  • the gate insulating layer 53 may be a silicon oxide film, and the thickness may be 0.1 ⁇ m to 0.2 ⁇ m.
  • a gate metal layer is deposited on the gate insulating layer 53, the material of the gate metal layer may be copper, and the thickness may be 0.5 ⁇ m ⁇ 0.7 ⁇ m.
  • the gate metal layer is formed into the gate 52 by a patterning process. For example, the gate metal layer can be wet-etched with a hydrogen peroxide solution under the action of a photoresist mask to form the gate 52. After the wet etching is completed, the gate 52 is not removed.
  • the photoresist is continued to dry the gate insulating layer 53 under the action of the photoresist mask.
  • a mixed gas of CF 4 and oxygen can be used to dry the gate insulating layer 53 to obtain the result shown in FIG. 12
  • the gate electrode 52 and the gate insulating layer 53 are then removed by a wet method.
  • an interlayer insulating layer 54 is deposited on the substrate 1 on which the gate 53 is formed.
  • the material may be silicon oxide, and the thickness may be 0.3 ⁇ m to 0.5 ⁇ m.
  • a via hole for connecting the source electrode, the drain electrode and the active layer 51 is formed in the layer 54.
  • the via hole may be formed by a dry etching process.
  • the via 541 shown in FIG. 12 is obtained.
  • the metal layer can be a metal such as copper or aluminum, with a thickness of 0.5 ⁇ m to 0.7 ⁇ m, and a patterning process is used to form source and drain patterns (for example, including source 551 and drain 552).
  • the source electrode 551 and the drain electrode 552 in the source-drain pattern are respectively electrically connected to the active layer 51 through a via 541 formed in the interlayer insulating layer 54 to complete the preparation of the top-gate TFT5.
  • a passivation layer 6 may be deposited.
  • the passivation layer 6 may be made of silicon oxide and may have a thickness of 0.3-0.5 microns.
  • the display device 20 includes the display panel 201 as described above.
  • the display panel 201 includes the array substrate 10 provided in any of the above embodiments. Therefore, the beneficial effects of the display device 20 are the same as the beneficial effects of the array substrate 10 provided by the foregoing embodiment, and will not be repeated here.
  • the display device provided in the foregoing embodiment may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital camera, a navigator, and the like.

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Abstract

一种阵列基板，包括衬底；设置在衬底一侧的第一遮光图案；以及，设置在第一遮光图案的远离衬底一侧的阻挡层，该阻挡层至少覆盖部分第一遮光图案。

Description

阵列基板及其制备方法、显示面板和显示装置
本申请要求于2019年03月07日提交的、申请号为201910173499.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及一种阵列基板及其制备方法、显示面板和显示装置。
背景技术
随着显示技术的不断发展，OLED(Organic Light Emitting Diode，有机发光二极管)面板因具有自发光、高对比度等优点，被广泛应用于显示装置中。
发明内容
一方面，提供一种阵列基板。所述阵列基板包括衬底；设置在衬底一侧的第一遮光图案；以及，设置在第一遮光图案的远离衬底一侧的阻挡层，该阻挡层至少覆盖部分第一遮光图案。
在一些实施例中，所述阵列基板还包括：设置在第一遮光图案的远离衬底一侧的第二遮光图案，第二遮光图案覆盖部分第一遮光图案；该阻挡层至少覆盖第一遮光图案未被第二遮光图案覆盖的部分。
在一些实施例中，该阻挡层在衬底上的正投影的至少部分边缘超出第一遮光图案未被第二遮光图案覆盖的部分在衬底上的正投影的边缘的距离小于或等于2μm。
在一些实施例中，该阻挡层的材料包括硬化光刻胶。
在一些实施例中，该阻挡层在垂直于衬底的方向上的尺寸大于或等于0.1μm。
在一些实施例中，第一遮光图案的材料包括铝或铝钕合金中的至少一种；第二遮光图案的材料包括钼、钼钨合金或钼铌合金中的至少一种。
在一些实施例中，第一遮光图案的厚度范围为0.1μm～0.15μm，第二遮光图案的厚度范围为0.05μm～0.08μm。
在一些实施例中，所述阵列基板还包括：设置在阻挡层及第二遮光图案的远离衬底一侧的薄膜晶体管，薄膜晶体管包括栅极和有源层，栅极位于有源层的远离衬底一侧。有源层在衬底上的正投影位于第一遮光图案在衬底上的正投影的范围之内。阻挡层在衬底上的正投影与有源层在衬底上的正投影至少部分重叠。
在一些实施例中，所述阵列基板还包括：缓冲层，设置于阻挡层、第 二遮光图案及有源层三者之间。
另一方面，提供一种显示面板。所述显示面板包括：如上述任一实施例所述的阵列基板。
再一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
又一方面，提供一种阵列基板的制备方法。所述制备方法包括：提供衬底；在衬底的一侧形成第一遮光图案；在第一遮光图案的远离衬底一侧形成阻挡层，阻挡层至少覆盖部分第一遮光图案。
在一些实施例中，所述制备方法还包括：在第一遮光图案的远离衬底一侧形成第二遮光图案，第二遮光图案覆盖部分第一遮光图案；该阻挡层至少覆盖第一遮光图案的未被第二遮光图案覆盖的部分。
在一些实施例中，在衬底的一侧形成第一遮光图案，以及在第一遮光图案的远离衬底的一侧形成第二遮光图案，包括：在衬底的一侧依次形成第一遮光层和第二遮光层，第二遮光层的刻蚀选择比大于第一遮光层的刻蚀选择比；在第二遮光层的远离衬底一侧涂覆光刻胶；通过一次构图工艺形成第一遮光图案、第二遮光图案及覆盖第一遮光图案和第二遮光图案的光刻胶图案，光刻胶图案在衬底上的正投影的边缘超出第一遮光图案在衬底上的正投影的边缘。
在一些实施例中，光刻胶图案包括彼此相连的第一部分和第二部分，第一部分在衬底上的正投影位于第二遮光图案在衬底上的正投影的范围之内，第二部分在衬底上的正投影的至少部分边缘超出第一遮光图案未被第二遮光图案覆盖的部分在衬底上的正投影的边缘。其中，第一部分的厚度小于或等于第二部分的厚度。
在一些实施例中，在第一遮光图案的远离衬底一侧形成阻挡层，包括：对光刻胶图案进行加热，使得光刻胶图案超出第二遮光图案的边缘的部分坍塌，以覆盖第一遮光图案未被第二遮光图案覆盖的部分；对光刻胶图案的第一部分进行灰化去除。
在一些实施例中，在对光刻胶图案的第一部分进行灰化去除之后，制备方法还包括：对残留的光刻胶进行硬化处理，以形成阻挡层。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还 可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术的一种阵列基板的结构图；
图2为根据本公开一些实施例的一种阵列基板的结构图；
图3为根据本公开一些实施例的另一种阵列基板的结构图；
图4为根据本公开一些实施例的一种阵列基板的制备方法的流程图；
图5为根据本公开一些实施例的另一种阵列基板的制备方法的流程图；
图6为根据本公开一些实施例的在衬底上形成第一遮光层、第二遮光层和光刻胶的结构图；
图7为根据本公开一些实施例的在图6的基础上通过半色调掩膜板形成光刻胶图案的结构图；
图8为根据本公开一些实施例的在图7的基础上在光刻胶图案的掩膜下对第一遮光层和第二遮光层进行刻蚀，形成第一遮光图案和第二遮光图案的结构图；
图9为根据本公开一些实施例的在图8的基础上对光刻胶图案进行加热使得光刻胶图案超出第二遮光图案的边缘的部分坍塌，覆盖第一遮光图案未被第二遮光图案覆盖的部分的结构图；
图10为根据本公开一些实施例的在图9的基础上对光刻胶半保留部分进行灰化处理，并对残留的光刻胶进行硬化处理形成阻挡层的结构图；
图11为根据本公开一些实施例的在图10的基础上形成缓冲层以及有源层的结构图；
图12为根据本公开一些实施例的在图11的基础上形成栅绝缘层、栅极和层间绝缘层的结构图；
图13为根据本公开一些实施例的在图12的基础上形成源漏极图案和钝化层的结构图；
图14为根据本公开一些实施例的一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
在本公开实施例的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件 必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
OLED面板(比如电视、广告屏等大尺寸OLED面板)中，顶栅型TFT(Thin Film Transistor，薄膜晶体管)相比底栅型TFT具有更高的开态电流、更高的开口率和更好的稳定性。因此，OLED面板中通常会设置顶栅型TFT。
相关技术中，如图1所示，OLED面板00包括衬底01和设置在衬底01上的顶栅型TFT 03。其中，顶栅型TFT是指其栅极与源极、漏极位于其有源层的同一侧的TFT，比如图1中的顶栅型TFT 03的栅极031与源极032、漏极033均位于其有源层034的远离衬底01的一侧。
顶栅型TFT在使用时，如果有源层034受到光线照射会造成阈值电压负漂，从而会影响该顶栅型TFT的工作稳定性。因此，如图1所示，相关技术中的OLED面板00还包括设置在衬底01与有源层034之间的遮光层02，通过遮光层02可以对有源层034进行遮光，防止有源层034受到光线照射。
然而，该遮光层02由金属铝材料制成，在加热等条件下会发生异常、形成凸起(如在后续的薄膜刻蚀、退火等工艺中，金属铝由于这些工艺中的加热作用会发生电迁移，从而形成凸起)，容易刺穿顶栅型TFT 03中的有源层034，从而会发生短路现象，不利于提高成品良率。
基于此，本公开的一些实施例提供一种阵列基板10。参见图2和图3，该阵列基板10包括衬底1、设置在衬底1一侧的第一遮光图案21以及设置在该第一遮光图案21的远离衬底1一侧的阻挡层3，该阻挡层3至少覆盖部分该第一遮光图案21。此时该阻挡层3在衬底1上的正投影与该第一遮光图案21在衬底1上的正投影至少部分重叠。
本实施例中，通过在该第一遮光图案21的远离衬底1的一侧设置阻挡层3，并使该阻挡层3至少覆盖部分该第一遮光图案21，能够利用阻挡层3对该第一遮光图案21中可能会产生凸起的部分进行阻挡，进而能够在阵列基板10还包括顶栅型TFT的情况下，防止顶栅型TFT的有源层被凸起刺穿，使阵列基板10中不易发生短路，提高了阵列基板10的成品良率。
示例性的，该第一遮光图案21的材料包括铝或铝钕合金中的至少一种，例如该第一遮光图案21的材料可以为铝，也可以为铝钕合金等， 或者，该第一遮光图案21的材料还可以同时包括铝和铝钕合金等。本示例中，通过第一遮光图案21可以阻挡光线射向阵列基板中TFT的有源层(如图2中顶栅型TFT 5的有源层51)，从而能够防止TFT的阈值电压发生漂移，提高了TFT的工作稳定性。并且，选用铝或铝钕合金中的至少一种材料制作第一遮光图案21，还有利于降低阵列基板10的制作成本，经济性较高。
需要说明的是，本公开各实施例中对第一遮光图案21的平面形状(也即第一遮光图案21在衬底1上的正投影的形状)不做限定，只要满足第一遮光图案21可以阻挡光线射向有源层51即可，例如，第一遮光图案21的平面形状可以呈条形，也可以呈其它不规则形状。又例如，参见图3，第一遮光图案21被配置为，使有源层51在衬底1上的正投影落入该第一遮光图案21在衬底1上的正投影的范围之内。
上述阻挡层3的设置方式有多种，在一些示例中，如图2所示，该阻挡层3完全覆盖该第一遮光图案21，利用该阻挡层3可以阻挡该第一遮光图案21的任意位置产生的凸起，从而能够防止该第一遮光图案21的任意位置产生的凸起刺穿有源层51。而在另一些示例中，该阻挡层3仅覆盖部分第一遮光图案21。例如，如图3所示，该阻挡层3可以仅覆盖第一遮光图案21的边缘部分。
在另一些实施例中，参见图3，该阵列基板10还包括第二遮光图案22，该第二遮光图案22设置在该第一遮光图案21远离衬底1的一侧，且该第二遮光图案22覆盖部分该第一遮光图案21，该阻挡层3至少覆盖该第一遮光图案21未被第二遮光图案22覆盖的部分。例如，如图3所示，该第二遮光图案22覆盖该第一遮光图案21的中间部分，该阻挡层3至少覆盖该第一遮光图案21的除中间部分以外的边缘部分。
本实施例中，第二遮光图案22和阻挡层3可以共同对第一遮光图案21上可能产生凸起的位置进行阻挡，从而能够防止因第一遮光图案21上产生凸起而刺穿有源层51，使阵列基板10中不易发生短路，提高了阵列基板10的成品良率。
示例性的，该第二遮光图案22的材料包括钼、钼钨合金或钼铌合金中的至少一种，该第二遮光图案22可以作为该第一遮光图案21的电迁移阻挡层，例如该阵列基板10中采用铝/钼(Al/Mo，Mo可以作为Al的电迁移阻挡层)结构，即第一遮光图案21的材料为铝，第二遮光 图案22的材料为钼。
示例性的，继续参见图2，该第一遮光图案21的厚度范围为0.1μm～0.15μm，该第二遮光图案22的厚度范围为0.05μm～0.08μm。这样可以在第一遮光图案21上产生凸起时，利用第二遮光图案22有效的阻挡该凸起刺穿TFT的有源层。
示例性的，如图2所示，该阻挡层3在衬底1上的正投影的至少部分边缘超出该第一遮光图案21未被该第二遮光图案22覆盖的部分在衬底1上的正投影的边缘的距离小于或等于2μm，例如1μm～2μm。这样可以使该第一遮光图案21容易发生异常突起的部分被阻挡层3完全遮挡，能够更好的防止因第一遮光图案21上产生凸起而刺穿TFT的有源层。
在一些实施例中，该阻挡层3的材料包括硬化光刻胶。需要说明的是，硬化光刻胶可以为对光刻胶进行烘烤碳化后所获得的产物。本实施例中，无需去除制作第一遮光图案和第二遮光图案所用到的光刻胶，直接对该光刻胶进行处理即可形成该阻挡层3，这样，不仅可以利用阻挡层3遮挡第一遮光图案21容易发生异常突起的部分，而且具有较高的经济性。
需要说明的是，上述阻挡层3的材料不局限于硬化光刻胶，任何能够对第一遮光图案21发生异常凸起进行阻挡的材料都可以用于制作阻挡层3，例如，该阻挡层3的材料也可以包括钼、钼钨合金或钼铌合金等中的至少一种。
示例性的，该阻挡层3在垂直于所述衬底的方向上的尺寸大于或等于0.1μm，这样可以通过该阻挡层3有效的阻挡第一遮光图案21上形成的凸起，从而防止有源层被刺穿。
在一些实施例中，如图3所示，该阵列基板10还包括设置在阻挡层3及所述第二遮光图案22的远离衬底1一侧的薄膜晶体管5(即顶栅型TFT)，所述薄膜晶体管5包括栅极52和有源层51，栅极52位于有源层51的远离衬底1一侧。该有源层51在衬底1上的正投影位于第一遮光图案21在衬底1上的正投影的范围之内。该阻挡层3在衬底1上的正投影与该有源层51在衬底1上的正投影至少部分重叠。这样不仅可以通过第一遮光图案21及第二遮光图案22阻挡光线射向有源层51，防止薄膜晶体管阈值电压负漂，提高薄膜晶体管的稳定性。而且还可以利用第二遮光图案22及阻 挡层3遮挡第一遮光图案21容易发生异常凸起的部分，以防止有源层51被凸起刺穿。
在一些实施例中，如图2和图3所示，该阵列基板10还包括设置于所述阻挡层、所述第二遮光图案及所述有源层三者之间的缓冲层4。这样可以使薄膜晶体管5的有源层51平整，同时更好的避免有源层51被第一遮光图案上形成的凸起刺穿，提高了可靠性。
本公开的一些实施例提供一种阵列基板的制备方法，参见图3和图4，该制备方法包括以下步骤：
S1、提供衬底1。
S2、在衬底1的一侧形成第一遮光图案21。
S4、在该第一遮光图案21的远离衬底1的一侧形成阻挡层3，该阻挡层3至少覆盖部分该第一遮光图案21。
本实施例中，通过在该第一遮光图案21远离衬底1的一侧形成阻挡层3，该阻挡层3至少覆盖部分该第一遮光图案21，因此，能够利用该阻挡层3对该第一遮光图案21中可能发生异常突起的部分进行阻挡，从而能够防止发生短路，提高成品良率。
在一些实施例中，如图4所示，该制备方法包括：
S3，在该第一遮光图案21的远离衬底1一侧形成第二遮光图案22，该第二遮光图案22形成在所述第一遮光图案21远离所述衬底1的一侧，且该第二遮光图案22覆盖部分第一遮光图案21，该阻挡层3至少覆盖该第一遮光图案21未被该第二遮光图案22覆盖的区域。例如，如图3所示，该第二遮光图案22覆盖该第一遮光图案21的中间部分，该阻挡层3至少覆盖该第一遮光图案21的除中间部分以外的边缘部分。此时，第二遮光图案22和阻挡层3可以共同对第一遮光图案21上可能产生凸起的位置进行阻挡，从而能够防止因第一遮光图案21上产生凸起而刺穿有源层，使阵列基板10中不易发生短路，提高了阵列基板10的成品良率。
在一些示例中，参见图5和图6，上述S2～S4包括：
S11、在衬底1的一侧依次形成第一遮光层100和第二遮光层200，该第二遮光层200的刻蚀选择比大于第一遮光层100的刻蚀选择比，如该第一遮光层100的材料可以为铝，第二遮光层200的材料可以为钼。 其中，示例性的，第一遮光层100的厚度可以为0.1μm～0.15μm，第二遮光层200的厚度可以为0.05μm～0.08μm。
S12、在第二遮光层200的远离衬底一侧涂覆光刻胶300。
S13、参见图7和图8，通过一次构图工艺形成第一遮光图案21、第二遮光图案22和覆盖该第一遮光图案21和第二遮光图案22的光刻胶图案301。示例性的，该光刻胶图案301在衬底1上的正投影的边缘超出该第一遮光图案21在衬底1上的正投影的边缘，例如该光刻胶图案301在衬底1上的正投影的边缘超出该第一遮光图案21在衬底1上的正投影的边缘的距离小于或等于2μm，例如该距离为1μm～2μm，这样能够在形成遮挡层3后，使阻挡层3在衬底1上的正投影的至少部分边缘超出第一遮光图案21未被第二遮光图案22覆盖的部分在衬底1上的正投影的边缘的距离小于或等于2μm。
示例性的，可以通过曝光、显影等工艺在待形成的第一遮光图案21和第二遮光图案22的上方形成光刻胶图案301，使得该光刻胶图案301在衬底1上的正投影的边缘超出该第一遮光图案21在衬底1上的正投影的边缘的距离为小于或等于2μm，例如该距离为1μm～2μm，接着，通过控制刻蚀时间，对第一遮光层100和第二遮光层200进行刻蚀，如可以采用硝酸、磷酸或醋酸进行刻蚀，由于第二遮光层200的刻蚀选择比大于第一遮光层的刻蚀选择比，因此，所获得的第二遮光图案22相对于第一遮光图案21向内缩进，即如图8所示，第二遮光图案22覆盖在该第一遮光图案21的中部。
其中，该光刻胶图案103可以采用普通掩膜版制备获得，也可以采用半色调掩膜版制备获得。
例如，当该光刻胶图案103采用普通掩膜版制备获得时，该光刻胶图案不同位置处的厚度一致，最终所形成的阻挡层3可以完全覆盖该第一遮光图案21和第二遮光图案22。
又例如，当该光刻胶图案103采用半色调掩膜版制备获得时，能够对位于不同区域的光刻胶图案103的厚度进行控制，从而能够尽可能地减少在第一遮光图案21上覆盖的光刻胶图案，能够避免硬化光刻胶中含有大量氢而对TFT的沟道层产生影响，造成阈值电压漂移。
基于此，示例性的，该光刻胶图案103包括彼此相连的第一部分A 1和第二部分A 2，第一部分A 1在衬底1上的正投影位于第二遮光图案22在衬 底1上的正投影的范围之内，第一遮光图案21未被第二遮光图案22覆盖的部分在衬底1上的正投影位于第二部分A 2在衬底1上的正投影的范围之内。例如，如图8所示，第一部分A 1在衬底1上的正投影位于第二遮光图案22在衬底1上的正投影的范围之内，第二部分A 2有两个，两个第二部分A 2位于第一部分A 1的相对两侧且分别与该第一部分A 1相连。
其中，第一部分A 1的厚度D 1小于或等于第二部分A 2的厚度D 2。示例性的，参见图7和图8，可以采用半色调掩膜版400对该光刻胶300进行曝光、显影形成上述光刻胶图案301。其中，该光刻胶图案301的第一部分A 1为光刻胶半保留部分，该光刻胶图案301的第二部分A 2为光刻胶完全保留部分。除此以外的光刻胶部分被完全去除，从而形成如图8所示的包含光刻胶完全保留部分(即第二部分A 2)和光刻胶半保留部分(即第一部分A 1)的光刻胶图案301。示例性的，如图8所示，该第一部分A 1的厚度D 1为1.2μm～1.3μm，该第二部分A 2厚度D 2为1μm。这样能够在该光刻胶图案301形成阻挡层后可以有效的阻挡第一折股阿奴个图案21上产生的凸起。
需要说明的是，参见图7，半色调掩模板400包括完全透光部分403、完全不透光部分402、以及半透光部分401。若光刻胶300为正性光刻胶，则如图7所示，半色调掩模板400的完全透光部分403与光刻胶完全去除部分对应，完全不透光部分402与光刻胶完全保留部分对应(即第二部分A 2)，半透光部分401与光刻胶半保留部分(即第一部分A 1)对应。若光刻胶300为负性光刻胶，则半色调掩模板400的完全透光部分与光刻胶完全保留部分对应(即第二部分A 2)，完全不透光部分与光刻胶完全去除部分对应，半透光部分与光刻胶半保留部分(即第一部分A 1)对应。
在形成所述第一遮光图案21和第二遮光图案22之后，示例性的，参见图5、图8和图9，上述S2～S4还包括：
S14、对覆盖在第一遮光图案21和第二遮光图案22上方的光刻胶图案301进行加热，使得该光刻胶图案超出该第二遮光图案22的边缘的部分坍塌，以覆盖该第一遮光图案21未被该第二遮光图案22覆盖的部分，形成如图9所示的结构。
其中，示例性的，加热的温度为130℃～180℃，时间为为2min～4min。由于光刻胶图案301在进行掩膜时未发生烘烤，因此，光刻胶 图案301中含有较多的溶剂，此时，通过对覆盖在第一遮光图案21和第二遮光图案22上方的光刻胶图案301进行加热，使光刻胶图案301中的溶剂挥发，能够使光刻胶图案301超出该第二遮光图案22的边缘的部分在加热烘烤作用下硬化坍塌至第一遮光图案21未被第二遮光图案22覆盖的部分，即使得第二遮光图案22缩进后，裸露在外的第一遮光图案21被光刻胶图案301覆盖。
S14、对该光刻胶图案的第一部分进行灰化去除，形成如图10所示的结构。这样可以尽可能地减少在第一遮光图案21上覆盖的光刻胶图案，从而能够避免硬化光刻胶中含有大量氢而对TFT的沟道层产生影响，造成阈值电压漂移。
而后，在对该光刻胶图案对应第二区域的部分进行灰化去除之后，参见图5，该制备方法还可以包括：
S15、对残留的光刻胶进行硬化处理以获得该阻挡层3，也即获得如图10所示的阻挡层3。此处，通过对光刻胶进行硬化处理，能够在后续的气相沉积工艺中减少光刻胶对腔室造成污染。
示例性的，可以采用离子注入法对残留的光刻胶进行硬化处理。如可采用磷烷或者硼烷进行离子注入，对光刻胶进行离子掺杂，以实现硬化处理。
综上所述，在整个制备过程中，通过一次构图工艺即可形成第一遮光图案21和第二遮光图案22，并通过该次构图工艺中采用的光刻胶300制备阻挡层3，能够在不增加掩膜次数的情况下完成阻挡层3的制备，同时，由于光刻胶图案302的第二部分A 2在衬底1上的正投影的边缘超出第一遮光图案未被第二遮光图案22覆盖的部分的在衬底1上的正投影的边缘(例如超出1μm～2μm)，能够使该第一遮光图案21未被该第二遮光图案22覆盖的部分完全被变性的光刻胶覆盖，从而能够提高工艺可靠性。在此基础上，通过采用半色调掩膜板400对光刻胶300进行掩膜，最终将覆盖在第二区域的光刻胶半保留部分灰化去除，能够尽可能减小阻挡层3在第一遮光图案21上的覆盖面积，从而能够避免硬化光刻胶中含有大量氢而对TFT的沟道层产生影响，造成阈值电压漂移。
在一些实施例中，在完成该阻挡层3的制备之后，参见图11，该制备方法还可以包括：
在制备有阻挡层3的衬底1上继续沉积缓冲层4，该缓冲层4的材料可以为氧化硅，厚度可以为0.3μm～0.5μm。
之后，继续参见图11，继续在缓冲层4上沉积一层半导体层，并通过构图工艺形成有源层51，该半导体层的材料可以为氧化铟锡，厚度可以为0.05μm～0.1μm。由于遮光需求，该遮光结构(如第一遮光图案21和/或第二遮光图案22)在衬底1上的正投影的边缘超出该有源层51在衬底上的正投影的边缘2μm～4μm。
接着，参见图12，在形成有有源层51的衬底1上继续沉积一层栅绝缘层53，该栅绝缘层53可以为氧化硅薄膜，厚度可以为0.1μm～0.2μm。再在栅绝缘层53上沉积一层栅金属层，该栅金属层的材料可以为铜，厚度可以为0.5μm～0.7μm。通过构图工艺使栅金属层形成栅极52，例如可以在光刻胶掩膜作用下通过过氧化氢溶液对栅金属层进行湿刻形成栅极52，湿刻完成后，不去除栅极52上的光刻胶，继续在光刻胶的掩膜作用下对栅绝缘层53进行干刻，如可以采用CF 4和氧气的混合气体对栅绝缘层53进行干刻，获得如图12所示的栅极52和栅绝缘层53，随后，通过湿法去除光刻胶。
然后，如图12所示，在形成有栅极53的衬底1上沉积一层层间绝缘层54，其材质可以为氧化硅，厚度可以为0.3μm～0.5μm，并在该层间绝缘层54中形成用于连接源极、漏极和有源层51的过孔，例如可以通过干刻工艺形成过孔。获得如图12所示过孔541。
最后，参见图13，沉积一层金属层，该金属层可以为铜或铝等金属，厚度可以为0.5μm～0.7μm，并通过构图工艺形成源漏极图案(例如包括源极551和漏极552)，该源漏极图案中的源极551和漏极552分别通过形成在层间绝缘层54中的一个过孔541与该有源层51电连接，从而完成顶栅型TFT5的制备。
当然，在顶栅型TFT5制备完成之后，继续参见图13，还可以继续沉积一层钝化层6，该钝化层6的材质可以为氧化硅，厚度可以为0.3-0.5微米。
本公开的另一些实施例提供一种显示面板，包括如上所述的阵列基板10。该显示面板的有益效果与上述实施例提供的阵列基板10的有益效果相同，在此不再赘述。
本公开的实施例提供一种显示装置20，参见图14，显示装置20 包括如上所述的显示面板201。而显示面板201包括上述任一实施例提供的阵列基板10。因此该显示装置20的有益效果与上述实施例提供的阵列基板10的有益效果相同，在此不再赘述。
其中，上述实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相机、导航仪等任何具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种阵列基板，包括:
    衬底；
    设置在所述衬底一侧的第一遮光图案；以及，
    设置在所述第一遮光图案的远离所述衬底一侧的阻挡层，所述阻挡层至少覆盖部分所述第一遮光图案。
  2. 根据权利要求1所述的阵列基板，还包括：
    设置在所述第一遮光图案的远离所述衬底一侧的第二遮光图案，所述第二遮光图案覆盖部分所述第一遮光图案；
    所述阻挡层至少覆盖所述第一遮光图案未被所述第二遮光图案覆盖的部分。
  3. 根据权利要求2所述的阵列基板，其中，
    所述阻挡层在所述衬底上的正投影的至少部分边缘超出所述第一遮光图案未被所述第二遮光图案覆盖的部分在所述衬底上的正投影的边缘的距离小于或等于2μm。
  4. 根据权利要求1～3中任一项所述的阵列基板，其中，
    所述阻挡层的材料包括硬化光刻胶。
  5. 根据权利要求1～4中任一项所述的阵列基板，其中，
    所述阻挡层在垂直于所述衬底的方向上的尺寸大于或等于0.1μm。
  6. 根据权利要求2～5中任一项所述的阵列基板，其中，
    所述第一遮光图案的材料包括铝或铝钕合金中的至少一种；
    所述第二遮光图案的材料包括钼、钼钨合金或钼铌合金中的至少一种。
  7. 根据权利要求2～6中任一项所述的阵列基板，其中，
    所述第一遮光图案的厚度范围为0.1μm～0.15μm，所述第二遮光图案的厚度范围为0.05μm～0.08μm。
  8. 根据权利要求2～7中任一项所述的阵列基板，还包括：
    设置在所述阻挡层及所述第二遮光图案的远离所述衬底一侧的薄膜晶体管，所述薄膜晶体管包括栅极和有源层，所述栅极位于所述有源层的远离所述衬底一侧；所述有源层在所述衬底上的正投影位于所述第一遮光图案在所述衬底上的正投影的范围之内；
    所述阻挡层在所述衬底上的正投影与所述有源层在所述衬底上的正投影至少部分重叠。
  9. 根据权利要求8所述的阵列基板，还包括：
    缓冲层，设置于所述阻挡层、所述第二遮光图案及所述有源层三者之间。
  10. 一种显示面板，包括：
    如权利要求1～9中任一项所述的阵列基板。
  11. 一种显示装置，包括：
    如权利要求10所述的显示面板。
  12. 一种阵列基板的制备方法，包括：
    提供衬底；
    在所述衬底的一侧形成第一遮光图案；
    在所述第一遮光图案的远离所述衬底一侧形成阻挡层，所述阻挡层至少覆盖部分所述第一遮光图案。
  13. 根据权利要求12所述的阵列基板的制备方法，还包括：
    在所述第一遮光图案的远离所述衬底一侧形成第二遮光图案，所述第二遮光图案覆盖部分所述第一遮光图案；
    所述阻挡层至少覆盖所述第一遮光图案的未被所述第二遮光图案覆盖的部分。
  14. 根据权利要求13所述的阵列基板的制备方法，其中，所述在所述衬底的一侧形成第一遮光图案，以及在所述第一遮光图案的远离所述衬底的一侧形成第二遮光图案，包括：
    在所述衬底的一侧依次形成第一遮光层和第二遮光层，所述第二遮光层的刻蚀选择比大于所述第一遮光层的刻蚀选择比；
    在所述第二遮光层的远离所述衬底一侧涂覆光刻胶；
    通过一次构图工艺形成所述第一遮光图案、所述第二遮光图案及覆盖所述第一遮光图案和所述第二遮光图案的光刻胶图案，所述光刻胶图案在所述衬底上的正投影的边缘超出所述第一遮光图案在所述衬底上的正投影的边缘。
  15. 根据权利要求14所述的阵列基板的制备方法，其中，
    所述光刻胶图案包括彼此相连的第一部分和第二部分，所述第一部分在所述衬底上的正投影位于所述第二遮光图案在所述衬底上的正投影的范围之内，所述第二部分在所述衬底上的正投影的至少部分边缘超出所述第一遮光图案未被所述第二遮光图案覆盖的部分在所述衬底上的正投影的边缘；
    所述第一部分的厚度小于或等于所述第二部分的厚度。
  16. 根据权利要求14或15所述的阵列基板的制备方法，其中，所述在所述第一遮光图案的远离所述衬底一侧形成阻挡层，包括：
    对所述光刻胶图案进行加热，使得所述光刻胶图案超出所述第二遮光图案的边缘的部分坍塌，以覆盖所述第一遮光图案未被所述第二遮光图案覆盖的部分；
    对所述光刻胶图案的第一部分进行灰化去除。
  17. 根据权利要求16所述的阵列基板的制备方法，其中，在对所述光刻胶图案的第一部分进行灰化去除之后，所述制备方法还包括：
    对残留的光刻胶进行硬化处理，以形成所述阻挡层。
PCT/CN2020/076814 2019-03-07 2020-02-26 阵列基板及其制备方法、显示面板和显示装置 WO2020177597A1 (zh)

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