WO2023024256A1 - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2023024256A1
WO2023024256A1 PCT/CN2021/127669 CN2021127669W WO2023024256A1 WO 2023024256 A1 WO2023024256 A1 WO 2023024256A1 CN 2021127669 W CN2021127669 W CN 2021127669W WO 2023024256 A1 WO2023024256 A1 WO 2023024256A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
oxide semiconductor
metal oxide
gate
pixel electrode
Prior art date
Application number
PCT/CN2021/127669
Other languages
English (en)
French (fr)
Inventor
王青
张有为
易志根
Original Assignee
京东方科技集团股份有限公司
南京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 南京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180004002.6A priority Critical patent/CN116018552A/zh
Publication of WO2023024256A1 publication Critical patent/WO2023024256A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the required pattern can be formed on each film layer through the mask process.
  • the array of oxide TFT with bottom gate structure is used.
  • the substrate requires 6 masking process, and the array substrate using top-gate structure oxide TFT requires 9 masking processes, which makes the process of preparing the array substrate too complicated, and the production cycle is longer, resulting in higher cost.
  • the present disclosure provides an array substrate, including a substrate, a plurality of sub-pixels arranged in an array on the substrate, and a thin film transistor for driving each of the sub-pixels, and the array substrate includes a pixel electrode;
  • the channel region of the thin film transistor includes a metal oxide semiconductor layer
  • the pixel electrode is a metal oxide conductive layer formed by conducting the metal oxide semiconductor
  • the channel region of the thin film transistor and the pixel electrode use the same
  • the metal oxide semiconductor layer is formed after patterning.
  • the thin film transistor includes a gate, the gate is located between the channel region and the substrate; the thin film transistor includes a common electrode and an auxiliary layer, and the auxiliary layer communicates with the common electrode Formed with the same metal oxide semiconductor film, the auxiliary layer and the common electrode are integrally structured, the gate is arranged on the auxiliary layer, and the common electrode includes at least the metal not covered by the gate
  • the oxide semiconductor film is a conductive layer formed by a conductorization process.
  • the auxiliary layer is an IGZO semiconductor film layer
  • the common electrode is an IGZO conductive layer.
  • the thin film transistor includes a source and drain
  • the pixel electrode includes a plurality of strip electrodes
  • the channel region is connected to the strip electrodes at one edge of the pixel electrode as an integral structure
  • the source The drain is disposed on the channel region
  • the source and drain include a source and a drain
  • the drain covers part of the pixel electrode and overlaps with the pixel electrode.
  • the array substrate includes a passivation layer, the passivation layer covers the source and drain electrodes, the channel region and the unconducted metal oxide semiconductor layer exposing the pixel electrode region, and the exposed The metal oxide semiconductor layer is ion-implanted to form a conductive pixel electrode.
  • the thin film transistor includes a gate and a gate insulating layer, the channel region is located between the gate and the substrate, the gate insulating layer covers the channel region, and the gate
  • the electrode is disposed on the gate insulating layer; the thin film transistor also includes an auxiliary conductive layer connecting the channel region and the pixel electrode, the channel region is located between the auxiliary conductive layers, and the auxiliary
  • the conductive layer, the channel region, and the pixel electrode are formed through the same metal oxide semiconductor film, and the auxiliary conductive layer and the pixel electrode include the area covered by the gate insulating layer that is not covered by the gate.
  • the metal oxide semiconductor thin film is a conductive layer formed by a conductorization process.
  • the channel region is an IGZO semiconductor film layer
  • the auxiliary conductive layer and the pixel electrode are IGZO conductive layers.
  • the pixel electrode includes a plurality of strip electrodes, and the auxiliary conductive layer is connected to the strip electrodes at one edge of the pixel electrode as an integral structure.
  • the thin film transistor includes a common electrode, a patterned light-shielding portion formed on the common electrode, a patterned photoresist layer formed on the light-shielding portion, covering the common electrode, the The light shielding part and the first buffer layer of the photoresist layer, the channel region and the pixel electrode are formed on the first buffer layer.
  • the thin film transistor further includes a patterned interlayer insulating layer, the interlayer insulating layer covers the gate, the edge of the auxiliary conductive layer close to the channel region, and partially covers the The gate is close to the auxiliary conductive layer on the side of the pixel electrode, and the orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the interlayer insulating layer on the substrate.
  • the thin film transistor further includes a source and drain and a second buffer layer, the source and drain are disposed on the interlayer insulating layer, the source and drain include a source and a drain, and the source The drain is connected to the auxiliary conductive layer located on the side of the gate away from the pixel electrode and exposing the interlayer insulating layer, and the drain is connected to the side of the gate close to the pixel electrode and exposing the The auxiliary conductive layer of the interlayer insulating layer is connected, the second buffer layer covers the source and drain electrodes and part of the interlayer insulating layer, and the orthographic projection of the pixel electrode on the substrate is the same as that of the second buffer layer.
  • the orthographic projections of the buffer layers on the substrate do not overlap.
  • the present disclosure also provides a method for preparing an array substrate, the array substrate comprising a plurality of sub-pixels arranged in an array and a thin film transistor driving each of the sub-pixels, the method comprising:
  • a first metal oxide semiconductor layer is patterned and formed by a half-tone mask process; a shielding layer is provided on a side of the first metal oxide semiconductor layer away from the substrate;
  • the first metal oxide semiconductor layer is conductorized, and at least part of the first metal oxide semiconductor layer shielded by the shielding layer is not conductorized, forming the In the channel region of the thin film transistor, at least a portion of the first metal oxide semiconductor layer not shielded by the shielding layer is conductorized to form a pixel electrode of the thin film transistor.
  • the first metal oxide semiconductor layer by patterning through a half-tone mask process further comprising:
  • the second metal oxide semiconductor layer is conductorized, the part of the second metal oxide semiconductor layer not shielded by the gate is conductorized, and the conductorized Part of it is diffused toward the gate to form a common electrode, and the rest of the second metal oxide semiconductor layer is not conductorized to form an auxiliary layer;
  • forming the first metal oxide semiconductor layer by patterning through a half-tone mask process includes:
  • a passivation layer is formed by patterning; the passivation layer covers the source and drain electrodes, and a part of the first metal oxide semiconductor layer close to the source and drain electrodes; the passivation layer is the shielding layer.
  • the first metal oxide semiconductor layer is conductorized, the first metal oxide semiconductor layer not shielded by the passivation layer is conductorized, and is conductorized A part of the first metal oxide semiconductor layer is not conductorized to form a channel region of the thin film transistor.
  • the first metal oxide semiconductor layer by patterning through a half-tone mask process further comprising:
  • the common electrode material layer is patterned to form a common electrode, and the light-shielding material layer is patterned to form a light-shielding layer; the photoresist required to form the light-shielding layer is partially retained, and A patterned photoresist layer is formed on the light shielding layer;
  • a first buffer layer covering the common electrode, the light shielding portion and the photoresist layer is formed.
  • forming the first metal oxide semiconductor layer by patterning through a half-tone mask process includes:
  • a gate insulating layer and a gate are formed by patterning on the first metal oxide semiconductor layer; the gate is disposed on the gate insulating layer, and the gate is the shielding layer.
  • the first metal oxide semiconductor layer is conductorized, and the first metal oxide semiconductor layer shielded by the gate is not conductorized, forming the thin film transistor a channel region, the remaining part of the first metal oxide semiconductor layer is conductorized to form an auxiliary conductive layer and a pixel electrode of the thin film transistor; the auxiliary conductive layer connects the channel region and the pixel electrode, The channel region is located between the auxiliary conductive layers.
  • the interlayer insulating material layer covers the gate, the edge of the auxiliary conductive layer close to the channel region, and partially covers a portion of the gate near the pixel electrode.
  • Source and drain electrodes are patterned on the interlayer insulating material layer; the source and drain electrodes include a source electrode and a drain electrode, and the source electrode is located on the side of the gate away from the pixel electrode and exposes the layer
  • the auxiliary conductive layer of the interlayer insulating material layer is connected, and the drain is connected to the auxiliary conductive layer located on the side of the gate close to the pixel electrode and exposing the interlayer insulating material layer;
  • the orthographic projection of the pixel electrode on the substrate is consistent with the interlayer insulating layer
  • the orthographic projections of the second buffer layer on the substrate do not overlap, and the second buffer layer covers the source and drain electrodes and the interlayer insulating layer.
  • the present disclosure also provides a display device, including the above-mentioned array substrate.
  • FIG. 1 shows a cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 shows a cross-sectional view of another array substrate according to an embodiment of the present disclosure
  • FIG. 3 shows a flowchart of steps of a method for manufacturing an array substrate according to an embodiment of the present disclosure
  • Fig. 11 shows the impedance data before and after the IGZO conductorization of the embodiment of the present disclosure and after baking;
  • Figure 12 shows the transmittance data before and after IGZO conductorization and after baking of an embodiment of the present disclosure
  • Fig. 13 shows the partial preparation conditions of the IGZO of the embodiment of the present disclosure and the lateral diffusion distance of IGZO conductorization
  • 23-36 show cross-sectional views of the process flow of the method for manufacturing the array substrate according to the embodiment of the present disclosure.
  • Figure 1 shows a cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • Figure 2 shows a cross-sectional view of another array substrate according to an embodiment of the present disclosure
  • the array substrate includes a substrate (in Figure 1 marked as 200, marked as 100 in FIG. 2), and a plurality of sub-pixels arranged in an array on the substrate and thin film transistors for driving each sub-pixel.
  • the array substrate includes pixel electrodes (marked as 204-3 in FIG. identified as 105-2).
  • the channel region of the thin film transistor (identified as 204-2 in FIG. 1 and 105-1 in FIG. 2) includes a metal oxide semiconductor layer, and the pixel electrode is a conductive metal oxide semiconductor formed by metal oxide semiconductor. Layer, the channel region of the thin film transistor and the pixel electrode are formed after patterning using the same metal oxide semiconductor layer.
  • the channel region of the thin film transistor and the pixel electrode can be formed after patterning using the same metal oxide semiconductor layer, wherein the channel region of the thin film transistor can include an unconducted metal oxide semiconductor layer, and the pixel electrode
  • the electrode can be a metal oxide conductive layer formed by conducting the metal oxide semiconductor.
  • the channel region and the pixel electrode of the thin film transistor can be patterned once based on the same layer of metal oxide semiconductor material to form the channel region.
  • the thin film transistor includes a gate 202 , and the gate 202 may be located between the channel region 204 - 2 and the substrate 200 .
  • the array substrate can adopt a bottom-gate structure oxide thin film transistor
  • the gate 202 of the array substrate is arranged close to the substrate 200
  • the channel region 204-2 is located away from the gate 202. 200 on one side.
  • the channel region and the pixel electrode can be formed by patterning only once, thereby reducing the cost of the array substrate of the bottom-gate structure oxide thin film transistor.
  • the mask plate patterning process simplifies the process steps of the array substrate of the oxide thin film transistor with the bottom gate structure, and reduces the process complexity of the array substrate of the oxide thin film transistor with the bottom gate structure.
  • the thin film transistor includes a common electrode 201-2 and an auxiliary layer 201-1, the auxiliary layer 201-1 and the common electrode 201-2 are formed by the same metal oxide semiconductor film, the auxiliary layer 201-1 and the common electrode 201-2 are In an integrated structure, the gate 202 is disposed on the auxiliary layer 201-1, and the common electrode 201-2 at least includes a conductive layer formed by conducting a metal oxide semiconductor thin film not covered by the gate 202.
  • the auxiliary layer 201-1 and the common electrode 201-2 may have an integral structure, and therefore, the auxiliary layer 201-1 and the common electrode 201-2 may be formed based on the same metal oxide semiconductor layer.
  • the gate 202 can be disposed on the auxiliary layer 201-1, and part of the common electrode 201-2 is not covered by the gate 202, so that the gate pattern and the common electrode pattern can be formed by patterning only once.
  • the gate and the common electrode can be formed only once by patterning, so that on the basis of forming the channel region and the pixel electrode by patterning once, the mask patterning process is further reduced, simplifying The process steps are simplified, and the process complexity is reduced.
  • the auxiliary layer 201-1 may be an IGZO (gallium indium zinc oxide) semiconductor film layer
  • the common electrode 201-2 may be an IGZO conductive layer.
  • a layer of IGZO material can be formed first, and then the layer of IGZO material is patterned, and then the patterned IGZO material layer is shielded by the patterned gate, and the patterned IGZO material layer is conductorized.
  • the IGZO material layer is blocked by the gate but not by the conductor.
  • the portion of the IGZO material layer that is not shielded by the gate and is conductive is used as the common electrode 201-2.
  • the conductorized IGZO will diffuse laterally toward the gate 202, so that the gate 202 covers part of the conductorized IGZO, that is, covers part of the common electrode 201-2, and the conductorized IGZO can be diffused laterally.
  • An ohmic contact is formed with the gate 202, so that the electrical connection between the gate 202 and the common electrode 201-2 can be realized.
  • both the auxiliary layer 201-1 and the common electrode 201-2 may be ITO (indium tin oxide) conductive layers.
  • a layer of ITO material can be formed first, and then the layer of ITO material is patterned.
  • baking treatment is required after patterning. After baking treatment, the layer of ITO material will be completely converted into a conductor, thereby Both the auxiliary layer 201-1 and the common electrode 201-2 are conductive ITO.
  • the entire layer of ITO is conductorized, which can be regarded as the gate 202 covering a part of the conductorized IGZO, that is, covering part of the common electrode 201-2.
  • the thin film transistor includes source and drain electrodes 205
  • the pixel electrode 204-3 includes a plurality of strip electrodes
  • the channel region 204-2 is connected to the strip electrodes on one edge of the pixel electrode 204-3 as An integrated structure
  • the source and drain 205 are arranged on the channel region 204-2
  • the source and drain 205 include a source 205-1 and a drain 205-2
  • the drain 205-2 covers part of the pixel electrode 204-3 and is connected to the pixel electrode 204-3 lap.
  • the source and drain electrodes 205 of the thin film transistor are located on the channel region 204-2, and part of the pixel electrode 204-3 is not covered by the source and drain electrodes 205. In this way, the channel region 204-2 can be formed by patterning only once. 2.
  • the pixel electrode is formed by conducting the metal oxide semiconductor layer, and there is no need to dig holes to overlap the pixel electrode through the source or drain, so it is suitable for the production of high PPI (pixel density) products, which is conducive to improving the competitiveness of display products in the market .
  • PPI pixel density
  • the channel region 204-2 is an IGZO semiconductor film layer
  • the pixel electrode 204-3 is an IGZO conductive layer.
  • a layer of IGZO material can be formed first, and then the layer of IGZO material is patterned, and then other film layers covering the channel region 204-2 and the source and drain electrodes 205 and exposing part of the IGZO material are used as shields to block the patterned IGZO material.
  • Conducting the material layer, the part of the IGZO material layer that is shielded by other film layers but not conductorized is used as the channel region 204-2, and the part of the IGZO material layer that is not shielded by other film layers but is conductorized is used as the pixel electrode 204 -3.
  • the conductorized IGZO will diffuse laterally toward the source and drain electrodes 205, so that the source and drain electrodes 205 cover part of the conductorized IGZO, that is, cover part of the pixel electrode 204-3, and the conductorized IGZO diffuses laterally.
  • an ohmic contact can be formed with the source and drain electrodes 205, so that the electrical connection between the source and drain electrodes 205 and the pixel electrode 204-3 can be realized.
  • the array substrate further includes a passivation layer 206, the passivation layer 206 covers the source and drain electrodes 205, the channel region 204-2 and the unconducted metal oxide semiconductor layer exposing the pixel electrode region, Ion implantation is performed on the exposed metal oxide semiconductor layer to form a conductive pixel electrode 204-3.
  • the passivation layer 206 can be used as a film layer that plays a shielding role in the above specific examples. Specifically, after forming the corresponding patterns of the channel region 204-2, the source and drain electrodes 205 and the pixel electrode 204-3, a passivation material layer can be formed and patterned to form the passivation layer 206, and then the patterned passivation layer 206 can be formed.
  • Layer 206 is for shielding, and the patterned IGZO material layer is conductorized, and the part of the IGZO material layer that is blocked by the passivation layer 206 and not conductorized is used as the channel region 204-2, and the part that is not shielded by the passivation layer in the IGZO material layer 206 is shielded and conductorized as the pixel electrode 204-3.
  • the passivation layer can protect the channel region during the conductorization process and prevent the channel region from being conductorized, and the passivation layer can also protect the prepared source and drain electrodes, improving the performance of the array substrate.
  • the thin film transistor includes a gate 106 and a gate insulating layer 107 , and the channel region 105 - 1 may be located between the gate 106 and the substrate 100 .
  • the array substrate may adopt a top-gate structure oxide thin film transistor
  • the channel region 105-1 of the array substrate is arranged close to the substrate 100
  • the gate 106 is located in the channel region 105 -1 side away from the substrate 100 .
  • the channel region and the pixel electrode can be formed by patterning only once, thereby reducing the cost of the array substrate of the top-gate structure oxide thin film transistor.
  • the mask plate patterning process simplifies the process steps of the array substrate of the oxide thin film transistor with the top gate structure, and reduces the process complexity of the array substrate of the oxide thin film transistor with the top gate structure.
  • the gate insulating layer 107 covers the channel region 105-1
  • the gate 106 is disposed on the gate insulating layer 107
  • the thin film transistor further includes an auxiliary conductive layer 105-1 connecting the channel region 105-1 and the pixel electrode 105-2.
  • the channel region 105-1 is located between the auxiliary conductive layer 105-3, the auxiliary conductive layer 105-3, the channel region 105-1 and the pixel electrode 105-2 are formed by the same metal oxide semiconductor film
  • the auxiliary conductive layer 105 - 3 and the pixel electrode 105 - 2 include a conductive layer formed by a conductorization process by the metal oxide semiconductor film not covered by the gate insulating layer 107 in the area covered by the gate 106 .
  • the gate 106 can be used as a shield to conduct conductorization on the same metal oxide semiconductor film, wherein the region of the metal oxide semiconductor film that is shielded by the gate 106 but not conductorized forms a channel region 105-1 , the conductive metal oxide semiconductor film region forms the auxiliary conductive layer 105-3 and the pixel electrode 105-2. Wherein, most of the auxiliary conductive layer 105-3 is covered by other film layers and is not exposed outside, while the pixel electrode 105-2 is not covered by other film layers and is exposed outside.
  • the auxiliary conductive layer 105-3 can serve as an electrical connection between the channel region 105-1 and the pixel electrode 105-2, the auxiliary conductive layer 105-3 is distributed on both sides of the channel region 105-1, and the auxiliary conductive layer 105-3 has contact areas for source and drain.
  • the channel region 105-1 is an IGZO semiconductor film layer
  • the auxiliary conductive layer 105-3 and the pixel electrode 105-2 are IGZO conductive layers.
  • a layer of IGZO material can be formed first, and then the layer of IGZO material is patterned, and then the patterned IGZO material layer is shielded by the patterned gate, and the patterned IGZO material layer is conductorized.
  • the IGZO material layer is blocked by the gate but not by the conductor.
  • the portion of the IGZO material layer that is not shielded by the gate and is conductive is used as the auxiliary conductive layer 105-3 and the pixel electrode 105-2.
  • the pixel electrode 105-2 may include a plurality of strip electrodes, and the auxiliary conductive layer is connected to the strip electrodes at one edge of the pixel electrode as an integral structure.
  • the part of the IGZO material layer that is not shielded by the gate and is conductorized is used as the auxiliary conductive layer 105- 3 and the pixel electrode 105-2, wherein the conductive part patterned into a plurality of strips is the pixel electrode 105-2, except for the unconducted channel region 105-1 and the conductive pixel electrode 105-2 , and the rest of the metal oxide semiconductor thin film area is the conductorized auxiliary conductive layer 105-3.
  • the thin film transistor includes a common electrode 101, a patterned light-shielding portion 102 formed on the common electrode 101, a patterned photoresist layer 103-3 formed on the light-shielding portion 102, covering the common electrode 101, the light-shielding portion 102 and the first buffer layer 104 of the photoresist layer 103 - 3 , the channel region 105 - 1 and the pixel electrode 105 - 2 are formed on the first buffer layer 104 .
  • the common electrode 101 , the light shielding portion 102 and the photoresist layer 103 - 3 all have gaps exposing the substrate 100 .
  • the design of the gap can prevent the thin film transistor and the common electrode from overlapping in the stacking direction of the display panel, and can reduce the coupling capacitance between the common electrode and the gate, source and drain of the thin film transistor.
  • the embodiment of the present disclosure does not limit the specific shape and position of the thin film transistor, as long as the function of separating the thin film transistor from the pixel electrode of the sub-pixel and the common electrode below the pixel electrode can be satisfied.
  • the insulating first buffer layer 104 is located between the common electrode 101 and the pixel electrode 105-2, so that there is no conduction between the common electrode 101 and the pixel electrode 105-2.
  • the thin film transistor further includes a patterned interlayer insulating layer 108, the interlayer insulating layer 108 covers the gate 106, the edge of the auxiliary conductive layer 105-3 close to the channel region 105-1, and partially covers the 106 is the auxiliary conductive layer 105 - 3 on the side close to the pixel electrode 105 - 2 , the orthographic projection of the pixel electrode 105 - 2 on the substrate 100 does not overlap with the orthographic projection of the interlayer insulating layer 108 on the substrate 100 .
  • the region where the auxiliary conductive layer 105-3 exposes the interlayer insulating layer 108 includes the connecting region of the source electrode and the drain electrode, and the pixel electrode 105-2 and the interlayer insulating layer 108 do not overlap in the stacking direction of the display panel. , the pixel electrode 105 - 2 is exposed from the interlayer insulating layer 108 .
  • the thin film transistor further includes a source and drain 109 and a second buffer layer 110, the source and drain 109 are disposed on the interlayer insulating layer 108, the source and drain 109 includes a source 109-1 and a drain 109-2, the source
  • the electrode 109-1 is connected to the auxiliary conductive layer 105-3 located on the side of the gate 106 away from the pixel electrode 105-2 and exposing the interlayer insulating layer 108
  • the drain 109-2 is connected to the side of the gate 106 close to the pixel electrode 105-2.
  • the second buffer layer 110 covers the source and drain electrodes 109 and part of the interlayer insulating layer 108, and the orthographic projection of the pixel electrode 105-2 on the substrate 100 is the same as the second buffer layer 110. Orthographic projections of the buffer layer 110 on the substrate 110 do not overlap.
  • the source and drain electrodes 109 of the thin film transistor are arranged on the interlayer insulating layer 108, and are connected to the auxiliary conductive layer 105-3 exposing the interlayer insulating layer 108, and the part of the auxiliary conductive layer connected to the source electrode 109-1 is located at The side of the gate 106 away from the pixel electrode 105-2, and the part of the auxiliary conductive layer connected to the drain 109-2 is located on the side of the gate 106 close to the pixel electrode 105-2.
  • the second buffer layer 110 only covers part of the interlayer insulating layer 108, therefore, the second buffer layer 110 and the layer None of the inter-insulating layers 108 forms a shield to the pixel electrode 105-2, so that the pixel electrode 105-2 can be exposed outside.
  • the channel region of the thin film transistor and the pixel electrode can be formed after patterning using the same metal oxide semiconductor layer, wherein the channel region of the thin film transistor can include an unconducted metal oxide semiconductor layer, and the pixel electrode
  • the electrode can be a metal oxide conductive layer formed by conducting the metal oxide semiconductor.
  • the channel region and the pixel electrode of the thin film transistor can be patterned once based on the same layer of metal oxide semiconductor material to form the channel region.
  • only one patterning is required to form the channel region and the pixel electrode, which reduces the mask patterning process, simplifies the process steps, and reduces the process complexity.
  • FIG. 3 it shows a flow chart of the steps of a method for preparing an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a plurality of sub-pixels arranged in an array and a thin film transistor for driving each sub-pixel.
  • the preparation method includes the following steps:
  • Step 101 Patterning and forming a first metal oxide semiconductor layer by a half-tone masking process; a shielding layer is provided on a side of the first metal oxide semiconductor layer away from the substrate.
  • Step 102 Conducting conductorization on the first metal oxide semiconductor layer under the shielding of the shielding layer, at least part of the first metal oxide semiconductor layer shielded by the shielding layer is not conductorized, forming a channel region of a thin film transistor At least part of the first metal oxide semiconductor layer that is not shielded by the shielding layer is conductorized to form a pixel electrode of the thin film transistor.
  • the first metal oxide semiconductor layer can be patterned and formed by a half-tone mask process, and under the shielding layer, the first metal oxide semiconductor layer is conductorized, and the first metal oxide shielded by the shielding layer is oxidized At least part of the material semiconductor layer is not conductorized, so that the channel region of the thin film transistor can be formed, and at least part of the first metal oxide semiconductor layer that is not blocked by the shielding layer is conductorized, then the pixel of the thin film transistor can be formed electrode.
  • the channel region and the pixel electrode of the thin film transistor can be patterned once based on the same layer of metal oxide semiconductor material to form the metal oxide semiconductor pattern of the channel region and the corresponding metal oxide semiconductor pattern of the pixel electrode, and then In the case of shielding the pattern of the channel region, the pattern corresponding to the pixel electrode is conductorized with a metal oxide semiconductor, thereby forming a semiconductor metal oxide channel region and a conductive metal oxide pixel electrode.
  • only one patterning is required to form the channel region and the pixel electrode, which reduces the mask patterning process, simplifies the process steps, and reduces the process complexity.
  • step 101 For an array substrate including oxide thin film transistors with a bottom gate structure, before step 101, the following steps may also be included:
  • the second metal oxide semiconductor layer is conductorized, the part of the second metal oxide semiconductor layer not shielded by the gate is conductorized, and the conductorized part diffuses toward the direction of the gate, A common electrode is formed, and the rest of the second metal oxide semiconductor layer is not conductorized to form an auxiliary layer.
  • the substrate 200 may be a glass substrate, which is of course only exemplary, and the present disclosure is not intended to be limiting.
  • a second metal oxide semiconductor material layer 201 - 1 such as IGZO, ITO, etc.
  • a gate material layer 202-1 may then be formed, and the gate material layer 202-1 covers the previously formed second metal oxide semiconductor material layer 201-1.
  • the gate material layer 202-1 may include a double-layer structure of a protective metal and a gate metal, the gate metal is closer to the substrate, and the protective metal may be, for example, titanium (Ti), silver (Ag), molybdenum (Mo), molybdenum Niobium alloy (MoNb), etc., and the gate metal may be copper (Cu), for example.
  • the protective metal can protect the gate metal, and in practical applications, the thickness of the protective metal is much smaller than that of the gate metal.
  • a photoresist can be coated on the gate material layer 202-1, and a half tone mask (Half Tone Mask) is used to expose the photoresist to form a photoresist as shown in FIG. Resin 001 pattern, wherein the area on the halftone mask plate corresponding to the part to be retained after photolithography has different transmittance from the area corresponding to the part to be removed after photolithography.
  • the first mask process is performed.
  • the gate material layer 202-1 may be etched.
  • Cu acid may be used to etch the gate material layer 202-1.
  • the pattern after etching is shown in FIG. 6 .
  • the second metal oxide semiconductor material layer 201 - 1 may be etched to obtain the second metal oxide semiconductor layer 201 .
  • oxalic acid may be used to etch the second metal oxide semiconductor material layer 201 , and the pattern after etching is shown in FIG. 7 .
  • the gate material layer 202-1 and the second metal oxide semiconductor material layer 201-1 can also be etched once with Cu acid containing fluorine (F), to obtain the pattern shown in FIG. 7 , which saves an etching process, simplifies the process steps, and reduces the process complexity.
  • the thickness of the photoresist 001 corresponding to different positions of the second metal oxide semiconductor layer 201 is different.
  • the thicker photoresist 001 can be used to form the gate auxiliary layer, and the thinner photoresist 001 can be used to form the common electrode.
  • the photoresist 001 can be ashed, for example, the photoresist 001 can be ashed by oxygen, so as to remove the thinner photoresist part, and the pattern of the photoresist 002 after ashing is shown in Figure 8 shown. Further, the gate material layer 202 - 1 is etched again to obtain the gate 202 , and the pattern after the photoresist is stripped is shown in FIG. 9 . In an optional example, Cu acid may be used to etch the gate material layer 202-1 again.
  • a gate insulating material layer 203 - 1 covering the second metal oxide semiconductor layer 201 and the gate electrode 202 may be formed, and then the second metal oxide semiconductor layer 201 is conductorized.
  • the second metal oxide semiconductor layer 201 may be made of IGZO material, and the IGZO material is still a semiconductor after baking, so it needs to be converted into a conductor through conductorization in a subsequent process.
  • the conductorization treatment is performed on the second metal oxide semiconductor layer 201, the part of the second metal oxide semiconductor layer not shielded by the gate 202 is conductorized, and the conductorized part diffuses toward the gate 202 to form a common For the electrode 201-2, the rest of the second metal oxide semiconductor layer is not conductorized, forming the auxiliary layer 201-1.
  • the auxiliary layer 201-1 is an unconducted IGZO semiconductor film layer
  • the common electrode 201-2 is a conductive IGZO conductive layer.
  • the conductorized part will diffuse toward the gate 202, the conductorized lateral diffusion distance is L1, and the conductorized diffused part is also a part of the common electrode 201-2, as shown in FIG. 10 .
  • the second metal oxide semiconductor layer 201 of IGZO material can be treated with plasma (plasma) in a hydrogen environment, so as to realize the conductorization of the second metal oxide semiconductor layer 201, and the conductorized IGZO transparent Overrate increase.
  • plasma plasma
  • the impedance data of IGZO before and after conductorization and after baking are shown in Figure 11, and the transmittance data are shown in Figure 12.
  • the block impedance of IGZO can be reduced to 150 ⁇ , and the transmittance can be increased to 87%, which can meet the conductive requirements and transmittance of the common electrode need.
  • the lateral diffusion distance L of IGZO conductorization can be regulated by some process parameters.
  • Figure 13 only lists a list of optional control parameters, it can be understood that other control parameters can also be determined by the single variable method. For example, with Taking thick IGZO as an example, after 300W H2 plasma treatment for 30 seconds, the lateral diffusion distance of IGZO conductorization exceeds 3.7um, and the lateral diffusion distance of IGZO conductorization can increase with the increase of conductorization power and time.
  • Figure 13 only exemplarily shows part of the preparation conditions of some IGZO samples, and the actual range of the conductorized lateral diffusion distance L of these IGZO samples. It can be understood that when some other preparation conditions change , the measurement result of conductorized lateral diffusion distance L is not necessarily as shown in FIG. 13 .
  • the second metal oxide semiconductor layer 201 can also use ITO material, and the ITO material can become a conductor after being baked, and the second metal oxide semiconductor layer 201 is processed by a half-tone mask process. After patterning, the formed first metal oxide semiconductor sublayer is directly used as an auxiliary layer, and the formed second metal oxide semiconductor sublayer is directly used as a common electrode, and both the auxiliary layer and the common electrode are conductive ITO conductive layers.
  • the gate insulating material layer 203 - 1 may be patterned to form a gate insulating layer 203 according to requirements, as shown in FIG. 14 .
  • a second mask process is performed.
  • step 101 may specifically include:
  • a passivation layer is formed by patterning; the passivation layer covers the source and drain electrodes, and a part of the first metal oxide semiconductor layer close to the source and drain electrodes; the passivation layer is a shielding layer.
  • a first metal oxide semiconductor material layer 204 - 4 such as IGZO, ITO, etc., may be formed on the gate insulating layer 203 .
  • a source-drain material layer 205-1 may then be formed, and the source-drain material layer 205-1 covers the previously formed first metal oxide semiconductor material layer 204-4.
  • the source-drain material layer 205-1 may also include a double-layer structure of protective metal and source-drain metal, the source-drain metal is closer to the substrate, and the protective metal includes but not limited to Ti, Ag, Mo, MoNb alloy, etc., and the source and drain metal may be Cu, for example.
  • the protective metal can protect the source and drain metals, and in practical applications, the thickness of the protective metal is much smaller than that of the source and drain metals.
  • a photoresist can be coated on the source-drain material layer 205-1, and a half tone mask (Half Tone Mask) is used to expose the photoresist to form a photoresist as shown in FIG. Resist 003 pattern, wherein, the area on the half-tone mask corresponding to the part to be retained after photolithography has different transmittance from the area corresponding to the part to be removed after photolithography.
  • the third mask process is performed.
  • the source-drain material layer 205-1 can be etched.
  • Cu acid can be used to etch the source-drain material layer 205-1.
  • the pattern after etching is shown in FIG. 17 .
  • the first metal oxide semiconductor material layer 204-4 may be etched to obtain the first metal oxide semiconductor layer 204-1.
  • oxalic acid may be used to etch the first metal oxide semiconductor material layer 204 - 4 , and the pattern after etching is shown in FIG. 18 .
  • the source-drain material layer 205-1 and the first metal-oxide-semiconductor material layer 204-4 can also be etched once with Cu acid containing F to obtain the pattern shown in FIG. 18 , thus An etching process can be saved, the process steps are simplified, and the process complexity is reduced.
  • the thickness of different positions on the photoresist 003 is different.
  • the thicker position of the photoresist 003 can be used to form the source and drain positions
  • the thicker position of the photoresist 003 and the thinner position between the thicker positions can be used to form the channel region, and the rest of the photoresist 003 is thinner.
  • the thin locations can be used to form pixel electrodes.
  • the photoresist 003 can be ashed, for example, by ashing the photoresist with oxygen, so as to remove the thinner photoresist part, and the pattern of the photoresist 004 after ashing is shown in Figure 19 Show.
  • the source-drain material layer 205-1 is etched again to obtain the source-drain 205, and the pattern after stripping the photoresist is shown in FIG. 20 .
  • the source-drain material layer 205-1 may be etched again with Cu acid.
  • a passivation material layer can be formed, and the passivation material layer is patterned to form a passivation layer 206.
  • the pattern of the formed passivation layer is shown in FIG. 21, wherein the passivation layer 206 covers the source and drain electrodes 205, and Part of the first metal oxide semiconductor layer 204 - 1 of the source and drain electrodes 205 .
  • the fourth mask process is performed.
  • the passivation layer 206 can be provided first, and then the first metal oxide semiconductor layer 204-1 is conductorized.
  • the passivation layer 206 can protect the channel region during the conductorization process and prevent the channel region from being and the passivation layer 206 can also protect the fabricated source and drain electrodes 205, improving the performance of the array substrate.
  • the patterned passivation layer can expose the pixel electrode, ensuring that the pixel electrode and the common electrode are connected to each other. The electric field strength formed by the electrodes.
  • step 202 can specifically include:
  • the first metal oxide semiconductor layer 204-1 is conductorized, and the first metal oxide semiconductor layer 204-1 not shielded by the passivation layer 206 is conductorized, and is conductorized Part of the first metal oxide semiconductor layer 204-1 is not conductorized to form the channel region 204-2 of the thin film transistor.
  • the first metal oxide semiconductor layer 204-1 may be subjected to conducting treatment by, for example, plasma treatment in a hydrogen atmosphere.
  • the first metal oxide semiconductor layer 204-1 not shielded by the passivation layer 206 is conductorized to form a pixel electrode 204-3, and the rest of the first metal oxide semiconductor layer 204-1 is not conductorized to form a trench Road District 204-2.
  • the channel region 204-2 is an unconducted IGZO semiconductor film layer
  • the pixel electrode 204-3 is a conductive IGZO conductive layer.
  • the conductorized part will diffuse toward the direction of the source and drain electrodes 205, and the lateral diffusion distance of the conductorization is L2.
  • the conductorized IGZO diffuses laterally, it can form an ohmic contact with the source and drain electrodes 205, realizing the connection between the source and drain electrodes 205 and the pixel electrode.
  • the transmittance of the conductive pixel electrode 204 - 3 is improved, and the channel region 204 - 2 is not conductive due to the protection of the passivation layer 206 , and the semiconductor characteristics can be maintained. So far, the manufacturing process of the array substrate is completed.
  • the preparation of an array substrate including a bottom-gate structure oxide thin film transistor can be realized by only 4 times of patterning, that is, 4-pass mask process, compared with the current 6-pass masking process with a bottom-gate structure.
  • the mask plate process can reduce the mask plate patterning process, simplify the process steps, and reduce the process complexity.
  • pixel electrode and the corresponding thin film transistor part are shown in each illustration of the embodiments of the present disclosure.
  • the pixel electrode in the figure shows multiple parts because the pixel electrode is a hollow pattern, and the cross-sectional view is taken as The multiple interrupted parts are not specifically limited in this application.
  • the part A shown in the figures of the above-mentioned embodiments is the terminal area of the array substrate, which is used to connect with the circuit board, so as to input the required electrical signals to the display area of the array substrate.
  • the terminal area is located in the non-display area of the array substrate.
  • the film layer structure in the terminal area only needs to meet the requirements of electrical connection and electrical signal transmission.
  • the terminal area shown in each figure is only an optional example, and only a part of the terminal area is shown. , the embodiments of the present disclosure do not intend to specifically limit the film layer structure of the terminal region.
  • step 101 for an array substrate including an oxide thin film transistor with a top gate structure, the following steps may also be included:
  • the common electrode material layer is patterned to form a common electrode, and the light-shielding material layer is patterned to form a light-shielding layer; the photoresist required to form the light-shielding layer is partially retained, and the patterning is formed on the light-shielding layer the photoresist layer;
  • a first buffer layer covering the common electrode, the light shielding portion and the photoresist layer is formed.
  • a common electrode material layer 101-1 may be formed on the substrate 100, and then, a light-shielding material layer 102-1 may be formed on the common electrode material layer 101-1.
  • a first photoresist layer is formed on the light-shielding material layer 102 - 1
  • a second photoresist layer 103 is formed by patterning the first photoresist layer through a half-tone mask process.
  • the second photoresist layer 103 includes a first region and a second region, the thickness of the second region is smaller than that of the first region, and the second region is used to form a light-shielding portion in a subsequent step. In this step, the first mask process is performed.
  • the light-shielding material layer 102 - 1 is etched based on the second photoresist layer 103 to form a light-shielding sub-layer 102 - 2 .
  • the common electrode 101 is formed by etching the common electrode material layer 101 - 1 based on the second photoresist layer 103 .
  • the first ashing treatment is performed on the second photoresist layer 103 to remove the second region to form the second photoresist sub-layer 103 - 1 .
  • the light shielding sublayer 102-2 is wet-etched to form a light shielding portion 102.
  • the light shielding portion 102 includes a first light shielding portion, and the first light shielding portion is formed on the substrate 100.
  • the orthographic projection covers the orthographic projection of the channel region of the thin film transistor to be formed on the substrate.
  • the second photoresist sublayer 103 - 1 is subjected to a second ashing treatment so that the second photoresist sublayer shrinks to the point where the orthographic projection of the second photoresist sublayer on the substrate 100 falls on the light shielding portion 102 on the substrate 100 In the orthographic projection, the photoresist layer 103-3 remains.
  • it is not necessary to remove the remaining photoresist layer 103 - 3 and keeping the remaining photoresist layer 103 - 3 can further reduce the coupling capacitance between the source drain and the common electrode.
  • a first buffer layer 104 is formed on the remaining photoresist layer 103-3.
  • step 101 may specifically include the following steps:
  • a gate insulating layer and a gate are formed by patterning on the first metal oxide semiconductor layer; the gate is arranged on the gate insulating layer, and the gate is a shielding layer.
  • a first metal oxide semiconductor material layer is formed on the first buffer layer 104 , and the first metal oxide semiconductor material layer is patterned to form a first metal oxide semiconductor layer 105 .
  • the material of the first metal oxide semiconductor layer 105 may be IGZO.
  • the second mask process is performed.
  • a gate insulating material layer is formed on the first metal oxide semiconductor layer 105, and a gate material layer is formed on the gate insulating material layer, and then, a gate insulating layer 107 and a gate 106 are formed by patterning at one time. , the gate 106 is disposed on the gate insulating layer 107 .
  • the orthographic projection of the gate 106 on the substrate 100 partially covers the orthographic projection of the first metal oxide semiconductor layer 105 on the substrate 100 .
  • the third mask process is performed.
  • step 202 can specifically include:
  • the first metal oxide semiconductor layer 105 is conductorized, and the first metal oxide semiconductor layer 105 shielded by the gate 106 is not conductorized, forming the channel region 105-1 of the thin film transistor , the rest of the first metal oxide semiconductor layer 105 is conductorized to form the auxiliary conductive layer 105-3 and the pixel electrode 105-2 of the thin film transistor; the auxiliary conductive layer 105-3 connects the channel region 105-1 and the pixel electrode 105 -2, the channel region 105-1 is located between the auxiliary conductive layers 105-3.
  • the first metal oxide semiconductor layer 105 can be conductiveized by, for example, plasma treatment under a hydrogen atmosphere, and the first metal oxide semiconductor layer 105 The part of the semiconductor layer 105 shielded by the gate 106 is not conductorized to form the channel region 105-1, and the rest of the first metal oxide semiconductor layer 105 is conductorized to form the auxiliary conductive layer 105-3 and the pixel of the thin film transistor Electrode 105-2.
  • the channel region 105-1 is an unconducted IGZO semiconductor film layer
  • the auxiliary conductive layer 105-3 and the pixel electrode 105-2 are conductive IGZO conductive layers.
  • step 202 the following steps may also be included:
  • the interlayer insulating material layer covers the gate, the edge of the auxiliary conductive layer near the channel region, partially covers the auxiliary conductive layer on the side of the gate near the pixel electrode, and the pixel electrode;
  • the source and drain are patterned on the interlayer insulating material layer;
  • the source and drain include a source and a drain, the source is connected to the auxiliary conductive layer that is located on the side of the gate away from the pixel electrode and exposes the interlayer insulating material layer, and the drain connected to the auxiliary conductive layer located on the side of the gate close to the pixel electrode and exposing the interlayer insulating material layer;
  • an interlayer insulating material layer 108 - 1 is deposited and formed on the gate 106 , and patterned to expose the region of the auxiliary conductive layer that needs to be connected to the source and drain. At this time, the interlayer insulating material layer 108-1 covers the pixel electrode 105-2. In this step, the fourth mask process is performed.
  • a source-drain material layer is formed by patterning on the interlayer insulating material layer 108 - 1 , and then a source-drain electrode 109 is patterned. In this step, the fifth mask process is performed.
  • the source and drain electrodes 109 are connected to the auxiliary conductive layer 105-3 exposing the interlayer insulating material layer 108-1, and the part of the auxiliary conductive layer connected to the source electrode 109-1 is located at the side of the gate 106 away from the pixel electrode 105-2. On one side, the part of the auxiliary conductive layer connected to the drain electrode 109-2 is located on the side of the gate electrode 106 close to the pixel electrode 105-2.
  • a second buffer material layer 110-1 may be formed, and the second buffer material layer 110-1 and the interlayer insulating material layer 108-1 are patterned, thereby obtaining a patterned second buffer layer 110 and layer
  • the interlayer insulating layer 108, the pixel electrode 105 exposes the second buffer layer 110 and the interlayer insulating layer 108 to form a thin film transistor, as shown in FIG. 36 .
  • the sixth mask process is performed.
  • the second-conductorized pixel electrode 105-2 can have further improved transmittance, can further reduce resistivity, and has better metal properties.
  • the preparation of an array substrate including a top-gate structure oxide thin film transistor can be realized by only 6 times of patterning, that is, 6-pass mask process, compared with the current 9-step masking process of the top-gate structure.
  • the mask plate process can reduce the mask plate patterning process, simplify the process steps, and reduce the process complexity.
  • the photoresist is only used as an example of a positive photoresist. It can be understood that the above-mentioned preparation methods can also use a negative photoresist. Not specifically limited.
  • the film layers named with the same name do not mean the same film layer, but Indicates film layers with the same or similar materials and the same or similar functions.
  • each of the above preparation methods may also include other conventional steps, which are not specifically limited in the embodiments of the present disclosure.
  • the embodiment of the present disclosure also discloses a display device, including the above-mentioned array substrate.
  • the array substrate included in the display device provided by the embodiments of the present disclosure corresponds to the array substrates provided by the above-mentioned several embodiments, the previous implementation manners are also applicable to this embodiment, and will not be described in detail in this embodiment.
  • references herein to "one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Additionally, please note that examples of the word “in one embodiment” herein do not necessarily all refer to the same embodiment.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the disclosure can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开提供了一种阵列基板及其制备方法、显示装置，涉及显示技术领域。其中，阵列基板，包括基板，以及在基板上阵列排布的多个子像素和驱动各子像素的薄膜晶体管，阵列基板包括像素电极；薄膜晶体管的沟道区包含金属氧化物半导体层，像素电极为金属氧化物半导体进行导体化形成的金属氧化物导电层，薄膜晶体管的沟道区与像素电极使用同一金属氧化物半导体层图案化后形成。在本公开实施例中，可以基于同一金属氧化物半导体层，仅通过一次图案化即可形成半导体的沟道区和导电的像素电极，减少了掩膜版图案化工序，简化了工艺步骤，降低了工艺复杂度。

Description

一种阵列基板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板及其制备方法、显示装置。
背景技术
目前，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)装置具有体积小、功耗低、无辐射等特点。
在目前的横向电场型TFT-LCD阵列基板的制备工艺中，可以通过掩膜版工艺在各膜层上形成所需的图案，在当前主流的制备流程中，采用底栅结构氧化物TFT的阵列基板需要6道掩膜版工艺，采用顶栅结构氧化物TFT的阵列基板需要9道掩膜版工艺，这使得制备阵列基板的过程过于复杂，生产节拍较长，造成较高成本。
发明内容
本公开提供了一种阵列基板，包括基板，以及在所述基板上阵列排布的多个子像素和驱动各所述子像素的薄膜晶体管，所述阵列基板包括像素电极；
所述薄膜晶体管的沟道区包含金属氧化物半导体层，所述像素电极为金属氧化物半导体进行导体化形成的金属氧化物导电层，所述薄膜晶体管的沟道区与所述像素电极使用同一金属氧化物半导体层图案化后形成。
可选地，所述薄膜晶体管包括栅极，所述栅极位于所述沟道区与所述基板之间；所述薄膜晶体管包括公共电极和辅助层，所述辅助层与所述公共电极通过同一个金属氧化物半导体薄膜形成，所述辅助层和所述公共电极为一体结构，所述栅极设置在所述辅助层上，所述公共电极至少包含所述栅极未覆盖的所述金属氧化物半导体薄膜通过导体化工艺形成的导电层。
可选地，所述辅助层为IGZO半导体膜层，所述公共电极为IGZO导电层。
可选地，所述薄膜晶体管包括源漏极，所述像素电极包含多个条状电极，所述沟道区与所述像素电极的其中一个边缘的条状电极连接为一体结构，所述源漏极设置在所述沟道区上，所述源漏极包括源极和漏极，所述漏极覆盖 部分所述像素电极并与所述像素电极搭接。
可选地，所述阵列基板包括钝化层，所述钝化层覆盖所述源漏极、所述沟道区以及露出像素电极区域的未导体化的金属氧化物半导体层，对所述露出的金属氧化物半导体层进行离子注入形成导体化的像素电极。
可选地，所述薄膜晶体管包括栅极和栅极绝缘层，所述沟道区位于所述栅极与所述基板之间，所述栅极绝缘层覆盖所述沟道区，所述栅极设置在所述栅极绝缘层上；所述薄膜晶体管还包括连接所述沟道区与所述像素电极的辅助导电层，所述沟道区位于所述辅助导电层之间，所述辅助导电层、所述沟道区与所述像素电极通过同一个金属氧化物半导体薄膜形成，所述辅助导电层和所述像素电极包括所述栅极绝缘层被所述栅极覆盖的区域未覆盖的所述金属氧化物半导体薄膜通过导体化工艺形成的导电层。
可选地，所述沟道区为IGZO半导体膜层，所述辅助导电层和所述像素电极为IGZO导电层。
可选地，所述像素电极包含多个条状电极，所述辅助导电层与所述像素电极的其中一个边缘的条状电极连接为一体结构。
可选地，所述薄膜晶体管包括公共电极，形成在所述公共电极上的图案化的遮光部，形成在所述遮光部上的图案化的光刻胶层，覆盖所述公共电极、所述遮光部和所述光刻胶层的第一缓冲层，所述沟道区和所述像素电极形成在所述第一缓冲层上。
可选地，所述薄膜晶体管还包括图案化的层间绝缘层，所述层间绝缘层覆盖所述栅极、靠近所述沟道区的所述辅助导电层的边缘，以及部分覆盖位于所述栅极靠近所述像素电极一侧的所述辅助导电层，所述像素电极在所述基板上的正投影与所述层间绝缘层在所述基板上的正投影不重叠。
可选地，所述薄膜晶体管还包括源漏极和第二缓冲层，所述源漏极设置在所述层间绝缘层上，所述源漏极包括源极和漏极，所述源极与位于所述栅极远离所述像素电极一侧且露出所述层间绝缘层的所述辅助导电层连接，所述漏极与位于所述栅极靠近所述像素电极一侧且露出所述层间绝缘层的所述辅助导电层连接，所述第二缓冲层覆盖所述源漏极和部分所述层间绝缘层，所述像素电极在所述基板上的正投影与所述第二缓冲层在所述基板上的正投影不重叠。
本公开还提供了一种阵列基板的制备方法，所述阵列基板包括阵列排布的多个子像素和驱动各所述子像素的薄膜晶体管，所述方法包括：
通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层；所述第一金属氧化物半导体层远离所述基板的一侧设置有遮挡层；
在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分被导体化，形成所述薄膜晶体管的像素电极。
可选地，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层之前，还包括：
在所述基板上形成第二金属氧化物半导体材料层；
在所述第二金属氧化物半导体材料层上形成栅极材料层；
通过半色调掩膜工艺，对所述第二金属氧化物半导体材料层进行图案化形成第二金属氧化物半导体层，以及对所述栅极材料层进行图案化形成栅极；
形成覆盖所述第二金属氧化物半导体层和所述栅极的栅极绝缘材料层；
在所述栅极的遮挡下，对所述第二金属氧化物半导体层进行导体化，未被所述栅极遮挡的部分所述第二金属氧化物半导体层被导体化，且被导体化的部分朝所述栅极的方向扩散，形成公共电极，所述第二金属氧化物半导体层的其余部分未被导体化，形成辅助层；
对栅极绝缘材料层图案化形成栅极绝缘层。
可选地，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层，包括：
在所述栅极绝缘层上形成第一金属氧化物半导体材料层；
在所述第一金属氧化物半导体材料层上形成源漏极材料层；
通过半色调掩膜工艺，对所述第一金属氧化物半导体材料层进行图案化形成第一金属氧化物半导体层，以及对所述源漏极材料层进行图案化形成源漏极；
图案化形成钝化层；所述钝化层覆盖所述源漏极，以及靠近所述源漏极的部分所述第一金属氧化物半导体层；所述钝化层为所述遮挡层。
可选地，所述在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分被导体化，形成所述薄膜晶体管的像素电极，包括：
在所述钝化层的遮挡下，对所述第一金属氧化物半导体层进行导体化，未被所述钝化层遮挡的所述第一金属氧化物半导体层被导体化，且被导体化的部分朝所述源漏极的方向扩散，形成所述薄膜晶体管的像素电极，所述第一金属氧化物半导体层的其余部分未被导体化，形成所述薄膜晶体管的沟道区。
可选地，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层之前，还包括：
在所述基板上形成公共电极材料层；
在所述公共电极材料层上形成遮光材料层；
通过半色调掩膜工艺，对所述公共电极材料层进行图案化形成公共电极，以及对所述遮光材料层进行图案化形成遮光层；形成所述遮光层所需的光刻胶部分保留，在所述遮光层上形成图案化的光刻胶层；
形成覆盖所述公共电极、所述遮光部和所述光刻胶层的第一缓冲层。
可选地，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层，包括：
在所述第一缓冲层上图案化形成第一金属氧化物半导体层；
在所述第一金属氧化物半导体层上图案化形成栅极绝缘层和栅极；所述栅极设置在所述栅极绝缘层上，所述栅极为所述遮挡层。
可选地，所述在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分被导体化，形成所述薄膜晶体管的像素电极，包括：
在所述栅极的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述栅极遮挡的所述第一金属氧化物半导体层未被导体化，形成所述薄膜晶 体管的沟道区，所述第一金属氧化物半导体层的其余部分被导体化，形成辅助导电层和所述薄膜晶体管的像素电极；所述辅助导电层连接所述沟道区与所述像素电极，所述沟道区位于所述辅助导电层之间。
可选地，所述在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分被导体化，形成所述薄膜晶体管的像素电极之后，还包括：
图案化形成层间绝缘材料层；所述层间绝缘材料层覆盖所述栅极、靠近所述沟道区的所述辅助导电层的边缘、部分覆盖位于所述栅极靠近所述像素电极一侧的所述辅助导电层，以及所述像素电极；
在所述层间绝缘材料层上图案化形成源漏极；所述源漏极包括源极和漏极，所述源极与位于所述栅极远离所述像素电极一侧且露出所述层间绝缘材料层的所述辅助导电层连接，所述漏极与位于所述栅极靠近所述像素电极一侧且露出所述层间绝缘材料层的所述辅助导电层连接；
形成第二缓冲材料层；
对所述第二缓冲材料层和所述层间绝缘材料层进行图案化，形成第二缓冲层和层间绝缘层；所述像素电极在所述基板上的正投影与所述层间绝缘层及所述第二缓冲层在所述基板上的正投影不重叠，所述第二缓冲层覆盖所述源漏极和所述层间绝缘层。
本公开还提供了一种显示装置，包括上述阵列基板。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在 不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开实施例的一种阵列基板的剖视图；
图2示出了本公开实施例的另一种阵列基板的剖视图；
图3示出了本公开实施例的一种阵列基板的制备方法的步骤流程图；
图4-10示出了本公开实施例的阵列基板的制备方法流程的剖视图；
图11示出了本公开实施例的IGZO导体化前后以及烘烤后的阻抗数据；
图12示出了本公开实施例的IGZO导体化前后以及烘烤后的透过率数据；
图13示出了本公开实施例的IGZO的部分制备条件及IGZO导体化的横向扩散距离；
图14-22示出了本公开实施例的阵列基板的制备方法流程的剖视图；
图23-36示出了本公开实施例的阵列基板的制备方法流程的剖视图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等方位词仅用于表示基于附图的相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1示出了本公开实施例的一种阵列基板的剖视图，图2示出了本公开实施例的另一种阵列基板的剖视图，参照图1和图2，阵列基板包括基板(图1中标识为200，图2中标识为100)，以及在基板上阵列排布的多个子像素和驱动各子像素的薄膜晶体管，阵列基板包括像素电极(图1中标识为204-3，图2中标识为105-2)。
其中，薄膜晶体管的沟道区(图1中标识为204-2，图2中标识为105-1)包含金属氧化物半导体层，像素电极为金属氧化物半导体进行导体化形成的金属氧化物导电层，薄膜晶体管的沟道区与像素电极使用同一金属氧化物半导体层图案化后形成。
在本公开实施例中，薄膜晶体管的沟道区与像素电极可以使用同一金属氧化物半导体层图案化后形成，其中，薄膜晶体管的沟道区可以包含未导体化的金属氧化物半导体层，像素电极可以为金属氧化物半导体进行导体化形成的金属氧化物导电层，如此，薄膜晶体管的沟道区和像素电极可以基于同一层金属氧化物半导体材料，先进行一次图案化，形成沟道区的金属氧化物半导体图案，以及像素电极对应的金属氧化物半导体图案，然后在遮挡沟道区图案的情况下，对像素电极对应的图案进行金属氧化物半导体的导体化，从而形成半导体的金属氧化物沟道区，以及导电的金属氧化物像素电极。在本公开实施例中，仅需要图案化一次，即可形成沟道区和像素电极，减少了掩膜版图案化工序，简化了工艺步骤，降低了工艺复杂度，从而降低了生产成本，提高产品的市场竞争力，具有广泛的应用前景。
在一些可选的实施例中，参照图1，薄膜晶体管包括栅极202，栅极202可以位于沟道区204-2与基板200之间。
也即是在一些可选的实施例中，阵列基板可以采用底栅结构的氧化物薄膜晶体管，该阵列基板的栅极202靠近基板200设置，沟道区204-2则位于栅极202远离基板200的一侧。在本公开实施例中，对于采用底栅结构氧化物薄膜晶体管的阵列基板，仅通过一次图案化，即可形成沟道区和像素电极，从而减少了底栅结构氧化物薄膜晶体管的阵列基板的掩膜版图案化工序，简化了底栅结构氧化物薄膜晶体管的阵列基板的工艺步骤，降低了底栅结构氧化物薄膜晶体管的阵列基板的工艺复杂度。
其中，薄膜晶体管包括公共电极201-2和辅助层201-1，辅助层201-1与 公共电极201-2通过同一个金属氧化物半导体薄膜形成，辅助层201-1和公共电极201-2为一体结构，栅极202设置在辅助层201-1上，公共电极201-2至少包含栅极202未覆盖的金属氧化物半导体薄膜通过导体化工艺形成的导电层。
辅助层201-1和公共电极201-2可以为一体结构，因此，辅助层201-1和公共电极201-2可以基于同一金属氧化物半导体层形成。另外，栅极202可以设置在辅助层201-1上，部分公共电极201-2不被栅极202所覆盖，如此，仅通过一次图案化，即可形成栅极图案和公共电极图案。在本公开实施例中，仅需要图案化一次，即可形成栅极和公共电极，从而在一次图案化形成沟道区和像素电极的基础上，又进一步减少了掩膜版图案化工序，简化了工艺步骤，降低了工艺复杂度。
具体地，在一种可选的实现方式中，辅助层201-1可以为IGZO(氧化镓铟锌)半导体膜层，公共电极201-2可以为IGZO导电层。
可以首先形成一层IGZO材料，然后对该层IGZO材料进行图案化，再以图案化的栅极为遮挡，对图案化的IGZO材料层进行导体化，IGZO材料层中被栅极遮挡而未被导体化的部分作为辅助层201-1，IGZO材料层中未被栅极遮挡而被导体化的部分作为公共电极201-2。
在该实现方式中，导体化的IGZO会朝栅极202的方向发生横向扩散，从而使得栅极202覆盖部分导体化的IGZO，也即覆盖部分公共电极201-2，IGZO导体化横向扩散后可以与栅极202形成欧姆接触，如此，可以实现栅极202与公共电极201-2的电连接。
在另一种可选的实现方式中，辅助层201-1和公共电极201-2均可以为ITO(氧化铟锡)导电层。
可以首先形成一层ITO材料，然后对该层ITO材料进行图案化，在常规的工艺中，图案化后需要进行烘烤处理，经过烘烤处理后，该层ITO材料会全部转换为导体，从而使得辅助层201-1和公共电极201-2都为导体化的ITO。
在该实现方式中，由于ITO材料在常规的烘烤工艺中同时实现了烘烤和导体化，因此，无需单独进行公共电极的导体化工艺，进一步减少了阵列基基板的制备工序，简化了工艺步骤，降低了工艺复杂度。
在该实现方式中，整层ITO都被导体化，可看作是栅极202覆盖了部分 导体化的IGZO，也即覆盖部分公共电极201-2。
可选地，参照图1，薄膜晶体管包括源漏极205，像素电极204-3包含多个条状电极，沟道区204-2与像素电极204-3的其中一个边缘的条状电极连接为一体结构，源漏极205设置在沟道区204-2上，源漏极205包括源极205-1和漏极205-2，漏极205-2覆盖部分像素电极204-3并与像素电极204-3搭接。
其中，薄膜晶体管的源漏极205位于沟道区204-2上，部分像素电极204-3不被源漏极205所覆盖，如此，仅通过一次图案化，即可形成包括沟道区204-2、像素电极204-3和源漏极205。在本公开实施例中，仅需要图案化一次，即可形成沟道区、像素电极和源漏极，从而在一次图案化形成沟道区和像素电极的基础上，又进一步减少了掩膜版图案化工序，简化了工艺步骤，降低了工艺复杂度。像素电极是由金属氧化物半导体层进行导体化形成，无需通过源极或漏极挖孔搭接像素电极，因此适合高PPI(像素密度)产品的生产，有利于提高显示产品在市场的竞争力。
具体地，在一种可选的实现方式中，沟道区204-2为IGZO半导体膜层，像素电极204-3为IGZO导电层。
可以首先形成一层IGZO材料，然后对该层IGZO材料进行图案化，再以覆盖沟道区204-2和源漏极205、且露出部分IGZO材料的其他膜层为遮挡，对图案化的IGZO材料层进行导体化，IGZO材料层中被其他膜层遮挡而未被导体化的部分作为沟道区204-2，IGZO材料层中未被其他膜层遮挡而被导体化的部分作为像素电极204-3。
在该实现方式中，导体化的IGZO会朝源漏极205的方向发生横向扩散，从而使得源漏极205覆盖部分导体化的IGZO，也即覆盖部分像素电极204-3，IGZO导体化横向扩散后可以与源漏极205形成欧姆接触，如此，可以实现源漏极205与像素电极204-3的电连接。
还可选地，参照图1，阵列基板还包括钝化层206，钝化层206覆盖源漏极205、沟道区204-2以及露出像素电极区域的未导体化的金属氧化物半导体层，对露出的金属氧化物半导体层进行离子注入形成导体化的像素电极204-3。
其中，该钝化层206即可作为上述具体示例中起遮挡作用的膜层。具体地，可以在形成沟道区204-2、源漏极205和像素电极204-3对应图案之后，形成钝化材料层，并进行图案化形成钝化层206，然后以图案化的钝化层206 为遮挡，对图案化的IGZO材料层进行导体化，IGZO材料层中被钝化层206遮挡而未被导体化的部分作为沟道区204-2，IGZO材料层中未被钝化层206遮挡而被导体化的部分作为像素电极204-3。钝化层可以在导体化过程中保护沟道区，避免沟道区被导体化，并且钝化层还能够保护已制好的源漏极，提高了阵列基板的性能。
在另一些可选的实施例中，参照图2，薄膜晶体管包括栅极106和栅极绝缘层107，沟道区105-1可以位于栅极106与基板100之间。
也即是在另一些可选的实施例中，阵列基板可以采用顶栅结构的氧化物薄膜晶体管，该阵列基板的沟道区105-1靠近基板100设置，栅极106则位于沟道区105-1远离基板100的一侧。在本公开实施例中，对于采用顶栅结构氧化物薄膜晶体管的阵列基板，仅通过一次图案化，即可形成沟道区和像素电极，从而减少了顶栅结构氧化物薄膜晶体管的阵列基板的掩膜版图案化工序，简化了顶栅结构氧化物薄膜晶体管的阵列基板的工艺步骤，降低了顶栅结构氧化物薄膜晶体管的阵列基板的工艺复杂度。
其中，栅极绝缘层107覆盖沟道区105-1，栅极106设置在栅极绝缘层107上，薄膜晶体管还包括连接沟道区105-1与像素电极105-2的辅助导电层105-3，沟道区105-1位于辅助导电层105-3之间，辅助导电层105-3、沟道区105-1与像素电极105-2通过同一个金属氧化物半导体薄膜形成，辅助导电层105-3和像素电极105-2包括栅极绝缘层107被栅极106覆盖的区域未覆盖的金属氧化物半导体薄膜通过导体化工艺形成的导电层。
参照图2，可以以栅极106作为遮挡，对同一个金属氧化物半导体薄膜进行导体化，其中，栅极106所遮挡而未被导体化的金属氧化物半导体薄膜区域形成沟道区105-1，被导体化的金属氧化物半导体薄膜区域形成辅助导电层105-3和像素电极105-2。其中，辅助导电层105-3的大部分被其他膜层所覆盖，不裸露在外，像素电极105-2则不被其他膜层所覆盖，裸露在外。辅助导电层105-3可以在沟道区105-1与像素电极105-2之间起电连接的作用，辅助导电层105-3分布在沟道区105-1的两侧，且辅助导电层105-3上具有源极和漏极的接触区域。
具体地，在一种可选的实现方式中，沟道区105-1为IGZO半导体膜层， 辅助导电层105-3和像素电极105-2为IGZO导电层。
可以首先形成一层IGZO材料，然后对该层IGZO材料进行图案化，再以图案化的栅极为遮挡，对图案化的IGZO材料层进行导体化，IGZO材料层中被栅极遮挡而未被导体化的部分作为沟道区105-1，IGZO材料层中未被栅极遮挡而被导体化的部分作为辅助导电层105-3和像素电极105-2。
可选地，参照图2，像素电极105-2可以包含多个条状电极，辅助导电层与像素电极的其中一个边缘的条状电极连接为一体结构。
接着以上述IGZO材料层形成沟道区105-1、辅助导电层105-3和像素电极105-2为例，IGZO材料层中未被栅极遮挡而被导体化的部分作为辅助导电层105-3和像素电极105-2，其中，图案化为多个条状的导体化部分即为像素电极105-2，除未导体化的沟道区105-1，以及导体化的像素电极105-2，其余的金属氧化物半导体薄膜区域即为导体化的辅助导电层105-3。
可选地，薄膜晶体管包括公共电极101，形成在公共电极101上的图案化的遮光部102，形成在遮光部102上的图案化的光刻胶层103-3，覆盖公共电极101、遮光部102和光刻胶层103-3的第一缓冲层104，沟道区105-1和像素电极105-2形成在第一缓冲层104上。
参照图2，公共电极101、遮光部102和光刻胶层103-3上都具有露出基板100的空隙。该空隙的设计可使薄膜晶体管与公共电极在显示面板的叠层方向上不存在交叠，可以减少公共电极与薄膜晶体管上的栅极和源漏极之间的耦合电容。当然，本领域技术人员应理解，本公开实施例并不限制薄膜晶体管的具体形状和位置，只要能够满足间隔开薄膜晶体管与该子像素的像素电极和像素电极下方的公共电极的功能即可。具有绝缘性的第一缓冲层104位于公共电极101与像素电极105-2之间，使公共电极101与像素电极105-2之间不存在导通。
可选地，薄膜晶体管还包括图案化的层间绝缘层108，层间绝缘层108覆盖栅极106、靠近沟道区105-1的辅助导电层105-3的边缘，以及部分覆盖位于栅极106靠近像素电极105-2一侧的辅助导电层105-3，像素电极105-2在基板100上的正投影与层间绝缘层108在基板100上的正投影不重叠。
其中，辅助导电层105-3露出层间绝缘层108的区域包括源极和漏极的连接区域，且像素电极105-2和层间绝缘层108在显示面板的叠层方向上不存在 交叠，像素电极105-2从层间绝缘层108露出。
可选地，薄膜晶体管还包括源漏极109和第二缓冲层110，源漏极109设置在层间绝缘层108上，源漏极109包括源极109-1和漏极109-2，源极109-1与位于栅极106远离像素电极105-2一侧且露出层间绝缘层108的辅助导电层105-3连接，漏极109-2与位于栅极106靠近像素电极105-2一侧且露出层间绝缘层108的辅助导电层105-3连接，第二缓冲层110覆盖源漏极109和部分层间绝缘层108，像素电极105-2在基板100上的正投影与第二缓冲层110在基板110上的正投影不重叠。
其中，薄膜晶体管的源漏极109设置在层间绝缘层108上，并与露出层间绝缘层108的辅助导电层105-3连接，其中的源极109-1所连接的辅助导电层部分位于栅极106远离像素电极105-2的一侧，漏极109-2所连接的辅助导电层部分位于栅极106靠近像素电极105-2的一侧。另外，像素电极105-2和第二缓冲层110在显示面板的叠层方向上不存在交叠，且第二缓冲层110只覆盖部分层间绝缘层108，因此，第二缓冲层110和层间绝缘层108均未对像素电极105-2形成遮挡，从而可使像素电极105-2裸露在外。
在本公开实施例中，薄膜晶体管的沟道区与像素电极可以使用同一金属氧化物半导体层图案化后形成，其中，薄膜晶体管的沟道区可以包含未导体化的金属氧化物半导体层，像素电极可以为金属氧化物半导体进行导体化形成的金属氧化物导电层，如此，薄膜晶体管的沟道区和像素电极可以基于同一层金属氧化物半导体材料，先进行一次图案化，形成沟道区的金属氧化物半导体图案，以及像素电极对应的金属氧化物半导体图案，然后在遮挡沟道区图案的情况下，对像素电极对应的图案进行金属氧化物半导体的导体化，从而形成半导体的金属氧化物沟道区，以及导电的金属氧化物像素电极。在本公开实施例中，仅需要图案化一次，即可形成沟道区和像素电极，减少了掩膜版图案化工序，简化了工艺步骤，降低了工艺复杂度。
参照图3，示出了本公开实施例的一种阵列基板的制备方法的步骤流程图，阵列基板包括阵列排布的多个子像素和驱动各子像素的薄膜晶体管，该制备方法包括以下步骤：
步骤101：通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层； 第一金属氧化物半导体层远离基板的一侧设置有遮挡层。
步骤102：在遮挡层的遮挡下，对第一金属氧化物半导体层进行导体化，被遮挡层遮挡的第一金属氧化物半导体层中的至少部分未被导体化，形成薄膜晶体管的沟道区，未被遮挡层遮挡的第一金属氧化物半导体层中的至少部分被导体化，形成薄膜晶体管的像素电极。
其中，可以通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层，并在遮挡层的遮挡下，对第一金属氧化物半导体层进行导体化，被遮挡层遮挡的第一金属氧化物半导体层中的至少部分未被导体化，从而可以形成薄膜晶体管的沟道区，未被遮挡层遮挡的第一金属氧化物半导体层中的至少部分被导体化，则可以形成薄膜晶体管的像素电极。如此，薄膜晶体管的沟道区和像素电极可以基于同一层金属氧化物半导体材料，先进行一次图案化，形成沟道区的金属氧化物半导体图案，以及像素电极对应的金属氧化物半导体图案，然后在遮挡沟道区图案的情况下，对像素电极对应的图案进行金属氧化物半导体的导体化，从而形成半导体的金属氧化物沟道区，以及导电的金属氧化物像素电极。在本公开实施例中，仅需要图案化一次，即可形成沟道区和像素电极，减少了掩膜版图案化工序，简化了工艺步骤，降低了工艺复杂度。
对于包括底栅结构的氧化物薄膜晶体管的阵列基板，在步骤101之前，还可以包括以下步骤：
在基板上形成第二金属氧化物半导体材料层；
在第二金属氧化物半导体材料层上形成栅极材料层；
通过半色调掩膜工艺，对第二金属氧化物半导体材料层进行图案化形成第二金属氧化物半导体层，以及对栅极材料层进行图案化形成栅极；
形成覆盖第二金属氧化物半导体层和栅极的栅极绝缘层；
在栅极的遮挡下，对第二金属氧化物半导体层进行导体化，未被栅极遮挡的部分第二金属氧化物半导体层被导体化，且被导体化的部分朝栅极的方向扩散，形成公共电极，第二金属氧化物半导体层的其余部分未被导体化，形成辅助层。
具体地，例如，基板200可以为玻璃基板，当然这仅是示例性的，本公开并不旨在进行限制。
参照图4，首先可以在基板200上形成第二金属氧化物半导体材料层201-1，例如IGZO、ITO等。然后可以形成栅极材料层202-1，栅极材料层202-1覆盖先前形成的第二金属氧化物半导体材料层201-1。其中，栅极材料层202-1可以包括保护金属和栅极金属的双层结构，栅极金属更靠近基板，保护金属例如可以是钛(Ti)、银(Ag)、钼(Mo)、钼铌合金(MoNb)等，栅极金属例如可以是铜(Cu)。保护金属可以对栅极金属起到保护作用，在实际应用中，保护金属的厚度比栅极金属小很多。
然后，参照图5，可以在栅极材料层202-1上涂布光刻胶，并采用半色调掩膜版(Half Tone Mask)对光刻胶进行曝光，形成如图5所示的光刻胶001图形，其中，半色调掩膜版上对应光刻后需保留部分的区域，与对应光刻后需去除部分的区域具有不同的透过率。在该步骤中，进行了第1次掩膜版工艺。
然后，可以对栅极材料层202-1进行刻蚀，在一可选的示例中，可以采用Cu酸刻蚀栅极材料层202-1，刻蚀后的图形如图6所示。之后，可以对第二金属氧化物半导体材料层201-1进行刻蚀，得到第二金属氧化物半导体层201。在一可选的示例中，可以采用草酸刻蚀第二金属氧化物半导体材料层201，刻蚀后的图形如图7所示。在实际应用中，还可以采用含氟(F)的Cu酸对栅极材料层202-1和第二金属氧化物半导体材料层201-1进行一次刻蚀，即可得到图7所示的图形，这样可以节省一次刻蚀工艺，简化了工艺步骤，降低了工艺复杂度。
光刻胶001上对应第二金属氧化物半导体层201不同位置的厚度不同。其中，光刻胶001较厚的位置可用于形成栅极辅助层，光刻胶001较薄的位置可用于形成公共电极。
刻蚀之后，可以对光刻胶001进行灰化，例如通过氧气对光刻胶001进行灰化，从而将厚度较薄的光刻胶部分去除，灰化后的光刻胶002图形如图8所示。进而再对栅极材料层202-1进行一次刻蚀，得到栅极202，光刻胶剥离后的图形如图9所示。在一可选的示例中，可以再次采用Cu酸刻蚀栅极材料层202-1。
之后，参照图10，可以形成覆盖第二金属氧化物半导体层201和栅极202的栅极绝缘材料层203-1，然后再进行第二金属氧化物半导体层201的导体化 处理。
具体地，在一些实施例中，第二金属氧化物半导体层201可以采用IGZO材料，IGZO材料经过烘烤仍然为半导体，因此，需要在之后的过程中通过导体化转化为导体。对第二金属氧化物半导体层201进行导体化处理后，未被栅极202遮挡的部分第二金属氧化物半导体层被导体化，且被导体化的部分朝栅极202的方向扩散，形成公共电极201-2，第二金属氧化物半导体层的其余部分未被导体化，形成辅助层201-1。其中，辅助层201-1为未导体化的IGZO半导体膜层，公共电极201-2为导体化的IGZO导电层。其中，被导体化的部分会朝栅极202的方向扩散，导体化的横向扩散距离为L1，导体化扩散的部分也为公共电极201-2的一部分，如图10所示。
其中，示例性地，可以在氢气环境下对IGZO材料的第二金属氧化物半导体层201进行等离子体(plasma)处理，从而实现第二金属氧化物半导体层201的导体化，导体化的IGZO透过率提升。
IGZO导体化前后以及烘烤后的阻抗数据如图11所示，透过率数据如图12所示。以
Figure PCTCN2021127669-appb-000001
厚度的IGZO为例，500W的H2 plasma处理30秒，并进行280℃烘烤后，IGZO的方块阻抗可降低至150Ω，透过率提升至87％，可满足公共电极的导电需求及透过率需求。
此外，IGZO导体化的横向扩散距离L(包括图示中的L1和L2)可以通过一些工艺参数进行调控，例如参照图13，可以通过控制IGZO成膜时的氧气含量、退火温度，来控制IGZO导体化的横向扩散距离L。图13仅列出了一写可选的调控参数，可以理解的是，还可以通过单一变量法来确定其他的调控参数。例如，以
Figure PCTCN2021127669-appb-000002
厚度的IGZO为例，300W的H2 plasma处理30秒后，IGZO导体化横向扩散距离超过3.7um，且IGZO导体化横向扩散距离可随导体化功率和时间的增加而增加。
需要说明的是，图13仅示例性地示出了一些IGZO样品的部分制备条件，以及这些IGZO样品的导体化横向扩散距离L的实际范围，可以理解的是，当一些其他制备条件发生变化时，导体化横向扩散距离L测量结果不一定如图13所示。
可选地，在另一些实施例中，第二金属氧化物半导体层201还可以采用ITO材料，ITO材料经过烘烤可成为导体，通过半色调掩膜工艺对第二金属氧 化物半导体层201进行图案化后，形成的第一金属氧化物半导体子层直接作为辅助层，形成的第二金属氧化物半导体子层直接作为公共电极，辅助层和公共电极均为导体化的ITO导电层。
如此，仅需要图案化一次，即可形成栅极和公共电极，无需额外进行离子注入的导体化处理，减少了掩膜版图案化工序，简化了工艺步骤，降低了工艺复杂度。
导体化处理之后，可以根据需求，对栅极绝缘材料层203-1进行图案化形成栅极绝缘层203，如图14所示。在该步骤中，进行了第2次掩膜版工艺。
在一些实施例中，可选地，步骤101具体可以包括：
在栅极绝缘层上形成第一金属氧化物半导体材料层；
在第一金属氧化物半导体材料层上形成源漏极材料层；
通过半色调掩膜工艺，对第一金属氧化物半导体材料层进行图案化形成第一金属氧化物半导体层，以及对源漏极材料层进行图案化形成源漏极；
图案化形成钝化层；钝化层覆盖源漏极，以及靠近源漏极的部分第一金属氧化物半导体层；钝化层为遮挡层。
其中，参照图15，可以在栅极绝缘层203上形成第一金属氧化物半导体材料层204-4，例如IGZO、ITO等。然后可以形成源漏极材料层205-1，源漏极材料层205-1覆盖先前形成的第一金属氧化物半导体材料层204-4。其中，与栅极材料层类似，源漏极材料层205-1也可以包括保护金属和源漏极金属的双层结构，源漏极金属更靠近基板，保护金属包括但不限于Ti、Ag、Mo、MoNb合金等，源漏极金属例如可以是Cu。保护金属可以对源漏极金属起到保护作用，在实际应用中，保护金属的厚度比源漏极金属小很多。
之后，参照图16，可以在源漏极材料层205-1上涂布光刻胶，并采用半色调掩膜版(Half Tone Mask)对光刻胶进行曝光，形成如图16所示的光刻胶003图形，其中，半色调掩膜版上对应光刻后需保留部分的区域，与对应光刻后需去除部分的区域具有不同的透过率。在该步骤中，进行了第3次掩膜版工艺。
然后，可以对源漏极材料层205-1进行刻蚀，在一可选的示例中，可以采用Cu酸刻蚀源漏极材料层205-1，刻蚀后的图形如图17所示。之后，可以对第一金属氧化物半导体材料层204-4进行刻蚀，得到第一金属氧化物半导体层 204-1。在一可选的示例中，可以采用草酸刻蚀第一金属氧化物半导体材料层204-4，刻蚀后的图形如图18所示。在实际应用中，还可以采用含F的Cu酸对源漏极材料层205-1和第一金属氧化物半导体材料层204-4进行一次刻蚀，即可得到图18所示的图形，这样可以节省一次刻蚀工艺，简化了工艺步骤，降低了工艺复杂度。
光刻胶003上不同位置的厚度不同。其中，光刻胶003较厚的位置可用于形成源漏极位置，光刻胶003较厚的位置以及较厚位置之间的较薄位置可用于形成沟道区，其余的光刻胶003较薄的位置可用于形成像素电极。
刻蚀之后，可以对光刻胶003进行灰化，例如通过氧气对光刻胶进行灰化，从而将厚度较薄的光刻胶部分去除，灰化后的光刻胶004图形如图19所示。进而再对源漏极材料层205-1进行一次刻蚀，得到源漏极205，光刻胶剥离后的图形如图20所示。在一可选的示例中，可以再次采用Cu酸刻蚀源漏极材料层205-1。
然后，可以形成钝化材料层，并对钝化材料层进行图案化形成钝化层206，形成的钝化层图形如图21所示，其中，钝化层206覆盖源漏极205，以及靠近源漏极205的部分第一金属氧化物半导体层204-1。在该步骤中，进行了第4次掩膜版工艺。
在本步骤中，可以先设置钝化层206，再对第一金属氧化物半导体层204-1进行导体化，钝化层206可以在导体化过程中保护沟道区，避免沟道区被导体化，并且钝化层206还能够保护已制好的源漏极205，提高了阵列基板的性能。另外，若像素电极顶部被钝化层206覆盖，则像素电极与公共电极形成的电场会很弱，只有侧面电场，因此，图案化的钝化层可以将像素电极露出，保证了像素电极与公共电极所形成的电场强度。
其中，钝化层206可以作为步骤101中所述的遮挡层，相应地，步骤202具体可以包括：
在钝化层206的遮挡下，对第一金属氧化物半导体层204-1进行导体化，未被钝化层206遮挡的第一金属氧化物半导体层204-1被导体化，且被导体化的部分朝源漏极205的方向扩散，形成薄膜晶体管的像素电极204-3，第一金属氧化物半导体层204-1的其余部分未被导体化，形成薄膜晶体管的沟道区204-2。
参照图22，在第一金属氧化物半导体层204-1采用IGZO材料的情况下，可以通过例如氢气气氛下等离子体处理等方式，对第一金属氧化物半导体层204-1进行导体化处理后，未被钝化层206遮挡的第一金属氧化物半导体层204-1被导体化，形成像素电极204-3，第一金属氧化物半导体层204-1的其余部分未被导体化，形成沟道区204-2。其中，沟道区204-2为未导体化的IGZO半导体膜层，像素电极204-3为导体化的IGZO导电层。其中，被导体化的部分会朝源漏极205的方向扩散，导体化的横向扩散距离为L2，IGZO导体化横向扩散后可以与源漏极205形成欧姆接触，实现源漏极205与像素电极204-3的电连接。导体化后的像素电极204-3透过率提升，沟道区204-2因钝化层206的保护不会被导体化，可维持半导体特性，至此，阵列基板制程完成。
在本公开实施例中，仅通过4次图案化，也即4道掩膜版工艺，便可实现包括底栅结构氧化物薄膜晶体管的阵列基板的制备，相较于底栅结构目前的6道掩膜版工艺，能够减少掩膜版图案化工序，简化工艺步骤，降低工艺复杂度。
需要说明的是，本公开实施例的各图示中仅示出一个像素电极和与之对应的薄膜晶体管部分，图中像素电极示出多个部分是因为像素电极为镂空图案，剖视图中截取为多个中断的部分，本申请不作具体限制。
此外，还需要说明的是，上述实施例涉及的各图示中示出的A部分，为阵列基板的端子区，用于与电路板连接，从而向阵列基板的显示区输入所需的电信号，端子区位于阵列基板的非显示区。在实际应用中，端子区中的膜层结构满足电连接及电信号传输的需求即可，各图示中示出的端子区仅为一种可选示例，且仅示出了端子区的一部分，本公开实施例并不旨在对端子区的膜层结构进行具体限定。
而对于包括顶栅结构的氧化物薄膜晶体管的阵列基板，在步骤101之前，还可以包括以下步骤：
在基板上形成公共电极材料层；
在公共电极材料层上形成遮光材料层；
通过半色调掩膜工艺，对公共电极材料层进行图案化形成公共电极，以及对遮光材料层进行图案化形成遮光层；形成遮光层所需的光刻胶部分保留， 在遮光层上形成图案化的光刻胶层；
形成覆盖公共电极、遮光部和光刻胶层的第一缓冲层。
参照图23，首先可以在基板100上形成公共电极材料层101-1，之后，在公共电极材料层101-1上形成遮光材料层102-1。
参照图24，在遮光材料层102-1上形成第一光刻胶层，并通过半色调掩膜工艺，对第一光刻胶层图案化形成第二光刻胶层103。第二光刻胶层103包括第一区域和第二区域，第二区域的厚度小于第一区域的厚度，该第二区域用于后续步骤中形成遮光部。在该步骤中，进行了第1次掩膜版工艺。
参照图25，基于第二光刻胶层103对遮光材料层102-1进行刻蚀形成遮光子层102-2。
参照图26，基于第二光刻胶层103对公共电极材料层101-1进行刻蚀形成公共电极101。
参照图27，对第二光刻胶层103进行第一次灰化处理去除第二区域形成第二光刻胶子层103-1。
参照图28，基于第二光刻胶子层103-1对遮光子层102-2进行湿法刻蚀形成遮光部102，遮光部102包括第一遮光部，第一遮光部在基板100上的正投影覆盖将要形成的薄膜晶体管的沟道区在基板上的正投影。
参照图29，对第二光刻胶子层103-1进行第二次灰化处理使得第二光刻胶子层内缩为在基板100上的正投影落在遮光部102在基板100上的正投影内，剩余光刻胶层103-3。在本公开的实施例中，不必去除剩余的光刻胶层103-3，保留剩余的光刻胶层103-3可以进一步降低源漏极与公共电极之间的耦合电容。
参照图30，在剩余的光刻胶层103-3上形成第一缓冲层104。
接下来，步骤101具体可以包括以下步骤：
在第一缓冲层上图案化形成第一金属氧化物半导体层；
在第一金属氧化物半导体层上图案化形成栅极绝缘层和栅极；栅极设置在栅极绝缘层上，栅极为遮挡层。
参照图31，在第一缓冲层104上形成第一金属氧化物半导体材料层，并对第一金属氧化物半导体材料层进行图案化形成第一金属氧化物半导体层105。其中，第一金属氧化物半导体层105的材料可以为IGZO。在该步骤中， 进行了第2次掩膜版工艺。
参照图32，在第一金属氧化物半导体层105上形成栅极绝缘材料层，并在栅极绝缘材料层上形成栅极材料层，然后，一次图案化形成栅极绝缘层107和栅极106，栅极106设置在栅极绝缘层107上。其中，栅极106在基板100上的正投影部分覆盖第一金属氧化物半导体层105在基板100上的正投影。在该步骤中，进行了第3次掩膜版工艺。
其中，栅极106可以作为步骤101中所述的遮挡层，相应地，步骤202具体可以包括：
在栅极106的遮挡下，对第一金属氧化物半导体层105进行导体化，被栅极106遮挡的第一金属氧化物半导体层105未被导体化，形成薄膜晶体管的沟道区105-1，第一金属氧化物半导体层105的其余部分被导体化，形成辅助导电层105-3和薄膜晶体管的像素电极105-2；辅助导电层105-3连接沟道区105-1与像素电极105-2，沟道区105-1位于辅助导电层105-3之间。
参照图33，在第一金属氧化物半导体层105采用IGZO材料的情况下，可以通过例如氢气气氛下等离子体处理等方式，对第一金属氧化物半导体层105进行导体化，第一金属氧化物半导体层105被栅极106遮挡的部分未被导体化，形成沟道区105-1，第一金属氧化物半导体层105的其余部分被导体化，形成辅助导电层105-3和薄膜晶体管的像素电极105-2。其中，沟道区105-1为未导体化的IGZO半导体膜层，辅助导电层105-3和像素电极105-2为导体化的IGZO导电层。
在步骤202之后，还可以包括以下步骤：
图案化形成层间绝缘材料层；层间绝缘材料层覆盖栅极、靠近沟道区的辅助导电层的边缘、部分覆盖位于栅极靠近像素电极一侧的辅助导电层，以及像素电极；
在层间绝缘材料层上图案化形成源漏极；源漏极包括源极和漏极，源极与位于栅极远离像素电极一侧且露出层间绝缘材料层的辅助导电层连接，漏极与位于栅极靠近像素电极一侧且露出层间绝缘材料层的辅助导电层连接；
形成第二缓冲材料层；
对第二缓冲材料层和层间绝缘材料层进行图案化，形成第二缓冲层和层间绝缘层；像素电极在基板上的正投影与层间绝缘层及第二缓冲层在基板上 的正投影不重叠，第二缓冲层覆盖源漏极和层间绝缘层。
其中，参照图34，在栅极106上沉积形成层间绝缘材料层108-1，并对其进行图案化露出需要连接源漏极的辅助导电层区域。此时的层间绝缘材料层108-1覆盖像素电极105-2。在该步骤中，进行了第4次掩膜版工艺。
然后，在层间绝缘材料层108-1上图案化形成源漏极材料层，进而图案化形成源漏极109。在该步骤中，进行了第5次掩膜版工艺。
其中，源漏极109与露出层间绝缘材料层108-1的辅助导电层105-3连接，其中的源极109-1所连接的辅助导电层部分位于栅极106远离像素电极105-2的一侧，漏极109-2所连接的辅助导电层部分位于栅极106靠近像素电极105-2的一侧。
参照图35，可以形成第二缓冲材料层110-1，并对第二缓冲材料层110-1和层间绝缘材料层108-1进行图案化，从而得到图案化的第二缓冲层110和层间绝缘层108，像素电极105露出第二缓冲层110和层间绝缘层108以形成薄膜晶体管，如图36所示。在该步骤中，进行了第6次掩膜版工艺。
进一步地，之后还可以进行以下包括：对像素电极105-2进行导体化，也就是对像素电极105-2进行二次导体化，即可得到如图2所示的阵列基板。二次导体化后的像素电极105-2能够具有进一步提升的透过率，同时可以进一步降低电阻率，具有更优良的金属特性。
在本公开实施例中，仅通过6次图案化，也即6道掩膜版工艺，便可实现包括顶栅结构氧化物薄膜晶体管的阵列基板的制备，相较于顶栅结构目前的9道掩膜版工艺，能够减少掩膜版图案化工序，简化工艺步骤，降低工艺复杂度。
需要说明的是，在上述的各制备方法中，仅以光刻胶为正性光刻胶为示例，可以理解的是，上述的各制备方法也可以采用负性光刻胶，本公开对此不作具体限定。
还需要说明的是，在本公开实施例中，由于顶栅结构与底栅结构是不同的结构，因此，在两种结构中，采用相同名称命名的膜层并不表示同一膜层，而是表示材料相同或类似、功能相同或类似的膜层。
此外，上述的各制备方法还可以包括其他等常规步骤，本公开实施例对此不作具体限定。
本公开实施例还公开了一种显示装置，包括上述阵列基板。
由于本公开实施例提供的显示装置中包括的阵列基板与上述几种实施例提供的阵列基板相对应，因此在前实施方式也适用于本实施例，在本实施例中不再详细描述。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (20)

  1. 一种阵列基板，其特征在于，包括基板，以及在所述基板上阵列排布的多个子像素和驱动各所述子像素的薄膜晶体管，所述阵列基板包括像素电极；
    所述薄膜晶体管的沟道区包含金属氧化物半导体层，所述像素电极为金属氧化物半导体进行导体化形成的金属氧化物导电层，所述薄膜晶体管的沟道区与所述像素电极使用同一金属氧化物半导体层图案化后形成。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管包括栅极，所述栅极位于所述沟道区与所述基板之间；所述薄膜晶体管包括公共电极和辅助层，所述辅助层与所述公共电极通过同一个金属氧化物半导体薄膜形成，所述辅助层和所述公共电极为一体结构，所述栅极设置在所述辅助层上，所述公共电极至少包含所述栅极未覆盖的所述金属氧化物半导体薄膜通过导体化工艺形成的导电层。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述辅助层为IGZO半导体膜层，所述公共电极为IGZO导电层。
  4. 根据权利要求2所述的阵列基板，其特征在于，所述薄膜晶体管包括源漏极，所述像素电极包含多个条状电极，所述沟道区与所述像素电极的其中一个边缘的条状电极连接为一体结构，所述源漏极设置在所述沟道区上，所述源漏极包括源极和漏极，所述漏极覆盖部分所述像素电极并与所述像素电极搭接。
  5. 根据权利要求2所述的阵列基板，其特征在于，所述阵列基板包括钝化层，所述钝化层覆盖所述源漏极、所述沟道区以及露出像素电极区域的未导体化的金属氧化物半导体层，对所述露出的金属氧化物半导体层进行离子注入形成导体化的像素电极。
  6. 根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管包括栅极和栅极绝缘层，所述沟道区位于所述栅极与所述基板之间，所述栅极绝缘层覆盖所述沟道区，所述栅极设置在所述栅极绝缘层上；所述薄膜晶体管还包括连接所述沟道区与所述像素电极的辅助导电层，所述沟道区位于所述辅助导电层之间，所述辅助导电层、所述沟道区与所述像素电极通过同一个 金属氧化物半导体薄膜形成，所述辅助导电层和所述像素电极包括所述栅极绝缘层被所述栅极覆盖的区域未覆盖的所述金属氧化物半导体薄膜通过导体化工艺形成的导电层。
  7. 根据权利要求6所述的阵列基板，其特征在于，所述沟道区为IGZO半导体膜层，所述辅助导电层和所述像素电极为IGZO导电层。
  8. 根据权利要求6所述的阵列基板，其特征在于，所述像素电极包含多个条状电极，所述辅助导电层与所述像素电极的其中一个边缘的条状电极连接为一体结构。
  9. 根据权利要求6所述的阵列基板，其特征在于，所述薄膜晶体管包括公共电极，形成在所述公共电极上的图案化的遮光部，形成在所述遮光部上的图案化的光刻胶层，覆盖所述公共电极、所述遮光部和所述光刻胶层的第一缓冲层，所述沟道区和所述像素电极形成在所述第一缓冲层上。
  10. 根据权利要求6所述的阵列基板，其特征在于，所述薄膜晶体管还包括图案化的层间绝缘层，所述层间绝缘层覆盖所述栅极、靠近所述沟道区的所述辅助导电层的边缘，以及部分覆盖位于所述栅极靠近所述像素电极一侧的所述辅助导电层，所述像素电极在所述基板上的正投影与所述层间绝缘层在所述基板上的正投影不重叠。
  11. 根据权利要求10所述的阵列基板，其特征在于，所述薄膜晶体管还包括源漏极和第二缓冲层，所述源漏极设置在所述层间绝缘层上，所述源漏极包括源极和漏极，所述源极与位于所述栅极远离所述像素电极一侧且露出所述层间绝缘层的所述辅助导电层连接，所述漏极与位于所述栅极靠近所述像素电极一侧且露出所述层间绝缘层的所述辅助导电层连接，所述第二缓冲层覆盖所述源漏极和部分所述层间绝缘层，所述像素电极在所述基板上的正投影与所述第二缓冲层在所述基板上的正投影不重叠。
  12. 一种阵列基板的制备方法，所述阵列基板包括基板，以及在所述基板上阵列排布的多个子像素和驱动各所述子像素的薄膜晶体管，其特征在于，所述方法包括：
    通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层；所述第一 金属氧化物半导体层远离所述基板的一侧设置有遮挡层；
    在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分被导体化，形成所述薄膜晶体管的像素电极。
  13. 根据权利要求12所述的方法，其特征在于，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层之前，还包括：
    在所述基板上形成第二金属氧化物半导体材料层；
    在所述第二金属氧化物半导体材料层上形成栅极材料层；
    通过半色调掩膜工艺，对所述第二金属氧化物半导体材料层进行图案化形成第二金属氧化物半导体层，以及对所述栅极材料层进行图案化形成栅极；
    形成覆盖所述第二金属氧化物半导体层和所述栅极的栅极绝缘材料层；
    在所述栅极的遮挡下，对所述第二金属氧化物半导体层进行导体化，未被所述栅极遮挡的部分所述第二金属氧化物半导体层被导体化，且被导体化的部分朝所述栅极的方向扩散，形成公共电极，所述第二金属氧化物半导体层的其余部分未被导体化，形成辅助层；
    对栅极绝缘材料层图案化形成栅极绝缘层。
  14. 根据权利要求13所述的方法，其特征在于，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层，包括：
    在所述栅极绝缘层上形成第一金属氧化物半导体材料层；
    在所述第一金属氧化物半导体材料层上形成源漏极材料层；
    通过半色调掩膜工艺，对所述第一金属氧化物半导体材料层进行图案化形成第一金属氧化物半导体层，以及对所述源漏极材料层进行图案化形成源漏极；
    图案化形成钝化层；所述钝化层覆盖所述源漏极，以及靠近所述源漏极的部分所述第一金属氧化物半导体层；所述钝化层为所述遮挡层。
  15. 根据权利要求14所述的方法，其特征在于，所述在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部 分被导体化，形成所述薄膜晶体管的像素电极，包括：
    在所述钝化层的遮挡下，对所述第一金属氧化物半导体层进行导体化，未被所述钝化层遮挡的所述第一金属氧化物半导体层被导体化，且被导体化的部分朝所述源漏极的方向扩散，形成所述薄膜晶体管的像素电极，所述第一金属氧化物半导体层的其余部分未被导体化，形成所述薄膜晶体管的沟道区。
  16. 根据权利要求12所述的方法，其特征在于，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层之前，还包括：
    在所述基板上形成公共电极材料层；
    在所述公共电极材料层上形成遮光材料层；
    通过半色调掩膜工艺，对所述公共电极材料层进行图案化形成公共电极，以及对所述遮光材料层进行图案化形成遮光层；形成所述遮光层所需的光刻胶部分保留，在所述遮光层上形成图案化的光刻胶层；
    形成覆盖所述公共电极、所述遮光部和所述光刻胶层的第一缓冲层。
  17. 根据权利要求16所述的方法，其特征在于，所述通过半色调掩膜工艺，图案化形成第一金属氧化物半导体层，包括：
    在所述第一缓冲层上图案化形成第一金属氧化物半导体层；
    在所述第一金属氧化物半导体层上图案化形成栅极绝缘层和栅极；所述栅极设置在所述栅极绝缘层上，所述栅极为所述遮挡层。
  18. 根据权利要求17所述的方法，其特征在于，所述在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分被导体化，形成所述薄膜晶体管的像素电极，包括：
    在所述栅极的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述栅极遮挡的所述第一金属氧化物半导体层未被导体化，形成所述薄膜晶体管的沟道区，所述第一金属氧化物半导体层的其余部分被导体化，形成辅助导电层和所述薄膜晶体管的像素电极；所述辅助导电层连接所述沟道区与所述像素电极，所述沟道区位于所述辅助导电层之间。
  19. 根据权利要求18所述的方法，其特征在于，所述在所述遮挡层的遮挡下，对所述第一金属氧化物半导体层进行导体化，被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分未被导体化，形成所述薄膜晶体管的沟道区，未被所述遮挡层遮挡的所述第一金属氧化物半导体层中的至少部分被导体化，形成所述薄膜晶体管的像素电极之后，还包括：
    图案化形成层间绝缘材料层；所述层间绝缘材料层覆盖所述栅极、靠近所述沟道区的所述辅助导电层的边缘、部分覆盖位于所述栅极靠近所述像素电极一侧的所述辅助导电层，以及所述像素电极；
    在所述层间绝缘材料层上图案化形成源漏极；所述源漏极包括源极和漏极，所述源极与位于所述栅极远离所述像素电极一侧且露出所述层间绝缘材料层的所述辅助导电层连接，所述漏极与位于所述栅极靠近所述像素电极一侧且露出所述层间绝缘材料层的所述辅助导电层连接；
    形成第二缓冲材料层；
    对所述第二缓冲材料层和所述层间绝缘材料层进行图案化，形成第二缓冲层和层间绝缘层；所述像素电极在所述基板上的正投影与所述层间绝缘层及所述第二缓冲层在所述基板上的正投影不重叠，所述第二缓冲层覆盖所述源漏极和所述层间绝缘层。
  20. 一种显示装置，其特征在于，包括权利要求1-11任一项所述的阵列基板。
PCT/CN2021/127669 2021-08-24 2021-10-29 一种阵列基板及其制备方法、显示装置 WO2023024256A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202180004002.6A CN116018552A (zh) 2021-08-24 2021-10-29 一种阵列基板及其制备方法、显示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110975502.6 2021-08-24
CN202110975502.6A CN113687548B (zh) 2021-08-24 2021-08-24 阵列基板及其制作方法、以及显示面板

Publications (1)

Publication Number Publication Date
WO2023024256A1 true WO2023024256A1 (zh) 2023-03-02

Family

ID=78581943

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/127669 WO2023024256A1 (zh) 2021-08-24 2021-10-29 一种阵列基板及其制备方法、显示装置

Country Status (2)

Country Link
CN (2) CN113687548B (zh)
WO (1) WO2023024256A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113687548B (zh) * 2021-08-24 2023-10-17 京东方科技集团股份有限公司 阵列基板及其制作方法、以及显示面板
CN114171457B (zh) * 2021-12-07 2023-07-04 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105068335A (zh) * 2015-08-12 2015-11-18 深圳市华星光电技术有限公司 一种ffs阵列基板的制造方法
CN105633016A (zh) * 2016-03-30 2016-06-01 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板
CN110676267A (zh) * 2019-09-29 2020-01-10 南京中电熊猫液晶显示科技有限公司 一种显示面板及其制造方法
CN113687548A (zh) * 2021-08-24 2021-11-23 京东方科技集团股份有限公司 阵列基板及其制作方法、以及显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786257B (zh) * 2019-01-18 2022-04-01 惠科股份有限公司 薄膜晶体管的制作方法、阵列基板和显示面板
CN109801952B (zh) * 2019-02-14 2021-07-23 惠科股份有限公司 显示面板及其制作方法
CN110071176B (zh) * 2019-04-08 2021-11-02 深圳市华星光电半导体显示技术有限公司 顶栅自对准金属氧化物半导体tft及其制作方法、显示面板
CN110600483A (zh) * 2019-08-30 2019-12-20 南京中电熊猫平板显示科技有限公司 一种阵列基板及其制造方法
CN210325749U (zh) * 2019-10-23 2020-04-14 成都中电熊猫显示科技有限公司 一种阵列基板及显示面板
CN111180471A (zh) * 2020-03-02 2020-05-19 南京中电熊猫平板显示科技有限公司 阵列基板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105068335A (zh) * 2015-08-12 2015-11-18 深圳市华星光电技术有限公司 一种ffs阵列基板的制造方法
CN105633016A (zh) * 2016-03-30 2016-06-01 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板
CN110676267A (zh) * 2019-09-29 2020-01-10 南京中电熊猫液晶显示科技有限公司 一种显示面板及其制造方法
CN113687548A (zh) * 2021-08-24 2021-11-23 京东方科技集团股份有限公司 阵列基板及其制作方法、以及显示面板

Also Published As

Publication number Publication date
CN116018552A (zh) 2023-04-25
CN113687548A (zh) 2021-11-23
CN113687548B (zh) 2023-10-17

Similar Documents

Publication Publication Date Title
WO2018099052A1 (zh) 阵列基板的制备方法、阵列基板及显示装置
CN106019751B (zh) 阵列基板及其制造方法、显示装置
WO2020177597A1 (zh) 阵列基板及其制备方法、显示面板和显示装置
US11087985B2 (en) Manufacturing method of TFT array substrate
WO2021036840A1 (zh) 显示基板及其制造方法、显示装置
WO2023024256A1 (zh) 一种阵列基板及其制备方法、显示装置
CN110148601B (zh) 一种阵列基板、其制作方法及显示装置
KR20100100693A (ko) Ｔｆｔ-ｌｃｄ 어레이 기판 및 그 제조 방법
TW201418855A (zh) 顯示面板之陣列基板及其製作方法
US10217851B2 (en) Array substrate and method of manufacturing the same, and display device
CN110931510B (zh) 阵列基板、显示面板及阵列基板的制备方法
CN110854205A (zh) 一种薄膜晶体管及制作方法、显示面板及显示装置
EP3709355A1 (en) Array substrate and manufacturing method therefor, and display device
JP3706043B2 (ja) 液晶用マトリクス基板の製造方法
WO2018040795A1 (zh) 一种阵列基板及其制备方法、显示面板及其制备方法
US11233072B2 (en) Array substrate, display panel and manufacturing method of array substrate
US11581339B2 (en) Pixel structure and manufacturing method therefor, array substrate, and display device
CN111128876B (zh) 一种阵列基板的制备方法
US10777686B2 (en) Thin film transistor and method for manufacturing the same, array substrate and display panel
CN107490911B (zh) 阵列基板及其制作方法和显示面板
CN203465496U (zh) 阵列基板、液晶显示装置
US20200098792A1 (en) Array substrate, manufacturing method of the array substrate, and display panel
CN111129083A (zh) 显示面板的制造方法及显示面板
CN111129084A (zh) 显示面板的制造方法及显示面板
CN113690181B (zh) Tft阵列基板及其制作方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE