WO2020238640A1 - 一种显示基板及其制作方法、显示装置 - Google Patents

一种显示基板及其制作方法、显示装置 Download PDF

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WO2020238640A1
WO2020238640A1 PCT/CN2020/090315 CN2020090315W WO2020238640A1 WO 2020238640 A1 WO2020238640 A1 WO 2020238640A1 CN 2020090315 W CN2020090315 W CN 2020090315W WO 2020238640 A1 WO2020238640 A1 WO 2020238640A1
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layer
area
metal layer
gate
display substrate
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PCT/CN2020/090315
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English (en)
French (fr)
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刘军
闫梁臣
周斌
梁亚东
刘宁
程磊磊
方金钢
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/265,789 priority Critical patent/US11961848B2/en
Publication of WO2020238640A1 publication Critical patent/WO2020238640A1/zh

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
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    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • This application relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • TFT Thin Film Transistor
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the embodiments of the present application provide a display substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the overlapped area between the gate line and the data line in the related art is prone to short circuit, which causes the panel yield to decrease.
  • an embodiment of the present application provides a display substrate, including: a base substrate, an active layer, a gate insulating layer, a first metal film layer, an interlayer insulating layer, A second metal film layer and a passivation layer; the first metal film layer includes a pattern of gates and gate lines, and the second metal film layer includes a pattern of source drains and data lines;
  • the gate line and the data line are partially disposed opposite to each other, and the surface of the opposing area of the gate line and the data line facing the data line has an oxide metal layer.
  • the opposing area includes: an overlapping area of the gate line and the data line, and an area extending along the extension direction of the gate line. Two symmetrical first regions of the overlapping region.
  • the width of the first region along the extending direction of the gate line is 2 ⁇ m-3 ⁇ m.
  • the width of the opposing area of the gate line exceeds the width of the area adjacent thereto.
  • the first metal film layer includes a first metal element
  • the oxide metal layer is an oxide of the first metal element
  • the first metal film layer includes a first metal film layer that is sequentially stacked on the side of the gate insulating layer away from the base substrate.
  • an embodiment of the present application also provides a display device, including any one of the above-mentioned display substrates provided in the embodiment of the present application.
  • an embodiment of the present application also provides a method for manufacturing any one of the foregoing display substrates, including:
  • An interlayer insulating layer, a second metal film layer and a passivation layer are sequentially formed on the oxide metal layer, and the second metal film layer includes patterns of data lines and source and drain electrodes.
  • forming a first metal film layer on the gate insulating layer specifically includes:
  • Patterning the first metal film layer to form patterns of gates and gate lines specifically includes:
  • the photoresist layer is patterned to form a photoresist pattern;
  • the photoresist pattern includes a partially reserved area, a completely reserved area, and a completely removed area; wherein the partially reserved area covers the opposite area, The completely reserved area covers the area where the gate and the gate line are located, and the completely removed area covers other areas;
  • wet etching is performed on the exposed first molybdenum metal layer, copper metal layer, aluminum metal layer, and second molybdenum metal layer to form the The gate and the pattern of the gate line.
  • forming an oxide metal layer on the surface of the region where the gate line is opposite to the data line to be formed includes:
  • the aluminum metal layer in the opposing area is oxidized by plasma containing O 2 to form an aluminum oxide layer.
  • the method before the oxidation treatment of the aluminum metal layer in the opposing area by the plasma containing O 2 , the method further includes:
  • the active layer exposed after dry etching is performed on the gate insulating layer is subjected to a conductive treatment.
  • patterning the photoresist layer specifically includes:
  • a halftone mask is used to pattern the photoresist layer; wherein, the halftone mask includes: a completely transparent area corresponding to the completely removed area, and a portion corresponding to the partially reserved area Partial light-transmitting area, and opaque area corresponding to the completely reserved area; the light transmission of the partially light-transmitting area is 75%-85% of the light transmission of the completely light-transmitting area.
  • the thickness of the photoresist layer is 2.0 ⁇ m-2.2 ⁇ m, and the photoresist pattern in the partially reserved area is The thickness is 0.3 ⁇ m-0.5 ⁇ m.
  • performing dry etching on the gate insulating layer specifically includes:
  • a combined gas of O 2 and CF 4 is used to perform dry etching treatment on the gate insulating layer, the flow of O 2 is 1000 sccm to 1500 sccm, and the flow of CF 4 is 2000 sccm to 2500 sccm.
  • FIG. 1 is a schematic diagram of the structure of a display substrate provided in the related art
  • FIG. 2 is a schematic diagram of the structure of a display substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic top view of a partial film layer of the display substrate shown in FIG. 2;
  • FIG. 7 is the fourth flow chart of the manufacturing method of the display substrate provided by the embodiment of the application.
  • 8A to 8N are schematic cross-sectional views of the manufacturing method of the display substrate provided by the embodiments of the application after each step is performed.
  • each layer of the film in the drawings do not reflect the true ratio of the display substrate, and the purpose is only to illustrate the content of the application.
  • the TFT with the top gate structure has a higher on-state current, higher aperture ratio and better TFT stability than the TFT with the bottom gate structure and has attracted attention.
  • a display substrate of a TFT with a top-gate structure in the related art includes a base substrate 1, and a light-shielding metal layer 2, a buffer layer 3, an active layer 4, and a gate which are sequentially arranged on the base substrate 1.
  • the gate metal layer 6 includes a gate 61 and a gate line 62
  • the source-drain metal layer 8 includes a source 81, a drain 82 and a data line 83.
  • the source 81 and the drain 82 are electrically connected to the active layer 4 through via holes penetrating the interlayer insulating layer 7 respectively.
  • the gate metal layer 6 and the source/drain metal layer 8 both use copper, and the thickness of the gate metal layer 6 using copper can reach more than 400 nm, and the source/drain metal layer 8 The thickness of copper used can reach more than 500nm.
  • the edge of the gate line 62 is steep due to the angle ⁇ , and the deposited interlayer insulating layer 7 will become thinner at the edge of the gate line 62 and cannot completely stop the gate line 62. It is short-circuited with the data line 83.
  • copper has thermal diffusivity for the interlayer insulating layer 7 (SiO material) during high-temperature deposition or etching processes.
  • FIG. 2 is a schematic cross-sectional structure diagram of the display substrate
  • FIG. 3 is a partial film layer in FIG. A schematic plan view of the structure.
  • the display substrate includes: a base substrate 1, an active layer 4, a gate insulating layer 5, a gate 61, an interlayer insulating layer 7, a source and drain (source and drain) which are sequentially stacked on the base substrate 1.
  • the gate line 62 and the data line 83 are partially disposed opposite to each other, and the surface of the opposing area of the gate line 62 and the data line 83 facing the data line 83 has an oxide metal layer 10.
  • an oxide metal layer is provided on the surface of the gate line that has an area opposite to the data line. Due to the high dielectric constant and breakdown voltage of the oxide metal layer, the gate can be greatly reduced. The possibility of a short circuit between the line and the data line in the overlapping area. Therefore, the use of the display substrate provided by the embodiments of the present application can solve the problem that the overlap area between the gate line and the data line in the related art is prone to short circuit, which causes the panel yield to decrease.
  • the display substrate may further include a light-shielding metal layer 2 and a buffer layer 3 located between the base substrate 1 and the active layer 4.
  • the opposing area includes: the overlapping area of the gate line 62 and the data line 83 (shown in the black dotted frame in FIG. ), and two symmetrical first regions A extending beyond the overlapping region along the extending direction of the gate line 62. That is, the oxide metal layer 10 covers the overlap area of the gate line 62 and the data line 83 (shown in the black dashed frame in FIG. 3), and covers two symmetrical first areas A extending beyond the overlap area along the extending direction of the gate line 62 .
  • the width of the first area A along the extending direction of the gate line 62 is 2 ⁇ m-3 ⁇ m.
  • the line is perpendicular to In the direction of the gate line 62, the width of the opposing area of the gate line 62 exceeds the width of the area adjacent thereto.
  • setting the size of the oxide metal layer 10 to be larger than the overlapping area of the gate line 62 and the data line 83 can prevent the coverage of aluminum oxide from shifting the overlapping area due to the production process.
  • the first metal film layer includes a first metal element
  • the oxide metal layer is an oxide of the first metal element. That is, the oxide metal layer may be a metal oxide layer formed by oxidizing the first metal element in the first metal film layer.
  • the first metal film layer includes a layer disposed on the side of the gate insulating layer 7 facing away from the base substrate 1.
  • the first molybdenum metal layer, the copper metal layer, the aluminum metal layer, and the second molybdenum metal layer, that is, the gate 61 in the embodiment of the present application is composed of the first molybdenum metal layer, the copper metal layer, the aluminum metal layer and the second molybdenum metal layer.
  • the molybdenum metal layer is composed; the opposite area includes a first molybdenum metal layer and a copper metal layer; the oxide metal layer 10 is an aluminum oxide layer formed after the aluminum metal layer is oxidized, that is, the first metal element in the first metal film layer is aluminum element . Due to the high dielectric constant and breakdown voltage of aluminum oxide, it can greatly reduce the possibility of a short circuit between the gate line and the data line in the overlapping area.
  • the opposite area of the gate may be a first molybdenum metal layer and a copper metal layer that are stacked. Layer and part of the aluminum metal layer, or only the first molybdenum metal layer and the copper metal layer remain.
  • the display substrate has a TFT area B, a capacitor area C, and an overlapping area of the gate line 62 and the data line 83. D.
  • the display substrate provided in the embodiments of the present application can be applied to a liquid crystal display panel (Liquid Crystal Display, LCD) and an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • the display substrate When the display substrate is applied to a liquid crystal display panel, the display substrate may also include a pixel electrode electrically connected to the drain of the TFT; further, it may also include a common electrode.
  • the display substrate When the display substrate is applied to an OLED display panel, the display substrate may further include an anode, a cathode, and an organic functional layer located between the anode and the cathode, which are electrically connected to the drain of the TFT.
  • an embodiment of the present application also provides a manufacturing method of a display substrate, as shown in FIG. 4, including:
  • S401 sequentially forming a stacked active layer and a gate insulating layer on a base substrate;
  • the manufacturing method of the display substrate provided by the embodiments of the present application is to form an oxide metal layer on the surface of the gate line that has an area opposite to the data line. Due to the high dielectric constant and breakdown voltage of the oxide metal layer, it can be greatly improved. , To reduce the possibility of short-circuiting of gate lines and data lines in the overlapping area. Therefore, the display substrate manufactured by the manufacturing method provided by the embodiment of the present application can solve the problem that the overlapped area between the gate line and the data line in the related art is prone to short circuit, which causes the panel yield to decrease.
  • forming the first metal film layer on the gate insulating layer may specifically include:
  • a first molybdenum metal layer, a copper metal layer, an aluminum metal layer, and a second molybdenum metal layer are sequentially deposited on the gate insulating layer.
  • patterning the first metal film layer to form patterns of gates and gate lines may specifically include:
  • the photoresist layer includes a partially reserved area, a completely reserved area, and a completely removed area; wherein the partially reserved area covers the opposite area, and the photoresist completely reserved area Cover the area where the gate and gate line are located, and completely remove the area to cover other areas;
  • an oxide metal layer is formed on the surface of the region opposite to the gate line and the data line to be formed.
  • patterning the photoresist layer specifically includes:
  • a halftone mask is used to pattern the photoresist layer; the halftone mask includes: a completely transparent area corresponding to a completely removed area, a partial transparent area corresponding to a partially reserved area, and a complete The opaque area corresponding to the reserved area; the light transmission of the partially light transmission area is 75%-85% of the light transmission of the complete light transmission area.
  • the thickness of the photoresist layer may be 2.0 ⁇ m-2.2 ⁇ m, and the thickness of the photoresist pattern in the partially reserved area may be 0.3 ⁇ m-0.5 ⁇ m.
  • performing dry etching on the gate insulating layer may specifically include:
  • a combined gas of O 2 and CF 4 is used to perform dry etching on the gate insulating layer, the flow of O 2 is 1000 sccm to 1500 sccm, and the flow of CF 4 is 2000 sccm to 2500 sccm.
  • a light-shielding metal film can be deposited on the base substrate 1 by chemical vapor deposition.
  • the light-shielding metal film can be a metal such as molybdenum or molybdenum-niobium alloy, and the thickness can be 0.10 ⁇ m ⁇ 0.15 ⁇ m, followed by exposure and development After the wet etching, the light-shielding metal layer 2 is formed, as shown in FIG. 8A; specifically, the wet-etching light-shielding metal film can be etched by mixed acid.
  • a buffer layer 3 can be deposited on the base substrate 1 by chemical vapor deposition or magnetron sputtering, as shown in FIG. 8B; specifically, the material of the buffer layer 3 can be silicon oxide with a thickness It can be 0.3 ⁇ m to 0.5 ⁇ m.
  • a metal oxide semiconductor film can be deposited on the buffer layer 3 by chemical vapor deposition, and then a patterning process is performed on the metal oxide semiconductor film to form the active layer 4, as shown in FIG. 8C, that is, the photoresist is coated After coating, the photoresist is exposed, developed, and etched with a common mask to form the active layer 4.
  • the material of the active layer 4 may be indium tin oxide (IGZO), and the thickness may be 0.05 ⁇ m to 0.1 ⁇ m.
  • a layer of gate insulating film 01 can be deposited on the base substrate 1 by chemical vapor deposition or magnetron sputtering, as shown in FIG. 8D; specifically, the material of the gate insulating film 01 can be Silicon oxide has a thickness of 0.1 ⁇ m to 0.2 ⁇ m.
  • a first metal film layer can be deposited on the base substrate 1 by using magnetron sputtering. Specifically, a first molybdenum metal layer 001 and a copper metal layer can be sequentially deposited on the gate insulating film 01. 002, the first metal film layer formed by the aluminum metal layer 003 and the second molybdenum metal layer 004, as shown in FIG.
  • the thickness of the first molybdenum metal layer 001 may be 0.03 ⁇ m to 0.04 ⁇ m, and the copper metal layer 002
  • the thickness of the aluminum metal layer 003 may be 0.4 ⁇ m ⁇ 0.5 ⁇ m
  • the thickness of the aluminum metal layer 003 may be 0.06 ⁇ m ⁇ 0.08 ⁇ m
  • the thickness of the second molybdenum metal layer 004 may be 0.05 ⁇ m.
  • a photoresist layer is formed on the second molybdenum metal layer 004, and then a halftone mask is used to expose, develop and etch the photoresist layer to form a photoresist pattern, as shown in FIG. 8F; Ground, the photoresist pattern includes a partially reserved area 021, a completely reserved area 022, and a completely removed area; wherein the partially reserved area 021 covers the opposite area (the opposite area of the gate line 62 to be formed), and the completely reserved area 022 covers the gate 61 The area where the grid line 62 is located except for the opposite area is completely removed to cover other areas.
  • the photoresist layer is a positive photoresist, and its thickness may be 2.0 ⁇ m to 2.2 ⁇ m, and the thickness of the photoresist in the partially reserved region 021 may be 0.3 ⁇ m to 0.5 ⁇ m.
  • wet etching is performed on the exposed first molybdenum metal layer 001, copper metal layer 002, aluminum metal layer 003, and second molybdenum metal layer 004,
  • the patterns of the gate 61 and the gate line 62 are formed as shown in FIG. 8G; specifically, the wet etching of the above four metal layers can be etched with mixed acids, such as nitric acid, acetic acid and phosphoric acid in a certain proportion.
  • the gate mask ie, the photoresist pattern 022
  • the gate insulating layer 5 is subjected to dry etching. Since the active layer 4 includes a channel region covered by the gate insulating layer 5 and a source contact region and a drain contact region located on both sides of the channel region, the source contact region and the drain contact region are electrically conductive.
  • the chemical treatment can reduce the contact resistance of the source 81, the drain 82 and the active layer 4 to be formed (as shown in FIG. 8M) and improve the conductivity.
  • ammonia gas (NH 3 ) or helium gas (He) can be used for the conduction treatment.
  • An interlayer insulating layer 7 is formed on the oxide metal layer 10, as shown in FIG. 8L.
  • the material of the interlayer insulating layer 7 may be silicon oxide, and the thickness may be 0.45 ⁇ m to 0.6 ⁇ m.
  • a second metal film layer is deposited on the interlayer insulating layer 7, and the source 81, the drain 82 and the data line 83 are formed through a patterning process, such as Shown in Figure 8M.
  • a layer of metal copper is deposited, the thickness can be 0.5 ⁇ m to 0.6 ⁇ m, and then a photolithography mask is performed.
  • the thickness of the source and drain mask photoresist can be 1.5 ⁇ m to 1.8 ⁇ m, and the photoresist used is positive Use this mask to perform data line wet etching. Copper wet etching can be performed with hydrogen peroxide (H 2 O 2 ) solution. After the wet etching is completed, the photoresist is stripped. After the photoresist stripping is completed, the data line 83 The line width should be 10 ⁇ m or less.
  • a passivation layer 9 is deposited, as shown in Figure 8N.
  • the material of the passivation layer 9 may be silicon oxide, and the thickness may be 0.3 ⁇ m to 0.5 ⁇ m.
  • an aluminum oxide layer can be formed in the opposite area of the gate line 62 and the data line 83, that is, the intersection area. Because the dielectric constant and breakdown voltage of aluminum oxide are higher, it is extremely The possibility of short circuit between the gate line 62 and the data line 83 is greatly reduced.
  • the preparation process of the display substrate provided by the embodiments of the present application may also include the steps of forming other patterns, such as For the step of forming the pattern of the capacitor region C in the display substrate (refer to FIG. 2), please refer to the description of the structure of the display substrate for details, which will not be repeated here.
  • an embodiment of the present application also provides a display device, including the above-mentioned display substrate provided by the embodiment of the present application.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display device reference may be made to the above-mentioned embodiment of the display substrate, and the repetition will not be repeated.
  • the display substrate, the manufacturing method thereof, and the display device provided by the embodiments of the present application include: a base substrate, a light-shielding metal layer, a buffer layer, an active layer, a gate insulating layer, The gate, the interlayer insulating layer, the source and drain, and the passivation layer; the first metal film layer where the gate is located also includes a gate line, and the second metal film layer where the source and drain are located also includes a data line; the gate line is in contact with the data
  • the surface of the line opposing area has an oxide metal layer.
  • an oxide metal layer is provided on the surface of the gate line that has an area opposite to the data line.
  • the overlap between the gate line and the data line can be greatly reduced.
  • the possibility of a short circuit in the area Therefore, the use of the display substrate provided by the embodiments of the present application can solve the problem that the overlap area between the gate line and the data line in the related art is prone to short circuit, which causes the panel yield to decrease.

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Abstract

本申请公开一种显示基板及其制作方法、显示装置。显示基板包括：衬底基板，位于衬底基板上依次层叠设置的有源层、栅极绝缘层、第一金属膜层、层间绝缘层、第二金属膜层和钝化层；第一金属膜层包括栅极和栅线的图案，第二金属膜层包括源漏极和数据线的图案；栅线与数据线部分相对设置，栅线与数据线的相对区域朝向数据线一侧的表面具有氧化物金属层。本申请通过在与数据线具有相对区域的栅线的表面设置氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本申请实施例提供的显示基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路而造成面板良率下降的问题。

Description

一种显示基板及其制作方法、显示装置
相关申请的交叉引用
本申请要求在2019年05月31日提交中国专利局、申请号为201910468906.9、申请名称为“一种阵列基板、其制作方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示基板及其制作方法、显示装置。
背景技术
目前，薄膜晶体管(Thin Film Transistor，TFT)是液晶显示器和有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)的主要驱动元件。在TFT制作过程中，由于工艺的原因会导致栅线和数据线之间的交叠区域发生短路，使得面板发生亮线，造成面板良率下降。
发明内容
本申请实施例提供一种显示基板及其制作方法、显示装置，用以解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
因此，本申请实施例提供了一种显示基板，包括：衬底基板，位于所述衬底基板上依次层叠设置的有源层、栅极绝缘层、第一金属膜层、层间绝缘层、第二金属膜层和钝化层；所述第一金属膜层包括栅极和栅线的图案，所述第二金属膜层包括源漏极和数据线的图案；
所述栅线与所述数据线部分相对设置，所述栅线与所述数据线的相对区域朝向所述数据线一侧的表面具有氧化物金属层。
可选地，在具体实施时，在本申请实施例提供的上述显示基板中，所述相对区域包括：所述栅线和所述数据线的交叠区域，以及沿所述栅线延伸方向超出所述交叠区域的两个对称的第一区域。
可选地，在具体实施时，在本申请实施例提供的上述显示基板中，所述第一区域沿所述栅线延伸方向的宽度为2μm-3μm。
可选地，沿垂直于所述栅线的方向，所述栅线的相对区域的宽度超出与其相邻的区域的宽度。
可选地，所述第一金属膜层包括第一金属元素，所述氧化物金属层为所述第一金属元素的氧化物。
可选地，在具体实施时，在本申请实施例提供的上述显示基板中，所述第一金属膜层包括位于所述栅极绝缘层背向所述衬底基板一侧依次层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层，所述相对区域包括所述第一钼金属层和所述铜金属层，所述氧化物金属层为所述铝金属层经过氧化后形成的氧化铝层。
相应地，本申请实施例还提供了一种显示装置，包括本申请实施例提供的上述任一项显示基板。
相应地，本申请实施例还提供了一种上述任一项显示基板的制作方法，包括：
在衬底基板上依次形成层叠设置的有源层和栅极绝缘层；
在所述栅极绝缘层上形成第一金属膜层，对所述第一金属膜层进行构图形成栅极和栅线的图案；
在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层；
在所述氧化物金属层上依次形成层间绝缘层、第二金属膜层和钝化层，所述第二金属膜层包括数据线和源漏极的图案。
可选地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，在所述栅极绝缘层上形成第一金属膜层，具体包括：
在所述栅极绝缘层上依次沉积第一钼金属层、铜金属层、铝金属层和第 二钼金属层；
对所述第一金属膜层进行构图形成栅极和栅线的图案，具体包括：
在所述第二钼金属层上形成光刻胶层；
对所述光刻胶层进行图案化处理，形成光刻胶图案；所述光刻胶图案包括部分保留区域、完全保留区域和完全去除区域；其中，所述部分保留区域覆盖所述相对区域，所述完全保留区域覆盖所述栅极和栅线所在区域，所述完全去除区域覆盖其它区域；
以所述光刻胶图案作为遮挡，对暴露出的所述第一钼金属层、所述铜金属层、所述铝金属层和所述第二钼金属层进行湿法刻蚀处理，形成所述栅极和所述栅线的图案。
可选地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层，具体包括：
采用灰化工艺去除所述部分保留区域的光刻胶层；
对所述栅极绝缘层进行干法刻蚀处理，同时刻蚀掉所述部分保留区域的第二金属钼层；
采用包含O 2的等离子体对所述相对区域的铝金属层进行氧化处理，形成氧化铝层。
可选地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，在采用包含O 2的等离子体对所述相对区域的铝金属层进行氧化处理之前，还包括：
对所述栅极绝缘层进行干法刻蚀处理后暴露出的所述有源层进行导体化处理。
可选地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，对所述光刻胶层进行图案化处理，具体包括：
采用半色调掩膜版对所述光刻胶层进行图案化处理；其中，所述半色调掩膜版包括：与所述完全去除区域对应的完全透光区域，与所述部分保留区 域对应的部分透光区域，以及与所述完全保留区域对应的不透光区域；所述部分透光区域的透光量为所述完全透光区域的透光量的75％-85％。
可选地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，所述光刻胶层的厚度为2.0μm-2.2μm，所述部分保留区域的光刻胶图案的厚度为0.3μm-0.5μm。
可选地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，对所述栅极绝缘层进行干法刻蚀处理，具体包括：
采用O 2和CF 4的组合气体对所述栅极绝缘层进行干法刻蚀处理，所述O 2的流量为1000sccm～1500sccm，CF 4的流量为2000sccm～2500sccm。
附图说明
图1为相关技术中提供的显示基板的结构示意图；
图2为本申请实施例提供的显示基板的结构示意图；
图3为图2所示的显示基板的部分膜层的俯视结构示意图；
图4为本申请实施例提供的显示基板的制作方法的流程图之一；
图5为本申请实施例提供的显示基板的制作方法的流程图之二；
图6为本申请实施例提供的显示基板的制作方法的流程图之三；
图7为本申请实施例提供的显示基板的制作方法的流程图之四；
图8A至图8N为本申请实施例提供的显示基板的制作方法中执行各步骤之后的剖面示意图。
具体实施方式
为了使本申请的目的，技术方案和优点更加清楚，下面结合附图，对本申请实施例提供的显示基板、其制作方法及显示装置的具体实施方式进行详细地说明。
附图中各层薄膜厚度和形状不反映显示基板的真实比例，目的只是示意说明本申请内容。
顶栅结构的TFT相比底栅结构的TFT具有高的开态电流、更高开口率和更好的TFT稳定性而受到关注。
如图1所示，相关技术中采用顶栅结构的TFT的显示基板包括衬底基板1，以及依次设置在衬底基板1上的遮光金属层2、缓冲层3、有源层4、栅极绝缘层5、栅极金属层6、层间绝缘层7，形成在层间绝缘层7上的源漏金属层8，以及覆盖源漏金属层8的钝化层9。栅极金属层6包括栅极61和栅线62，源漏金属层8包括源极81、漏极82和数据线83。其中源极81和漏极82分别通过贯穿层间绝缘层7的过孔与有源层4电连接。
在制备采用顶栅结构的TFT的显示基板的过程中，栅极金属层6和源漏金属层8均使用铜，且栅极金属层6使用铜的厚度可达到400nm以上，源漏金属层8使用铜的厚度可达到500nm以上。因沉积铜厚度较厚，湿刻后铜角度(栅线62的侧面和底面之间的夹角θ)难以改善，且该夹角θ通常在60度以上，这样在后续采用沉积工艺在栅极金属层6上沉积层间绝缘层7时，因夹角θ的原因，栅线62的边缘较陡，沉积的层间绝缘层7在栅线62的边缘会变薄，无法完全阻止栅线62和数据线83短路，另外铜在高温沉积或刻蚀工艺时针对层间绝缘层7(SiO材料)具有热扩散性，故而在栅线62和数据线83的交叠区域(图1中虚线框所示)较易发生栅线62和数据线83短路，使得显示面板产生亮线，造成显示面板良率下降。
有鉴于此，为了解决上述问题，本申请实施例提供了一种显示基板，如图2和图3所示，图2为该显示基板的剖面结构示意图，图3为图2中部分膜层的俯视结构示意图，该显示基板包括：衬底基板1，位于衬底基板1上依次层叠设置的有源层4、栅极绝缘层5、栅极61、层间绝缘层7、源漏极(源极81和漏极82)和钝化层9；栅极61所在的第一金属膜层还包括栅线62，源漏极(源极81和漏极82)所在的第二金属膜层还包括数据线83；
栅线62与数据线83部分相对设置，栅线62与数据线83的相对区域朝向数据线83一侧的表面具有氧化物金属层10。
本申请实施例提供的显示基板，通过在与数据线具有相对区域的栅线的 表面设置氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本申请实施例提供的显示基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
具体的，如图2和图3所示，显示基板还可以包括位于衬底基板1和有源层4之间的遮光金属层2和缓冲层3。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板中，如图3所示，相对区域包括：栅线62和数据线83的交叠区域(图3中黑色虚线框所示)，以及沿栅线62延伸方向超出交叠区域的两个对称的第一区域A。即氧化物金属层10覆盖栅线62和数据线83的交叠区域(图3中黑色虚线框所示)，以及覆盖沿栅线62延伸方向超出交叠区域的两个对称的第一区域A。
可选的，如图3所示，第一区域A沿栅线62延伸方向的宽度为2μm-3μm。
进一步地，在具体实施时，如图3所示，为了保证氧化物金属层10完全覆盖栅线62与数据线83的交叠区域，在本申请实施例提供的上述显示基板中，沿垂直于栅线62的方向，栅线62的相对区域的宽度超出与其相邻的区域的宽度。
具体的，将氧化物金属层10的尺寸设置为大于栅线62与数据线83的交叠区域，可以避免因生产工艺导致氧化铝的覆盖范围偏移交叠区域。
进一步地，在具体实施时，本申请实施例提供的显示基板中，第一金属膜层包括第一金属元素，氧化物金属层为第一金属元素的氧化物。即氧化物金属层可以是第一金属膜层中第一金属元素被氧化所形成的金属氧化物层。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板中，如图2所示，第一金属膜层包括位于栅极绝缘层7背向衬底基板1一侧依次层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层，即本申请实施例中栅极61是由层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层构成；相对区域包括第一钼金属层和铜金属层；氧化物金属层10为铝 金属层经过氧化后形成的氧化铝层，即第一金属膜层中第一金属元素为铝元素。由于氧化铝的介电常数和击穿电压较高，因此可以极大的降低栅线和数据线在交叠区域发生短路的可能性。
具体的，本申请实施例中，相对区域处的铝金属层可以仅表面部分被氧化，也可以全部被氧化，进而，栅极的相对区域可以是由层叠设置的第一钼金属层、铜金属层和部分铝金属层构成，也可以是仅剩第一钼金属层和铜金属层。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板中，如图2所示，该显示基板具有TFT区域B，电容区域C，以及栅线62和数据线83的交叠区域D。
需要说明的是，本申请实施例提供的显示基板可以应用于液晶显示面板(Liquid Crystal Display，LCD)和有机电致发光二极管(Organic Light Emitting Diode，OLED)显示面板。
当显示基板应用于液晶显示面板时，该显示基板还可以包括与TFT的漏极电连接的像素电极；进一步地，还可以包括公共电极。
当显示基板应用于OLED显示面板时，该显示基板还可以包括与TFT的漏极电连接的阳极、阴极以及位于阳极和阴极之间的有机功能层。
基于同一发明构思，本申请实施例还提供了一种显示基板的制作方法，如图4所示，包括：
S401、在衬底基板上依次形成层叠设置的有源层和栅极绝缘层；
S402、在栅极绝缘层上形成第一金属膜层，对第一金属膜层进行构图形成栅极和栅线的图案；
S403、在栅线与将要形成的数据线相对区域的表面形成氧化物金属层；
S404、在氧化物金属层上依次形成层间绝缘层、第二金属膜层和钝化层，第二金属膜层包括数据线和源漏极的图案。
本申请实施例提供的显示基板的制作方法，通过在与数据线具有相对区域的栅线的表面形成氧化物金属层，由于氧化物金属层的介电常数和击穿电 压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本申请实施例提供的制作方法制得的显示基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，在栅极绝缘层上形成第一金属膜层，具体可以包括：
在栅极绝缘层上依次沉积第一钼金属层、铜金属层、铝金属层和第二钼金属层。
如图5所示，对第一金属膜层进行构图形成栅极和栅线的图案，具体可以包括：
S501、在第二钼金属层上形成光刻胶层；
S502、对光刻胶层进行图案化处理，形成光刻胶图案；光刻胶图案包括部分保留区域、完全保留区域和完全去除区域；其中，部分保留区域覆盖相对区域，光刻胶完全保留区域覆盖栅极和栅线所在区域，完全去除区域覆盖其它区域；
S503、以光刻胶图案作为遮挡，对暴露出的第一钼金属层、铜金属层、铝金属层和第二钼金属层进行湿法刻蚀处理，形成栅极和栅线的图案。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，如图6所示，在栅线与将要形成的数据线相对区域的表面形成氧化物金属层，具体可以包括：
S601、采用灰化工艺去除部分保留区域的光刻胶层；
S602、对栅极绝缘层进行干法刻蚀处理的同时，刻蚀掉部分保留区域的第二金属钼层；
S603、采用包含O 2的等离子体对相对区域的铝金属层进行氧化处理，形成氧化铝层。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，如图7所示，在采用包含O 2的等离子体对相对区域的铝金属层进行氧化处理之前，还包括：
S603’、对栅极绝缘层进行干法刻蚀处理后暴露出的有源层进行导体化处理。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，对光刻胶层进行图案化处理，具体包括：
采用半色调掩膜版对光刻胶层进行图案化处理；其中，半色调掩膜版包括：与完全去除区域对应的完全透光区域，与部分保留区域对应的部分透光区域，以及与完全保留区域对应的不透光区域；部分透光区域的透光量为完全透光区域的透光量的75％-85％。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，光刻胶层的厚度可以为2.0μm-2.2μm，部分保留区域的光刻胶图案的厚度可以为0.3μm-0.5μm。
进一步地，在具体实施时，在本申请实施例提供的上述显示基板的制作方法中，对栅极绝缘层进行干法刻蚀处理，具体可以包括：
采用O 2和CF 4的组合气体对栅极绝缘层进行干法刻蚀处理，O 2的流量为1000sccm～1500sccm，CF 4的流量为2000sccm～2500sccm。
下面通过具体实施例对本申请实施例提供的显示基板的制作方法进行详细说明。
(1)可以利用化学气相沉积法在衬底基板1上沉积一层遮光金属薄膜，遮光金属薄膜可以为钼或钼铌合金等金属，厚度可以为0.10μm～0.15μm，紧接着通过曝光、显影和湿法刻蚀后形成遮光金属层2，如图8A所示；具体地，湿法刻蚀遮光金属薄膜可采用混酸进行刻蚀。
(2)可以利用化学气相沉积法或者磁控溅射的方法在衬底基板1上沉积一层缓冲层3，如图8B所示；具体地，该缓冲层3的材料可以为氧化硅，厚度可以为0.3μm～0.5μm。
(3)可以利用化学气相沉积法在缓冲层3上沉积金属氧化物半导体薄膜，然后对金属氧化物半导体薄膜进行一次构图工艺形成有源层4，如图8C所示，即在光刻胶涂覆后，用普通的掩膜板对光刻胶进行曝光、显影、刻蚀形成有 源层4。具体地，有源层4的材料可以为氧化铟锡(IGZO)，厚度可以为0.05μm～0.1μm。
(4)可以利用化学气相沉积法或者磁控溅射的方法在衬底基板1上沉积一层栅极绝缘薄膜01，如图8D所示；具体地，该栅极绝缘薄膜01的材料可以为氧化硅，厚度为0.1μm～0.2μm。
(5)可以利用磁控溅射的方法在衬底基板1上沉积一层第一金属膜层，具体地，可以在栅极绝缘薄膜01上依次沉积由第一钼金属层001、铜金属层002、铝金属层003和第二钼金属层004构成的第一金属膜层，如图8E所示；具体地，第一钼金属层001的厚度可以为0.03μm～0.04μm，铜金属层002的厚度可以为0.4μm～0.5μm，铝金属层003的厚度可以为0.06μm～0.08μm，第二钼金属层004的厚度可以为0.05μm。
(6)在第二钼金属层004上形成光刻胶层，然后利用半色调掩膜板对光刻胶层进行曝光、显影和刻蚀，形成光刻胶图案，如图8F所示；具体地，光刻胶图案包括部分保留区域021、完全保留区域022和完全去除区域；其中，部分保留区域021覆盖相对区域(即将形成的栅线62的相对区域)，完全保留区域022覆盖栅极61和栅线62除相对区域外的所在区域，完全去除区域覆盖其它区域。具体地，光刻胶层为正性光刻胶，其厚度可以为2.0μm～2.2μm，部分保留区域021的光刻胶厚度可以为0.3μm～0.5μm。
(7)以光刻胶图案(021和022)作为遮挡，对暴露出的第一钼金属层001、铜金属层002、铝金属层003和第二钼金属层004进行湿法刻蚀处理，形成栅极61和栅线62的图案，如图8G所示；具体地，湿法刻蚀上述四个金属层可采用混酸进行刻蚀，例如一定配比的硝酸、醋酸和磷酸。
(8)采用灰化工艺去除部分保留区域021的光刻胶层，如图8H所示；具体地，采用流量为10000sccm～12000sccm的O 2、控制相应时间以及采用高源功率和高偏置功率进行灰化掉部分保留区域021的0.3μm～0.5μm的光刻胶。
(9)保留栅极61上方的栅极掩膜(即光刻胶图案022)对栅极绝缘薄膜 01进行干法刻蚀处理，形成栅极绝缘层5，在对栅极绝缘薄膜02进行干法刻蚀处理的同时，刻蚀掉相对区域的第二金属钼层004，从而暴露出相对区域的铝金属层003，如图8I所示；具体地，采用流量为2000sccm～2500sccm的CF 4和流量为1000sccm～1500sccm的O 2混合气体对无光刻胶保护的栅极绝缘薄膜01进行干法刻蚀，特别的栅极绝缘薄膜01在干法刻蚀的同时，可以将栅线62最上方的第二金属钼层004刻蚀掉。
(10)继续保留栅极61上方的栅极掩膜(即光刻胶图案022)对在栅极绝缘层5进行干法刻蚀处理后暴露出的有源层4进行导体化处理。由于有源层4包括被栅极绝缘层5覆盖的沟道区以及分别位于沟道区两侧的源极接触区域漏极接触区，因此，通过对源极接触区和漏极接触区进行导体化处理，能够降低即将形成的源极81、漏极82和有源层4的接触电阻(如图8M所示)，提高导电性。具体地，可以采用氨气(NH 3)或者氦气(He)进行导体化处理。
(11)采用包含O 2的等离子体对相对区域的铝金属层003的表面进行氧化处理，使铝金属层003的表面形成氧化物金属层10，即氧化铝层，如图8J所示；具体地，可以采用流量为10000sccm～12000sccm的O 2，由于栅极绝缘薄膜01在干刻时使完全保留区域022的光刻胶的表面生成了表面硬化光阻，该氧化处理过程中不仅可以对相对区域的铝金属层003的表面进行氧化使其转变为氧化铝，而且可以将光刻胶表面生成的硬化光阻去掉。
(12)对完全保留区域022的光刻胶进行湿法剥离，如图8K所示。
(13)在氧化物金属层10上形成层间绝缘层7，如图8L所示。具体地，层间绝缘层7的材料可以为氧化硅，厚度可以为0.45μm～0.6μm。
(14)采用和制作栅极61、栅线62类似的方法，在层间绝缘层7上沉积一层第二金属膜层，通过构图工艺形成源极81、漏极82和数据线83，如图8M所示。具体地，如沉积一层金属铜，厚度可以为0.5μm～0.6μm，随后进行光刻掩膜，源漏极掩膜光刻胶的厚度可以为1.5μm～1.8μm，所用光刻胶为正性光刻胶，利用此掩膜先进行数据线湿刻，铜湿刻可采用双氧水(H 2O 2) 药液进行，湿刻完成后进行光阻剥离，光阻剥离完成后数据线83的线宽应为10μm以下。
(15)最后沉积一层钝化层9，如图8N所示。具体地，钝化层9的材料可以为氧化硅，厚度可以为0.3μm～0.5μm。
通过上述步骤(1)至步骤(15)后即可在栅线62和数据线83的相对区域即交叉区域形成氧化铝层，由于氧化铝的介电常数和击穿电压更高，故而可极大降低栅线62与数据线83短路的可能性。另外，需要说明的是，虽然上述步骤中仅详细说明了TFT，栅线和数据线等区域的图案形成过程，但本申请实施例提供的显示基板制备流程也可以包括形成其他图案的步骤，例如形成显示基板中电容区域C图案的步骤(参考图2所示)，具体可以参考对显示基板的结构描述，此处不再赘述。
基于同一发明构思，本申请实施例还提供了一种显示装置，包括本申请实施例提供的上述显示基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示基板的实施例，重复之处不再赘述。
本申请实施例提供的显示基板、其制作方法及显示装置，该显示基板包括：衬底基板，位于衬底基板上依次层叠设置的遮光金属层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏极和钝化层；栅极所在的第一金属膜层还包括栅线，源漏极所在的第二金属膜层还包括数据线；栅线在与数据线相对区域的表面具有氧化物金属层。本申请通过在与数据线具有相对区域的栅线的表面设置氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本申请实施例提供的显示基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种显示基板，其中，包括：衬底基板，位于所述衬底基板上依次层叠设置的有源层、栅极绝缘层、第一金属膜层、层间绝缘层、第二金属膜层和钝化层；所述第一金属膜层包括栅极和栅线的图案，所述第二金属膜层包括源漏极和数据线的图案；
    所述栅线与所述数据线部分相对设置，所述栅线与所述数据线的相对区域朝向所述数据线一侧的表面具有氧化物金属层。
  2. 如权利要求1所述的显示基板，其中，所述相对区域包括：所述栅线和所述数据线的交叠区域，以及沿所述栅线延伸方向超出所述交叠区域的两个对称的第一区域。
  3. 如权利要求2所述的显示基板，其中，所述第一区域沿所述栅线延伸方向的宽度为2μm-3μm。
  4. 如权利要求2所述的显示基板，其中，沿垂直于所述栅线的方向，所述栅线的相对区域的宽度超出与其相邻的区域的宽度。
  5. 如权利要求1所述的显示基板，其中，所述第一金属膜层包括第一金属元素，所述氧化物金属层为所述第一金属元素的氧化物。
  6. 如权利要求5所述的显示基板，其中，所述第一金属膜层包括位于所述栅极绝缘层背向所述衬底基板一侧依次层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层，所述相对区域包括所述第一钼金属层和所述铜金属层，所述氧化物金属层为所述铝金属层经过氧化后形成的氧化铝层。
  7. 一种显示装置，其中，包括如权利要求1-6任一项所述的显示基板。
  8. 一种如权利要求1-6任一项所述的显示基板的制作方法，其中，包括：
    在衬底基板上依次形成层叠设置的有源层和栅极绝缘层；
    在所述栅极绝缘层上形成第一金属膜层，对所述第一金属膜层进行构图形成栅极和栅线的图案；
    在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层；
    在所述氧化物金属层上依次形成层间绝缘层、第二金属膜层和钝化层，所述第二金属膜层包括数据线和源漏极的图案。
  9. 如权利要求8所述的显示基板的制作方法，其中，在所述栅极绝缘层上形成第一金属膜层，具体包括：
    在所述栅极绝缘层上依次沉积第一钼金属层、铜金属层、铝金属层和第二钼金属层；
    对所述第一金属膜层进行构图形成栅极和栅线的图案，具体包括：
    在所述第二钼金属层上形成光刻胶层；
    对所述光刻胶层进行图案化处理，形成光刻胶图案；所述光刻胶图案包括部分保留区域、完全保留区域和完全去除区域；其中，所述部分保留区域覆盖所述相对区域，所述完全保留区域覆盖所述栅极和栅线所在区域，所述完全去除区域覆盖其它区域；
    以所述光刻胶图案作为遮挡，对暴露出的所述第一钼金属层、所述铜金属层、所述铝金属层和所述第二钼金属层进行湿法刻蚀处理，形成所述栅极和所述栅线的图案。
  10. 如权利要求9所述的显示基板的制作方法，其中，在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层，具体包括：
    采用灰化工艺去除所述部分保留区域的光刻胶层；
    对所述栅极绝缘层进行干法刻蚀处理，同时刻蚀掉所述部分保留区域的第二金属钼层；
    采用包含O 2的等离子体对所述相对区域的铝金属层进行氧化处理，形成氧化铝层。
  11. 如权利要求10所述的显示基板的制作方法，其中，在采用包含O 2的等离子体对所述相对区域的铝金属层进行氧化处理之前，还包括：
    对所述栅极绝缘层进行干法刻蚀处理后暴露出的所述有源层进行导体化处理。
  12. 如权利要求9所述的显示基板的制作方法，其中，对所述光刻胶层 进行图案化处理，具体包括：
    采用半色调掩膜版对所述光刻胶层进行图案化处理；其中，所述半色调掩膜版包括：与所述完全去除区域对应的完全透光区域，与所述部分保留区域对应的部分透光区域，以及与所述完全保留区域对应的不透光区域；所述部分透光区域的透光量为所述完全透光区域的透光量的75％-85％。
  13. 如权利要求12所述的显示基板的制作方法，其中，所述光刻胶层的厚度为2.0μm-2.2μm，所述部分保留区域的光刻胶图案的厚度为0.3μm-0.5μm。
  14. 如权利要求10所述的显示基板的制作方法，其中，对所述栅极绝缘层进行干法刻蚀处理，具体包括：
    采用O 2和CF 4的组合气体对所述栅极绝缘层进行干法刻蚀处理，所述O 2的流量为1000sccm～1500sccm，CF 4的流量为2000sccm～2500sccm。
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