WO2016145726A1 - 一种低温多晶硅薄膜晶体管阵列基板的制作方法 - Google Patents

一种低温多晶硅薄膜晶体管阵列基板的制作方法 Download PDF

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WO2016145726A1
WO2016145726A1 PCT/CN2015/077964 CN2015077964W WO2016145726A1 WO 2016145726 A1 WO2016145726 A1 WO 2016145726A1 CN 2015077964 W CN2015077964 W CN 2015077964W WO 2016145726 A1 WO2016145726 A1 WO 2016145726A1
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doped region
region
photoresist
drain electrode
source electrode
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PCT/CN2015/077964
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French (fr)
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卢马才
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深圳市华星光电技术有限公司
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Priority to US14/888,645 priority Critical patent/US10269974B2/en
Publication of WO2016145726A1 publication Critical patent/WO2016145726A1/zh

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Definitions

  • the invention belongs to the technical field of liquid crystal display, and in particular to a method for fabricating a low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) array substrate.
  • LTPS low temperature polycrystalline silicon
  • TFT thin film transistor
  • a buffer layer 312, a polysilicon (p-Si) layer 313, a first insulating layer 314, and a first metal layer 315 are sequentially formed on the substrate 311, as shown in FIG. 2-1, where the substrate 311 can be, for example, an insulating layer.
  • step 230 specifically includes:
  • an N-channel region is defined by a fourth stripe mask (eg, a GTM (Gray Tone Mask) mask or a HTM (Half Tone Mask) mask).
  • a fourth stripe mask eg, a GTM (Gray Tone Mask) mask or a HTM (Half Tone Mask) mask.
  • the metal electrode region at the heavily doped region 317a of the drain electrode, the metal electrode region at the heavily doped region 316a of the source electrode of the N-channel region, and the metal electrode region of the doped region 318 of the source electrode of the P-channel region And a metal electrode region at the doped region 319 of the drain electrode of the P channel region.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供一种低温多晶硅薄膜晶体管阵列基板的制作方法，包括步骤：A）利用第一带条纹的光罩定义出N沟道的源电极的重掺杂区（316a）和轻掺杂区（316b）、N沟道的漏电极的重掺杂区（317a）和轻掺杂区（317b）；B）利用第二带条纹的光罩定义出P沟道的源电极的掺杂区（318）和漏电极的掺杂区（319）；C）利用第三带条纹的光罩定义出像素区、N沟道的漏电极的重掺杂区（317a）和源电极的重掺杂区（316a）处的接触孔区、P沟道的源电极的掺杂区（318）和漏电极的掺杂区（319）的接触孔区；D）利用第四带条纹的光罩定义出N沟道的漏电极的重掺杂区（317a）和源电极的重掺杂区（316a）处的金属电极区、P沟道的源电极的掺杂区（318）和漏电极的掺杂区（319）处的金属电极区。

Description

一种低温多晶硅薄膜晶体管阵列基板的制作方法 技术领域
本发明属于液晶显示技术领域，具体地讲，涉及一种低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)阵列基板的制作方法。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已成为市场的主流。
目前，作为LCD的开关元件而广泛采用的是非晶硅薄膜三极管(a-Si TFT)，但a-Si TFT LCD在满足薄型、轻量、高精细度、高亮度、高可靠性、低功耗等要求仍受到限制。低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)TFT LCD与a-Si TFT LCD相比，在满足上述要求方面，具有明显优势。但是，现有的LTPS TFT的工序较为复杂，一般需要至少8道光罩(Mask)来形成LTPS TFT。
现有技术的采用8道光罩形成LTPS TFT阵列基板的工艺依次包括：p-Si图案化，其具体为经过p-Si干刻后形成多晶硅图案；屏蔽P型区域，对N型区域实行离子注入(源极/漏极)；栅极沉积，形成第一金属层，定义出栅极；屏蔽N型区域，对P型区域实行离子注入；形成接触孔；布线层沉积，形成第二金属层，定义出数据线图案；平坦层沉积，形成接触孔；定义像素电极形状。现有技术的形成LTPS TFT阵列基板的工序步骤复杂，同时不利于降低成本。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种低温多晶硅薄膜晶体管阵列基板的制作方法，包括步骤：A)利用第一带条纹的光罩定义 出N沟道区域的源电极的重掺杂区、N沟道区域的源电极的轻掺杂区、N沟道区域的漏电极的重掺杂区及N沟道区域的漏电极的轻掺杂区；B)利用第二带条纹的光罩定义出P沟道区域的源电极的掺杂区及P沟道区域的漏电极的掺杂区；C)利用第三带条纹的光罩定义出像素区、N沟道区域的漏电极的重掺杂区处的接触孔区、N沟道区域的源电极的重掺杂区处的接触孔区、P沟道区域的源电极的掺杂区处的接触孔区及P沟道区域的漏电极的掺杂区处的接触孔区；D)利用第四带条纹的光罩定义出N沟道区域的漏电极的重掺杂区处的金属电极区、N沟道区域的源电极的重掺杂区处的金属电极区、P沟道区域的源电极的掺杂区的金属电极区及P沟道区域的漏电极的掺杂区处的金属电极区。
进一步地，所述第一带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
进一步地，所述第二带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
进一步地，所述第三带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
进一步地，所述第四带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
进一步地，所述步骤A)进一步包括：在基板上依次形成缓冲层、多晶硅层、第一绝缘层和第一金属层；在第一金属层上涂布一层光刻胶；利用所述第一带条纹的光罩对所述光刻胶进行曝光、显影，以将N沟道区域的源电极的重掺杂区和漏电极的重掺杂区上方的光刻胶去除，并将源电极的轻掺杂区和漏电极的轻掺杂区上方的部分光刻胶去除；将N沟道区域的源电极的重掺杂区及漏电极的重掺杂区上方的第一金属层刻蚀去除；对N沟道区域的源电极的重掺杂区及漏电极的重掺杂区进行离子注入；将N沟道区域的源电极的轻掺杂区和漏电极的轻掺杂区上方剩余的光刻胶去除；将源电极的轻掺杂区和漏电极的轻掺杂区上方的第一金属层刻蚀去除；对N沟道区域的源电极的重掺杂区、轻掺杂区以及漏电极的重掺杂区、轻掺杂区再次进行离子注入；将剩余的光刻胶全部去除。
进一步地，所述步骤B)进一步包括：在完成所述步骤A)的基板上涂布光刻胶；利用所述第二带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域与P沟道区域之间的光刻胶去除，并将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的部分光刻胶去除；将N沟道区域与P沟道区域之间的多晶硅层、第一绝缘层和第一金属层刻蚀去除；将P沟道区域的源电极的掺杂区及漏电极 的掺杂区上方的剩余光刻胶去除；将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的第一金属层刻蚀去除。对P沟道区域的源电极的掺杂区和漏电极的掺杂区进行离子注入；将剩余的光刻胶全部去除。
进一步地，所述步骤C)进一步包括：在完成所述步骤B)的基板上形成第二绝缘层、透明导电层和光刻胶；利用所述第三带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的光刻胶以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的光刻胶去除；将N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的第一绝缘层、透明导电层和第二绝缘层去除，以形成接触孔；将除所述像素区的光刻胶之外的光刻胶全部去除，以使除所述像素区的透明导电层之外的透明导电层暴露；将所述暴露的透明导电层去除。
进一步地，所述步骤D)进一步包括：在完成所述步骤C)的基板上形成第二金属层；在第二金属层上涂布光刻胶，并利用所述第四带条纹的光罩对光刻胶进行曝光、显影，以将除N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的光刻胶以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的光刻胶之外的光刻胶去除；将暴露的第二金属层刻蚀去除；将N沟道区域的漏电极的重掺杂区上方的光刻胶和P沟道区域的源电极的掺杂区上方的光刻胶去除，并将N沟道区域的漏电极的源电极的重掺杂区上方的部分光刻胶和P沟道区域的漏电极的掺杂区上方的部分光刻胶去除；沉积形成钝化层；将N沟道区域的漏电极的源电极的重掺杂区上方的部分光刻胶和钝化层以及P沟道区域的漏电极的掺杂区上方的部分光刻胶和钝化层。
本发明的低温多晶硅薄膜晶体管阵列基板的制作方法，与现有技术的制作方法相比，仅利用四道带条纹的光罩来完成对低温多晶硅薄膜晶体管阵列基板的制作，能够大幅度降低光罩的使用数量，在降低制作成本的同时提高生产效率。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的制作方法的流程图；
图2-1至图2-25是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的制作结构图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，相同的标号将始终被用于表示相同的元件。
在本发明的低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)阵列基板的制作方法中，LTPS TFT阵列基板至少包括N沟道区域和P沟道区域，但本发明不限制于此。
图1是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的制作方法的流程图。图2-1至图2-25是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的制作结构图。
参照图1、图2-1至图2-25，在步骤210中，利用第一带条纹的光罩(例如，GTM(Gray Tone Mask，灰阶掩膜)光罩或者HTM(Half Tone Mask，半色调掩膜)光罩)定义出N沟道区域的源电极的重掺杂区316a、N沟道区域的源电极的轻掺杂区316b、N沟道区域的漏电极的重掺杂区317a及N沟道区域的漏电极的轻掺杂区317b。
进一步地，步骤210具体包括：
首先，在基板311上依次形成缓冲层312、多晶硅(p-Si)层313、第一绝缘层314和第一金属层315，如图2-1所示，这里，基板311可例如为一绝缘的玻璃基板或石英基板；缓冲层312可例如为通过PECVD工艺在基板311上形成的SiNx/SiOx结构；多晶硅层313的形成方式可例如是以溅射方式在缓冲层312表面形成一非晶硅(a-Si)层，再以退火方式使非晶硅层再结晶；第一 绝缘层314可例如为通过PECVD工艺在基板311上形成的SiNx/SiOx结构；第一金属层315作为栅电极金属层，其可例如为钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构。
接着，在第一金属层315上涂布一层光刻胶(图中以灰色框表示)，如图2-2所示。
接着，利用第一带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域的源电极的重掺杂区316a和漏电极的重掺杂区317a上方的光刻胶去除，并将源电极的轻掺杂区316b和漏电极的轻掺杂区317b上方的部分光刻胶去除，从而定义出N沟道区域的源电极的重掺杂区316a和轻掺杂区316b以及漏电极的重掺杂区317a和轻掺杂区317b，如图2-3所示。
接着，将N沟道区域的源电极的重掺杂区316a及漏电极的重掺杂区317a上方的第一金属层315刻蚀去除，如图2-4所示，这里，可采用干法刻蚀(Dry etch)或湿法刻蚀(Wet etch)。
接着，对N沟道区域的源电极的重掺杂区316a及漏电极的重掺杂区317a进行离子注入，如图2-5所示，这里，可采用磷/砷(P/As)离子进行注入。
接着，对剩余的光刻胶进行灰化(Ashing)处理，以将源电极的轻掺杂区316b和漏电极的轻掺杂区317b上方剩余的光刻胶去除，如图2-6所示。
接着，将源电极的轻掺杂区316b和漏电极的轻掺杂区317b上方的第一金属层315刻蚀去除，如图2-7所示，这里，可采用干法刻蚀或湿法刻蚀。
接着，对N沟道区域的源电极的重掺杂区316a、轻掺杂区316b以及漏电极的重掺杂区317a、轻掺杂区317b再次进行离子注入，如图2-8所示，这里，可采用磷/砷离子进行注入。
最后，利用灰化处理将剩余的光刻胶全部去除。
在步骤220中，利用第二带条纹的光罩(例如，GTM(Gray Tone Mask，灰阶掩膜)光罩或者HTM(Half Tone Mask，半色调掩膜)光罩)定义出P沟道区域的源电极的掺杂区318及P沟道区域的漏电极的掺杂区319。
进一步地，步骤220具体包括：
首先，在完成步骤210的基板311上涂布光刻胶(图中以灰色框表示)，如图2-9所示。
接着，利用第二带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域与P沟道区域之间的光刻胶去除，并将P沟道区域的源电极的掺杂区318及漏电极的掺杂区319上方的部分光刻胶去除，如图2-10所示。
接着，将N沟道区域与P沟道区域之间的多晶硅层313、第一绝缘层314和第一金属层315刻蚀去除，如图2-11所示，这里，可采用干法刻蚀或湿法刻蚀。
接着，对剩余的光刻胶进行灰化处理，以将P沟道区域的源电极的掺杂区318及漏电极的掺杂区319上方的剩余光刻胶去除，如图2-12所示。
接着，将P沟道区域的源电极的掺杂区318及漏电极的掺杂区319上方的第一金属层315刻蚀去除，如图2-13所示，这里，可采用干法刻蚀或湿法刻蚀。
接着，对P沟道区域的源电极的掺杂区318及漏电极的掺杂区319进行离子注入，以形成P沟道区域的源电极和漏电极，如图2-14所示，这里，可采用磷/砷离子进行注入。
最后，利用灰化处理将剩余的光刻胶全部去除。
在步骤230中，利用第三带条纹的光罩(例如，GTM(Gray Tone Mask，灰阶掩膜)光罩或者HTM(Half Tone Mask，半色调掩膜)光罩)定义出像素区、N沟道区域的漏电极的重掺杂区317a处的接触孔区、N沟道区域的源电极的重掺杂区316a处的接触孔区、P沟道区域的源电极的掺杂区318处的接触孔区及P沟道区域的漏电极的掺杂区319处的接触孔区。
进一步地，步骤230具体包括：
首先，在完成步骤220的基板311上形成第二绝缘层320、透明导电层324和光刻胶，如图2-15所示，这里，第二绝缘层320可例如是SiO/SiNx叠层结 构，透明导电层324可例如为铟锡氧化物(ITO)、锌基氧化物(AZO、BZO等)、铟镓锌氧化物(IGZO)等透明的且导电能力较好的金属氧化物薄膜层。
接着，利用第三带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域的漏电极的重掺杂区317a、源电极的重掺杂区316a上方的光刻胶以及P沟道区域的源电极的掺杂区318、漏电极的掺杂区319上方的光刻胶去除，如图2-16所示。
接着，将N沟道区域的漏电极的重掺杂区317a、源电极的重掺杂区316a上方的以及P沟道区域的源电极的掺杂区318、漏电极的掺杂区319上方的第一绝缘层314、透明导电层324和第二绝缘层320去除，以使接触孔321贯穿透明导电层324、第二绝缘层320和第一绝缘层314，从而使N沟道区域的漏电极的重掺杂区317a、源电极的重掺杂区316a以及P沟道区域的源电极的掺杂区318、漏电极的掺杂区319都暴露出，如图2-17所示。
接着，对剩余的光刻胶进行灰化处理，以将除像素区的光刻胶之外的光刻胶全部去除，以使除像素区的透明导电层324之外的透明导电层324暴露，如图2-18所示。
最后，将暴露出的透明导电层324去除掉，如图2-19所示。
在步骤240中，利用第四带条纹的光罩(例如，GTM(Gray Tone Mask，灰阶掩膜)光罩或者HTM(Half Tone Mask，半色调掩膜)光罩)定义出N沟道区域的漏电极的重掺杂区317a处的金属电极区、N沟道区域的源电极的重掺杂区316a处的金属电极区、P沟道区域的源电极的掺杂区318的金属电极区及P沟道区域的漏电极的掺杂区319处的金属电极区。
进一步地，步骤240具体包括：
首先，在完成步骤230的基板311上形成第二金属层322，如图2-20所示，这里，第二金属层322可例如为钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构。
接着，在第二金属层322上涂布光刻胶，并利用第四带条纹的光罩对光刻胶进行曝光、显影，以将除N沟道区域的漏电极的重掺杂区317a和源电极的 重掺杂区316a上方的光刻胶以及P沟道区域的源电极的掺杂区318和漏电极的掺杂区319上方的光刻胶之外的光刻胶去除，如图2-21所示。
接着，对暴露出的第二金属层322进行刻蚀去除，如图2-22所示，这里，可采用干法刻蚀或湿法刻蚀。
接着，将N沟道区域的漏电极的重掺杂区317a上方的光刻胶和P沟道区域的源电极的掺杂区318上方的光刻胶去除，并将N沟道区域的漏电极的源电极的重掺杂区316a上方的部分光刻胶和P沟道区域的漏电极的掺杂区319上方的部分光刻胶去除，如图2-23所示。
接着，沉积形成钝化层323，如图2-24所示，这里，钝化层323采用的材料可例如为SiNx。
最后，将N沟道区域的漏电极的源电极的重掺杂区316a上方的部分光刻胶和钝化层323以及P沟道区域的漏电极的掺杂区319上方的部分光刻胶和钝化层323去除，从而使N沟道区域的漏电极的重掺杂区317a上方的第二金属层322和P沟道区域的源电极的掺杂区318上方的第二金属层322漏出，以连接外部驱动电路。
综上所述，根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的制作方法仅利用四道带条纹的光罩来完成对低温多晶硅薄膜晶体管阵列基板的制作，能够大幅度降低带条纹的光罩的使用数量，在降低制作成本的同时提高生产效率。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种低温多晶硅薄膜晶体管阵列基板的制作方法，其中，包括步骤：
    A)利用第一带条纹的光罩定义出N沟道区域的源电极的重掺杂区、N沟道区域的源电极的轻掺杂区、N沟道区域的漏电极的重掺杂区及N沟道区域的漏电极的轻掺杂区；
    B)利用第二带条纹的光罩定义出P沟道区域的源电极的掺杂区及P沟道区域的漏电极的掺杂区；
    C)利用第三带条纹的光罩定义出像素区、N沟道区域的漏电极的重掺杂区处的接触孔区、N沟道区域的源电极的重掺杂区处的接触孔区、P沟道区域的源电极的掺杂区处的接触孔区及P沟道区域的漏电极的掺杂区处的接触孔区；
    D)利用第四带条纹的光罩定义出N沟道区域的漏电极的重掺杂区处的金属电极区、N沟道区域的源电极的重掺杂区处的金属电极区、P沟道区域的源电极的掺杂区的金属电极区及P沟道区域的漏电极的掺杂区处的金属电极区。
  2. 根据权利要求1所述的制作方法，其中，所述第一带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
  3. 根据权利要求1所述的制作方法，其中，所述第二带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
  4. 根据权利要求1所述的制作方法，其中，所述第三带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
  5. 根据权利要求1所述的制作方法，其中，所述第四带条纹的光罩为灰阶掩膜光罩或半色调掩膜光罩。
  6. 根据权利要求1所述的制作方法，其中，所述步骤A)进一步包括：
    在基板上依次形成缓冲层、多晶硅层、第一绝缘层和第一金属层；
    在第一金属层上涂布一层光刻胶；
    利用所述第一带条纹的光罩对所述光刻胶进行曝光、显影，以将N沟道区域的源电极的重掺杂区和漏电极的重掺杂区上方的光刻胶去除，并将源电极的轻掺杂区和漏电极的轻掺杂区上方的部分光刻胶去除；
    将N沟道区域的源电极的重掺杂区及漏电极的重掺杂区上方的第一金属层刻蚀去除；
    对N沟道区域的源电极的重掺杂区及漏电极的重掺杂区进行离子注入；
    将N沟道区域的源电极的轻掺杂区和漏电极的轻掺杂区上方剩余的光刻胶去除；
    将源电极的轻掺杂区和漏电极的轻掺杂区上方的第一金属层刻蚀去除；
    对N沟道区域的源电极的重掺杂区、轻掺杂区以及漏电极的重掺杂区、轻掺杂区再次进行离子注入；
    将剩余的光刻胶全部去除。
  7. 根据权利要求2所述的制作方法，其中，所述步骤A)进一步包括：
    在基板上依次形成缓冲层、多晶硅层、第一绝缘层和第一金属层；
    在第一金属层上涂布一层光刻胶；
    利用所述第一带条纹的光罩对所述光刻胶进行曝光、显影，以将N沟道区域的源电极的重掺杂区和漏电极的重掺杂区上方的光刻胶去除，并将源电极的轻掺杂区和漏电极的轻掺杂区上方的部分光刻胶去除；
    将N沟道区域的源电极的重掺杂区及漏电极的重掺杂区上方的第一金属层刻蚀去除；
    对N沟道区域的源电极的重掺杂区及漏电极的重掺杂区进行离子注入；
    将N沟道区域的源电极的轻掺杂区和漏电极的轻掺杂区上方剩余的光刻胶去除；
    将源电极的轻掺杂区和漏电极的轻掺杂区上方的第一金属层刻蚀去除；
    对N沟道区域的源电极的重掺杂区、轻掺杂区以及漏电极的重掺杂区、轻掺杂区再次进行离子注入；
    将剩余的光刻胶全部去除。
  8. 根据权利要求1所述的制作方法，其中，所述步骤B)进一步包括：
    在完成所述步骤A)的基板上涂布光刻胶；
    利用所述第二带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域与P沟道区域之间的光刻胶去除，并将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的部分光刻胶去除；
    将N沟道区域与P沟道区域之间的多晶硅层、第一绝缘层和第一金属层刻蚀去除；
    将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的剩余光刻胶去除；
    将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的第一金属层刻蚀去除。
    对P沟道区域的源电极的掺杂区和漏电极的掺杂区进行离子注入；
    将剩余的光刻胶全部去除。
  9. 根据权利要求3所述的制作方法，其中，所述步骤B)进一步包括：
    在完成所述步骤A)的基板上涂布光刻胶；
    利用所述第二带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域与P沟道区域之间的光刻胶去除，并将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的部分光刻胶去除；
    将N沟道区域与P沟道区域之间的多晶硅层、第一绝缘层和第一金属层刻蚀去除；
    将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的剩余光刻胶去除；
    将P沟道区域的源电极的掺杂区及漏电极的掺杂区上方的第一金属层刻蚀去除。
    对P沟道区域的源电极的掺杂区和漏电极的掺杂区进行离子注入；
    将剩余的光刻胶全部去除。
  10. 根据权利要求1所述的制作方法，其中，所述步骤C)进一步包括：
    在完成所述步骤B)的基板上形成第二绝缘层、透明导电层和光刻胶；
    利用所述第三带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的光刻胶以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的光刻胶去除；
    将N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的第一绝缘层、透明导电层和第二绝缘层去除，以形成接触孔；
    将除所述像素区的光刻胶之外的光刻胶全部去除，以使除所述像素区的透明导电层之外的透明导电层暴露；
    将所述暴露的透明导电层去除。
  11. 根据权利要求4所述的制作方法，其中，所述步骤C)进一步包括：
    在完成所述步骤B)的基板上形成第二绝缘层、透明导电层和光刻胶；
    利用所述第三带条纹的光罩对光刻胶进行曝光、显影，以将N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的光刻胶以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的光刻胶去除；
    将N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的第一绝缘层、透明导电层和第 二绝缘层去除，以形成接触孔；
    将除所述像素区的光刻胶之外的光刻胶全部去除，以使除所述像素区的透明导电层之外的透明导电层暴露；
    将所述暴露的透明导电层去除。
  12. 根据权利要求1所述的制作方法，其中，所述步骤D)进一步包括：
    在完成所述步骤C)的基板上形成第二金属层；
    在第二金属层上涂布光刻胶，并利用所述第四带条纹的光罩对光刻胶进行曝光、显影，以将除N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的光刻胶以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的光刻胶之外的光刻胶去除；
    将暴露的第二金属层刻蚀去除；
    将N沟道区域的漏电极的重掺杂区上方的光刻胶和P沟道区域的源电极的掺杂区上方的光刻胶去除，并将N沟道区域的漏电极的源电极的重掺杂区上方的部分光刻胶和P沟道区域的漏电极的掺杂区上方的部分光刻胶去除；
    沉积形成钝化层；
    将N沟道区域的漏电极的源电极的重掺杂区上方的部分光刻胶和钝化层以及P沟道区域的漏电极的掺杂区上方的部分光刻胶和钝化层。
  13. 根据权利要求5所述的制作方法，其中，所述步骤D)进一步包括：
    在完成所述步骤C)的基板上形成第二金属层；
    在第二金属层上涂布光刻胶，并利用所述第四带条纹的光罩对光刻胶进行曝光、显影，以将除N沟道区域的漏电极的重掺杂区和源电极的重掺杂区上方的光刻胶以及P沟道区域的源电极的掺杂区和漏电极的掺杂区上方的光刻胶之外的光刻胶去除；
    将暴露的第二金属层刻蚀去除；
    将N沟道区域的漏电极的重掺杂区上方的光刻胶和P沟道区域的源电极的掺杂区上方的光刻胶去除，并将N沟道区域的漏电极的源电极的重掺杂区上方的部分光刻胶和P沟道区域的漏电极的掺杂区上方的部分光刻胶去除；
    沉积形成钝化层；
    将N沟道区域的漏电极的源电极的重掺杂区上方的部分光刻胶和钝化层以及P沟道区域的漏电极的掺杂区上方的部分光刻胶和钝化层。
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