WO2019090868A1 - 垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管 - Google Patents

垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管 Download PDF

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WO2019090868A1
WO2019090868A1 PCT/CN2017/114067 CN2017114067W WO2019090868A1 WO 2019090868 A1 WO2019090868 A1 WO 2019090868A1 CN 2017114067 W CN2017114067 W CN 2017114067W WO 2019090868 A1 WO2019090868 A1 WO 2019090868A1
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layer
thin film
film transistor
source
structure thin
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PCT/CN2017/114067
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English (en)
French (fr)
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邓永
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深圳市华星光电技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors

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  • the present invention relates to the field of thin film transistor liquid crystal display, and more particularly to a method for fabricating a vertical structure thin film transistor and a vertical structure thin film transistor.
  • a conventional thin film transistor liquid crystal display device includes a thin film transistor.
  • the thin film transistor is a thin film transistor of a BCE structure or a thin film transistor of a Top-gate structure.
  • Thin film transistor the structure of the thin film transistor of the vertical structure is shown in FIG. 1.
  • the thin film transistor of the structure comprises a substrate 110, a source 120, a flat layer 130, a first insulating layer 140, a pixel electrode 150, an active layer 160, and a gate.
  • the channel width of the thin film transistor of the vertical structure can be made narrow, thereby increasing the on-state current; and the thin film transistor can be made small and the opening can be improved. rate.
  • a vertical structure thin film transistor is complicated in process, and generally requires more than five masks, and the cost is high.
  • a technical problem to be solved by embodiments of the present invention is to provide a method of fabricating a vertical structure thin film transistor and a vertical structure thin film transistor.
  • the process of the vertical structure thin film transistor can be simplified.
  • the first aspect of the present invention provides a method for manufacturing a vertical structure thin film transistor, including:
  • first insulating layer and a second metal layer on the substrate, respectively, and patterning the first insulating layer and the second metal layer by a first mask to respectively form a pad insulating layer and a source, wherein the source The pole is located on the high insulation layer;
  • the second insulating layer forms a passivation protective layer, a gate electrode, and a gate insulating layer.
  • the method further includes forming a via hole on the passivation protective layer through the third photomask.
  • the second photomask and the third photomask are halftone masks.
  • the gate is located above the active layer, and an area where the gate overlaps with the source and/or the drain on a horizontal plane respectively is 0.
  • the material of the oxide semiconductor layer is IGZO.
  • a second aspect of the present invention provides a vertical structure thin film transistor, including
  • An active layer and a doped layer on both sides of the active layer wherein a doped layer on one side is located on the source, a doped layer on the other side at least partially forms a drain, and the drain is located at the source Below the side;
  • a gate insulating layer formed on the active layer and the doped layer
  • a gate electrode on the gate insulating layer and above the active layer
  • a passivation protective layer is located on the gate.
  • the gate is located above the active layer, and an area of the gate overlapping with a projection of the source and/or the drain on a horizontal plane is 0.
  • the passivation protective layer is provided with a via hole.
  • the material of the active layer is IGZO
  • the doped layer is formed by doping hydrogen ions with IGZO.
  • the shape of the active layer is "L” type or "Z" type.
  • the vertical structure thin film transistor can be fabricated through three masks, the process is greatly simplified, thereby reducing the cost. Moreover, the vertical structure thin film transistor has a simple structure, and the lateral channel width can be made narrow, so that the thin film transistor can be made small, which is advantageous for increasing the aperture ratio and increasing the on-state current.
  • FIG. 1 is a cross-sectional view of a prior art vertical structure thin film transistor
  • FIG. 2 is a flow chart showing a method of fabricating a vertical structure thin film transistor according to an embodiment of the present invention
  • 3a-3c are schematic views showing deposition of respective film layers of a vertical structure thin film transistor on a substrate
  • 4a-4c are cross-sectional views of a vertical structure thin film transistor processed by a photomask
  • 5a-5c are top views of a vertical structure thin film transistor processed through a reticle.
  • Embodiments of the present invention provide a method for fabricating a vertical structure thin film transistor. Referring to FIG. 2, the method includes:
  • the substrate 210 is a glass substrate.
  • the present invention is not limited thereto.
  • the substrate may also be a light-transmissive substrate such as a flexible substrate or a plastic substrate.
  • S120 forming a first insulating layer and a second metal layer on the substrate, respectively, and patterning the first insulating layer and the second metal layer by using a first mask to form a pad insulating layer and a source, respectively.
  • the source is located on the pad insulating layer;
  • the material of the first insulating layer 220 is, for example, SiOx or the like.
  • the pad insulating layer 221 is disposed under the side of the source electrode 231 for raising the height of the source electrode 231.
  • the first insulating layer 220 and the second metal layer 230 are sequentially formed on the substrate 210, and then, referring to FIG. 4a and FIG. 5a, the second photomask is used to After the photoresist on the second metal layer 230 is exposed, the photoresist of the specific region is washed away, and then the second metal layer 230 is wet-etched to form the source 231, and then the second insulating layer 250 is dried. The etching is patterned to form the pad insulating layer 221.
  • the second metal layer and the first insulating layer may be patterned by one dry etching to form a source and a pad insulating layer.
  • the second metal layer 230 is patterned to form a data line 232, and the data line 232 is also located on the pad insulating layer 221, and the data line 232 and the corresponding The source 231 is electrically connected.
  • the pad insulating layer 221 is disposed under the source 231 side, the pad insulating layer 221 is relatively thick, thereby padding the source 231 located above the pad insulating layer 221, and
  • the longitudinal distance between the elongated source 231 and the later-mentioned drain, that is, the thickness of the later-mentioned active layer 241 can be elongated, that is, the travel of electrons in the active layer 241 is elongated.
  • S130 forming an oxide semiconductor layer on the source and the substrate, and patterning the oxide semiconductor layer to form an active layer by a second mask, and doping hydrogen ion formation on a portion of the oxide semiconductor layer a doped layer on both sides of the active layer, wherein one side of the doped layer is on the source, the other side of the doped layer at least partially forms a drain, and the drain is located below the source side;
  • oxygen is formed on the source 231 and the substrate 210.
  • the semiconductor layer 240 is, for example, an IGZO semiconductor layer.
  • the active layer 241 is formed by patterning the oxide semiconductor layer 240 through a second mask, and a portion of the oxide semiconductor layer 240 is doped with hydrogen ions to form an active layer. Doped layer on both sides of 241.
  • the photoresist on the oxide semiconductor layer 240 is exposed through the second mask, and then the first development and etching are performed to remove the unnecessary oxide semiconductor layer. 240.
  • a photoresist is formed on the oxide semiconductor layer 240 on the source 231, corresponding to the region where the active layer 241 is located and the region where the drain is located, and then passes through the second development.
  • the photoresist on the source and the drain is removed, and a photoresist is further formed on the active layer, and the exposed oxide semiconductor layer 240 is doped with hydrogen ions to form a doped layer, and then subjected to a third development. The remaining photoresist is removed to form the active layer 241.
  • the doped layer on the left side of the active layer 241 is referred to as a first doped layer 242, and the doped layer on the right side of the active layer 241 is referred to as a second doped layer 243.
  • the first doped layer 242 is located above the source 231 and is electrically connected to the source 231, and the second doped layer 243 is at least partially used as the drain, the first doped layer 242 and the second doped layer. 243 is located in a different plane.
  • the second mask is a half tone mask, so that one exposure can form different degrees of exposure to the photoresist, and then the photoresist of different regions is removed by several developments. Therefore, some areas can be removed by one development, and some areas require several developments to completely remove the photoresist.
  • the active layer 241 is designed to be "L" type, and the active layer 241 includes a longitudinal portion and a lateral portion, which can be reduced due to the presence of the longitudinal portion.
  • the lateral width of the active layer 241 is small, so that the size of the thin film transistor can be reduced, and the on-state current can be increased.
  • the active layer may also be of the "Z" type.
  • the drain is located below the side of the source 231, specifically on the substrate 210, so that the source 231 and the drain have a height difference.
  • the height difference may be used to lengthen the length of the channel of the active layer 241, specifically, elongated by the longitudinal portion of the active layer 241.
  • the length of the channel can prevent the active layer 241 from being short in the channel and affecting the electrical characteristics of the thin film transistor. For example, the problem that the source 231 and the drain are broken down due to the short channel of the active layer 241 can be prevented.
  • the substrate in order to prevent impurities in the substrate from entering the active layer, the doped layer, and the drain, the substrate is An isolation insulating layer may also be provided, the pad insulating layer, the second doping layer and the drain being on the isolation insulating layer.
  • the oxide semiconductor layer 240 further forms a pixel electrode 244 by doping hydrogen ions, and the pixel electrode 244 is electrically connected to the drain.
  • S140 sequentially forming a second insulating layer, a first metal layer, and a third insulating layer on the active layer and the doped layer, and patterning the third insulating layer and the first metal layer by using a third mask And a second insulating layer forms a passivation protective layer, a gate and a gate insulating layer.
  • a second insulating layer 250 is formed on the active layer 241, the first doping layer 242, the second doping layer 243, and the pixel electrode 244, and the second insulating layer 250 is A first metal layer 260 is formed thereon, and a third insulating layer 270 is formed on the first metal layer 260.
  • the exposure is performed by the third mask.
  • the third mask is a half tone mask, and the light on the third insulating layer 270 is The exposure is performed to different degrees, and then the first development and etching are performed to form a gate insulating layer 251, which may be a GI protective layer or a dielectric layer.
  • a second development and etching is performed to form a gate electrode 261 and a passivation protective layer 271.
  • the first metal layer 260 may be patterned to form the scan line 262, and the scan line 262 is electrically connected to the gate 261.
  • the vertical structure thin film transistor can be fabricated through three photomasks, the process is greatly simplified, thereby reducing the cost. Moreover, the vertical structure thin film transistor has a simple structure, and the lateral channel width can be made narrow, so that the thin film transistor can be made small, which is advantageous for increasing the aperture ratio.
  • the manufacturing method further includes:
  • the via 272 is located above the partial scan line 262 or above the gate 261, so that the scan line 262 or the gate 261 is exposed to facilitate the scan line 262 or the gate 261 and other lines. Electrical connections, such as electrical connections to peripheral lines, cause electrical signals from peripheral lines to pass to the scan lines 262 or gates 261.
  • the gate 261 is located above the active layer 241, and the area of the gate 261 overlapping with the projection of the source 231 and the drain on the horizontal plane is 0, thereby
  • the parasitic capacitance between the gate 261 and the source 231 and the drain is very small or absent, compared to the background art.
  • the vertical structure thin film transistor has a large parasitic capacitance, and the performance of the vertical structure thin film transistor of the embodiment of the present invention is greatly improved.
  • the gate may also overlap with the projection of the source on the horizontal plane by 0, or the gate may only be at the horizontal plane with the drain. The area on the top of the projection overlaps to zero.
  • the embodiment of the invention further provides a vertical structure thin film transistor, as shown in FIG. 4c, comprising:
  • a gate 261 located on the gate insulating layer 251 and above the active layer 241;
  • a passivation protective layer 271 is disposed on the gate 261.
  • the gate 261 is located above the active layer 241, and the area of the gate 261 overlapping with the projection of the source 231 and/or the drain on the horizontal plane is 0.
  • a via 272 is disposed on the passivation protective layer 271.
  • the material of the active layer 241 is IGZO, and the doped layer is formed by doping hydrogen ions with IGZO.
  • the shape of the active layer 241 is "L" type or "Z" type.
  • the present invention has the following advantages:
  • the vertical structure thin film transistor can be fabricated through three masks, the process is greatly simplified, thereby reducing the cost. Moreover, the vertical structure thin film transistor has a simple structure, and the lateral channel width can be made narrow, so that the thin film transistor can be made small, which is advantageous for increasing the aperture ratio and improving On-state current.

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Abstract

一种垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管，包括：提供基板（210）（S110）；在基板（210）上分别形成第一绝缘层（220）和第二金属层（230），并通过第一光罩图案化所述第一绝缘层（220）、第二金属层（230）以分别形成垫高绝缘层（221）、源极（231）（S120）；在源极（231）和所述基板（210）上形成氧化物半导体层（240），并通过第二光罩图案化所述氧化物半导体层（240）形成有源层（241），并对所述氧化物半导体层（240）部分区域掺杂氢离子形成位于有源层两侧的掺杂层（242、244）（S130）；在所述有源层（241）、掺杂层（242、244）上依次形成第二绝缘层（250）、第一金属层（260）和第三绝缘层（270），并通过第三光罩图案化所述第三绝缘层（270）、第一金属层（260）和第二绝缘层（250）形成钝化保护层（271）、栅极（261）和栅极绝缘层（251）（S140）。采用上述方法，具有简化垂直结构薄膜晶体管的制程的优点。

Description

垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管
本发明要求2017年11月10日递交的发明名称为“垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管”的申请号201711105478.0的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及薄膜晶体管液晶显示领域，特别是涉及一种垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管。
背景技术
现有的薄膜晶体管液晶显示装置，包括薄膜晶体管，一般说来，所述薄膜晶体管为BCE结构的薄膜晶体管或者Top-gate结构的薄膜晶体管，随着技术的进步，最近产品上出现了垂直结构的薄膜晶体管，该种垂直结构的薄膜晶体管结构请参见图1，该种结构的薄膜晶体管包括基板110、源极120、平坦层130、第一绝缘层140、像素电极150、有源层160、栅极绝缘层170和栅极180等膜层，该种垂直结构的薄膜晶体管沟道宽度可以做的很窄，进而可以提高开态电流；而且此种薄膜晶体管可以做的很小，还可以提高开口率。然而，目前此种垂直结构薄膜晶体管制程复杂，普遍需要5道以上的光罩，成本较高。
发明内容
本发明实施例所要解决的技术问题在于，提供一种垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管。可简化垂直结构薄膜晶体管的制程。
为了解决上述技术问题，本发明第一方面实施例提供了一种垂直结构薄膜晶体管的制造方法，包括：
提供基板；
在基板上分别形成第一绝缘层和第二金属层，并通过第一光罩图案化所述第一绝缘层、第二金属层以分别形成垫高绝缘层、源极，其中，所述源极位于所述垫高绝缘层上；
在源极和所述基板上形成氧化物半导体层，并通过第二光罩图案化所述氧化物半导体层形成有源层，并对所述氧化物半导体层部分区域掺杂氢离子形成位于有源层两侧的掺杂层，其中一侧的掺杂层位于源极上，另一侧的掺杂层至少部分形成漏极，并所述漏极位于所述源极的侧下方；
在所述有源层、掺杂层上依次形成第二绝缘层、第一金属层和第三绝缘层层，并通过第三光罩图案化所述第三绝缘层、第一金属层和第二绝缘层形成钝化保护层、栅极和栅极绝缘层。
其中，还包括：通过所述第三光罩在钝化保护层上形成过孔。
其中，所述第二光罩和所述第三光罩为半色调光罩。
其中，所述栅极位于有源层的上方，且所述栅极分别与所述源极和/或漏极在水平面上投影重叠的面积为0。
其中，所述氧化物半导体层的材料为IGZO。
本发明第二方面实施例提供了一种垂直结构薄膜晶体管，包括
基板；
垫高绝缘层，其位于所述基板上；
源极，其位于所述垫高绝缘层上；
有源层和位于有源层两侧的掺杂层，其中一侧的掺杂层位于源极上，另一侧的掺杂层至少部分形成漏极，并所述漏极位于所述源极的侧下方；
栅极绝缘层，其形成在有源层和掺杂层上；
栅极，其位于在所述栅极绝缘层上且位于所述有源层的上方；
钝化保护层，其位于所述栅极上。
其中，所述栅极位于有源层的上方，且所述栅极分别与所述源极和/或漏极在水平面上的投影重叠的面积为0。
其中，所述钝化保护层上设有过孔。
其中，所述有源层的材料为IGZO，所述掺杂层通过IGZO掺杂氢离子形成。
其中，所述有源层的形状为“L”型或者“Z”型。
实施本发明实施例，具有如下有益效果：
由于所述垂直结构薄膜晶体管通过3道光罩就可以制成，极大的简化了制程，从而降低了成本。而且，所述垂直结构薄膜晶体管结构简单，而且横向沟道宽度可以做的很窄，可以使薄膜晶体管做的很小，有利于提高开口率和提高开态电流。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术垂直结构薄膜晶体管的剖视示意图；
图2是本发明一实施例垂直结构薄膜晶体管的制造方法的流程图；
图3a-图3c是垂直结构薄膜晶体管的各个膜层沉积在基板上的示意图；
图4a-图4c是通过光罩处理后垂直结构薄膜晶体管的剖视图；
图5a-图5c是通过光罩处理后垂直结构薄膜晶体管的俯视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同的对象，而并非用于描述特定的顺序。
本发明实施例提供一种垂直结构薄膜晶体管的制造方法，请参见图2，包括：
S110：提供基板；
在本实施例中，所述基板210为玻璃基板，当然，本发明不限于此，在本发明的其他实施例中，所述基板还可以为柔性基板、塑料基板等透光的基板。
S120:在基板上分别形成第一绝缘层和第二金属层，并通过第一光罩图案化所述第一绝缘层、第二金属层以分别形成垫高绝缘层、源极，其中，所述源极位于所述垫高绝缘层上；
在本实施例中，所述第一绝缘层220的材料例如为SiOx等。在本实施例中，所述源极231的侧下方设有所述垫高绝缘层221，用于垫高所述源极231的高度。
在本实施例中，请参见图3a，在基板210上依序形成第一绝缘层220和第二金属层230，其后，请参见图4a和图5a，通过第二光罩对所述第二金属层230上的光阻曝光后，洗掉特定区域的光阻，然后对所述第二金属层230进行湿蚀刻图案化以形成源极231，接着对所述第二绝缘层250进行干蚀刻图案化以形成垫高绝缘层221。当然，在本发明的其他实施例中，所述第二金属层和所述第一绝缘层可以通过一次干蚀刻图案化以形成源极和垫高绝缘层。另外，在本实施例中，所述第二金属层230图案化后还形成数据线232，所述数据线232也位于所述垫高绝缘层221上，所述数据线232与对应的所述源极231电连接。
在本实施例中，由于所述源极231侧下方设有垫高绝缘层221，所述垫高绝缘层221比较厚，从而垫高了位于垫高绝缘层221之上的源极231，可以拉长源极231与后面提到的漏极之间的纵向距离，也即可以拉长后面提到的有源层241的厚度，也即拉长了电子在有源层241中的行程。
S130：在源极和所述基板上形成氧化物半导体层，并通过第二光罩图案化所述氧化物半导体层形成有源层，并对所述氧化物半导体层部分区域掺杂氢离子形成位于有源层两侧的掺杂层，其中一侧的掺杂层位于源极上，另一侧的掺杂层至少部分形成漏极，并所述漏极位于所述源极的侧下方；
在本实施例中，请参见图3b，在所述源极231和所述基板210上形成氧 化物半导体层240，所述氧化物半导体层240例如为IGZO半导体层。请参见图4b和图5b，其后通过第二光罩图案化所述氧化物半导体层240形成有源层241，并对所述氧化物半导体层240部分区域掺杂氢离子形成位于有源层241两侧的掺杂层。
具体说来，形成氧化物半导体层240后，通过第二光罩对所述氧化物半导体层240上的光阻进行曝光，然后进行第一次显影和蚀刻，去除掉不需要的氧化物半导体层240，此时，所述源极231上面、对应后面提到的有源层241所在的区域和漏极所在的区域的氧化物半导体层240上面还存在光阻，其后，通过第二次显影，去除掉源极和漏极上面的光阻，此时有源层上面还存在光阻，对露出的氧化物半导体层240掺杂氢离子处理，从而形成掺杂层，然后进行第三次显影，去除剩余的光阻，以形成有源层241。在本实施例中，位于有源层241左侧的掺杂层称作第一掺杂层242，位于有源层241右边的掺杂层称作第二掺杂层243。在本实施例中，第一掺杂层242位于源极231的上面且与源极231电连接，第二掺杂层243至少部分作为漏极，第一掺杂层242和第二掺杂层243位于不同的平面。在本实施例中，所述第二光罩为半色调光罩(half tone mask)，从而一次曝光可以对光阻形成不同程度的曝光，其后通过几次显影去除掉不同区域的光阻，从而有的区域经过一次显影就可以把光阻去掉，有的区域需要几次显影才能把光阻完全去掉。
为了减小所述薄膜晶体管的大小，在本实施例中，所述有源层241设计为“L”型，所述有源层241包括纵向部和横向部，由于存在纵向部，从而可以减小所述有源层241的横向宽度，从而可以缩小薄膜晶体管的尺寸，而且可以提高开态电流。另外，在本发明的其他实施例中，所述有源层还可以为“Z”型。为了不缩短电子的行程，在本实施例中，所述漏极位于所述源极231的侧下方，具体为位于所述基板210上，从而所述源极231和所述漏极存在高度差，而所述有源层位于所述源极231和漏极之间，该高度差可以用来拉长了有源层241沟道的长度，具体为通过有源层241的纵向部拉长了沟道的长度，可以防止有源层241沟道较短而影响薄膜晶体管的电性特性，例如可以防止由于有源层241沟道较短而导致源极231和漏极击穿的问题。另外，在本发明的其他实施例中，为了防止基板内的杂质进入到有源层、掺杂层、漏极中，所述基板上 还可以设有隔离绝缘层，所述垫高绝缘层、第二掺杂层和漏极位于隔离绝缘层上。
在本实施例中，所述氧化物半导体层240还通过掺杂氢离子形成像素电极244，所述像素电极244与所述漏极电连接。
S140：在所述有源层、掺杂层上依次形成第二绝缘层、第一金属层和第三绝缘层层，并通过第三光罩图案化所述第三绝缘层、第一金属层和第二绝缘层形成钝化保护层、栅极和栅极绝缘层。
具体说来，请参见图3c，在所述有源层241、第一掺杂层242、第二掺杂层243、像素电极244上形成第二绝缘层250，在所述第二绝缘层250上形成第一金属层260，在所述第一金属层260上形成第三绝缘层270。其后，请参见图4c和图5c，通过第三光罩进行曝光，在本实施例中所述第三光罩为半色调光罩(half tone mask)，对第三绝缘层270上面的光阻进行不同程度的曝光，其后进行第一次显影、蚀刻，形成栅极绝缘层251，所述栅极绝缘层251可以是GI保护层或者介电层。其后进行第二次显影和蚀刻，形成栅极261和钝化保护层271。另外，在本实施例中，还可以图案化所述第一金属层260形成所述扫描线262，所述扫描线262与所述栅极261电连接。
在本实施例中，由于所述垂直结构薄膜晶体管通过3道光罩就可以制成，极大的简化了制程，从而降低了成本。而且，所述垂直结构薄膜晶体管结构简单，而且横向沟道宽度可以做的很窄，可以使薄膜晶体管做的很小，有利于提高开口率。
在本实施例中，所述制造方法还包括：
S150：通过所述第三光罩在钝化保护层上形成过孔。
在本实施例中，所述过孔272位于部分扫描线262的上方或者栅极261的上方，从而使扫描线262或者栅极261露出来，有利于扫描线262或者栅极261与其他线路的电连接，例如与周边线路电连接，使周边线路的电信号传递给所述扫描线262或者栅极261。
在本实施例中，所述栅极261位于有源层241的上方，且所述栅极261分别与所述源极231、漏极在水平面上的投影重叠的面积为0，从而，所述栅极261与所述源极231、漏极之间的寄生电容非常小或者没有，相比背景技术 中的垂直结构薄膜晶体管具有较大的寄生电容，本发明实施例的垂直结构的薄膜晶体管本身性能得到了很大提高。另外，在本发明的其他实施例中，所述栅极还可以只与所述源极在水平面上的投影重叠的面积为0，或者，所述栅极还可以只与所述漏极在水平面上的投影重叠的面积为0。
本发明实施例还提供一种垂直结构薄膜晶体管，请参见图4c，包括：
基板210；
垫高绝缘层221，其位于所述基板210上；
源极231，其位于所述垫高绝缘层221上；
有源层241和位于有源层241两侧的掺杂层，其中一侧的掺杂层(第一掺杂层241)位于源极231上，另一侧的掺杂层(第一掺杂层242)至少部分形成漏极，并所述漏极位于所述源极231的侧下方；
栅极绝缘层251，其形成在有源层241和掺杂层上；
栅极261，其位于在所述栅极绝缘层251上且位于所述有源层241的上方；
钝化保护层271，其位于所述栅极261上。
在本实施例中，所述栅极261位于有源层241的上方，且所述栅极261分别与所述源极231和/或漏极在水平面上的投影重叠的面积为0。所述钝化保护层271上设有过孔272。所述有源层241的材料为IGZO，所述掺杂层通过IGZO掺杂氢离子形成。所述有源层241的形状为“L”型或者“Z”型。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
通过上述实施例的描述，本发明具有以下优点：
由于所述垂直结构薄膜晶体管通过3道光罩就可以制成，极大的简化了制程，从而降低了成本。而且，所述垂直结构薄膜晶体管结构简单，而且横向沟道宽度可以做的很窄，可以使薄膜晶体管做的很小，有利于提高开口率和提高 开态电流。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种垂直结构薄膜晶体管的制造方法，其中，包括：
    提供基板；
    在基板上分别形成第一绝缘层和第二金属层，并通过第一光罩图案化所述第一绝缘层、第二金属层以分别形成垫高绝缘层、源极，其中，所述源极位于所述垫高绝缘层上；
    在源极和所述基板上形成氧化物半导体层，并通过第二光罩图案化所述氧化物半导体层形成有源层，并对所述氧化物半导体层部分区域掺杂氢离子形成位于有源层两侧的掺杂层，其中一侧的掺杂层位于源极上，另一侧的掺杂层至少部分形成漏极，并所述漏极位于所述源极的侧下方；
    在所述有源层、掺杂层上依次形成第二绝缘层、第一金属层和第三绝缘层层，并通过第三光罩图案化所述第三绝缘层、第一金属层和第二绝缘层形成钝化保护层、栅极和栅极绝缘层。
  2. 如权利要求1所述的垂直结构薄膜晶体管的制造方法，其中，还包括：
    通过所述第三光罩在钝化保护层上形成过孔。
  3. 如权利要求1所述的垂直结构薄膜晶体管的制造方法，其中，所述第二光罩和所述第三光罩为半色调光罩。
  4. 如权利要求1所述的垂直结构薄膜晶体管的制造方法，其中，所述栅极位于有源层的上方，且所述栅极分别与所述源极和/或漏极在水平面上投影重叠的面积为0。
  5. 如权利要求1所述的垂直结构薄膜晶体管的制造方法，其中，所述氧化物半导体层的材料为IGZO。
  6. 一种垂直结构薄膜晶体管，其中，包括：
    基板；
    垫高绝缘层，其位于所述基板上；
    源极，其位于所述垫高绝缘层上；
    有源层和位于有源层两侧的掺杂层，其中一侧的掺杂层位于源极上，另一侧的掺杂层至少部分形成漏极，并所述漏极位于所述源极的侧下方；
    栅极绝缘层，其形成在有源层和掺杂层上；
    栅极，其位于在所述栅极绝缘层上且位于所述有源层的上方；
    钝化保护层，其位于所述栅极上。
  7. 如权利要求6所述的垂直结构薄膜晶体管，其中，所述栅极位于有源层的上方，且所述栅极分别与所述源极和/或漏极在水平面上的投影重叠的面积为0。
  8. 如权利要求6所述的垂直结构薄膜晶体管，其中，所述钝化保护层上设有过孔。
  9. 如权利要求6所述的垂直结构薄膜晶体管，其中，所述有源层的材料为IGZO，所述掺杂层通过IGZO掺杂氢离子形成。
  10. 如权利要求6所述的垂直结构薄膜晶体管，其中，所述有源层的形状为“L”型或者“Z”型。
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