WO2020181731A1 - 一种薄膜晶体管及其制造方法 - Google Patents

一种薄膜晶体管及其制造方法 Download PDF

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WO2020181731A1
WO2020181731A1 PCT/CN2019/102751 CN2019102751W WO2020181731A1 WO 2020181731 A1 WO2020181731 A1 WO 2020181731A1 CN 2019102751 W CN2019102751 W CN 2019102751W WO 2020181731 A1 WO2020181731 A1 WO 2020181731A1
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electrode
region
layer
semiconductor material
area
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PCT/CN2019/102751
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English (en)
French (fr)
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赵文达
戴超
曹焜
彭云霞
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南京中电熊猫平板显示科技有限公司
南京中电熊猫液晶显示科技有限公司
南京华东电子信息科技股份有限公司
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Publication of WO2020181731A1 publication Critical patent/WO2020181731A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • the invention belongs to the field of thin film transistors, and specifically relates to a thin film transistor and a manufacturing method thereof.
  • the prior art proposes an ultra-short channel TFT design based on the back-channel etched thin film transistor (TFT) structure.
  • the schematic diagram of the structure is shown in Figure 1, and the top view as shown in picture 2.
  • the TFT structure includes a gate 11, a gate insulating layer 12, a semiconductor layer 13, a first electrode 141, an isolation layer 15 and a second electrode 142 which are sequentially formed.
  • the second electrode 142 is connected to the semiconductor layer 13 through the contact hole of the isolation layer 15.
  • the source and drain of different layers are isolated by the isolation layer 15, which can avoid the problem of the limitation of the metal exposure distance of the same layer.
  • the channel length L1 can be less than or equal to 1um, and the total length of the source and drain plus the channel can be less than or equal to 6um.
  • the second electrode 142 partially covers the channel, forming a top gate effect, resulting in deterioration of the TFT device characteristics.
  • the overlapping area of the second electrode 142 and the gate 11 is large, which is prone to generate a large parasitic capacitance.
  • the present invention provides a thin film transistor and a manufacturing method thereof.
  • a first electrode region formed by conducting semiconductor materials and a second electrode of a different layer constitute the source and drain of the thin film transistor, so as to realize an ultra-short channel and avoid Deterioration of TFT device characteristics and large parasitic capacitance occur.
  • the first aspect of the present invention provides a thin film transistor including:
  • the semiconductor material layer is located above the gate insulating layer; the semiconductor material layer includes a first electrode region formed by conducting semiconductor material and a first semiconducting region and a second semiconducting region respectively located on both sides of the first electrode region ;
  • the second electrode is in contact with the upper surface of the first semiconductor region and is not in direct contact with the first electrode region;
  • the first lead electrode is located above the isolation layer and contacts the first electrode area through the first contact hole;
  • the first electrode region and the second electrode define the channel region of the thin film transistor, and the isolation layer covers the upper surface of the channel region.
  • the second aspect of the present invention provides another thin film transistor, including:
  • the second electrode is located above the gate insulating layer
  • the semiconductor material layer includes a first electrode region formed by conducting a semiconductor material and a first semiconducting region and a second semiconducting region respectively located on both sides of the first electrode region; part of the lower surface of the first semiconducting region and the second semiconducting region The two electrodes are in contact, the lower surface of the second semiconductor region is in contact with the gate insulating layer, and the first electrode region is not in direct contact with the second electrode;
  • a first extraction electrode located above the isolation layer and contacting the first electrode area through the first contact hole;
  • the first electrode region and the second electrode define the channel region of the thin film transistor, and the isolation layer covers the upper surface of the channel region.
  • the third aspect of the present invention provides yet another thin film transistor, including:
  • the semiconductor material layer includes a first electrode region formed by conducting semiconductor material and a first semiconducting region and a second semiconducting region respectively located on both sides of the first electrode region;
  • the second electrode is in contact with part of the upper surface of the first semiconductor region, and is not in direct contact with the first electrode region;
  • a first extraction electrode located above the isolation layer and contacting the first electrode area through the first contact hole;
  • the gate insulating layer is located above the isolation layer and the first lead electrode;
  • the gate is located above the gate insulating layer
  • a passivation layer covering the gate and the gate insulating layer
  • the first electrode region and the second electrode define the channel region of the thin film transistor, and the isolation layer covers the upper surface of the channel region.
  • the fourth aspect of the present invention provides yet another thin film transistor, including:
  • the semiconductor material layer includes a first electrode region formed by conducting a semiconductor material and a first semiconducting region and a second semiconducting region respectively located on both sides of the first electrode region; part of the lower surface of the first semiconducting region and the second semiconducting region The two electrodes are in contact, and the first electrode area is not in direct contact with the second electrode;
  • a first extraction electrode located above the isolation layer and contacting the first electrode area through the first contact hole;
  • the gate insulating layer is located above the isolation layer and the first lead electrode;
  • the gate is located above the gate insulating layer
  • the passivation layer covers the gate and the gate insulating layer.
  • the first extraction electrode only contacts a part of the upper surface of the first electrode area in the first contact hole, and the first contact hole still exposes a part of the first electrode area Upper surface
  • the first electrode region and the second electrode define the channel region of the thin film transistor, and the isolation layer covers the upper surface of the channel region.
  • the present invention provides a method for manufacturing a thin film transistor, including the steps:
  • S5 forming an isolation layer covering the second electrode and the second semiconductor region, and patterning the isolation layer to form a first contact hole exposing at least part of the upper surface of the semiconductor material layer;
  • S6 Use the isolation layer as a shielding layer to conduct the conductorization of the semiconductor material layer exposed in the first contact hole to form a first electrode region, and the unconducted regions of the semiconductor material layer form first semiconductors located on both sides of the first electrode region.
  • the isolation layer covers the upper surface of the channel region;
  • the present invention provides a method for manufacturing a thin film transistor, including the steps:
  • a semiconductor material layer is formed of a semiconductor material, part of its lower surface is in contact with the gate insulating layer, and a part of the lower surface is in contact with the second electrode;
  • S5 forming an isolation layer covering the second electrode and the semiconductor material layer, and patterning the isolation layer to form a first contact hole exposing at least part of the upper surface of the semiconductor material layer;
  • S6 Use the isolation layer as a shielding layer to conduct the conductorization of the semiconductor material layer exposed in the first contact hole to form a first electrode region, and the unconducted regions of the semiconductor material layer form first semiconductors located on both sides of the first electrode region.
  • Area and the second semiconducting area part of the lower surface of the first semiconducting area is in contact with the second electrode, the lower surface of the second semiconducting area is in contact with the gate insulating layer, and the first electrode area is not in direct contact with the second electrode;
  • the first electrode region and the second electrode define the channel region of the thin film transistor, and the isolation layer covers the upper surface of the channel region;
  • the present invention provides a method for manufacturing a thin film transistor, including the steps:
  • a semiconductor material layer is formed from a semiconductor material
  • S3 forming an isolation layer covering the second electrode and the semiconductor material layer, and patterning the isolation layer to form a first contact hole exposing at least a part of the upper surface of the semiconductor material layer;
  • S4 Conducting the semiconductor material layer exposed in the first contact hole by using the isolation layer as a shielding layer to form a first electrode region, and the unconducted regions of the semiconductor material layer form first semiconductors located on both sides of the first electrode region.
  • the isolation layer covers the upper surface of the channel region;
  • the present invention provides a method for manufacturing a thin film transistor, including the steps:
  • a semiconductor material layer is formed of a semiconductor material, part of the lower surface of which is in contact with the second electrode;
  • S3 forming an isolation layer covering the second electrode and the semiconductor material layer, and patterning the isolation layer to form a first contact hole exposing at least a part of the upper surface of the semiconductor material layer;
  • S4 Conducting the semiconductor material layer exposed in the first contact hole by using the isolation layer as a shielding layer to form a first electrode region, and the unconducted regions of the semiconductor material layer form first semiconductors located on both sides of the first electrode region. Region and the second semiconductor region; part of the lower surface of the first semiconductor region is in contact with the second electrode, the first electrode region and the second electrode are not in direct contact; the first electrode region and the second electrode define the channel region of the thin film transistor , The isolation layer covers the upper surface of the channel region;
  • the method for conducting the semiconductor material layer is plasma treatment or ion implantation.
  • the present invention can bring at least one of the following beneficial effects:
  • the channel length can be further shortened on the basis of the original process limitation; the channel length can reach 1um and below, achieving ultra-short Channel
  • the first lead-out electrode is in contact with at least part of the first electrode area through the first contact hole of the isolation layer, which can effectively reduce the area of the overlap area between the gate and the first electrode area in the vertical direction, and avoid parasitic formation. capacitance;
  • the isolation layer covers the channel region of the thin film transistor, and plays a role of protecting the upper surface of the channel region in the subsequent manufacturing steps, and avoids the deterioration of the characteristics of the thin film transistor caused by damage to the upper surface of the channel region.
  • FIG. 1 is a schematic diagram of the structure of a conventional etching protection type thin film transistor
  • FIG. 2 is a top view of the thin film transistor shown in FIG. 1;
  • FIG. 3 is a schematic diagram of the overlapping area of the second electrode and the gate in the thin film transistor shown in FIG. 1;
  • FIG. 4 is a schematic structural diagram of a thin film transistor according to the first embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for manufacturing a thin film transistor according to the first embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a thin film transistor according to the second embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for manufacturing a thin film transistor according to the second embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the structure of a thin film transistor according to the third embodiment of the present invention.
  • FIG. 9 is a flowchart of a method for manufacturing a thin film transistor according to the third embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a thin film transistor according to the fourth embodiment of the present invention.
  • FIG. 11 is a flowchart of a method for manufacturing a thin film transistor according to the fourth embodiment of the present invention.
  • the thin film transistor proposed by the present invention includes a semiconductor material layer formed of a semiconductor material, and a part of the semiconductor material layer is conductorized to form a first electrode.
  • the unconducted regions of the semiconductor material layer are formed on both sides of the first electrode area.
  • the second electrode of the thin film transistor is in contact with the first semiconducting region or the second semiconducting region, and is not in direct contact with the first electrode region.
  • a part of the semiconductor material layer between the adjacent edges of the first electrode region and the second electrode serves as a semiconductor active region, and one of the first electrode region and the second electrode serves as a source electrode, and the other serves as a drain electrode.
  • the length of the semiconductor active region is the channel length. Since there is no problem of the limitation of the exposure distance between the same layer of metal, there will be a certain penetration during the conductorization process, so that the channel length can be further shortened on the basis of the original process limitation; Can reach 1um and below, realize ultra-short channel.
  • an isolation layer covering the second electrode and the semiconductor material layer is used as a shielding layer.
  • the isolation layer includes a first contact hole exposing at least part of the upper surface of the semiconductor material layer. , Conducting only the semiconductor material layer exposed in the first contact hole.
  • the method of conductorization is plasma treatment or ion implantation. Accurate selection of localized conductorization without a shielding layer requires precise equipment.
  • the shielding layer with the first contact hole in the present invention realizes the conductorization of the precise selection of the local area at low cost; and the isolation layer covers the channel area of the thin film transistor, in the subsequent manufacturing steps (especially the patterning step of the metal layer) It plays a role in protecting the upper surface of the channel region and avoids the deterioration of the characteristics of the thin film transistor caused by the damage on the upper surface of the channel region.
  • the second electrode and the semiconductor active region do not overlap in the vertical direction, which can avoid the top gate effect, thereby avoiding the deterioration of the TFT device characteristics.
  • the first lead electrode is in contact with the first electrode area through the first contact hole of the isolation layer, which can effectively reduce the area of the overlap area between the gate and the first electrode area in the vertical direction, and avoid the formation of parasitic capacitance.
  • the thin film transistor of the present invention and its manufacturing method will be described in detail below with specific embodiments.
  • FIG. 4 is a schematic structural diagram of a thin film transistor according to Embodiment 1 of the present invention.
  • the thin film transistor is of a bottom gate type and a part of the semiconductor material layer is located below the second electrode 042 when it is in contact with the second electrode 042.
  • the thin film transistor includes: a gate electrode 01 on a substrate (not shown), a gate insulating layer 02 covering the gate electrode 01, a semiconductor material layer above the gate insulating layer 02, and a semiconductor material layer
  • the second electrode 042, the isolation layer 05, and the first extraction electrode 0411 are in contact with the upper surface of a part of the area.
  • the semiconductor material layer is formed of a semiconductor material, and includes a first electrode region 041 formed by conducting the semiconductor material and a first semiconducting region 031 and a second semiconducting region 032 respectively located on both sides of the first electrode region 041.
  • the second electrode 042 is in contact with the upper surface of the first semiconductor region 031, and is not in direct contact with the first electrode region 041.
  • a part of the semiconductor material layer between the adjacent edges of the first electrode region 041 and the second electrode 042 is the semiconductor active region 0311, and the projection of the semiconductor active region 0311 and the gate electrode 01 in the vertical direction at least partially overlap.
  • the isolation layer 05 covers the second electrode 042 and the second semiconducting region 032, and the isolation layer 05 has a first contact hole exposing at least a part of the upper surface of the first electrode region 041.
  • the first extraction electrode 0411 is located above the isolation layer 05 and contacts the first electrode area 041 through the first contact hole.
  • a passivation layer 06 located above the isolation layer 05 and the first extraction electrode 0411 is subsequently formed to prevent environmental water and oxygen from affecting the device.
  • the length L1 of the semiconductor active region 0311 is the channel length. Since there is no problem of the limitation of the exposure distance of the same layer of metal, there will be a certain penetration during the conductive process, so that the channel length can be based on the original process limitation.
  • the upper part is further shortened; the channel length L1 can reach 1um and below to realize an ultra-short channel.
  • the second electrode 042 and the semiconductor active region 0311 do not overlap in the vertical direction, which can avoid the top gate effect, thereby avoiding the deterioration of the TFT device characteristics.
  • the first lead electrode 0411 is in contact with the first electrode area 041 through the first contact hole of the isolation layer 05, which can effectively reduce the area of the overlap area between the gate electrode 01 and the first electrode area 041 in the vertical direction, and avoid the formation of parasitic capacitance .
  • the first extraction electrode 0411 only contacts a part of the upper surface of the first electrode area 041 in the first contact hole, and the first contact hole still exposes part of the upper surface of the first electrode area 041, so as to further reduce the gate 01 and its Parasitic capacitance formed by the upper metal layer.
  • FIG. 5 is a flowchart of a method for manufacturing a thin film transistor according to the first embodiment of the present invention. The method includes the following steps:
  • a layer of semiconductor material located above the gate insulating layer 02 is formed of a semiconductor material
  • S5 forming an isolation layer 05 covering the second electrode 042 and the second semiconductor region 032, and patterning the isolation layer 05 to form a first contact hole exposing at least part of the upper surface of the semiconductor material layer;
  • S6 Use the isolation layer 05 as a shielding layer to conduct the conductorization of the semiconductor material layer exposed in the first contact hole to form the first electrode region 041.
  • the unconducted regions of the semiconductor material layer form the first electrode region 041 respectively.
  • the first electrode area 041 and the second electrode 042 define the channel area of the thin film transistor, and the isolation layer 05 covers the upper surface of the channel area, and plays a role in protecting the upper surface of the channel area during the patterning process of the first extraction electrode 0411 , To avoid the deterioration of the characteristics of the thin film transistor caused by the damage on the upper surface of the channel region.
  • the method for conducting the semiconductor material layer is plasma treatment or ion implantation, but it is not limited thereto.
  • FIG. 6 is a schematic structural diagram of a thin film transistor according to the second embodiment of the present invention.
  • the thin film transistor is of a bottom gate type and a part of the semiconductor material layer is located above the second electrode 042 when it is in contact with the second electrode 042.
  • the thin film transistor includes: a gate electrode 01 on a substrate (not shown), a gate insulating layer 02 covering the gate electrode 01, a second electrode 04 above the gate insulating layer 02, a part of the lower surface
  • the semiconductor material layer in contact with the semiconductor material layer, the isolation layer 05 and the first lead electrode 0411.
  • the semiconductor material layer is formed of semiconductor material, part of its lower surface is in contact with the gate insulating layer 02, and part of the lower surface is in contact with the second electrode 042.
  • the semiconductor material layer includes a first electrode region 041 formed by conducting a semiconductor material, and a first semiconducting region 031 and a second semiconducting region 032 respectively located on both sides of the first electrode region 041. Part of the bottom surface of the first semiconducting region 031 is in contact with the second electrode 042, the bottom surface of the second semiconducting region 032 is in contact with the gate insulating layer 02, and the first electrode region 041 and the second electrode 042 are not in direct contact.
  • a part of the semiconductor material layer between the adjacent edges of the first electrode region 041 and the second electrode 042 is the semiconductor active region 0311, and the projection of the semiconductor active region 0311 and the gate electrode 01 in the vertical direction at least partially overlap.
  • the isolation layer 05 covers the first semiconductor region 031 and the second semiconductor region 032, and the isolation layer 05 has a first contact hole exposing at least part of the upper surface of the first electrode region 041.
  • the first extraction electrode 0411 is located above the isolation layer 05 and contacts the first electrode area 041 through the first contact hole.
  • a passivation layer 06 located above the isolation layer 05 and the first extraction electrode 0411 is subsequently formed to prevent environmental water and oxygen from affecting the device.
  • the length of the semiconductor active region 0311 is the channel length. Since there is no problem of the same layer of metal exposure spacing limitation, there will be a certain penetration during the conductive process, so that the channel length can be based on the original process limitation. , Further shorten; the channel length can reach 1um and below, realize the ultra-short channel.
  • the second electrode 042 and the semiconductor active region 0311 do not overlap in the vertical direction, which can avoid the top gate effect, thereby avoiding the deterioration of the TFT device characteristics.
  • the first lead electrode 0411 is in contact with at least a part of the first electrode region 041 through the first contact hole of the isolation layer 05, which can effectively reduce the area of the overlapped area of the gate electrode 01 and the first electrode region 041 in the vertical direction. Avoid the formation of parasitic capacitance.
  • the first extraction electrode 0411 only contacts a part of the upper surface of the first electrode area 041 in the first contact hole, and the first contact hole still exposes part of the upper surface of the first electrode area 041, so as to further reduce the gate 01 and its Parasitic capacitance formed by the upper metal layer.
  • FIG. 7 is a flowchart of a method for manufacturing a thin film transistor according to the second embodiment of the present invention. The method includes the following steps:
  • a semiconductor material layer is formed of a semiconductor material, part of its lower surface is in contact with the gate insulating layer 02, and a part of the lower surface is in contact with the second electrode 042;
  • S5 forming an isolation layer 05 covering the second electrode 042 and the semiconductor material layer, and patterning the isolation layer 05 to form a first contact hole exposing at least part of the upper surface of the semiconductor material layer;
  • S6 Use the isolation layer 05 as a shielding layer to conduct the conductorization of the semiconductor material layer exposed in the first contact hole to form the first electrode region 041, and the unconducted regions of the semiconductor material layer form the first electrode region 041 respectively located on both sides of the first electrode region 041
  • the first electrode area 041 and the second electrode 042 define the channel area of the thin film transistor, and the isolation layer 05 covers the upper surface of the channel area, and plays a role in protecting the upper surface of the channel area during the patterning process of the first extraction electrode 0411 , To avoid the deterioration of the characteristics of the thin film transistor caused by the damage on the upper surface of the channel region.
  • the method for conducting the semiconductor material layer is plasma treatment or ion implantation, but it is not limited thereto.
  • the thin film transistor is of a top gate type and a part of the semiconductor material layer is located below the second electrode 042 when it is in contact with the second electrode 042.
  • the thin film transistor includes: a semiconductor material layer on a substrate (not shown), a second electrode 042, an isolation layer 05, and a first extraction electrode 0411 in contact with a part of the upper surface of the first semiconductor region 031 ,
  • the semiconductor material layer is formed of a semiconductor material, and includes a first electrode region 041 formed by conducting the semiconductor material and a first semiconducting region 031 and a second semiconducting region 032 respectively located on both sides of the first electrode region 041.
  • the second electrode 042 is in contact with part of the upper surface of the first semiconductor region 031, and is not in direct contact with the first electrode region 041.
  • a part of the semiconductor material layer between the adjacent edges of the first electrode region 041 and the second electrode 042 is the semiconductor active region 0311, and the projection of the semiconductor active region 0311 and the gate electrode 01 in the vertical direction at least partially overlap.
  • the isolation layer 05 covers the second electrode 042 and the second semiconducting region 032, and the isolation layer 05 has a first contact hole exposing at least a part of the upper surface of the first electrode region 041.
  • the first extraction electrode 0411 is located above the isolation layer 05 and contacts the first electrode area 041 through the first contact hole.
  • the length of the semiconductor active region 0311 is the channel length. Since there is no problem of the limitation of the exposure distance of the same layer of metal, there will be a certain penetration during the conductive process, so that the channel length can be based on the original process limitation. , Further shorten; the channel length can reach 1um and below, realize the ultra-short channel.
  • the second electrode 042 and the semiconductor active region 0311 do not overlap in the vertical direction, which can avoid the top gate effect, thereby avoiding the deterioration of the TFT device characteristics.
  • the first extraction electrode 0411 is in contact with at least a part of the first electrode area 041 through the first contact hole of the isolation layer 05, which can effectively reduce the area of the overlap area of the gate electrode 01 and the first electrode area 041 in the vertical direction. Avoid the formation of parasitic capacitance.
  • the first extraction electrode 0411 only contacts a part of the upper surface of the first electrode area 041 in the first contact hole, and the first contact hole still exposes part of the upper surface of the first electrode area 041, so as to further reduce the gate 01 and its Parasitic capacitance formed by the upper metal layer.
  • FIG. 9 is a flowchart of a method for manufacturing a thin film transistor according to a third embodiment of the present invention, and the method includes the following steps:
  • a semiconductor material layer is formed from a semiconductor material
  • S3 forming an isolation layer 05 covering the second electrode 042 and the semiconductor material layer, and patterning the isolation layer 05 to form a first contact hole exposing at least part of the upper surface of the semiconductor material layer;
  • S4 Use the isolation layer 05 as a shielding layer to conduct the conductorization of the semiconductor material layer exposed in the first contact hole to form the first electrode region 041, and the unconducted regions of the semiconductor material layer form the first electrode region 041 respectively.
  • the first electrode area 041 and the second electrode 042 define the channel area of the thin film transistor, and the isolation layer 05 covers the upper surface of the channel area, and plays a role in protecting the upper surface of the channel area during the patterning process of the first extraction electrode 0411 , To avoid the deterioration of the characteristics of the thin film transistor caused by the damage on the upper surface of the channel region.
  • the method for conducting the semiconductor material layer is plasma treatment or ion implantation, but it is not limited thereto.
  • the thin film transistor is of a top gate type and a part of the semiconductor material layer is located above the second electrode 042 when it is in contact with the second electrode 042.
  • the thin film transistor includes: an electrode located on a substrate (not shown), a semiconductor material layer on a part of the lower surface in contact with the second electrode 042, an isolation layer 05, a first extraction electrode 0411, an isolation layer 05 and The gate insulating layer 02 above the first extraction electrode 0411, the gate 01 located above the gate insulating layer 02, and the passivation layer 06 covering the gate 01 and the gate insulating layer 02.
  • the semiconductor material layer is formed of a semiconductor material, and includes a first electrode region 041 formed by conducting the semiconductor material and a first semiconductor region 031 and a second semiconductor region 032 located on both sides of the first electrode region 041, respectively. Part of the lower surface of the first semiconducting region 031 is in contact with the second electrode 042, and the first electrode region 041 and the second electrode 042 are not in direct contact. A part of the semiconductor material layer between the adjacent edges of the first electrode region 041 and the second electrode 042 is the semiconductor active region 0311, and the projection of the semiconductor active region 0311 and the gate electrode 01 in the vertical direction at least partially overlap.
  • the isolation layer 05 covers the first semiconductor region 031 and the second semiconductor region 032, and the isolation layer 05 has a first contact hole exposing at least part of the upper surface of the first electrode region 041.
  • the first extraction electrode 0411 is located above the isolation layer 05 and contacts the first electrode area 041 through the first contact hole.
  • the length of the semiconductor active region 0311 is the channel length. Since there is no problem of the limitation of the exposure distance between the same layer of metal, there will be a certain penetration during the conductive process, so that the channel length can be based on the original process limitation. , Further shorten; the channel length can reach 1um and below, realize the ultra-short channel.
  • the second electrode 042 and the semiconductor active region 0311 do not overlap in the vertical direction, which can avoid the top gate effect, thereby avoiding the deterioration of the TFT device characteristics.
  • the first extraction electrode 0411 is in contact with at least a part of the first electrode area 041 through the first contact hole of the isolation layer 05, which can effectively reduce the area of the overlap area of the gate electrode 01 and the first electrode area 041 in the vertical direction. Avoid the formation of parasitic capacitance.
  • the first extraction electrode 0411 only contacts a part of the upper surface of the first electrode area 041 in the first contact hole, and the first contact hole still exposes part of the upper surface of the first electrode area 041, so as to further reduce the gate 01 and its Parasitic capacitance formed by the upper metal layer.
  • FIG. 11 is a flowchart of a method for manufacturing a thin film transistor according to the fourth embodiment of the present invention. The method includes the following steps:
  • a semiconductor material layer is formed of a semiconductor material, part of the lower surface of which is in contact with the second electrode 042;
  • S3 forming an isolation layer 05 covering the second electrode 042 and the semiconductor material layer, and patterning the isolation layer 05 to form a first contact hole exposing at least part of the upper surface of the semiconductor material layer;
  • S4 Use the isolation layer 05 as a shielding layer to conduct the conductorization of the semiconductor material layer exposed in the first contact hole to form the first electrode region 041, and the unconducted regions of the semiconductor material layer form the first electrode region 041 respectively.
  • the first electrode area 041 and the second electrode 042 define the channel area of the thin film transistor, and the isolation layer 05 covers the upper surface of the channel area, and plays a role in protecting the upper surface of the channel area during the patterning process of the first extraction electrode 0411 , To avoid the deterioration of the characteristics of the thin film transistor caused by the damage on the upper surface of the channel region.
  • the method for conducting the semiconductor material layer is plasma treatment or ion implantation, but it is not limited thereto.
  • semiconductor materials include but are not limited to amorphous silicon, oxide semiconductor, polysilicon, organic semiconductors, etc.
  • the materials of the gate 01 and the second electrode 042 include but are not limited to single-layer metal, laminated Layer metal, such as Mo single layer, laminated Ti/Cu, Mo/Al/Mo, etc.
  • the material of the first lead electrode 0411 includes, but is not limited to, a single layer of metal, metal oxide and a combination of laminated layers, such as Mo single layer, ITO , Mo/Cu, ITO/Cu, etc.
  • the materials of the gate insulating layer 02, the isolation layer 05, and the passivation layer 06 include but are not limited to SiO2, SiOx, Al2O3, SiNx, etc., or stack of multilayer insulating materials that are preferred according to the device characteristics .

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Abstract

本发明提出了一种薄膜晶体管及其制造方法，属于薄膜晶体管领域；该薄膜晶体管包括：半导体材料层、第二电极、隔离层以及第一引出电极；半导体材料层由半导体材料形成，包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区，第二电极与第一半导区的上表面接触，且与第一电极区不直接接触；隔离层覆盖第二电极和第二半导区，具有暴露出至少部分第一电极区上表面的第一接触孔；第一引出电极通过第一接触孔与第一电极区接触；本发明的薄膜晶体管通过半导体材料导体化所形成的第一电极区和不同层的第二电极构成薄膜晶体管的源极和漏极，实现超短沟道，并避免产生TFT器件特性恶化和较大的寄生电容。

Description

一种薄膜晶体管及其制造方法
本申请要求于2019年03月12日提交中国专利局、申请号为201910182679.3、发明名称为“一种薄膜晶体管及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于薄膜晶体管领域，具体涉及薄膜晶体管及其制造方法。
背景技术
为实现超高PPI像素设计，现有技术基于背沟道刻蚀型薄膜晶体管(Thin Film Transistor，TFT)结构提出了一种超短沟道的TFT设计，其结构示意图如图1所示，俯视图如图2所示。该TFT结构包括依次形成的栅极11、栅极绝缘层12、半导体层13、第一电极141、隔离层15和第二电极142，第二电极142通过隔离层15的接触孔与半导体层13相接触，通过隔离层15隔离不同层的源极和漏极，可以避免同层金属曝光间距限制的问题，沟道长度L1可小于或等于1um，源漏极加沟道总长度可小于或等于6um。
然而，如图3所示，该TFT结构中第二电极142部分覆盖于沟道上方，形成顶栅效应，导致TFT器件特性恶化。此外，如图3所示，第二电极142和栅极11的交叠区域面积大，易产生较大的寄生电容。
发明内容
本发明提供了一种薄膜晶体管及其制造方法，通过半导体材料导体化所形成的第一电极区和不同层的第二电极构成薄膜晶体管的源极和漏极，实现超短沟道，并避免产生TFT器件特性恶化和较大的寄生电容。
所述技术方案如下：
本发明的第一方面提出了一种薄膜晶体管，包括：
栅极；
栅极绝缘层，覆盖所述栅极；
半导体材料层，位于所述栅极绝缘层上方；半导体材料层包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；
第二电极，与第一半导区的上表面接触，且与第一电极区不直接接触；
隔离层，覆盖第二电极和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
第一引出电极，位于所述隔离层的上方，通过第一接触孔与第一电极区接触；
第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
本发明的第二方面提出了另一种薄膜晶体管，包括：
栅极；
栅极绝缘层，覆盖所述栅极；
第二电极，位于所述栅极绝缘层上方；
半导体材料层，包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第二半导区的下表面与栅极绝缘层接触，第一电极区与第二电极不直接接触；
隔离层，覆盖第一半导区和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
第一引出电极，位于所述隔离层的上方，通过所述第一接触孔与第一电极区接触；
第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
本发明的第三方面提出了又一种薄膜晶体管，包括：
半导体材料层，包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；
第二电极，与第一半导区的部分上表面接触，且与第一电极区不直接接触；
隔离层，覆盖第二电极和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
第一引出电极，位于所述隔离层的上方，通过所述第一接触孔与第一电极区接触；
栅极绝缘层，位于隔离层和第一引出电极上方；
栅极，位于所述栅极绝缘层上方；
钝化层，覆盖所述栅极和栅极绝缘层；
第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
本发明的第四方面提出了再一种薄膜晶体管，包括：
第二电极；
半导体材料层，包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第一电极区与第二电极不直接接触；
隔离层，覆盖第一半导区和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
第一引出电极，位于所述隔离层的上方，通过所述第一接触孔与第一电极区接触；
栅极绝缘层，位于隔离层和第一引出电极上方；
栅极，位于所述栅极绝缘层上方；
钝化层，覆盖所述栅极和栅极绝缘层。
进一步地，本发明所提出的上述任一种薄膜晶体管，其第一引出电极仅与第一接触孔内第一电极区的部分上表面接触，第一接触孔仍暴露出第一电极区的部分上表面；
第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
根据本发明的第一方面，本发明提出了一种薄膜晶体管的制造方法，包括步骤：
S1：形成栅极；
S2：形成覆盖栅极的栅极绝缘层；
S3：由半导体材料形成位于栅极绝缘层上方的半导体材料层；
S4：形成第二电极，第二电极与半导体材料层的部分区域的上表面接触；
S5：形成覆盖第二电极和第二半导区的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层上表面的第一接触孔；
S6：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的上表面与第二电极接触，第一电极区和第二电极不直接接触；第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
S7：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第一接触孔与第一电极区接触；
S8：形成位于隔离层和第一引出电极上方的钝化层。
根据本发明的第二方面，本发明提出了一种薄膜晶体管的制造方法，包括步骤：
S1：形成栅极；
S2：形成覆盖栅极的栅极绝缘层；
S3：形成位于栅极绝缘层上方的第二电极；
S4：由半导体材料形成半导体材料层，其部分下表面与栅极绝缘层接触，部分下表面与第二电极接触；
S5：形成覆盖第二电极和半导体材料层的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层上表面的第一接触孔；
S6：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第二半导区的下表面与栅极绝缘层接触，第一电极区与第二电极不直接接触；第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
S7：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第一接触孔与第一电极区接触；
S8：形成位于隔离层和第一引出电极上方的钝化层。
根据本发明的第三方面，本发明提出了一种薄膜晶体管的制造方法，包括步骤：
S1：由半导体材料形成半导体材料层；
S2：形成第二电极，第二电极与半导体材料层的部分区域的上表面接触；
S3：形成覆盖第二电极和半导体材料层的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层的上表面的第一接触孔；
S4：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的上表面与第二电极接触，第一电极区和第二电极不直接接触；第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
S5：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第一接触孔与第一电极区接触；
S6：形成位于隔离层和第一引出电极上方的栅极绝缘层；
S7：形成位于栅极绝缘层上方的栅极；
S8：形成覆盖栅极和栅极绝缘层的钝化层。
根据本发明的第四方面，本发明提出了一种薄膜晶体管的制造方法，包括步骤：
S1：形成第二电极；
S2：由半导体材料形成半导体材料层，其部分下表面与第二电极接触；
S3：形成覆盖第二电极和半导体材料层的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层的上表面的第一接触孔；
S4：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第一电极区和第二电极不直接接触；第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
S5：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第 一接触孔与第一电极区接触；
S6：形成位于隔离层和第一引出电极上方的栅极绝缘层；
S7：形成位于栅极绝缘层上方的栅极；
S8：形成覆盖栅极和栅极绝缘层的钝化层。
进一步地，本发明所提出的上述任一种薄膜晶体管的制造方法中，对半导体材料层进行导体化的方法为等离子体处理或离子注入。
与现有技术相比，本发明能够带来以下至少一项有益效果：
1、由于不存在同层金属曝光间距限制的问题，同时导体化过程中会有一定渗透，使沟道长度可以在原工艺限制基础上，进一步缩短；沟道长度可以达到1um及以下，实现超短沟道；
2、第二电极与半导体有源区在垂直方向上没有交叠，可以避免顶栅效应，进而避免导致TFT器件特性恶化；
3、第一引出电极通过隔离层的第一接触孔与第一电极区的至少部分区域相接触，可以有效减小栅极和第一电极区在垂直方向上的交叠区域面积，避免形成寄生电容；
4、隔离层覆盖薄膜晶体管的沟道区域，在后续制造步骤中起到保护沟道区域上表面的作用，避免沟道区域上表面损伤引起的薄膜晶体管特性劣化。
附图说明
下面将以明确易懂的方式，结合附图说明优选实施方式，对本发明予以进一步说明。
图1为一种现有的刻蚀保护型薄膜晶体管的结构示意图；
图2为图1所示薄膜晶体管的俯视图；
图3为图1所示薄膜晶体管中第二电极和栅极交叠区域的示意图；
图4为根据本发明实施例一的薄膜晶体管的结构示意图；
图5为根据本发明实施例一的薄膜晶体管的制造方法的流程图；
图6为根据本发明实施例二的薄膜晶体管的结构示意图；
图7为根据本发明实施例二的薄膜晶体管的制造方法的流程图；
图8为根据本发明实施例三的薄膜晶体管的结构示意图；
图9为根据本发明实施例三的薄膜晶体管的制造方法的流程图；
图10为根据本发明实施例四的薄膜晶体管的结构示意图；
图11为根据本发明实施例四的薄膜晶体管的制造方法的流程图。
具体实施方式
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
本发明所提出的薄膜晶体管包括由半导体材料形成的半导体材料层，对半导体材料层的部分区域进行导体化以形成第一电极，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区。薄膜晶体管的第二电极与第一半导区或第二半导区相接触，且不与第一电极区直接接触。
第一电极区和第二电极相靠近的边缘之间的部分半导体材料层作为半导体有源区，第一电极区和第二电极的其中一者作为源极，其中另一者作为漏极。半导体有源区的长度为沟道长度，由于不存在同层金属曝光间距限制的问题，同时导体化过程中会有一定渗透，使沟道长度可以在原工艺限制基础上，进一步缩短；沟道长度可以达到1um及以下，实现超短沟道。
在对半导体材料层的部分区域进行导体化的步骤中，利用覆盖第二电极和半导体材料层的一隔离层作为遮挡层，隔离层包括具有暴露出至少部分半导体材料层上表面的第一接触孔，仅对第一接触孔中暴露的半导体材 料层进行导体化。导体化的方法为等离子体处理或离子注入，在不存在遮挡层的情况下进行精确选择局部区域的导体化需要精密的设备。本发明中具有第一接触孔的遮挡层以低成本实现了精确选择局部区域的导体化；并且隔离层覆盖薄膜晶体管的沟道区域，在后续制造步骤(尤其是金属层的图案化步骤)中起到保护沟道区域上表面的作用，避免沟道区域上表面损伤引起的薄膜晶体管特性劣化。
本发明所提出的薄膜晶体管中，第二电极与半导体有源区在垂直方向上没有交叠，可以避免顶栅效应，进而避免导致TFT器件特性恶化。第一引出电极通过隔离层的第一接触孔与第一电极区相接触，可以有效减小栅极和第一电极区在垂直方向上的交叠区域面积，避免形成寄生电容。
下面以具体实施例详细介绍本发明的薄膜晶体管及其制造方法。
实施例一：
图4为根据本发明实施例一的薄膜晶体管的结构示意图，该薄膜晶体管为底栅型且半导体材料层的部分区域与第二电极042接触时位于第二电极042的下方。
如图4所示，该薄膜晶体管包括：位于基板(图未示)的栅极01、覆盖栅极01的栅极绝缘层02、位于栅极绝缘层02上方的半导体材料层、与半导体材料层的部分区域的上表面相接触的第二电极042、隔离层05以及第一引出电极0411。
其中，半导体材料层由半导体材料形成，包括对半导体材料进行导体化形成的第一电极区041和分别位于第一电极区041两侧的第一半导区031和第二半导区032。第二电极042与第一半导区031的上表面接触，且与第一电极区041不直接接触。第一电极区041和第二电极042相靠近的边缘之间的部分半导体材料层为半导体有源区0311，半导体有源区0311与栅极01在垂直方向的投影至少部分交叠。隔离层05覆盖第二电极042和第二半导区032，隔离层05具有暴露出至少部分第一电极区041上表面的第一接触孔。第一引出电极0411位于所述隔离层05的上方，通过第一接触孔与第一电极区041接触。
优选地，后续形成位于所述隔离层05和第一引出电极0411上方的钝化层06以避免环境水氧等对器件产生影响。
如图4所示，半导体有源区0311的长度L1为沟道长度，由于不存在同层金属曝光间距限制的问题，同时导体化过程中会有一定渗透，使沟道长度可以在原工艺限制基础上，进一步缩短；沟道长度L1可以达到1um及以下，实现超短沟道。第二电极042与半导体有源区0311在垂直方向上没有交叠，可以避免顶栅效应，进而避免导致TFT器件特性恶化。第一引出电极0411通过隔离层05的第一接触孔与第一电极区041相接触，可以有效减小栅极01和第一电极区041在垂直方向上的交叠区域面积，避免形成寄生电容。
优选地，第一引出电极0411仅与第一接触孔内第一电极区041的部分上表面接触，第一接触孔仍暴露出第一电极区041的部分上表面，以进一步减少栅极01与其上方金属层形成的寄生电容。
图5为根据本发明实施例一的薄膜晶体管的制造方法的流程图，该方法包括以下步骤：
S1：形成栅极01；
S2：形成覆盖栅极01的栅极绝缘层02；
S3：由半导体材料形成位于栅极绝缘层02上方的半导体材料层；
S4：形成第二电极042，第二电极042与半导体材料层的部分区域的上表面接触；
S5：形成覆盖第二电极042和第二半导区032的隔离层05，对隔离层05进行图案化形成暴露出至少部分半导体材料层上表面的第一接触孔；
S6：利用隔离层05作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区041，半导体材料层未导体化的区域形成分别位于第一电极区041两侧的第一半导区031和第二半导区032；部分第一半导区031的上表面与第二电极042接触，第一电极区041和第二电极042不直接接触；
S7：形成位于隔离层05上方的第一引出电极0411，第一引出电极0411通过所述第一接触孔与第一电极区041接触；
S8：形成位于隔离层05和第一引出电极0411上方的钝化层06。
第一电极区041和第二电极042限定薄膜晶体管的沟道区域，隔离层05覆盖沟道区域的上表面，在第一引出电极0411的图案化过程中起到保 护沟道区域上表面的作用，避免沟道区域上表面损伤引起的薄膜晶体管特性劣化。
其中，对半导体材料层进行导体化的方法为等离子体处理或离子注入，但不限于此。
实施例二：
图6为根据本发明实施例二的薄膜晶体管的结构示意图，该薄膜晶体管为底栅型且半导体材料层的部分区域与第二电极042接触时位于第二电极042的上方。
如图6所示，该薄膜晶体管包括：位于基板(图未示)的栅极01、覆盖栅极01的栅极绝缘层02、位于栅极绝缘层02上方的第二电极042、部分下表面与半导体材料层接触的半导体材料层、隔离层05以及第一引出电极0411。
其中，半导体材料层由半导体材料形成，其部分下表面与栅极绝缘层02接触，部分下表面与第二电极042接触。半导体材料层包括对半导体材料进行导体化形成的第一电极区041和分别位于第一电极区041两侧的第一半导区031和第二半导区032。部分第一半导区031的下表面与第二电极042接触，第二半导区032的下表面与栅极绝缘层02接触，第一电极区041与第二电极042不直接接触。第一电极区041和第二电极042相靠近的边缘之间的部分半导体材料层为半导体有源区0311，半导体有源区0311与栅极01在垂直方向的投影至少部分交叠。隔离层05覆盖第一半导区031和第二半导区032，隔离层05具有暴露出至少部分第一电极区041上表面的第一接触孔。第一引出电极0411位于所述隔离层05的上方，通过第一接触孔与第一电极区041接触。
优选地，后续形成位于所述隔离层05和第一引出电极0411上方的钝化层06以避免环境水氧等对器件产生影响。
如图6所示，半导体有源区0311的长度为沟道长度，由于不存在同层金属曝光间距限制的问题，同时导体化过程中会有一定渗透，使沟道长度可以在原工艺限制基础上，进一步缩短；沟道长度可以达到1um及以下，实现超短沟道。第二电极042与半导体有源区0311在垂直方向上没有交叠，可以避免顶栅效应，进而避免导致TFT器件特性恶化。第一引出电极0411 通过隔离层05的第一接触孔与第一电极区041的至少部分区域相接触，可以有效减小栅极01和第一电极区041在垂直方向上的交叠区域面积，避免形成寄生电容。
优选地，第一引出电极0411仅与第一接触孔内第一电极区041的部分上表面接触，第一接触孔仍暴露出第一电极区041的部分上表面，以进一步减少栅极01与其上方金属层形成的寄生电容。
图7为根据本发明实施例二的薄膜晶体管的制造方法的流程图，该方法包括以下步骤：
S1：形成栅极01；
S2：形成覆盖栅极01的栅极绝缘层02；
S3：形成位于栅极绝缘层02上方的第二电极042；
S4：由半导体材料形成半导体材料层，其部分下表面与栅极绝缘层02接触，部分下表面与第二电极042接触；
S5：形成覆盖第二电极042和半导体材料层的隔离层05，对隔离层05进行图案化形成暴露出至少部分半导体材料层上表面的第一接触孔；
S6：利用隔离层05作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区041，半导体材料层未导体化的区域形成分别位于第一电极区041两侧的第一半导区031和第二半导区032；部分第一半导区031的下表面与第二电极042接触，第一电极区041和第二电极042不直接接触；
S7：形成位于隔离层05上方的第一引出电极0411，第一引出电极0411通过所述第一接触孔与第一电极区041接触；
S8：形成位于隔离层05和第一引出电极0411上方的钝化层06。
第一电极区041和第二电极042限定薄膜晶体管的沟道区域，隔离层05覆盖沟道区域的上表面，在第一引出电极0411的图案化过程中起到保护沟道区域上表面的作用，避免沟道区域上表面损伤引起的薄膜晶体管特性劣化。
其中，对半导体材料层进行导体化的方法为等离子体处理或离子注入，但不限于此。
实施例三：
图8为根据本发明实施例三的薄膜晶体管的结构示意图，该薄膜晶体管为顶栅型且半导体材料层的部分区域与第二电极042接触时位于第二电极042的下方。
如图8所示，该薄膜晶体管包括：位于基板(图未示)的半导体材料层、与第一半导区031的部分上表面接触的第二电极042、隔离层05、第一引出电极0411、位于隔离层05和第一引出电极0411上方的栅极绝缘层02、位于栅极绝缘层02上方的栅极01、覆盖栅极01和栅极绝缘层02的钝化层06。
其中，半导体材料层由半导体材料形成，包括对半导体材料进行导体化形成的第一电极区041和分别位于第一电极区041两侧的第一半导区031和第二半导区032。第二电极042与第一半导区031的部分上表面接触，且与第一电极区041不直接接触。第一电极区041和第二电极042相靠近的边缘之间的部分半导体材料层为半导体有源区0311，半导体有源区0311与栅极01在垂直方向的投影至少部分交叠。隔离层05覆盖第二电极042和第二半导区032，隔离层05具有暴露出至少部分第一电极区041上表面的第一接触孔。第一引出电极0411位于所述隔离层05的上方，通过第一接触孔与第一电极区041接触。
如图8所示，半导体有源区0311的长度为沟道长度，由于不存在同层金属曝光间距限制的问题，同时导体化过程中会有一定渗透，使沟道长度可以在原工艺限制基础上，进一步缩短；沟道长度可以达到1um及以下，实现超短沟道。第二电极042与半导体有源区0311在垂直方向上没有交叠，可以避免顶栅效应，进而避免导致TFT器件特性恶化。第一引出电极0411通过隔离层05的第一接触孔与第一电极区041的至少部分区域相接触，可以有效减小栅极01和第一电极区041在垂直方向上的交叠区域面积，避免形成寄生电容。
优选地，第一引出电极0411仅与第一接触孔内第一电极区041的部分上表面接触，第一接触孔仍暴露出第一电极区041的部分上表面，以进一步减少栅极01与其上方金属层形成的寄生电容。
图9为根据本发明实施例三的薄膜晶体管的制造方法的流程图，该方法包括以下步骤：
S1：由半导体材料形成半导体材料层；
S2：形成第二电极042，第二电极042与半导体材料层的部分区域的上表面接触；
S3：形成覆盖第二电极042和半导体材料层的隔离层05，对隔离层05进行图案化形成暴露出至少部分半导体材料层的上表面的第一接触孔；
S4：利用隔离层05作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区041，半导体材料层未导体化的区域形成分别位于第一电极区041两侧的第一半导区031和第二半导区032；部分第一半导区031的上表面与第二电极042接触，第一电极区041和第二电极042不直接接触；
S5：形成位于隔离层05上方的第一引出电极0411，第一引出电极0411通过所述第一接触孔与第一电极区041接触；
S6：形成位于隔离层05和第一引出电极0411上方的栅极绝缘层02；
S7：形成位于栅极绝缘层02上方的栅极01；
S8：形成覆盖栅极01和栅极绝缘层02的钝化层06。
第一电极区041和第二电极042限定薄膜晶体管的沟道区域，隔离层05覆盖沟道区域的上表面，在第一引出电极0411的图案化过程中起到保护沟道区域上表面的作用，避免沟道区域上表面损伤引起的薄膜晶体管特性劣化。
其中，对半导体材料层进行导体化的方法为等离子体处理或离子注入，但不限于此。
实施例四：
图10为根据本发明实施例四的薄膜晶体管的结构示意图，该薄膜晶体管为顶栅型且半导体材料层的部分区域与第二电极042接触时位于第二电极042的上方。
如图10所示，该薄膜晶体管包括：位于基板(图未示)的电极、部分下表面与第二电极042接触的半导体材料层、隔离层05、第一引出电极0411、位于隔离层05和第一引出电极0411上方的栅极绝缘层02、位于栅极绝缘层02上方的栅极01、覆盖栅极01和栅极绝缘层02的钝化层06。
其中，半导体材料层由半导体材料形成，包括对半导体材料进行导体 化形成的第一电极区041和分别位于第一电极区041两侧的第一半导区031和第二半导区032。部分第一半导区031的下表面与第二电极042接触，第一电极区041与第二电极042不直接接触。第一电极区041和第二电极042相靠近的边缘之间的部分半导体材料层为半导体有源区0311，半导体有源区0311与栅极01在垂直方向的投影至少部分交叠。隔离层05覆盖第一半导区031和第二半导区032，隔离层05具有暴露出至少部分第一电极区041上表面的第一接触孔。第一引出电极0411位于所述隔离层05的上方，通过第一接触孔与第一电极区041接触。
如图10所示，半导体有源区0311的长度为沟道长度，由于不存在同层金属曝光间距限制的问题，同时导体化过程中会有一定渗透，使沟道长度可以在原工艺限制基础上，进一步缩短；沟道长度可以达到1um及以下，实现超短沟道。第二电极042与半导体有源区0311在垂直方向上没有交叠，可以避免顶栅效应，进而避免导致TFT器件特性恶化。第一引出电极0411通过隔离层05的第一接触孔与第一电极区041的至少部分区域相接触，可以有效减小栅极01和第一电极区041在垂直方向上的交叠区域面积，避免形成寄生电容。
优选地，第一引出电极0411仅与第一接触孔内第一电极区041的部分上表面接触，第一接触孔仍暴露出第一电极区041的部分上表面，以进一步减少栅极01与其上方金属层形成的寄生电容。
图11为根据本发明实施例四的薄膜晶体管的制造方法的流程图，该方法包括以下步骤：
S1：形成第二电极042；
S2：由半导体材料形成半导体材料层，其部分下表面与第二电极042接触；
S3：形成覆盖第二电极042和半导体材料层的隔离层05，对隔离层05进行图案化形成暴露出至少部分半导体材料层的上表面的第一接触孔；
S4：利用隔离层05作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区041，半导体材料层未导体化的区域形成分别位于第一电极区041两侧的第一半导区031和第二半导区032；部分第一半导区031的下表面与第二电极042接触，第一电极区041和第二电极042 不直接接触；
S5：形成位于隔离层05上方的第一引出电极0411，第一引出电极0411通过所述第一接触孔与第一电极区041接触；
S6：形成位于隔离层05和第一引出电极0411上方的栅极绝缘层02；
S7：形成位于栅极绝缘层02上方的栅极01；
S8：形成覆盖栅极01和栅极绝缘层02的钝化层06。
第一电极区041和第二电极042限定薄膜晶体管的沟道区域，隔离层05覆盖沟道区域的上表面，在第一引出电极0411的图案化过程中起到保护沟道区域上表面的作用，避免沟道区域上表面损伤引起的薄膜晶体管特性劣化。
其中，对半导体材料层进行导体化的方法为等离子体处理或离子注入，但不限于此。
需要说明的是，本发明的薄膜晶体管中，半导体材料包括但不限于非晶硅、氧化物半导体、多晶硅、有机半导体等；栅极01、第二电极042的材料包括不限于单层金属、叠层金属，例如Mo单层，叠层Ti/Cu，Mo/Al/Mo等；第一引出电极0411的材料包括不限于单层金属、金属氧化物及其叠层组合，例如Mo单层，ITO，Mo/Cu，ITO/Cu等；栅极绝缘层02、隔离层05、钝化层06的材料包括不限于SiO2、SiOx、Al2O3、SiNx等，或者根据器件特性要求优选的多层绝缘材料叠加。
应当说明的是，以上所述仅是本发明的优选实施方式，但是本发明并不限于上述实施方式中的具体细节，应当指出，对于本技术领域的普通技术人员来说，在本发明的技术构思范围内，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，对本发明的技术方案进行多种等同变换，这些改进、润饰和等同变换也应视为本发明的保护范围。

Claims (10)

  1. 一种薄膜晶体管，其特征在于，包括：
    栅极；
    栅极绝缘层，覆盖所述栅极；
    半导体材料层，位于所述栅极绝缘层上方；半导体材料层包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；
    第二电极，与第一半导区的上表面接触，且与第一电极区不直接接触；
    隔离层，覆盖第二电极和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
    第一引出电极，位于所述隔离层的上方，通过第一接触孔与第一电极区接触；
    第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
  2. 一种薄膜晶体管，其特征在于，包括：
    栅极；
    栅极绝缘层，覆盖所述栅极；
    第二电极，位于所述栅极绝缘层上方；
    半导体材料层，包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第二半导区的下表面与栅极绝缘层接触，第一电极区与第二电极不直接接触；
    隔离层，覆盖第一半导区和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
    第一引出电极，位于所述隔离层的上方，通过所述第一接触孔与第一电极区接触；
    第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
  3. 一种薄膜晶体管，其特征在于，包括：
    半导体材料层，包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；
    第二电极，与第一半导区的部分上表面接触，且与第一电极区不直接接触；
    隔离层，覆盖第二电极和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
    第一引出电极，位于所述隔离层的上方，通过所述第一接触孔与第一电极区接触；
    栅极绝缘层，位于隔离层和第一引出电极上方；
    栅极，位于所述栅极绝缘层上方；
    钝化层，覆盖所述栅极和栅极绝缘层；
    第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
  4. 一种薄膜晶体管，其特征在于，包括：
    第二电极；
    半导体材料层，包括对半导体材料进行导体化形成的第一电极区和分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第一电极区与第二电极不直接接触；
    隔离层，覆盖第一半导区和第二半导区；隔离层具有暴露出至少部分第一电极区上表面的第一接触孔；隔离层用作导体化步骤的遮挡层；
    第一引出电极，位于所述隔离层的上方，通过所述第一接触孔与第一电极区接触；
    栅极绝缘层，位于隔离层和第一引出电极上方；
    栅极，位于所述栅极绝缘层上方；
    钝化层，覆盖所述栅极和栅极绝缘层；
    第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面。
  5. 根据权利要求1至4任一项所述的薄膜晶体管，其特征在于，第一引出电极仅与第一接触孔内第一电极区的部分上表面接触，第一接触孔仍暴露出第一电极区的部分上表面。
  6. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成栅极；
    S2：形成覆盖栅极的栅极绝缘层；
    S3：由半导体材料形成位于栅极绝缘层上方的半导体材料层；
    S4：形成第二电极，第二电极与半导体材料层的部分区域的上表面接触；
    S5：形成覆盖第二电极和第二半导区的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层上表面的第一接触孔；
    S6：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的上表面与第二电极接触，第一电极区和第二电极不直接接触，第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
    S7：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第一接触孔与第一电极区接触；
    S8：形成位于隔离层和第一引出电极上方的钝化层。
  7. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成栅极；
    S2：形成覆盖栅极的栅极绝缘层；
    S3：形成位于栅极绝缘层上方的第二电极；
    S4：由半导体材料形成半导体材料层，其部分下表面与栅极绝缘层接触，部分下表面与第二电极接触；
    S5：形成覆盖第二电极和半导体材料层的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层上表面的第一接触孔；
    S6：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第二半导区的下表面与栅极绝缘层接触，第一电极区与第二电极不直接接触，第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
    S7：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第一接触孔与第一电极区接触；
    S8：形成位于隔离层和第一引出电极上方的钝化层。
  8. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：由半导体材料形成半导体材料层；
    S2：形成第二电极，第二电极与半导体材料层的部分区域的上表面接触；
    S3：形成覆盖第二电极和半导体材料层的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层的上表面的第一接触孔；
    S4：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的上表面与第二电极接触，第一电极区和第二电极不直接接触，第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
    S5：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第一接触孔与第一电极区接触；
    S6：形成位于隔离层和第一引出电极上方的栅极绝缘层；
    S7：形成位于栅极绝缘层上方的栅极；
    S8：形成覆盖栅极和栅极绝缘层的钝化层。
  9. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成第二电极；
    S2：由半导体材料形成半导体材料层，其部分下表面与第二电极接触；
    S3：形成覆盖第二电极和半导体材料层的隔离层，对隔离层进行图案化形成暴露出至少部分半导体材料层的上表面的第一接触孔；
    S4：利用隔离层作为遮挡层对第一接触孔内暴露的半导体材料层进行导体化形成第一电极区，半导体材料层未导体化的区域形成分别位于第一电极区两侧的第一半导区和第二半导区；部分第一半导区的下表面与第二电极接触，第一电极区和第二电极不直接接触，第一电极区和第二电极限定薄膜晶体管的沟道区域，隔离层覆盖沟道区域的上表面；
    S5：形成位于隔离层上方的第一引出电极，第一引出电极通过所述第 一接触孔与第一电极区接触；
    S6：形成位于隔离层和第一引出电极上方的栅极绝缘层；
    S7：形成位于栅极绝缘层上方的栅极；
    S8：形成覆盖栅极和栅极绝缘层的钝化层。
  10. 根据权利要求6～9任一项所述的制造薄膜晶体管的方法，其特征在于，对半导体材料层进行导体化的方法为等离子体处理或离子注入。
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