WO2020062666A1 - 一种薄膜晶体管及其制造方法 - Google Patents

一种薄膜晶体管及其制造方法 Download PDF

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WO2020062666A1
WO2020062666A1 PCT/CN2018/123482 CN2018123482W WO2020062666A1 WO 2020062666 A1 WO2020062666 A1 WO 2020062666A1 CN 2018123482 W CN2018123482 W CN 2018123482W WO 2020062666 A1 WO2020062666 A1 WO 2020062666A1
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electrode
semiconductor layer
layer
forming
gate
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PCT/CN2018/123482
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English (en)
French (fr)
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戴超
赵文达
任洋洋
王志军
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南京中电熊猫平板显示科技有限公司
南京中电熊猫液晶显示科技有限公司
南京华东电子信息科技股份有限公司
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Publication of WO2020062666A1 publication Critical patent/WO2020062666A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • the invention belongs to the field of thin film transistors, and particularly relates to a thin film transistor and a manufacturing method thereof.
  • Traditional bottom-gate staggered TFTs generally include an etch-protected device structure and a back-channel etched device structure.
  • the etch-protected device structure is sequentially formed into a gate 01, a gate insulation layer, a semiconductor layer 02, an etch protection layer 03, and a source and a drain 04 at the same time.
  • the resulting thin film transistor is shown in Figure 1. As shown.
  • the channel length of this device is a + 2b
  • a is the distance between the source and drain metals in the same layer, which is limited by the accuracy of the exposure machine, and b must ensure that the source and drain can be protected after etching
  • a back channel etched device structure was later developed.
  • the back-channel etched device structure is sequentially formed into a gate 01, a gate insulating layer, a semiconductor layer 02, and a source and a drain 03 at the same time.
  • the resulting thin film transistor is shown in FIG. 2.
  • the channel length of the device is a, a is the distance between the source and drain metals in the same layer, which is limited by the accuracy of the exposure machine.
  • the device width has been reduced, but it still takes up a lot of space, which is not suitable for ultra-high-resolution panel design.
  • TFTs occupy a large area and are not suitable for the development of ultra-high-resolution displays; the channel length L of the TFT is limited and cannot be reduced further, which is not conducive to the improvement of current.
  • the invention provides a new thin-film transistor structure and manufacturing method, which mainly consists of manufacturing a source metal and a drain metal of a TFT separately, and effectively avoids the problem that the distance between the same layer of metal is limited by the process and the channel length is limited. , To achieve ultra-high-resolution pixel design and stronger thin-film transistor driving capabilities.
  • the invention provides a thin film transistor, including:
  • a gate a gate insulating layer covering the gate; a semiconductor layer located above the gate insulating layer; a first electrode and a second electrode located on different layers, the first electrode and the second electrode Both are in contact with the semiconductor layer; an isolation layer is located between the first electrode and the second electrode and covers a part of the semiconductor layer, and the isolation layer is provided with a first contact hole in the semiconductor layer, The second electrode is in contact with the semiconductor layer through the first contact hole.
  • the invention also provides a thin film transistor, including:
  • a gate a gate insulating layer covering the gate; a first electrode and a second electrode located in different layers; the first electrode and the second electrode are both located above the gate insulating layer; a semiconductor layer Is located between the first electrode and the second electrode and is in contact with the first electrode and the second electrode, and the semiconductor layer portion is located on the gate insulating layer.
  • an isolation layer is further included between the first electrode and the second electrode, and the isolation layer is above the semiconductor layer and at a position where the semiconductor layer and the gate insulating layer are in contact.
  • a first contact hole is provided everywhere, and the second electrode or the first electrode is in contact with a part of the semiconductor layer through the first contact hole.
  • the invention also provides a thin film transistor, including:
  • a first electrode and a second electrode located in different layers; a semiconductor layer located between the first electrode and the second electrode and in contact with the first electrode and the second electrode; a gate insulating layer, The first electrode, the second electrode, and the semiconductor layer are covered; a gate is located above the gate insulating layer.
  • an isolation layer is further included between the first electrode and the second electrode, and the isolation layer is provided above the semiconductor layer and a first is provided at a position where the semiconductor layer and the substrate are in contact with each other.
  • a contact hole, the second electrode or the first electrode is in contact with a part of the semiconductor layer through the first contact hole.
  • the invention also provides a thin film transistor, including:
  • a first electrode and a second electrode located on different layers; an isolation layer between the first electrode and the second electrode, the isolation layer being provided with a first contact hole; a semiconductor layer, located on the isolation layer Above, a part of the semiconductor layer is in contact with the second electrode, and another part of the semiconductor layer is in the first contact hole and is in contact with the first electrode; a gate insulating layer covering the isolation layer and The semiconductor layer and a gate are located above the gate insulating layer.
  • the semiconductor layer when a part of the semiconductor layer is in contact with the second electrode, it is located above or below the second electrode.
  • the invention also provides a method for manufacturing a thin film transistor, comprising the steps:
  • S5 forming an isolation layer covering the gate insulating layer, the first electrode, and the semiconductor layer, and the isolation layer is provided with a first contact hole at a position of another part of the semiconductor layer;
  • the invention also provides a method for manufacturing a thin film transistor, comprising the steps:
  • the isolation layer is provided with a first contact hole at a position of another part of the semiconductor layer; the second electrode passes through the first contact hole In contact with another part of the semiconductor layer.
  • the invention also provides a method for manufacturing a thin film transistor, comprising the steps:
  • the isolation layer is provided with a first contact hole at a position of another part of the semiconductor layer; the second electrode communicates with the semiconductor layer through the first contact hole Contact with the other part.
  • the invention also provides a method for manufacturing a thin film transistor, comprising the steps:
  • S3 forming a semiconductor layer partially covering the isolation layer and another portion covering the first electrode, and another portion of the semiconductor layer is in contact with the first electrode in the first contact hole;
  • the invention also provides a method for manufacturing a thin film transistor, comprising the steps:
  • the present invention effectively avoids the problem of spacing between the same layer of metal and the problem of channel limitation; the present invention achieves ultra-high heights by adding an isolation layer for isolating the source and drain electrodes Resolution pixel design and stronger TFT driving capability.
  • FIG. 1 is a schematic structural diagram of a conventional etch-protected thin film transistor device
  • FIG. 2 is a schematic structural diagram of a conventional back-channel etching type thin film transistor device
  • FIG. 3 is a schematic structural diagram of a first embodiment of a bottom-gate thin film transistor according to the present invention.
  • FIG. 4 is a schematic top view of a first embodiment of a bottom-gate thin film transistor according to the present invention.
  • FIG. 5 is a flowchart of a method for manufacturing a bottom-gate thin film transistor according to a first embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a second embodiment of a bottom-gate thin film transistor according to the present invention.
  • FIG. 7 is a flowchart of a manufacturing method of a second embodiment of a bottom-gate thin film transistor according to the present invention.
  • FIG. 8 is a schematic structural diagram of a third embodiment of a bottom-gate thin film transistor according to the present invention.
  • FIG. 9 is a flowchart of a manufacturing method of a third embodiment of a bottom-gate thin film transistor according to the present invention.
  • FIG. 10 is a schematic structural diagram of a fourth embodiment of a top-gate thin film transistor according to the present invention.
  • FIG. 11 is a flowchart of a manufacturing method of a fourth embodiment of a top-gate thin film transistor according to the present invention.
  • FIG. 12 is a schematic structural diagram of a fifth embodiment of a top-gate thin film transistor according to the present invention.
  • FIG. 13 is a flowchart of a manufacturing method of a fifth embodiment of a top-gate thin film transistor according to the present invention.
  • FIG. 14 is a schematic structural diagram of a sixth embodiment of a top-gate thin film transistor according to the present invention.
  • FIG. 15 is a flowchart of a method for manufacturing a top-gate thin film transistor according to a sixth embodiment of the present invention.
  • FIG. 16 is a schematic structural diagram of a seventh embodiment of a top-gate thin film transistor according to the present invention.
  • FIG. 17 is a flowchart of a manufacturing method of a seventh embodiment of a top-gate thin film transistor according to the present invention.
  • the thin film transistor proposed by the present invention is called TFT structure (isolated source and drain TFT (ISD-TFT)).
  • the thin film transistor of the present invention is applicable to any type of semiconductor TFT, such as amorphous Silicon, oxide semiconductors, low temperature polysilicon (LTPS), organic semiconductors, and more.
  • the thin film transistor of the present invention is a bottom gate thin film transistor and a top gate thin film transistor.
  • the bottom-gate thin film transistor includes three embodiments: only the isolation layer is used to isolate the source and the drain, the semiconductor layer is used to isolate the source and the drain, the semiconductor layer and the isolation layer jointly isolate the source and the drain, and the bottom-gate thin film
  • the transistor includes four embodiments: only the isolation layer is used to isolate the source and drain, the semiconductor layer is used to isolate the source and drain, and the semiconductor layer and the isolation layer are used to isolate the source and drain together.
  • the bottom-gate thin-film transistor and the top-gate thin-film transistor according to the present invention are described below.
  • the first type bottom gate thin film transistor:
  • FIG. 3 is a schematic structural diagram of Embodiment 1 of a bottom-gate thin-film transistor according to the present invention.
  • the source and drain are separated only by an isolation layer.
  • the thin-film transistor includes a gate 01 on a substrate (not shown). , A gate insulating layer 02 covering the gate 01, a semiconductor layer 03 above the gate insulating layer 02, a first electrode 04, an isolation layer 05, and a second electrode 06 located at a different layer from the first electrode 04, the first electrode Both 04 and the second electrode 06 are in contact with the semiconductor layer 03.
  • the semiconductor layer 03 includes a first portion 031 along the extending direction of the gate 01 and a second portion 032 connected to the first portion (that is, the semiconductor layer 03 is divided into left and right portions); the first electrode 04 is provided on the gate On the electrode insulating layer 02 and the semiconductor layer 03, wherein the first electrode 04 covers the first portion 031 of the semiconductor layer; and the isolation layer 05 covers the gate insulating layer 02, the first electrode 04, and the semiconductor layer A second portion 032, the isolation layer 05 is located between the first electrode 04 and the second electrode 06 and covers a portion of the semiconductor layer 03, and a first contact hole 07 is provided at the position of the second portion 032 of the semiconductor layer; The second electrode 06 covers the second portion 032 of the semiconductor layer, and the second electrode 06 is in contact with the second portion 032 of the semiconductor layer through the first contact hole 07.
  • the second electrode 06 is a drain; when the first electrode 04 is a drain, the second electrode 06 is a source.
  • FIG. 4 is a schematic top view of a first embodiment of a bottom-gate thin-film transistor according to the present invention, which includes a gate 01, a gate insulating layer 02, a semiconductor layer 03, and a first layer on a substrate (not shown) in order from bottom to top.
  • the channel length is a
  • the metal width of the first electrode 04 is b
  • the width of the first contact hole 07 is c.
  • the channel length a of the thin film transistor is smaller than the two solutions in the background art.
  • the driving current of the linear region of the thin film transistor is approximately:
  • the channel length of the thin film transistor is L.
  • L the driving current of the thin film transistor will increase inversely.
  • FIG. 5 is a flowchart of a method for manufacturing a bottom-gate thin film transistor according to a first embodiment of the present invention. The method includes the following steps:
  • S3 forming a semiconductor layer 03 on the gate insulating layer 02, the semiconductor layer includes a first portion 031 and a second portion 032 connected to the first portion 031;
  • a second electrode 06 is formed.
  • the second electrode 06 is located on the second portion 032 of the semiconductor layer.
  • the second electrode 06 is in contact with the second portion 032 of the semiconductor layer through the first contact hole 07.
  • the first electrode 04 and the second electrode 06 are mainly separated by an isolation layer 05.
  • the ISD-TFT device can be formed according to the thin film transistor manufacturing method shown in FIG. 5.
  • the subsequent process flow can be set according to the display needs.
  • a protective layer is added to prevent the water and oxygen from affecting the device.
  • FIG. 6 is a schematic structural diagram of a second embodiment of a bottom-gate thin film transistor according to the present invention.
  • a source and a drain are separated by a semiconductor layer.
  • the thin film transistor includes a gate 01, The gate insulating layer 02, the first electrode 03, the semiconductor layer 04 covering the gate 01, and the second electrode 06 located at a different layer from the first electrode 03. Both the first electrode 03 and the second electrode 06 are in contact with the semiconductor layer 04. contact.
  • the first electrode 03 is located on the gate insulation layer 02; the semiconductor layer 04 is partially located on the gate insulation layer 02, and the semiconductor layer 04 extends from the gate insulation layer 02 to the first On the electrode 03, the semiconductor layer 04 includes a first portion 041 located on the first electrode 03 and a second portion 042 connected to the first portion; the second electrode 06 covers and contacts the second portion 042 of the semiconductor layer .
  • the channel length can be less than 1um in the process, so the layout space occupied by the thin film transistor is very small, which is beneficial to achieve ultra-high resolution And stronger driving capabilities.
  • FIG. 7 is a flowchart of a method for manufacturing a bottom-gate thin film transistor according to a second embodiment of the present invention, including the following steps:
  • S4 forming a semiconductor layer 04 covering a portion of the first electrode 03 and a portion of the gate insulating layer 02, the semiconductor layer 04 extending from the gate insulating layer 02 to the first electrode 03, the semiconductor layer 04 including A first portion 041 located on the first electrode 03 and a second portion 042 connected to the first portion 041;
  • the first electrode 03 and the second electrode 06 are mainly separated by the semiconductor layer 04.
  • FIG. 8 is a schematic structural diagram of a third embodiment of a bottom-gate thin film transistor according to the present invention.
  • a source and a drain are simultaneously separated by a semiconductor layer and an isolation layer.
  • the thin film transistor includes a gate 01 on a substrate (not shown) and a cover gate
  • the gate insulating layer 02, the first electrode 03, the semiconductor layer 04, the isolation layer 05 located above the semiconductor layer 04, and the second electrode 06, the first electrode 03, and the second electrode located on a different layer from the first electrode 03. 06 are in contact with the semiconductor layer 04.
  • the structure of the third embodiment of the thin film transistor is basically the same as that of the second embodiment of the thin film transistor.
  • the difference is that an isolation layer 05 is further provided between the first electrode 03 and the second electrode 06, and the isolation layer 05 covers the gate insulation.
  • Layer 02, the first electrode 03, and the semiconductor layer 04, and the isolation layer 05 is provided with a first contact hole 07 at a second portion 042 where the semiconductor layer and the gate insulating layer 02 are in contact,
  • the second electrode 06 is in contact with the second portion 042 of the semiconductor layer through the first contact hole 07.
  • the channel length can be less than 1um in the manufacturing process, so the layout space occupied by the thin film transistor is small, which is conducive to achieving ultra-high resolution and stronger Drive capability.
  • FIG. 9 is a flowchart of a method for manufacturing a bottom-gate thin film transistor according to a third embodiment of the present invention, including the following steps:
  • S4 forming a semiconductor layer 04 covering a portion of the first electrode 03 and a portion of the gate insulating layer 02, the semiconductor layer 04 extending from the gate insulating layer 02 to the first electrode 03, the semiconductor layer 04 including A first portion 041 located on the first electrode 03 and a second portion 042 connected to the first portion 041;
  • the first electrode 03 and the second electrode 06 are mainly separated by the semiconductor layer 04 and the isolation layer 05.
  • a protective layer can be formed to isolate the impact of the environment (such as water, oxygen, nitrogen, etc.) on the device.
  • the second type top-gate thin film transistor:
  • FIG. 10 is a schematic structural diagram of a fourth embodiment of a top-gate thin film transistor according to the present invention.
  • a source and a drain are separated by a semiconductor layer.
  • the thin film transistor includes a first electrode 01 and a semiconductor layer 02 on a substrate (not shown), and The first electrode 01 is located on the second electrode 04, the gate insulating layer 05, and the gate 06 in different layers. Both the first electrode 01 and the second electrode 04 are in contact with the semiconductor layer 02.
  • the semiconductor layer 02 extends from the substrate to the first electrode 01, and the semiconductor layer 02 includes a first portion 021 located on the first electrode 04 and a second portion 022 connected to the first portion;
  • the second electrode 04 covers and contacts the second portion 022 of the semiconductor layer;
  • the gate insulating layer 05 covers the substrate, the first electrode 01, the semiconductor layer 02, and the second electrode 04;
  • the gate 06 is located on the gate Electrode insulation layer 05.
  • the channel length can be less than 1um in the process, so the layout space occupied by the thin film transistor is small, which is conducive to achieving ultra-high resolution And stronger driving capabilities.
  • FIG. 11 is a flowchart of a method for manufacturing a top gate thin film transistor according to a fourth embodiment of the present invention, including the following steps:
  • S2 forming a semiconductor layer 02 covering a portion of the first electrode 01, the semiconductor layer 02 extending from the substrate to the first electrode 01, the semiconductor layer 02 including a first portion 021 located on the first electrode 01 and A second part 022 connected to the first part 021;
  • a gate 06 is formed on the gate insulating layer 05.
  • the first electrode 01 and the second electrode 04 are mainly separated by the semiconductor layer 02.
  • FIG. 12 is a schematic structural diagram of a fifth embodiment of a top-gate thin film transistor according to the present invention.
  • a source and a drain are simultaneously separated by a semiconductor layer and an isolation layer.
  • the thin film transistor includes a first electrode 01 and a semiconductor on a substrate (not shown).
  • Layer 02, isolation layer 03 above semiconductor layer 02, second electrode 04, gate insulating layer 05, and gate 06 located at different layers from the first electrode 01, and the first and second electrodes 01 and 04 are all The semiconductor layer 02 is in contact.
  • the structure of the thin film transistor embodiment 5 is basically the same as the structure of the thin film transistor embodiment 4. The difference is that an isolation layer 03 is further provided between the first electrode 01 and the second electrode 04, and the isolation layer 03 covers the substrate. , The first electrode 01 and the semiconductor layer 02, the isolation layer 03 is provided with a first contact hole 07 at the position of the second portion 022 of the semiconductor, and the second electrode 04 passes through the first contact The hole 07 is in contact with the second portion 022 of the semiconductor layer.
  • the channel length can be less than 1um in the manufacturing process, so that the layout space occupied by the thin film transistor is small, which is conducive to achieving ultra-high resolution and stronger Driving capacity.
  • FIG. 13 is a flowchart of a manufacturing method of a fifth embodiment of a top-gate thin film transistor according to the present invention, including the following steps:
  • S2 forming a semiconductor layer 02 covering a portion of the first electrode 01, the semiconductor layer 02 extending from the substrate to the first electrode 01, the semiconductor layer 02 including a first portion 021 located on the first electrode 01 and A second part 022 connected to the first part 021;
  • S3 forming an isolation layer 03 covering the first electrode 01 and the semiconductor layer 02, the isolation layer 03 is provided with a first contact hole 07 at the position of the second portion 022 of the semiconductor; the second electrode 04 passes through the first The contact hole 07 is in contact with the second portion 022 of the semiconductor layer;
  • a gate 06 is formed on the gate insulating layer 05.
  • the first electrode 01 and the second electrode 04 are mainly separated by the semiconductor layer 02 and the isolation layer 03.
  • a protective layer can be formed to isolate the environment (such as water, oxygen, nitrogen, etc.) from affecting the device.
  • FIG. 14 is a schematic structural diagram of a sixth embodiment of a top-gate thin film transistor according to the present invention.
  • a source and a drain are separated by a semiconductor layer and an isolation layer.
  • the thin film transistor shown in FIG. 14 includes a substrate (not shown).
  • Both the first electrode 01 and the second electrode 04 are in contact with the semiconductor layer 02.
  • the isolation layer 02 extends from the substrate and covers the first electrode 01.
  • the isolation layer 02 includes a first portion 021 covering the first electrode 01 and a second portion 022 connected to the first portion.
  • a first contact hole 07 is provided at a position 021 of the first portion 02 of the 02;
  • a semiconductor layer 03 is formed above the isolation layer 02 and the first electrode 01, and the semiconductor layer 03 includes a first portion 031 covering the isolation layer 02 and a first portion 031
  • the second part 032 of the 031 connection, the second part 032 of the semiconductor layer 03 is in contact with the first electrode 01 in the first contact hole 07;
  • the second electrode 04 is formed on the first part 031 of the semiconductor layer 03;
  • the electrode insulating layer 05 covers the substrate, the isolation layer 02, the second electrode 04, and the semiconductor layer 03;
  • the gate 06 is located on the gate insulating layer 05.
  • the channel length can be less than 1um in the manufacturing process, so that the layout space occupied by the thin film transistor is small, which is conducive to achieving ultra-high resolution and stronger Driving capacity.
  • FIG. 15 is a flowchart of a method for manufacturing a top-gate thin film transistor according to a sixth embodiment of the present invention, including the following steps:
  • S2 forming an isolation layer 02 on the substrate and the first electrode 01, the isolation layer 02 extending from the substrate and covering the first electrode 01, the isolation layer 02 including a first portion 021 covering the first electrode 01, and A second portion 022 that is partially connected, and a first contact hole 07 is provided at the position of the first portion 021 of the isolation layer 02;
  • the semiconductor layer 03 includes a first portion 031 covering the isolation layer 02 and a second portion 032 connected to the first portion 031.
  • the semiconductor layer 03 The second portion 032 is in contact with the first electrode 01 in the first contact hole 07;
  • a gate 06 is formed on the gate insulating layer 05.
  • the first electrode 01 and the second electrode 04 are mainly separated by an isolation layer 02 and a semiconductor layer 03.
  • a protective layer can be formed to isolate the environment (such as water, oxygen, nitrogen, etc.) from affecting the device.
  • FIG. 16 is a schematic structural diagram of a seventh embodiment of a top-gate thin film transistor according to the present invention.
  • the source and drain are separated by an isolation layer.
  • the thin film transistor includes a first electrode on a substrate (not shown). 01.
  • An isolation layer 02 located between the first electrode 01 and the second electrode 03, a semiconductor layer 04, a second electrode 03 located at a different layer from the first electrode 01, a gate insulating layer 05, and a gate 06.
  • the first electrode Both 01 and the second electrode 03 are in contact with the semiconductor layer 04.
  • the structure of the thin film transistor embodiment 7 is basically the same as that of the thin film transistor embodiment 6. The difference is that the semiconductor layer 04 is formed above the first electrode 01, the isolation layer 02, and the second electrode 03.
  • the semiconductor layer 04 includes a first portion 041 covering the second electrode 03 and a second portion 042 connected to the first portion 041.
  • the second portion 042 of the semiconductor layer 04 is in contact with the first electrode 01 in the first contact hole 07.
  • the channel length can be less than 1um in the manufacturing process, so that the layout space occupied by the thin film transistor is small, which is conducive to achieving ultra-high resolution and stronger Driving capacity.
  • FIG. 17 is a flowchart of a manufacturing method of a seventh embodiment of a top-gate thin film transistor according to the present invention, including the following steps:
  • S2 forming an isolation layer 02 on the substrate and the first electrode 01, the isolation layer 02 extending from the substrate and covering the first electrode 01, the isolation layer 02 including a first portion 021 covering the first electrode 01, and The second part 022 connected to the first part is provided with a first contact hole 07 at the position of the first part 021 of the isolation layer 02;
  • S4 forming a semiconductor layer 04 covering the first electrode 01, the isolation layer 02, and the second electrode 03, the semiconductor layer 04 includes a first portion 041 covering the second electrode 03 and a second portion 042 connected to the first portion 041, The second portion 042 of the semiconductor layer 04 is in contact with the first electrode 01 in the first contact hole 07;
  • a gate 06 is formed on the gate insulating layer 05.
  • the first electrode 01 and the second electrode 03 are mainly separated by an isolation layer 02 and a semiconductor layer 04.
  • a protective layer can be formed to isolate the environment (such as water, oxygen, nitrogen, etc.) from affecting the device.
  • the material of the semiconductor layer is not limited to amorphous silicon, oxide semiconductor, polysilicon, organic semiconductor, etc .; the materials of the gate, source, and drain metal layers are not limited to single-layer metal and stacked metal.

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Abstract

一种薄膜晶体管结构和制造方法。薄膜晶体管适配于基板上，包括：栅极（01）；栅极绝缘层（02），覆盖栅极；半导体层（03），位于栅极绝缘层的上方；位于不同层的第一电极（04）和第二电极（06），第一电极和第二电极均与半导体层接触；隔离层（05），位于第一电极和第二电极之间且覆盖部分半导体层，隔离层在半导体层上设有第一接触孔（07），第二电极通过第一接触孔与半导体层接触。能够实现超高解析度的像素设计和更强的薄膜晶体管驱动能力。

Description

一种薄膜晶体管及其制造方法
本申请要求于2018年09月30日提交中国专利局、申请号为201811153521.5、发明名称为“一种薄膜晶体管及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于薄膜晶体管领域，具体涉及薄膜晶体管及其制造方法。
背景技术
传统的底栅错列型TFT一般包括刻蚀保护型器件结构和背沟道刻蚀型器件结构。刻蚀保护型器件结构依次成膜顺序为形成栅极01、形成栅绝缘层、形成半导体层02、形成刻蚀保护层03、同时形成源极和漏极04，最终形成的薄膜晶体管如图1所示。该器件的沟道长度为a+2b，a是同层源极和漏极金属之间的距离，受限制于曝光机精度，b要确保在源极和漏极刻蚀后能把刻蚀保护层03的孔覆盖住，这样整个器件占用的版图宽度为W＝a+4b+2c，器件无法小型化，且沟道长度较大。
为了减少制程光罩数量，降低寄生电容影响，后来开发了背沟道刻蚀型器件结构。背沟道刻蚀型器件结构依次成膜顺序为形成栅极01、形成栅绝缘层、形成半导体层02、同时形成源极和漏极03，最终形成的薄膜晶体管如图2所示。该器件的沟道长度为a，a是同层源极和漏极金属之间的距离，受限制于曝光机精度。这样整个器件占用的版图宽度为W＝a+2b，相对比与刻蚀保护型器件，器件宽度已有所缩小，但是依然占用空间较大，不适合应用于超高解析度的面板设计。
以上两种薄膜晶体管结构都存在以下缺点：TFT占用面积大，不适用于开发超高解析度的显示器；TFT的沟道长度L受限制，无法再减小，不利于电流提升。
发明内容
本发明提供了一种全新的薄膜晶体管结构和制造方法，主要在于将TFT的源极金属和漏极金属分开制造，有效避免同层金属之间的间距受制 程限制和沟道长度受限制的问题，实现超高解析度的像素设计和更强的薄膜晶体管驱动能力。
所述技术方案如下：
本发明提供一种薄膜晶体管，包括：
栅极；栅极绝缘层，覆盖所述栅极；半导体层，位于所述栅极绝缘层的上方；位于不同层的第一电极和第二电极，所述第一电极和所述第二电极均与所述半导体层接触；隔离层，位于所述第一电极和所述第二电极之间且覆盖部分所述半导体层，所述隔离层在所述半导体层上设有第一接触孔，所述第二电极通过所述第一接触孔与所述半导体层接触。
本发明还提供一种薄膜晶体管，包括：
栅极；栅极绝缘层，覆盖所述栅极；位于不同层的第一电极和第二电极，所述第一电极和所述第二电极均位于所述栅极绝缘层的上方；半导体层，位于所述第一电极和所述第二电极之间且均与所述第一电极和所述第二电极接触，所述半导体层部分位于所述栅极绝缘层上。
进一步地，还包括位于所述第一电极和所述第二电极之间的隔离层，所述隔离层在所述半导体层的上方且在所述半导体层和所述栅极绝缘层接触的位置处设有第一接触孔，所述第二电极或所述第一电极通过所述第一接触孔与所述半导体层的部分接触。
本发明还提供一种薄膜晶体管，包括：
位于不同层的第一电极和第二电极；半导体层，位于所述第一电极和所述第二电极之间且均与所述第一电极和所述第二电极接触；栅极绝缘层，覆盖所述第一电极、所述第二电极和所述半导体层；栅极，位于所述栅极绝缘层上方。
进一步地，还包括位于所述第一电极和所述第二电极之间的隔离层，所述隔离层在所述半导体层的上方且在所述半导体层和基板接触的位置处设有第一接触孔，所述第二电极或所述第一电极通过所述第一接触孔与所述半导体层的部分接触。
本发明还提供一种薄膜晶体管，包括：
位于不同层的第一电极和第二电极；隔离层，位于所述第一电极和所述第二电极之间，所述隔离层设有第一接触孔；半导体层，位于所述隔离 层的上方，所述半导体层的一部分与所述第二电极接触，所述半导体层的另一部分位于所述第一接触孔内与所述第一电极接触；栅极绝缘层，覆盖所述隔离层和所述半导体层；栅极，位于所述栅极绝缘层上方。
进一步地，所述半导体层的一部分与所述第二电极接触时位于所述第二电极的上方或下方。
本发明还提供一种薄膜晶体管的制造方法，包括步骤：
S1：形成栅极；
S2：形成覆盖栅极的栅极绝缘层；
S3：形成位于栅极绝缘层上的半导体层；
S4：形成覆盖部分栅极绝缘层和覆盖部分半导体层的第一电极；
S5：形成覆盖栅极绝缘层、第一电极以及半导体层的隔离层，所述隔离层在所述半导体层的另一部分的位置处设第一接触孔；
S6：形成位于第一接触孔内的第二电极。
本发明还提供一种薄膜晶体管的制造方法，包括步骤：
S1：形成栅极；
S2：形成覆盖栅极的栅极绝缘层；
S3：形成位于栅极绝缘层上的第一电极；
S4：形成覆盖部分第一电极和覆盖部分栅极绝缘层的半导体层；
S5：形成覆盖半导体层的另一部分的第二电极。
进一步地，还包括步骤：
形成覆盖栅极绝缘层、第一电极以及半导体层的隔离层，所述隔离层在所述半导体层的另一部分的位置处设第一接触孔；所述第二电极通过所述第一接触孔与所述半导体层的另一部分接触。
本发明还提供一种薄膜晶体管的制造方法，包括步骤：
S1：形成第一电极；
S2：形成覆盖部分第一电极的半导体层；
S3：形成覆盖半导体层另一部分的第二电极；
S4：形成覆盖第一电极、半导体层以及第二电极的栅极绝缘层；
S5：形成位于栅极绝缘层上的栅极。
进一步地，还包括步骤：
形成覆盖第一电极以及半导体层的隔离层，所述隔离层在所述半导体层的另一部分的位置处设第一接触孔；所述第二电极通过所述第一接触孔与所述半导体层的另一部分接触。
本发明还提供一种薄膜晶体管的制造方法，包括步骤：
S1：形成第一电极；
S2：形成一部分覆盖第一电极和另一部分覆盖基板的隔离层，所述隔离层的一部分位置处设有第一接触孔；
S3：形成一部分覆盖隔离层和另一部分覆盖第一电极的半导体层，所述半导体层的另一部分在第一接触孔内与第一电极接触；
S4：形成位于半导体层一部分上的第二电极；
S5：形成覆盖隔离层、第二电极以及半导体层的栅极绝缘层；
S6：形成位于栅极绝缘层上的栅极。
本发明还提供一种薄膜晶体管的制造方法，包括步骤：
S1：形成第一电极；
S2：形成一部分覆盖第一电极和另一部分覆盖基板的隔离层，所述隔离层的一部分位置处设有第一接触孔；
S3：形成位于隔离层另一部分上的第二电极；
S4：形成一部分覆盖第二电极和另一部分覆盖第一电极的半导体层，所述半导体层的另一部分在第一接触孔内与第一电极接触；
S5：形成覆盖隔离层和半导体层的栅极绝缘层；
S6：形成位于栅极绝缘层上的栅极。
本发明通过将源极和漏极位于不同层，有效避免同层金属之间的间距问题和沟道限制问题；本发明通过新增一层隔离层用于隔离源极和漏极，实现超高解析度的像素设计和更强的薄膜晶体管驱动能力。
附图说明
下面将以明确易懂的方式，结合附图说明优选实施方式，对本发明予以进一步说明。
图1是传统的刻蚀保护型薄膜晶体管器件结构示意图；
图2是传统的背沟道刻蚀型薄膜晶体管器件结构示意图；
图3是本发明底栅式薄膜晶体管实施例一的结构示意图；
图4是本发明底栅式薄膜晶体管实施例一的俯视示意图；
图5是本发明底栅式薄膜晶体管实施例一的制造方法的流程图；
图6是本发明底栅式薄膜晶体管实施例二的结构示意图；
图7是本发明底栅式薄膜晶体管实施例二的制造方法的流程图；
图8是本发明底栅式薄膜晶体管实施例三的结构示意图；
图9是本发明底栅式薄膜晶体管实施例三的制造方法的流程图；
图10是本发明顶栅式薄膜晶体管实施例四的结构示意图；
图11是本发明顶栅式薄膜晶体管实施例四的制造方法的流程图；
图12是本发明顶栅式薄膜晶体管实施例五的结构示意图；
图13是本发明顶栅式薄膜晶体管实施例五的制造方法的流程图；
图14是本发明顶栅式薄膜晶体管实施例六的结构示意图；
图15是本发明顶栅式薄膜晶体管实施例六的制造方法的流程图；
图16是本发明顶栅式薄膜晶体管实施例七的结构示意图；
图17是本发明顶栅式薄膜晶体管实施例七的制造方法的流程图。
具体实施方式
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
下面详细介绍本发明的技术方案。
本发明提出的一种薄膜晶体管，其称之为隔离源极和漏极的TFT结构(isolated Source and Drain TFT(ISD-TFT))，本发明薄膜晶体管适用于任何类型的半导体TFT，例如非晶硅，氧化物半导体，低温多晶硅(LTPS)、有机半导体等等。
本发明薄膜晶体管分别为底栅式薄膜晶体管和顶栅式薄膜晶体管。其中，底栅式薄膜晶体管包括三种实施例：仅用隔离层隔离源极和漏极、半导体层隔离源极和漏极、半导体层与隔离层共同隔离源极和漏极，底栅式薄膜晶体管包括四种实施例：仅用隔离层隔离源极和漏极、半导体层隔离源极和漏极、半导体层与隔离层共同隔离源极和漏极。
下面分别介绍本发明底栅式薄膜晶体管和顶栅式薄膜晶体管。
第一种：底栅式薄膜晶体管：
图3是本发明底栅式薄膜晶体管实施例一的结构示意图，仅用隔离层隔离源极和漏极，如图1所示，该薄膜晶体管包括位于基板(图未示)上的栅极01、覆盖栅极01的栅极绝缘层02、位于栅极绝缘层02上方的半导体层03、第一电极04、隔离层05以及与第一电极04位于不同层的第二电极06，第一电极04和第二电极06均与所述半导体层03接触。
其中，所述半导体层03包括沿栅极01延伸方向的第一部分031以及与所述第一部分连接的第二部分032(即半导体层03分成左右两部分)；第一电极04设于所述栅极绝缘层02以及所述半导体层03上，其中，所述第一电极04覆盖了所述半导体层的第一部分031；隔离层05覆盖所述栅极绝缘层02、第一电极04以及半导体层的第二部分032，所述隔离层05位于第一电极04和第二电极06之间且覆盖部分半导体层03，在所述半导体层的第二部分032位置处设有第一接触孔07；第二电极06覆盖所述半导体层的第二部分032，所述第二电极06通过所述第一接触孔07与所述半导体层的第二部分032接触。
需要说明的是，当第一电极04是源极时，第二电极06是漏极；当第一电极04是漏极时，第二电极06是源极。
图4所示为本发明底栅式薄膜晶体管实施例一的俯视示意图，从下往上依次包括位于基板(图未示)上的栅极01、栅极绝缘层02、半导体层03、第一电极04、隔离层05、第二电极06。其中，沟道长度是a，第一电 极04金属宽度是b，第一接触孔07的宽度是c，整个薄膜晶体管的宽度可以缩小到W＝a+b+c，例如a＝1um，b＝3um，c＝2um，最小宽度W＝6um。同时薄膜晶体管的沟道长度a相比背景技术中的两种方案均较小，薄膜晶体管的线性区驱动电流公示近似为：
Figure PCTCN2018123482-appb-000001
其中，薄膜晶体管的沟道长度为L，当L很小时，薄膜晶体管的驱动电流会反比增加。a是TFT器件的沟道长度(L＝a)，由于源极和漏极金属不是同层金属且有隔离层分开，其沟道长度a在制程上甚至可以做到小于1um，这样薄膜晶体管所占的版图空间很小，利于实现超高解析度和更强的驱动能力。
图5所示是本发明底栅式薄膜晶体管实施例一的制造方法的流程图，该方法包括以下步骤：
S1：在基板上形成栅极01；
S2：形成覆盖栅极01的栅极绝缘层02；
S3：形成位于栅极绝缘层02上的半导体层03，半导体层包括第一部分031以及与所述第一部分031连接的第二部分032；
S4：形成覆盖部分栅极绝缘层02和覆盖部分半导体层03的第一电极04，其中，所述第一电极04覆盖所述半导体层的第一部分031；
S5：形成覆盖栅极绝缘层02、第一电极04以及半导体层03的隔离层05，所述隔离层05在所述半导体层的第二部分032处设有第一接触孔07；
S6：形成第二电极06，第二电极06位于半导体层的第二部分032上，所述第二电极06通过所述第一接触孔07与所述半导体层的第二部分032接触。
第一电极04和第二电极06主要是通过隔离层05隔离开。
根据图5所示的薄膜晶体管制造方法就能形成ISD-TFT器件，后续工艺流程可以根据显示需要进行设置，一般会增加保护层以避免环境水氧等对器件产生影响。
图6为本发明底栅式薄膜晶体管实施例二的结构示意图，通过半导体层隔离源极和漏极，如图6所示，该薄膜晶体管包括位于基板(图未示) 上的栅极01、覆盖栅极01的栅极绝缘层02、第一电极03、半导体层04以及与第一电极03位于不同层的第二电极06，第一电极03和第二电极06均与所述半导体层04接触。
其中，第一电极03位于所述栅绝缘层02上；所述半导体层04部分位于所述栅极绝缘层02上，所述半导体层04从所述栅极绝缘层02延伸至所述第一电极03上，所述半导体层04包括位于所述第一电极03的第一部分041以及与所述第一部分连接的第二部分042；第二电极06覆盖并且接触所述半导体层的第二部分042。
由于源极和漏极金属不是同层金属且有半导体层用作隔离分开，其沟道长度在制程上可以做到小于1um，这样薄膜晶体管所占的版图空间很小，利于实现超高解析度和更强的驱动能力。
图7所示是本发明底栅式薄膜晶体管实施例二的制造方法的流程图,包括以下步骤：
S1：在基板上形成栅极01；
S2：形成覆盖栅极01的栅极绝缘层02；
S3：形成位于栅极绝缘层02上的第一电极03；
S4：形成覆盖部分第一电极03和覆盖部分栅极绝缘层02的半导体层04，所述半导体层04从所述栅绝缘层02延伸至所述第一电极03上，所述半导体层04包括位于所述第一电极03的第一部分041以及与所述第一部分041连接的第二部分042；
S5：形成覆盖半导体层04第二部分042的第二电极06。
第一电极03和第二电极06主要是通过半导体层04隔离开。
图8为本发明底栅式薄膜晶体管实施例三的结构示意图，通过半导体层和隔离层同时隔离源极和漏极，该薄膜晶体管包括位于基板(图未示)上的栅极01、覆盖栅极01的栅极绝缘层02、第一电极03、半导体层04、位于半导体层04上方的隔离层05以及与第一电极03位于不同层的第二电极06，第一电极03和第二电极06均与所述半导体层04接触。
薄膜晶体管实施例三的结构与薄膜晶体管实施例二的结构基本相同，其区别在于第一电极03与第二电极06之间还设有隔离层05，所述隔离层05覆盖所述栅极绝缘层02、所述第一电极03以及所述半导体层04，所述 隔离层05在所述半导体层和栅极绝缘层02接触的第二部分042位置处设有第一接触孔07，所述第二电极06通过所述第一接触孔07与所述半导体层的第二部分042接触。
由于源极和漏极不是同层金属且有隔离层分开，其沟道长度在制程上可以做到小于1um，这样薄膜晶体管所占的版图空间很小，利于实现超高解析度和更强的驱动能力。
图9所示是本发明底栅式薄膜晶体管实施例三的制造方法的流程图，包括以下步骤：
S1：在基板上形成栅极01；
S2：形成覆盖栅极01的栅极绝缘层02；
S3：形成位于栅极绝缘层02上的第一电极03；
S4：形成覆盖部分第一电极03和覆盖部分栅极绝缘层02的半导体层04，所述半导体层04从所述栅绝缘层02延伸至所述第一电极03上，所述半导体层04包括位于所述第一电极03的第一部分041以及与所述第一部分041连接的第二部分042；
S5：形成覆盖栅极绝缘层02、第一电极03以及半导体层04的隔离层05，所述隔离层05在半导体的第二部分042位置处设有第一接触孔07；所述第二电极06通过所述第一接触孔07与所述半导体层的第二部分042接触；
S6：形成覆盖半导体层04第二部分042的第二电极06。
第一电极03和第二电极06主要是通过半导体层04和隔离层05隔离开。
在TFT器件制造完成后，可以再形成一层保护层用以隔离环境(例如水，氧气，氮气等)对器件产生的影响。
第二种：顶栅式薄膜晶体管：
图10为本发明顶栅式薄膜晶体管实施例四的结构示意图，通过半导体层隔离源极和漏极，该薄膜晶体管包括位于基板(图未示)上的第一电极01和半导体层02、与第一电极01位于不同层的第二电极04、栅极绝缘层05以及栅极06，第一电极01和第二电极04均与所述半导体层02接触。
其中，所述半导体层02从基板上延伸至所述第一电极01上，所述半导体层02包括位于所述第一电极04的第一部分021以及与所述第一部分连接的第二部分022；第二电极04，覆盖并且接触所述半导体层的第二部分022；栅极绝缘层05，覆盖所述基板、第一电极01、半导体层02以及第二电极04；栅极06位于所述栅极绝缘层05上。
由于源极和漏极金属不是同层金属且有半导体层用作隔离分开，其沟道长度在制程上可以做到小于1um，这样薄膜晶体管所占的版图空间很小，利于实现超高解析度和更强的驱动能力。
图11所示是本发明顶栅式薄膜晶体管实施例四的制造方法的流程图，包括以下步骤：
S1：在基板上形成第一电极01；
S2：形成覆盖部分第一电极01的半导体层02，所述半导体层02从基板上延伸至所述第一电极01上，所述半导体层02包括位于所述第一电极01的第一部分021以及与所述第一部分021连接的第二部分022；
S3：形成覆盖半导体层02的第二部分022的第二电极04；
S4：形成覆盖第一电极01、半导体层02以及第二电极04的栅极绝缘层05；
S5：形成位于栅极绝缘层05上的栅极06。
第一电极01和第二电极04主要是通过半导体层02隔离开。
图12为本发明顶栅式薄膜晶体管实施例五的结构示意图，通过半导体层和隔离层同时隔离源极和漏极，该薄膜晶体管包括位于基板(图未示)上的第一电极01和半导体层02、位于半导体层02上方的隔离层03、与第一电极01位于不同层的第二电极04、栅极绝缘层05以及栅极06，第一电极01和第二电极04均与所述半导体层02接触。
薄膜晶体管实施例五的结构与薄膜晶体管实施例四的结构基本相同，其区别在于所述第一电极01和第二电极04之间还设有隔离层03，所述隔离层03覆盖所述基板、所述第一电极01以及所述半导体层02，所述隔离层03在所述半导体的第二部分022位置处设有第一接触孔07，所述第二电极04通过所述第一接触孔07与所述半导体层的第二部分022接触。
由于源极和漏极金属不是同层金属且有隔离层分开，其沟道长度在制程上可以做到小于1um，这样薄膜晶体管所占的版图空间很小，利于实现超高解析度和更强的驱动能力。
图13所示是本发明顶栅式薄膜晶体管实施例五的制造方法的流程图，包括以下步骤：
S1：在基板上形成第一电极01；
S2：形成覆盖部分第一电极01的半导体层02，所述半导体层02从基板上延伸至所述第一电极01上，所述半导体层02包括位于所述第一电极01的第一部分021以及与所述第一部分021连接的第二部分022；
S3：形成覆盖第一电极01以及半导体层02的隔离层03，所述隔离层03在半导体的第二部分022位置处设有第一接触孔07；所述第二电极04通过所述第一接触孔07与所述半导体层的第二部分022接触；
S4：形成覆盖半导体层02的第二部分022的第二电极04；
S5：形成覆盖第一电极01、半导体层02以及第二电极04的栅极绝缘层05；
S6：形成位于栅极绝缘层05上的栅极06。
第一电极01和第二电极04主要是通过半导体层02和隔离层03隔离开。
在TFT器件制造完成后，可以再形成一层保护层用以隔离环境(例如水，氧气，氮气等)对器件的产生影响。
图14所示是本发明顶栅式薄膜晶体管实施例六的结构示意图，通过半导体层与隔离层共同隔离源极和漏极，如图14所示该薄膜晶体管包括位于基板(图未示)上的第一电极01、位于第一电极01和第二电极04之间的隔离层02、半导体层03、与第一电极01位于不同层的第二电极04、栅极绝缘层05以及栅极06，第一电极01和第二电极04均与所述半导体层02接触。
其中，所述隔离层02从基板上延伸并覆盖第一电极01，所述隔离层02包括覆盖在第一电极01的第一部分021以及与第一部分连接的第二部分022，在所述隔离层02的第一部分021位置处设有第一接触孔07；半导体层03形成于隔离层02以及第一电极01的上方，所述半导体层03包括 覆盖在隔离层02的第一部分031以及与第一部分031连接的第二部分032，所述半导体层03的第二部分032在第一接触孔07内与第一电极01接触；所述第二电极04形成于半导体层03的第一部分031上；栅极绝缘层05覆盖所述基板、隔离层02、第二电极04以及半导体层03；栅极06位于所述栅极绝缘层05上。
由于源极和漏极金属不是同层金属且有隔离层分开，其沟道长度在制程上可以做到小于1um，这样薄膜晶体管所占的版图空间很小，利于实现超高解析度和更强的驱动能力。
图15所示是本发明顶栅式薄膜晶体管实施例六的制造方法的流程图，包括以下步骤：
S1：在基板上形成第一电极01；
S2：形成位于基板以及第一电极01上隔离层02，所述隔离层02从基板上延伸并覆盖第一电极01，所述隔离层02包括覆盖在第一电极01的第一部分021以及与第一部分连接的第二部分022，在所述隔离层02的第一部分021位置处设有第一接触孔07；
S3：形成位于隔离层02以及第一电极01的上方半导体层03，所述半导体层03包括覆盖在隔离层02的第一部分031以及与第一部分031连接的第二部分032，所述半导体层03的第二部分032在第一接触孔07内与第一电极01接触；
S4：形成位于半导体层03第一部分031上的第二电极04；
S5：形成覆盖隔离层03、第二电极04以及半导体层03的栅极绝缘层05；
S6：形成位于栅极绝缘层05上的栅极06。
第一电极01和第二电极04主要是通过隔离层02和半导体层03隔离开。
在TFT器件制造完成后，可以再形成一层保护层用以隔离环境(例如水，氧气，氮气等)对器件的产生影响。
图16所示是本发明顶栅式薄膜晶体管实施例七的结构示意图，通过隔离层隔离源极和漏极，如图16所示该薄膜晶体管包括位于基板(图未示)上的第一电极01、位于第一电极01和第二电极03之间的隔离层02、半导 体层04、与第一电极01位于不同层的第二电极03、栅极绝缘层05以及栅极06，第一电极01和第二电极03均与所述半导体层04接触。
其中，薄膜晶体管实施例七的结构与薄膜晶体管实施例六的结构基本相同，其区别在于所述半导体层04形成于第一电极01、隔离层02以及第二电极03的上方，所述半导体层04包括覆盖在第二电极03的第一部分041以及与第一部分041连接的第二部分042，所述半导体层04的第二部分042在第一接触孔07内与第一电极01接触。
由于源极和漏极金属不是同层金属且有隔离层分开，其沟道长度在制程上可以做到小于1um，这样薄膜晶体管所占的版图空间很小，利于实现超高解析度和更强的驱动能力。
图17所示是本发明顶栅式薄膜晶体管实施例七的制造方法的流程图，包括以下步骤：
S1：在基板上形成第一电极01；
S2：形成位于基板以及第一电极01上的隔离层02，所述隔离层02从基板上延伸并覆盖第一电极01，所述隔离层02包括覆盖在第一电极01的第一部分021以及与第一部分连接的第二部分022，在所述隔离层02的第一部分021位置处设有第一接触孔07；
S3：形成位于隔离层02第二部分022上的第二电极03；
S4：形成覆盖第一电极01、隔离层02以及第二电极03的半导体层04，所述半导体层04包括覆盖在第二电极03的第一部分041以及与第一部分041连接的第二部分042，所述半导体层04的第二部分042在第一接触孔07内与第一电极01接触；
S5：形成覆盖隔离层02以及半导体层04的栅极绝缘层05；
S6：形成位于栅极绝缘层05的栅极06。
第一电极01和第二电极03主要是通过隔离层02和半导体层04隔离开。
在TFT器件制造完成后，可以再形成一层保护层用以隔离环境(例如水，氧气，氮气等)对器件的产生影响。
以上所述七种结构的实施例中，半导体层材料不限于非晶硅、氧化物半导体、多晶硅、有机半导体等；栅极、源极、漏极金属层材料不限于单 层金属、叠层金属，例如Mo单层，叠层Ti/Cu，Mo/Al/Mo等；栅极绝缘层、隔离层材料不限于SiO2、SiOx、Al2O3、SiNx等，或者可以根据TFT器件特性要求优选多层绝缘材料叠加。
应当说明的是，以上所述仅是本发明的优选实施方式，但是本发明并不限于上述实施方式中的具体细节，应当指出，对于本技术领域的普通技术人员来说，在本发明的技术构思范围内，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，对本发明的技术方案进行多种等同变换，这些改进、润饰和等同变换也应视为本发明的保护范围。

Claims (14)

  1. 一种薄膜晶体管，其特征在于，包括：
    栅极；
    栅极绝缘层，覆盖所述栅极；
    半导体层，位于所述栅极绝缘层的上方；
    位于不同层的第一电极和第二电极，所述第一电极和所述第二电极均与所述半导体层接触；
    隔离层，位于所述第一电极和所述第二电极之间且覆盖部分所述半导体层，所述隔离层在所述半导体层上设有第一接触孔，所述第二电极通过所述第一接触孔与所述半导体层接触。
  2. 一种薄膜晶体管，其特征在于，包括：
    栅极；
    栅极绝缘层，覆盖所述栅极；
    位于不同层的第一电极和第二电极，所述第一电极和所述第二电极均位于所述栅极绝缘层的上方；
    半导体层，位于所述第一电极和所述第二电极之间且均与所述第一电极和所述第二电极接触，所述半导体层部分位于所述栅极绝缘层上。
  3. 根据权利要求2所述的一种薄膜晶体管，其特征在于，还包括位于所述第一电极和所述第二电极之间的隔离层，所述隔离层在所述半导体层的上方且在所述半导体层和所述栅极绝缘层接触的位置处设有第一接触孔，所述第二电极或第一电极通过所述第一接触孔与所述半导体层的部分接触。
  4. 一种薄膜晶体管，其特征在于，包括：
    位于不同层的第一电极和第二电极；
    半导体层，位于所述第一电极和所述第二电极之间且均与所述第一电极和所述第二电极接触；
    栅极绝缘层，覆盖所述第一电极、所述第二电极和所述半导体层；
    栅极，位于所述栅极绝缘层上方。
  5. 根据权利要求4所述的一种薄膜晶体管，其特征在于，还包括位于所述第一电极和第二电极之间的隔离层，所述隔离层在所述半导体层的上方且在所述半导体层和基板接触的位置处设有第一接触孔，所述第二电极或所述第一电极通过所述第一接触孔与所述半导体层的部分接触。
  6. 一种薄膜晶体管，其特征在于，包括：
    位于不同层的第一电极和第二电极；
    隔离层，位于所述第一电极和所述第二电极之间，所述隔离层设有第一接触孔；
    半导体层，位于所述隔离层的上方，所述半导体层的一部分与所述第二电极接触，所述半导体层的另一部分位于所述第一接触孔内与所述第一电极接触；
    栅极绝缘层，覆盖所述隔离层和所述半导体层；
    栅极，位于所述栅极绝缘层上方。
  7. 根据权利要求6所述的一种薄膜晶体管，其特征在于，所述半导体层的一部分与所述第二电极接触时位于所述第二电极的上方或下方。
  8. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成栅极；
    S2：形成覆盖栅极的栅极绝缘层；
    S3：形成位于栅极绝缘层上的半导体层；
    S4：形成覆盖部分栅极绝缘层和覆盖部分半导体层的第一电极；
    S5：形成覆盖栅极绝缘层、第一电极以及半导体层的隔离层，所述隔离层在所述半导体层的另一部分的位置处设第一接触孔；
    S6：形成位于第一接触孔内的第二电极。
  9. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成栅极；
    S2：形成覆盖栅极的栅极绝缘层；
    S3：形成位于栅极绝缘层上的第一电极；
    S4：形成覆盖部分第一电极和覆盖部分栅极绝缘层的半导体层；
    S5：形成覆盖半导体层的另一部分的第二电极。
  10. 根据权利要求9所述的一种薄膜晶体管的制造方法，其特征在于，还包括步骤：
    形成覆盖栅极绝缘层、第一电极以及半导体层的隔离层，所述隔离层在所述半导体层的另一部分的位置处设第一接触孔；所述第二电极通过所述第一接触孔与所述半导体层的另一部分接触。
  11. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成第一电极；
    S2：形成覆盖部分第一电极的半导体层；
    S3：形成覆盖半导体层另一部分的第二电极；
    S4：形成覆盖第一电极、半导体层以及第二电极的栅极绝缘层；
    S5：形成位于栅极绝缘层上的栅极。
  12. 根据权利要求11所述的一种制造薄膜晶体管的方法，其特征在于，还包括步骤：
    形成覆盖第一电极以及半导体层的隔离层，所述隔离层在所述半导体层的另一部分的位置处设第一接触孔；所述第二电极通过所述第一接触孔与所述半导体层的另一部分接触。
  13. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成第一电极；
    S2：形成一部分覆盖第一电极和另一部分覆盖基板的隔离层，所述隔离层的一部分位置处设有第一接触孔；
    S3：形成一部分覆盖隔离层和另一部分覆盖第一电极的半导体层，所述半导体层的另一部分在第一接触孔内与第一电极接触；
    S4：形成位于半导体层一部分上的第二电极；
    S5：形成覆盖隔离层、第二电极以及半导体层的栅极绝缘层；
    S6：形成位于栅极绝缘层上的栅极。
  14. 一种薄膜晶体管的制造方法，其特征在于，包括步骤：
    S1：形成第一电极；
    S2：形成一部分覆盖第一电极和另一部分覆盖基板的隔离层，所述隔离层的一部分位置处设有第一接触孔；
    S3：形成位于隔离层另一部分上的第二电极；
    S4：形成一部分覆盖第二电极和另一部分覆盖第一电极的半导体层，所述半导体层的另一部分在第一接触孔内与第一电极接触；
    S5：形成覆盖隔离层和半导体层的栅极绝缘层；
    S6：形成位于栅极绝缘层上的栅极。
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