CN106847927A - 薄膜晶体管及其制作方法、液晶面板 - Google Patents

薄膜晶体管及其制作方法、液晶面板 Download PDF

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Publication number
CN106847927A
CN106847927A CN201710058106.0A CN201710058106A CN106847927A CN 106847927 A CN106847927 A CN 106847927A CN 201710058106 A CN201710058106 A CN 201710058106A CN 106847927 A CN106847927 A CN 106847927A
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China
Prior art keywords
electrode
source electrode
tft
thin film
film transistor
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CN201710058106.0A
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黄贵华
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201710058106.0A priority Critical patent/CN106847927A/zh
Priority to PCT/CN2017/073802 priority patent/WO2018133148A1/zh
Priority to US15/509,506 priority patent/US20180231816A1/en
Publication of CN106847927A publication Critical patent/CN106847927A/zh
Pending legal-status Critical Current

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Abstract

本发明提供了一种薄膜晶体管，包括基板，所述基板上沉积有图案化的源极以及公共电极，在源极以及公共电极上覆盖有衬垫层，所述源极远离公共电极的一侧裸露在衬垫层外形成裸露部，在衬垫层上沉积漏极并图案化形成像素电极，所述像素电极位于源极的一侧、裸露部以及基板位于源极的一侧上依次沉积有图案化的半导体层、栅极绝缘层以及图案化的栅极，从而形成截面为阶梯结构的半导体沟道，所述像素电极通过半导体层与源极连接。本发明还提供了一种薄膜晶体管的制作方法以及液晶面板与现有技术相比，提高了薄膜晶体管的开关比，也提高了开口率；能够应用于高解析度面板上；减少了工艺流程，节约成本。

Description

薄膜晶体管及其制作方法、液晶面板
技术领域
本发明涉及一种显示技术领域，特别是一种基于IPS结构的薄膜晶体管及其制作方法、液晶面板。
背景技术
目前TFT(薄膜晶体管)阵列基板中TFT器件的半导体沟道大多采用二维平面结构，沟道长度均会做得比较长，从而限制了TFT器件的开关比；TFT阵列基板中的TFT器件的尺寸会做得比较大，导致降低了开口率；TFT制作过程中，需要使用多道光罩(一般至少5道光罩)，制程繁琐且成本较高。这些都制约了TFT阵列基板的发展。
发明内容
为克服现有技术的不足，本发明提供一种薄膜晶体管及其制作方法、液晶面板，从而提高TFT器件的开关比，而且也提高了开口率。
本发明提供了一种薄膜晶体管，包括基板，所述基板上沉积有图案化的源极以及公共电极，在源极以及公共电极上覆盖有衬垫层，所述源极远离公共电极的一侧裸露在衬垫层外形成裸露部，在衬垫层上沉积漏极并图案化形成像素电极，所述像素电极位于源极的一侧、裸露部以及基板位于源极的一侧上依次沉积有图案化的半导体层、栅极绝缘层以及图案化的栅极，从而形成截面为阶梯结构的半导体沟道，所述像素电极通过半导体层与源极连接。
进一步地，所述漏极以及衬垫层的坡度角为45-60度。
进一步地，所述衬垫层采用SiOx或SiNx制成。
进一步地，所述衬垫层的厚度为300-1200nm。
进一步地，所述半导体层为IGZO或a-Si材料中的一种。
进一步地，所述源极及漏极由一层金属层构成或由多层金属层构成的金属叠层结构。
进一步地，所述源极及漏极的厚度为100-400nm。
本发明还提供了一种薄膜晶体管的制作方法，包括如下步骤：
步骤一、在基板上分别沉积源极及公共电极，并对源极和公共电极分别进行图案化；
步骤二、在源极以及公共电极上沉积衬垫层以及漏极，所述源极远离公共电极的一侧通过对衬垫层以及漏极进行刻蚀，使源极远离公共电极的一侧形成裸露部，对漏极图形化后形成像素电极；
步骤三、在基板上位于源极的一侧、源极的裸露部以及像素电极位于源极的一侧上沉积有半导体层，对半导体层进行图案化后在半导体层上沉积栅极绝缘层；在栅极绝缘层上沉积栅极并进行图案化，得到截面为阶梯结构的半导体沟道，所述源极通过半导体层与像素电极连接。
进一步地，所述步骤一以及步骤二中漏极以及衬垫层的坡度角为45-60度。
本发明还提供了一种液晶面板，包括TFT阵列基板，所述TFT阵列基板包括所述的薄膜晶体管。
本发明与现有技术相比，通过将薄膜晶体管的半导体沟道设置为阶梯结构，提高了薄膜晶体管的开关比，也提高了开口率；而将漏极作为像素电极形成IPS结构，使得能够应用于高解析度面板上；而通过三道工序制作薄膜晶体管，减少了工艺流程，节约成本。
附图说明
图1是本发明的薄膜晶体管制作方法步骤一的结构示意图；
图2是本发明的薄膜晶体管制作方法步骤二的结构示意图；
图3是本发明的薄膜晶体管制作方法步骤三的结构示意图；
图4是本发明平面投影图。
具体实施方式
下面结合附图和实施例对本发明作进一步详细说明。
如图3和图4所示，本发明的一种薄膜晶体管，包括基板1，所述基板1上沉积有图案化的源极(Source)2以及图案化的公共电极(COM)3，所述源极2以及公共电极3设于同一层，在源极2以及公共电极3上覆盖有衬垫层(Spacer)4，所述源极2远离公共电极3的一侧(图3的左侧)裸露在衬垫层4外形成裸露部5，在衬垫层4上沉积漏极(Drain)并图案化形成像素电极6，所述像素电极6位于源极2的一侧(图3的左侧)、裸露部5以及基板1位于源极2的一侧上依次沉积有图案化的半导体层8、栅极绝缘层9以及图案化的栅极10，从而形成截面为阶梯结构的半导体沟道7，所述像素电极6通过半导体层8与源极2连接，本发明将半导体沟道7制作成具有垂直面的阶梯结构7，提高了薄膜晶体管的开关比以及开口率；同时利用漏极作为IPS结构的像素电极，可以应用于高解析度面板上。
本发明中半导体层8、栅极绝缘层9以及栅极10高于像素电极6的表面。
所述漏极2以及衬垫层4的坡度角为45-60度，以便后续膜层的沉积。
具体地，所述衬垫层4采用SiOx或SiNx制成，衬垫层4的厚度为300-1200nm；所述半导体层8为IGZO或a-Si材料中的一种；所述源极2及漏极6由一层金属层构成或由多层金属层构成的金属叠层结构，如Mo、Mo/Al/Mo、Mo/Ti等材料构成的金属叠层，厚度为100-400nm。
本发明的一种薄膜晶体管的制作方法，包括如下步骤：
步骤一、如图1所示，在基板1上分别采用现有技术沉积源极2及公共电极3，并对源极2和公共电极3分别进行图案化；
步骤二、如图2所示，在源极2以及公共电极3上通过现有技术沉积衬垫层4以及漏极，所述源极2远离公共电极3的一侧(图2左侧)通过对衬垫层4以及漏极的刻蚀使源极2远离公共电极3的一侧形成裸露部5；对漏极图形化后形成像素电极6；
步骤三、如图3和图4所示，在基板1上位于源极2的一侧、源极2的裸露部5以及像素电极6位于源极2的一侧上沉积有半导体层8，对半导体层8进行图案化后在半导体层8上沉积栅极绝缘层9；在栅极绝缘层9上沉积栅极10并进行图案化，得到截面为阶梯结构的半导体沟道7，所述源极2通过半导体层8与像素电极6连接。
所述步骤一以及步骤二中漏极以及衬垫层4的坡度角为45-60度。
具体地，所述衬垫层4采用SiOx或SiNx制成，衬垫层4的厚度为300-1200nm；所述半导体层8为IGZO或a-Si材料中的一种；所述源极2及漏极6由一层金属层构成或由多层金属层构成的金属叠层结构，如Mo、Mo/Al/Mo、Mo/Ti等材料构成的金属叠层，厚度为100-400nm。
所述漏极及衬垫层4的蚀刻采用干法加湿法的刻蚀工艺进行。
本发明的薄膜晶体管的制作方法只需三道工序即可制作出薄膜晶体管，减少了工艺流程，节约了成本。
本发明还公开了一种液晶面板，所述TFT阵列基板包括上述的薄膜晶体管，在此不在赘述。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (10)

1.一种薄膜晶体管，包括基板(1)，其特征在于：所述基板(1)上沉积有图案化的源极(2)以及公共电极(3)，在源极(2)以及公共电极(3)上覆盖有衬垫层(4)，所述源极(2)远离公共电极(3)的一侧裸露在衬垫层(4)外形成裸露部(5)，在衬垫层(4)上沉积漏极并图案化形成像素电极(6)，所述像素电极(6)位于源极(2)的一侧、裸露部(5)以及基板(1)位于源极(2)的一侧上依次沉积有图案化的半导体层(8)、栅极绝缘层(9)以及图案化的栅极(10)，从而形成截面为阶梯结构的半导体沟道(7)，所述像素电极(6)通过半导体层(8)与源极(2)连接。
2.根据权利要求1所述的薄膜晶体管，其特征在于：所述漏极以及衬垫层(4)的坡度角为45-60度。
3.根据权利要求1所述的薄膜晶体管，其特征在于：所述衬垫层(4)采用SiOx或SiNx制成。
4.根据权利要求1或2所述的薄膜晶体管，起特征在于：所述衬垫层(4)的厚度为300-1200nm。
5.根据权利要求1所述的薄膜晶体管，其特征在于：所述半导体层(8)为IGZO或a-Si材料中的一种。
6.根据权利要求1所述的薄膜晶体管，其特征在于：所述源极(2)及漏极(6)由一层金属层构成或由多层金属层构成的金属叠层结构。
7.根据权利要求1或5所述的薄膜晶体管，其特征在于：所述源极(2)及漏极(6)的厚度为100-400nm。
8.一种薄膜晶体管的制作方法，其特征在于：包括如下步骤：
步骤一、在基板(1)上分别沉积源极(2)及公共电极(3)，并对源极(2)和公共电极(3)分别进行图案化；
步骤二、在源极(2)以及公共电极(3)上沉积衬垫层(4)以及漏极，所述源极(2)远离公共电极(3)的一侧通过对衬垫层(4)以及漏极进行刻蚀，使源极(2)远离公共电极(3)的一侧形成裸露部(5)，对漏极图形化后形成像素电极(6)；
步骤三、在基板(1)上位于源极(2)的一侧、源极(2)的裸露部(5)以及像素电极(6)位于源极(2)的一侧上沉积有半导体层(8)，对半导体层(8)进行图案化后在半导体层(8)上沉积栅极绝缘层(9)；在栅极绝缘层(9)上沉积栅极(10)并进行图案化，得到截面为阶梯结构的半导体沟道(7)，所述源极(2)通过半导体层(8)与像素电极(6)连接。
9.根据权利要求8所述的薄膜晶体管的制作方法，其特征在于：所述步骤一以及步骤二中漏极以及衬垫层(4)的坡度角为45-60度。
10.一种液晶面板，包括TFT阵列基板，其特征在于：所述TFT阵列基板包括如权利要求1-7任意一项所述的薄膜晶体管。
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